High-level effective 3-8 decoder based on hybrid logic

Abstract

The invention discloses a high-level effective 3-8 decoder based on hybrid logic, which comprises two phase inverters and eight logic gate circuits, the eight logic gate circuits are one NOR gate and seven AND gates, in the seven AND gates, four AND gates are AND gates based on transmission gate logic, and three AND gates are AND gates based on transmission tube logic, the PTL logic is used to reduce the number of transistors in a logic gate circuit, the reduction of the number of the transistors not only reduces the occupied area, but also reduces the logic workload, reduces the overall switching activity in the circuit, thereby reducing the power consumption, and at the same time, the reduction of the number of the transistors reduces the capacitance. The use of the TGL logic reduces the on resistance of the logic gate circuit during signal transmission, thereby improving the decoding speed. The decoding circuit has the advantages that the decoding function is effectively realized, the delay is relatively small, the decoding speed is relatively high, the number of consumed transistors is relatively small, the occupied area is relatively small, and the power consumption is relatively low.

Description

Technical Field

[0001] The present invention relates to a high level effective 3-8 decoder, and in particular to a high level effective 3-8 decoder based on hybrid logic. Background Art

[0002] With the development of ultra-large-scale integrated circuits, the scale of memory is getting larger and larger. As an important part of the peripheral circuit of the memory, the scale of the decoder is also expanding. Therefore, the design of the decoder affects the performance of the memory. The traditional decoder is composed of a complementary metal oxide semiconductor (CMOS) logic gate circuit and an inverter, and has two types: high-level active type and low-level active type. For the traditional high-level active 3-8 decoder, such as the traditional 54-tube CMOS logic high-level active 3-8 decoder disclosed in "Digital Integrated Circuits - Circuits, Systems and Design Digital Integrated Circuits - Circuits, Systems and Design", it is usually composed of 3 inverters and 8 CMOS logic-based NOR gates. Although the traditional high-level active 3-8 decoder has good voltage driving capability and can effectively realize the decoding function, the on-resistance of the CMOS logic gate circuit used is large and the signal propagation path is long, resulting in a large delay and a slow decoding speed. In addition, the CMOS logic gate circuit consumes a large number of transistors, and the switching activity of the transistors is large, resulting in a large occupied area and high power consumption. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a high-level effective 3-8 decoder based on hybrid logic which has small delay, fast decoding speed, consumes fewer transistors, occupies a smaller area and has lower power consumption while effectively realizing the decoding function.

[0004] The technical solution adopted by the present invention to solve the above technical problems is: a high-level effective 3-8 decoder based on hybrid logic, including two inverters and 8 logic gate circuits, the 8 logic gate circuits are a NOR gate and 7 AND gates, the NOR gate is a NOR gate based on CMOS logic, has three input terminals and one output terminal, the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, each inverter has an input terminal and an output terminal, the two inverters are respectively referred to as the first inverter and the second inverter, the 7 AND gates are respectively referred to as the first AND gate, the second AND gate, the third AND gate, the fourth AND gate, the fifth AND gate, the sixth AND gate and the seventh AND gate, the first AND gate, the third AND gate, the fifth AND gate and the seventh AND gate The seven AND gates are all AND gates based on transmission gate logic, and the second AND gate, the fourth AND gate and the sixth AND gate are all AND gates based on transmission tube logic; the first AND gate, the third AND gate, the fifth AND gate and the seventh AND gate all have five input terminals and one output terminal, and their five input terminals are respectively referred to as their first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal, the second AND gate, the fourth AND gate and the sixth AND gate all have four input terminals and one output terminal, and their four input terminals are respectively referred to as their first input terminal, second input terminal, third input terminal and fourth input terminal, and the first input terminal of the NOR gate is connected to the first input terminal of the seven AND gates. The first input terminal of the hybrid logic-based high-level active 3-8 decoder is connected, and its connection end is the first input terminal of the hybrid logic-based high-level active 3-8 decoder, the input terminal of the first inverter, the second input terminal of the NOR gate, the fourth input terminal of the first AND gate, the second input terminal of the third AND gate, the second input terminal of the fourth AND gate, the fourth input terminal of the fifth AND gate and the second input terminal of the seventh AND gate. The second input terminal of the hybrid logic-based high-level active 3-8 decoder is connected, and its connection end is the second input terminal of the hybrid logic-based high-level active 3-8 decoder, the input terminal of the second inverter, the third input terminal of the NOR gate, the fifth input terminal of the first AND gate, the fourth input terminal of the second AND gate, the fifth input terminal of the third AND gate, the third input terminal of the fourth AND gate The first input terminal, the third input terminal of the fifth AND gate, the third input terminal of the sixth AND gate and the third input terminal of the seventh AND gate are connected, and the connection terminal is the third input terminal of the high-level effective 3-8 decoder based on hybrid logic. The first input terminal, the second input terminal and the third input terminal of the high-level effective 3-8 decoder based on hybrid logic serve as its three-bit input terminals for accessing the binary three-bit address signal ABC, wherein the first input terminal of the high-level effective 3-8 decoder based on hybrid logic is connected to the first address signal A of the three-bit address signal ABC, and the second input terminal of the high-level effective 3-8 decoder based on hybrid logic is connected to the second address signal B of the three-bit address signal ABC.The third input end of the high-level active 3-8 decoder based on hybrid logic is connected to the third address signal C of the three-bit address signal ABC, the output end of the first inverter is respectively connected to the second input end of the first AND gate, the second input end of the second AND gate, the fourth input end of the third AND gate, the second input end of the fifth AND gate, the second input end of the sixth AND gate and the fourth input end of the seventh AND gate, the output end of the second inverter is respectively connected to the third input end of the first AND gate, the third input end of the second AND gate, the third input end of the third AND gate The output end of the NOR gate, the output end of the first AND gate, the output end of the second AND gate, the output end of the third AND gate, the output end of the fourth AND gate, the output end of the fifth AND gate, the output end of the sixth AND gate and the output end of the seventh AND gate, a total of 8 output ends, serve as the 8-bit output ends of the high-level active 3-8 decoder based on the hybrid logic, and are used to output the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, wherein the output end of the NOR gate serves as the first output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the first decoded data Y0 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7; the output end of the first AND gate serves as the second output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the second decoded data Y1 of the 8-bit decoded data Y0 Y1 Y2 Y3Y4 Y5 Y6 Y7; the output end of the second AND gate serves as the third output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the third decoded data Y2 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7; the output end of the third AND gate serves as the fourth output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 The output end of the fourth AND gate serves as the fifth output end of the high-level effective type 3-8 decoder based on the hybrid logic, which is used to output the 5th decoded data Y4 of the 8-bit decoded data Y0 Y1Y2 Y3 Y4 Y5 Y6 Y7, the output end of the fifth AND gate serves as the sixth output end of the high-level effective type 3-8 decoder based on the hybrid logic, which is used to output the 6th decoded data Y5 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, the output end of the sixth AND gate serves as the seventh output end of the high-level effective type 3-8 decoder based on the hybrid logic,The output terminal of the seventh AND gate is used as the eighth output terminal of the high-level effective 3-8 decoder based on mixed logic, and is used to output the eighth-bit decoded data Y7 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7.

[0005] The AND gate based on transmission gate logic includes a first transmission gate, a second transmission gate, a first NMOS tube and a second NMOS tube. The first transmission gate includes a first PMOS tube and a third NMOS tube. The source of the first PMOS tube is connected to the drain of the third NMOS tube, and the connection end thereof is the first input end of the first transmission gate. The gate of the third NMOS tube is the second input end of the first transmission gate. The gate of the first PMOS tube is the third input end of the first transmission gate. The drain of the first PMOS tube is connected to the source of the third NMOS tube, and the connection end thereof is the output end of the first transmission gate. The second transmission gate includes a second PMOS tube and a fourth NMOS tube. The source of the second PMOS tube is connected to the drain of the fourth NMOS tube, and the connection end thereof is the first input end of the second transmission gate. The gate of the fourth NMOS tube is the second input end of the second transmission gate. The gate of the second PMOS tube is the third input end of the second transmission gate. The drain of the second PMOS tube is connected to the source of the third NMOS tube, and the connection end thereof is the output end of the first transmission gate. The source of the NMOS tube is connected, and its connection end is the output end of the second transmission gate, the first input end of the first transmission gate is the first input end of the AND gate based on the transmission gate logic, the second input end of the first transmission gate is the second input end of the AND gate based on the transmission gate logic, the third input end of the first transmission gate is connected to the gate of the second NMOS tube, and its connection end is the fourth input end of the AND gate based on the transmission gate logic, the output end of the first transmission gate is connected to the first input end of the second transmission gate, the second input end of the second transmission gate is the third input end of the AND gate based on the transmission gate logic, the third input end of the second transmission gate is connected to the gate of the first NMOS tube, and its connection end is the fifth input end of the AND gate based on the transmission gate logic, the output end of the second transmission gate, the drain of the first NMOS tube and the drain of the second NMOS tube are connected, and their connection ends serve as the output end of the AND gate based on the transmission gate logic, and the source of the first NMOS tube and the source of the second NMOS tube are both grounded GND.

[0006] The AND gate based on transmission tube logic includes a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, the source of the fourth PMOS tube is the third input terminal of the AND gate based on transmission tube logic, the drain of the fourth PMOS tube is connected to the source of the third PMOS tube, the drain of the third PMOS tube, the drain of the fifth NMOS tube, the drain of the sixth NMOS tube and the drain of the seventh NMOS tube are connected, and their connection ends are the output terminals of the AND gate based on transmission tube logic. The source of the fifth NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are all grounded GND, the gate of the third PMOS tube is connected to the gate of the seventh NMOS tube, and the connection end thereof serves as the first input end of the AND gate based on the transmission tube logic, the gate of the fourth PMOS tube is connected to the gate of the sixth NMOS tube, and the connection end thereof serves as the second input end of the AND gate based on the transmission tube logic, and the gate of the fifth NMOS tube serves as the fourth input end of the AND gate based on the transmission tube logic.

[0007] Compared with the prior art, the advantage of the present invention is that a high-level active 3-8 decoder based on hybrid logic is formed by two inverters and 8 logic gate circuits. Only two inverters are used, which reduces the number of inverters compared with the traditional high-level active 3-8 decoder. At the same time, although the number of logic gate circuits is the same as that of the traditional high-level active 3-8 decoder, which is 8, in the high-level active 3-8 decoder based on hybrid logic, 4 AND gates are based on transmission gate logic (Transmission gate logic, TGL) logic design, and 3 AND gates are based on pass transistor logic (Pass transistor logic, PTL) design. The use of PTL logic reduces the number of transistors in the logic gate circuit. The reduction in the number of transistors not only reduces the occupied area, but also reduces the logic workload and reduces the overall switching activity inside the circuit, thereby reducing power consumption. At the same time, because the reduction in the number of transistors reduces the capacitance, the use of TGL logic reduces the on-resistance of the logic gate circuit during signal transmission, thereby improving the decoding speed. Therefore, while effectively realizing the decoding function, the present invention has a small delay, a fast decoding speed, consumes fewer transistors, occupies a smaller area, and has lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A circuit diagram of a high level active 3-8 decoder based on hybrid logic of the present invention;

[0009] Figure 2A circuit diagram of an AND gate based on transmission gate logic (TGL) logic of a high level active 3-8 decoder based on hybrid logic of the present invention;

[0010] Figure 3 A circuit diagram of an AND gate based on passtransistor logic (PTL) of a high level active 3-8 decoder based on hybrid logic of the present invention;

[0011] Figure 4 It is a functional simulation waveform diagram of the high-level effective 3-8 decoder based on hybrid logic of the present invention;

[0012] Figure 5 It is a delay comparison diagram of the high-level active 3-8 decoder based on hybrid logic of the present invention and the traditional CMOS logic decoder;

[0013] Figure 6 This is a power consumption comparison diagram of the hybrid logic-based high-level active 3-8 decoder of the present invention and the traditional CMOS logic decoder. DETAILED DESCRIPTION

[0014] The present invention is further described in detail below with reference to the accompanying drawings.

[0015] Embodiment 1: Figure 1As shown, a high-level active 3-8 decoder based on hybrid logic includes two inverters and 8 logic gate circuits. The 8 logic gate circuits are a NOR gate and 7 AND gates. The NOR gate is a NOR gate based on CMOS logic, having three input terminals and an output terminal. The three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal. Each inverter has an input terminal and an output terminal. The two inverters are respectively referred to as the first inverter INV1 and the second inverter INV2. The 7 AND gates are respectively referred to as the first AND gate AND1, the second AND gate AND2, the third AND gate AND3, the fourth AND gate AND4, the fifth AND gate AND5, the sixth AND gate AND6 and the seventh AND gate AND7. The four AND gates, namely the first AND gate AND1, the third AND gate AND3, the fifth AND gate AND5 and the seventh AND gate AND7, are all AND gates based on transmission gate logic, and the three AND gates, namely the second AND gate AND2, the fourth AND gate AND4 and the sixth AND gate AND6, are all AND gates based on transmission tube logic; the first AND gate AND1, the third AND gate AND3, the fifth AND gate AND5 and the seventh AND gate AND7 each have five input terminals and one output terminal, and their five input terminals are respectively referred to as their first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal, and the second AND gate AND2, the fourth AND gate AND4 and the sixth AND gate AND6 each have four input terminals and one output terminal, and their four input terminals are respectively referred to as their first input terminal The first input end, the second input end, the third input end and the fourth input end of the NOR gate NOR are connected to the first input ends of the 7 AND gates, and the connection end thereof is the first input end of the high-level active 3-8 decoder based on the hybrid logic, the input end of the first inverter INV1, the second input end of the NOR gate NOR, the fourth input end of the first AND gate AND1, the second input end of the third AND gate AND3, the second input end of the fourth AND gate AND4, the fourth input end of the fifth AND gate AND5 and the second input end of the seventh AND gate AND7 are connected, and the connection end thereof is the second input end of the high-level active 3-8 decoder based on the hybrid logic, the input end of the second inverter INV2, the third input end of the NOR gate NOR, the first AND gate AND1 The fifth input terminal of D1, the fourth input terminal of the second AND gate AND2, the fifth input terminal of the third AND gate AND3, the third input terminal of the fourth AND gate AND4, the third input terminal of the fifth AND gate AND5, the third input terminal of the sixth AND gate AND6 and the third input terminal of the seventh AND gate AND7 are connected, and the connection terminal is the third input terminal of the high-level active 3-8 decoder based on hybrid logic, and the first input terminal, the second input terminal and the third input terminal of the high-level active 3-8 decoder based on hybrid logic are used as its three-bit input terminals for accessing the binary three-bit address signal ABC, wherein the first input terminal of the high-level active 3-8 decoder based on hybrid logic is accessed to the first address signal A of the three-bit address signal ABC,The second input terminal of the high-level active 3-8 decoder based on hybrid logic is connected to the second address signal B of the three-bit address signal ABC, the third input terminal of the high-level active 3-8 decoder based on hybrid logic is connected to the third address signal C of the three-bit address signal ABC, the output terminal of the first inverter INV1 is respectively connected to the second input terminal of the first AND gate AND1, the second input terminal of the second AND gate AND2, the fourth input terminal of the third AND gate AND3, the second input terminal of the fifth AND gate AND5, the second input terminal of the sixth AND gate AND6 and the fourth input terminal of the seventh AND gate AND7, the output terminal of the second inverter INV2 is respectively connected to the third input terminal of the first AND gate AND1, the second input terminal of the second AND gate AND2, the fourth input terminal of the third AND gate AND3, the second input terminal of the fifth AND gate AND5, the second input terminal of the sixth AND gate AND6 and the fourth input terminal of the seventh AND gate AND7. The third input terminal of ND2, the third input terminal of the third AND gate AND3, the fourth input terminal of the fourth AND gate AND4, the fifth input terminal of the fifth AND gate AND5, the fourth input terminal of the sixth AND gate AND6 and the fifth input terminal of the seventh AND gate AND7 are connected, and the output terminal of the NOR gate NOR, the output terminal of the first AND gate AND1, the output terminal of the second AND gate AND2, the output terminal of the third AND gate AND3, the output terminal of the fourth AND gate AND4, the output terminal of the fifth AND gate AND5, the output terminal of the sixth AND gate AND6 and the output terminal of the seventh AND gate AND7, a total of 8 output terminals, serve as 8-bit output terminals of the high-level active 3-8 decoder based on hybrid logic, for outputting 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, wherein the output end of the NOR gate NOR serves as the first output end of the high level effective type 3-8 decoder based on the hybrid logic, for outputting the first bit decoded data Y0 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6Y7, the output end of the first AND gate AND1 serves as the second output end of the high level effective type 3-8 decoder based on the hybrid logic, for outputting the second bit decoded data Y1 of the 8-bit decoded data Y0 Y1 Y2 Y3Y4 Y5 Y6 Y7, the output end of the second AND gate AND2 serves as the third output end of the high level effective type 3-8 decoder based on the hybrid logic, for outputting the third bit decoded data Y2 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, and the output end of the third AND gate AND3 serves as the fourth output end of the high level effective type 3-8 decoder based on the hybrid logic, for outputting the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5Y6 The output end of the fourth AND gate AND4 serves as the fifth output end of the high-level active 3-8 decoder based on hybrid logic, which is used to output the 5th decoded data Y4 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, and the output end of the fifth AND gate AND5 serves as the sixth output end of the high-level active 3-8 decoder based on hybrid logic, which is used to output the 6th decoded data Y5 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7.The output end of the sixth AND gate AND6 serves as the seventh output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the 7th decoded data Y6 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4Y5 Y6 Y7. The output end of the seventh AND gate AND7 serves as the eighth output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the 8th decoded data Y7 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7.

[0016] In this embodiment, the working principle of the high-level active 3-8 decoder based on hybrid logic is as follows: when the three-bit binary address signal ABC is input to the first input terminal, the second input terminal and the third input terminal of the high-level active 3-8 decoder based on hybrid logic, the three-bit address signal ABC is a specific 3-bit binary number, and the corresponding output terminal of the high-level active 3-8 decoder based on hybrid logic will be activated and output a high level, while the other output terminals remain in an inactive state and output a low level.

[0017] When the three-bit address signal ABC=000, the first-bit address signal A=0 is input to the first input terminal of the NOR gate NOR, the second-bit address signal B=0 is input to the second input terminal of the NOR gate NOR, and the third-bit address signal C=0 is input to the third input terminal of the NOR gate NOR. At this time, the output terminal of the NOR gate NOR outputs a valid signal "1", and the first output terminal of the high-level valid 3-8 decoder based on the mixed logic is activated to output a high level, while the other 7 output terminals of the high-level valid 3-8 decoder based on the mixed logic will remain in an inactive state and output a low level.

[0018] When the three-bit address signal ABC=100, the first-bit address signal A=1 is input to the first input terminal of the first AND gate AND1, the second-bit address signal B=0 is input to the second input terminal of the first AND gate AND1 after passing through the first inverter INV1, the third-bit address signal C=0 is input to the third input terminal of the first AND gate AND1 after passing through the second inverter INV2, the second-bit address signal B=0 is input to the fourth input terminal of the first AND gate AND1, and the third-bit address signal C=0 is input to the fifth input terminal of the first AND gate AND1. At this time, the output terminal of the first AND gate AND1 outputs a valid signal "1", and the second output terminal of the high-level valid 3-8 decoder based on the hybrid logic is activated to output a high level, while the other 7 output terminals of the high-level valid 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0019] When the three-bit address signal ABC=010, the first-bit address signal A=0 is input to the first input terminal of the second AND gate AND2, the second-bit address signal B=1 is input to the second input terminal of the second AND gate AND2 after passing through the first inverter INV1, the third-bit address signal C=0 is input to the third input terminal of the second AND gate AND2 after passing through the second inverter INV2, and the third-bit address signal C=0 is input to the fourth input terminal of the second AND gate AND2. At this time, the output terminal of the second AND gate AND2 outputs a valid signal "1", and the third output terminal of the high-level valid 3-8 decoder based on the hybrid logic is activated to output a high level, while the other 7 output terminals of the high-level valid 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0020] When the three-bit address signal ABC=110, the first-bit address signal A=1 is input to the first input terminal of the third AND gate AND3, the second-bit address signal B=1 is input to the second input terminal of the third AND gate AND3, the third-bit address signal C=0 is input to the third input terminal of the third AND gate AND3 after passing through the second inverter INV2, the second-bit address signal B=1 is input to the fourth input terminal of the third AND gate AND3 after passing through the first inverter INV1, and the third-bit address signal C=0 is input to the fifth input terminal of the third AND gate AND3. At this time, the output terminal of the third AND gate AND3 outputs a valid signal "1", and the corresponding fourth output terminal of the high-level valid 3-8 decoder based on the hybrid logic is activated to output a high level, while the other 7 output terminals of the high-level valid 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0021] When the three-bit address signal ABC=001, the first-bit address signal A=0 is input to the first input terminal of the fourth AND gate AND4, the second-bit address signal B=0 is input to the second input terminal of the fourth AND gate AND4, the third-bit address signal C=1 is input to the third input terminal of the fourth AND gate AND4, and the third-bit address signal C=1 is input to the fourth input terminal of the fourth AND gate AND4 after passing through the second inverter INV2. At this time, the output terminal of the fourth AND gate AND4 outputs a valid signal "1", and the fifth output terminal of the high-level valid 3-8 decoder based on the hybrid logic is activated to output a high level, while the other 7 output terminals of the high-level valid 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0022] When the three-bit address signal ABC=101, the first-bit address signal A=1 is input to the first input terminal of the fifth AND gate AND5, the second-bit address signal B=0 is input to the second input terminal of the fifth AND gate AND5 after passing through the first inverter INV1, the third-bit address signal C=1 is input to the third input terminal of the fifth AND gate AND5, the second-bit address signal B=0 is input to the fourth input terminal of the fifth AND gate AND5, and the third-bit address signal C=1 is input to the fifth input terminal of the fifth AND gate AND5 after passing through the second inverter INV2. At this time, the output terminal of the fifth AND gate AND5 outputs a valid signal "1", corresponding to the sixth output terminal of the high-level valid 3-8 decoder based on the hybrid logic is activated to output a high level, and the other 7 output terminals of the high-level valid 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0023] When the three-bit address signal ABC=011, the first-bit address signal A=0 is input to the first input terminal of the sixth AND gate AND6, the second-bit address signal B=1 is input to the second input terminal of the sixth AND gate AND6 after passing through the first inverter INV1, the third-bit address signal C=1 is input to the third input terminal of the sixth AND gate AND6, and the third-bit address signal C=1 is input to the fourth input terminal of the sixth AND gate AND6 after passing through the second inverter INV2. At this time, the output terminal of the sixth AND gate AND6 outputs a valid signal "1", and the seventh output terminal of the high-level valid 3-8 decoder based on the hybrid logic is activated to output a high level, while the other 7 output terminals of the high-level valid 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0024] When the three-bit address signal ABC=111, the first-bit address signal A=1 is input to the first input terminal of the seventh AND gate AND7, the second-bit address signal B=1 is input to the second input terminal of the seventh AND gate AND7, the third-bit address signal C=1 is input to the third input terminal of the seventh AND gate AND7, the second-bit address signal B=1 is input to the fourth input terminal of the seventh AND gate AND7 after passing through the first inverter INV1, and the third-bit address signal C=1 is input to the fifth input terminal of the seventh AND gate AND7 after passing through the second inverter INV2. At this time, the output terminal of the seventh AND gate AND7 outputs a valid signal "1", and the eighth output terminal of the high-level valid type 3-8 decoder based on the hybrid logic is activated to output a high level, while the other 7 output terminals of the high-level valid type 3-8 decoder based on the hybrid logic will remain in an inactive state and output a low level.

[0025] In this embodiment, the high-level active 3-8 decoder based on hybrid logic uses only two inverters, which reduces the number of inverters compared to the traditional high-level active 3-8 decoder. At the same time, although the number of logic gate circuits is the same as that of the traditional high-level active 3-8 decoder, which is 8, in the high-level active 3-8 decoder based on hybrid logic, 4 AND gates are designed based on transmission gate logic (Transmission gate logic, TGL) logic, and 3 AND gates are designed based on pass transistor logic (Pass transistor logic, PTL). The use of PTL logic reduces the number of transistors in the logic gate circuit. The reduction in the number of transistors not only reduces the occupied area, but also reduces the logic workload and reduces the overall switching activity inside the circuit, thereby reducing power consumption. At the same time, because the reduction in the number of transistors reduces the capacitance, the use of TGL logic reduces the on-resistance of the logic gate circuit during signal transmission, thereby improving the decoding speed. Therefore, while effectively realizing the decoding function, the present invention has a small delay, a fast decoding speed, consumes a small number of transistors, occupies a small area, and has low power consumption.

[0026] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 2As shown, the AND gate based on the transmission gate logic includes a first transmission gate TG1, a second transmission gate TG2, a first NMOS tube N1 and a second NMOS tube N2. The first transmission gate TG1 includes a first PMOS tube P1 and a third NMOS tube N3. The source of the first PMOS tube P1 is connected to the drain of the third NMOS tube N3, and the connection end thereof is the first input end of the first transmission gate TG1. The gate of the third NMOS tube N3 is the second input end of the first transmission gate TG1. The gate of the first PMOS tube P1 is the third input end of the first transmission gate TG1. The drain of the first PMOS tube P1 is connected to the source of the third NMOS tube N3, and the connection end thereof is the output end of the first transmission gate TG1. The second transmission gate TG2 includes the second PMOS tube P2 and the fourth NMOS tube N4. The source of the second PMOS tube P2 is connected to the drain of the fourth NMOS tube N4, and the connection end thereof is the first input end of the second transmission gate TG2. The gate of the fourth NMOS tube N4 is the second input end of the second transmission gate TG2. The gate of the second PMOS tube P2 is the third input end of the second transmission gate TG2. The drain of the PMOS tube P2 is connected to the source of the fourth NMOS tube N4, and the connection end thereof is the output end of the second transmission gate TG2. The first input end of the first transmission gate TG1 is the first input end of the AND gate based on the transmission gate logic. The second input end of the first transmission gate TG1 is the second input end of the AND gate based on the transmission gate logic. The third input end of the first transmission gate TG1 is connected to the gate of the second NMOS tube N2, and the connection end thereof is the fourth input end of the AND gate based on the transmission gate logic. The output end of the first transmission gate TG1 is connected to the first input end of the second transmission gate TG2. The input end is connected, the second input end of the second transmission gate TG2 is the third input end of the AND gate based on the transmission gate logic, the third input end of the second transmission gate TG2 is connected to the gate of the first NMOS tube N1, and its connection end is the fifth input end of the AND gate based on the transmission gate logic, the output end of the second transmission gate TG2, the drain of the first NMOS tube N1 and the drain of the second NMOS tube N2 are connected, and the connection end serves as the output end of the AND gate based on the transmission gate logic, and the source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both grounded GND.

[0027] In this embodiment, the first input terminal, the second input terminal and the third input terminal of the AND gate based on the transmission gate logic are connected to the binary three-bit address signal, and the binary three-bit address signal is represented as D1D2D3. The fourth input terminal and the fifth input terminal of the AND gate based on the transmission gate logic are connected to the inverted signal D4D5 of the binary signal D2D3, that is, The first input terminal of the AND gate based on the transmission gate logic is connected to the first address signal D1 of the three-bit address signal D1D2D3, the second input terminal of the AND gate based on the transmission gate logic is connected to the second address signal D2 of the three-bit address signal D1D2D3, the third input terminal of the AND gate based on the transmission gate logic is connected to the third address signal D3 of the three-bit address signal D1D2D3, the fourth input terminal of the AND gate based on the transmission gate logic is connected to the inverted signal D4 of D2, and the fifth input terminal of the AND gate based on the transmission gate logic is connected to the inverted signal D5 of D3.

[0028] If the three-bit address signal D3D2D1=000, D5D4=11, the first transmission gate TG1 and the second transmission gate TG2 are turned off, the first NMOS tube N1 and the second NMOS tube N2 are turned on, and GND pulls the output end of the AND gate based on the transmission gate logic to the low level "0" through the first NMOS tube N1 and the second NMOS tube N2, that is, the output data Y=0.

[0029] If the three-bit address signal D3D2D1=001, D5D4=11, the first transmission gate TG1 and the second transmission gate TG2 are turned off, the first NMOS tube N1 and the second NMOS tube N2 are turned on, and GND pulls the output end of the AND gate based on the transmission gate logic to the low level "0" through the first NMOS tube N1 and the second NMOS tube N2, that is, the output data Y=0.

[0030] If the three-bit address signal D3D2D1=010, D5D4=10, the first transmission gate TG1 is turned on, the second transmission gate TG2 is turned off, the first NMOS tube N1 is turned on, the second NMOS tube N2 is turned off, and GND pulls the output end of the AND gate based on the transmission gate logic to the low level "0" through the first NMOS tube N1, that is, the output data Y=0.

[0031] If the three-bit address signal D3D2D1=011, D5D4=10, the first transmission gate TG1 is turned on, the second transmission gate TG2 is turned off, the first NMOS tube N1 is turned on, the second NMOS tube N2 is turned off, and GND pulls the output end of the AND gate based on the transmission gate logic to the low level "0" through the first NMOS tube N1, that is, the output data Y=0.

[0032] If the three-bit address signal D3D2D1=100, D5D4=01, the first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, the first NMOS tube N1 is turned off, the second NMOS tube N2 is turned on, and GND pulls the output end of the AND gate based on the transmission gate logic to the low level "0" through the second NMOS tube N2, that is, the output data Y=0.

[0033] If the three-bit address signal D3D2D1=101, D5D4=01, the first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, the first NMOS tube N1 is turned off, the second NMOS tube N2 is turned on, and GND pulls the output end of the AND gate based on the transmission gate logic to the low level "0" through the second NMOS tube N2, that is, the output data Y=0.

[0034] If the three-bit address signal D3D2D1=110, D5D4=00, at this time, the first transmission gate TG1 is turned on and the second transmission gate TG2 is turned on, the first NMOS tube N1 is turned off and the second NMOS tube N2 is turned off, and the data "0" at the first input end of the AND gate based on the transmission gate logic passes through the first transmission gate TG1 and the second transmission gate TG2 to reach the output end of the AND gate based on the transmission gate logic to output a low level "0", that is, the output data Y=0.

[0035] If the three-bit address signal D3D2D1=111, D5D4=00, at this time, the first transmission gate TG1 is turned on and the second transmission gate TG2 is turned on, the first NMOS tube N1 is turned off and the second NMOS tube N2 is turned off, and the data "1" at the first input end of the AND gate based on the transmission gate logic passes through the first transmission gate TG1 and the second transmission gate TG2 to reach the output end of the AND gate based on the transmission gate logic to output a low level "1", that is, the output data Y=1.

[0036] Embodiment 3: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 3 As shown, the AND gate based on the transmission tube logic includes a third PMOS tube P3, a fourth PMOS tube P4, a fifth NMOS tube N5, a sixth NMOS tube N6 and a seventh NMOS tube N7, the source of the fourth PMOS tube P4 is the third input terminal of the AND gate based on the transmission tube logic, the drain of the fourth PMOS tube P4 is connected to the source of the third PMOS tube P3, the drain of the third PMOS tube P3, the drain of the fifth NMOS tube N5, the drain of the sixth NMOS tube N6 and the drain of the seventh NMOS tube N7 are connected, and the connection ends are based on the transmission tube logic. The source of the fifth NMOS tube N5, the source of the sixth NMOS tube N6 and the source of the seventh NMOS tube N7 are all grounded GND, the gate of the third PMOS tube P3 is connected to the gate of the seventh NMOS tube N7, and the connecting end thereof serves as the first input end of the AND gate based on the transmission tube logic, the gate of the fourth PMOS tube P4 is connected to the gate of the sixth NMOS tube N6, and the connecting end thereof serves as the second input end of the AND gate based on the transmission tube logic, and the gate of the fifth NMOS tube N5 serves as the fourth input end of the AND gate based on the transmission tube logic.

[0037] In this embodiment, the first input terminal, the second input terminal and the third input terminal of the AND gate based on the transmission tube logic are used to access the binary three-bit address signal, and the binary three-bit address signal is represented as D1D2D3. The fourth input terminal of the AND gate based on the transmission tube logic is used to access the inverted signal D4 of the binary signal D3, that is, The first input terminal of the AND gate based on the transmission tube logic is connected to the first address signal D1 of the three-bit address signal D1D2D3, the second input terminal of the AND gate based on the transmission tube logic is connected to the second address signal D2 of the three-bit address signal D1D2D3, the third input terminal of the AND gate based on the transmission tube logic is connected to the third address signal D3 of the three-bit address signal D1D2D3, and the fourth input terminal of the AND gate based on the transmission tube logic is connected to the inverted signal D4 of D3.

[0038] If the three-bit address signal D3D2D1=000, D4=1, at this time, the third PMOS tube P3 and the fourth PMOS tube P4 are turned on, the fifth NMOS tube N5 is turned on, the sixth NMOS tube N6 and the seventh NMOS tube N7 are turned off, and the data "0" at the third input end of the AND gate based on the transmission tube logic passes through the third PMOS tube P3 and the fourth PMOS tube P4 to reach the output end of the AND gate based on the transmission tube logic. At the same time, GND pulls the output end of the AND gate based on the transmission tube logic to the low level "0" through the fifth NMOS tube N5, that is, the output data Y=0.

[0039] If the three-bit address signal D3D2D1=001, D4=1, the third PMOS tube P3 is turned off, the fourth PMOS tube P4 is turned on, the fifth NMOS tube N5 is turned on, the sixth NMOS tube N6 and the seventh NMOS tube N7 are turned off, and GND pulls the output end of the AND gate of the transmission tube logic to the low level "0" through the fifth NMOS tube N5, that is, the output data Y=0.

[0040] If the three-bit address signal D3D2D1=010, D4=1, the third PMOS tube P3 is turned on, the fourth PMOS tube P4 is turned off, the fifth NMOS tube N5 and the sixth NMOS tube N6 are turned on, and the seventh NMOS tube N7 is turned off. GND pulls the output end of the AND gate of the transmission tube logic to the low level "0" through the fifth NMOS tube N5 and the sixth NMOS tube N6, that is, the output data Y=0.

[0041] If the three-bit address signal D3D2D1=011, D4=1, the third PMOS tube P3 and the fourth PMOS tube P4 are turned off, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 are turned on, and GND pulls the output end of the AND gate of the transmission tube logic to the low level "0" through the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7, that is, the output data Y=0.

[0042] If the three-bit address signal D3D2D1=100, D4=0, the third PMOS tube P3 and the fourth PMOS tube P4 are turned on, the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 are turned off, and the data "1" at the third input end of the AND gate based on the transmission tube logic passes through the third PMOS tube P3 and the fourth PMOS tube P4 to reach the output end of the AND gate based on the transmission tube logic, that is, the output data Y=1.

[0043] If the three-bit address signal D3D2D1=101, D4=0, the third PMOS tube P3 is turned off, the fourth PMOS tube P4 is turned on, the fifth NMOS tube N5 and the sixth NMOS tube N6 are turned off, and the seventh NMOS tube N7 is turned on. GND pulls the output end of the AND gate based on the transmission tube logic to the low level "0" through the seventh NMOS tube N7, that is, the output data Y=0.

[0044] If the three-bit address signal D3D2D1=110, D4=0, the third PMOS tube P3 is turned on, the fourth PMOS tube P4 is turned off, the fifth NMOS tube N5 and the seventh NMOS tube N7 are turned off, and the sixth NMOS tube N6 is turned on. GND pulls the output end of the AND gate of the transmission tube logic to the low level "0" through the sixth NMOS tube N6, that is, the output data Y=0.

[0045] If the three-bit address signal D3D2D1=111, D4=0, the third PMOS tube P3 and the fourth PMOS tube P4 are turned off, the fifth NMOS tube N5 is turned off, the sixth NMOS tube N6 and the seventh NMOS tube N7 are turned on, and GND pulls the output end of the AND gate based on the transmission tube logic to the low level "0" through the sixth NMOS tube N6 and the seventh NMOS tube N7, that is, the output data Y=0.

[0046] Under the standard voltage of 0.75V of TSMC 7nm process, Spectre is used to perform functional simulation on the active high 3-8 decoder based on hybrid logic of the present invention, as shown in FIG. Figure 4 Analysis Figure 4 It can be seen that the high-level effective 3-8 decoder based on hybrid logic of the present invention can realize an effective high-level decoding function and has correct functional logic.

[0047] In order to verify the performance of the active high 3-8 decoder based on hybrid logic of the present invention, the active high 3-8 decoder based on hybrid logic of the present invention is compared with two existing decoders based on CMOS logic in terms of delay and power consumption. The delay comparison diagram of the active high 3-8 decoder based on hybrid logic of the present invention and the existing CMOS logic decoder is shown in FIG. Figure 5As shown; the power consumption comparison diagram of the high level active 3-8 decoder based on hybrid logic of the present invention and the existing CMOS logic decoder is as shown Figure 6 shown. Figure 5 and Figure 6 In the figure, CMOS represents the traditional 54-tube CMOS logic high-level effective 3-8 decoder disclosed in "Digital Integrated Circuits - Circuits, Systems and Design", CMOSI represents the traditional 54-tube CMOS logic low-level effective 3-8 decoder disclosed in "Digital Integrated Circuits - Circuits, Systems and Design", and HPLP represents the high-level effective 3-8 decoder based on hybrid logic of the present invention. Figure 5 It can be clearly seen that under three different voltages of 0.6V, 0.75V and 0.9V, the high-level active 3-8 decoder based on hybrid logic of the present invention has a smaller delay. Figure 6 It can be clearly seen that under three different voltages of 0.6V, 0.75V and 0.9V, the high-level effective 3-8 decoder based on hybrid logic of the present invention has lower power consumption.

[0048] In summary, the present invention can effectively realize the decoding function while having a small delay, a fast decoding speed, and consumes fewer transistors, occupies a smaller area, and has lower power consumption.

Claims

1. A high level active 3-8 decoder based on hybrid logic, characterized in that The invention comprises two inverters and eight logic gate circuits, wherein the eight logic gate circuits are one NOR gate and seven AND gates, wherein the NOR gate is an NOR gate based on CMOS logic, and has three input terminals and one output terminal, wherein the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, each inverter has an input terminal and an output terminal, the two inverters are respectively referred to as the first inverter and the second inverter, the seven AND gates are respectively referred to as the first AND gate, the second AND gate, the third AND gate, the fourth AND gate, the fifth AND gate, the sixth AND gate and the seventh AND gate, wherein the first AND gate, the third AND gate, the fifth AND gate and the seventh AND gate are all AND gates based on transmission gate logic, the second AND gate, The fourth AND gate and the sixth AND gate are AND gates based on transmission tube logic; the first AND gate, the third AND gate, the fifth AND gate and the seventh AND gate all have five input terminals and one output terminal, and their five input terminals are respectively referred to as their first input terminal, second input terminal, third input terminal, fourth input terminal and fifth input terminal; the second AND gate, the fourth AND gate and the sixth AND gate all have four input terminals and one output terminal, and their four input terminals are respectively referred to as their first input terminal, second input terminal, third input terminal and fourth input terminal; the first input terminal of the NOR gate is connected to the first input terminals of the seven AND gates, and its connection terminal is the high-voltage mixed logic-based gate. The first input end of the high level effective type 3-8 decoder, the input end of the first inverter, the second input end of the NOR gate, the fourth input end of the first AND gate, the second input end of the third AND gate, the second input end of the fourth AND gate, the fourth input end of the fifth AND gate and the second input end of the seventh AND gate are connected, and the connection end is the second input end of the high level effective type 3-8 decoder based on mixed logic, the input end of the second inverter, the third input end of the NOR gate, the fifth input end of the first AND gate, the fourth input end of the second AND gate, the fifth input end of the third AND gate, the third input end of the fourth AND gate, the fifth input end of the The third input terminal, the third input terminal of the sixth AND gate and the third input terminal of the seventh AND gate are connected, and the connection terminal is the third input terminal of the high-level effective 3-8 decoder based on hybrid logic. The first input terminal, the second input terminal and the third input terminal of the high-level effective 3-8 decoder based on hybrid logic serve as its three-bit input terminals for accessing the binary three-bit address signal ABC, wherein the first input terminal of the high-level effective 3-8 decoder based on hybrid logic accesses the first address signal A of the three-bit address signal ABC, and the second input terminal of the high-level effective 3-8 decoder based on hybrid logic accesses the second address signal B of the three-bit address signal ABC.The third input end of the high-level active 3-8 decoder based on hybrid logic is connected to the third address signal C of the three-bit address signal ABC, the output end of the first inverter is respectively connected to the second input end of the first AND gate, the second input end of the second AND gate, the fourth input end of the third AND gate, the second input end of the fifth AND gate, the second input end of the sixth AND gate and the fourth input end of the seventh AND gate, the output end of the second inverter is respectively connected to the third input end of the first AND gate, the third input end of the second AND gate, the third input end of the third AND gate The output end of the NOR gate, the output end of the first AND gate, the output end of the second AND gate, the output end of the third AND gate, the output end of the fourth AND gate, the output end of the fifth AND gate, the output end of the sixth AND gate and the output end of the seventh AND gate, a total of 8 output ends, serve as the 8-bit output ends of the high-level active 3-8 decoder based on the hybrid logic, and are used to output the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, wherein the output end of the NOR gate serves as the first output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the first decoded data Y0 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7; the output end of the first AND gate serves as the second output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the second decoded data Y1 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7; the output end of the second AND gate serves as the third output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the third decoded data Y2 of the 8-bit decoded data Y0 Y1 Y2Y3 Y4 Y5 Y6 Y7; the output end of the third AND gate serves as the fourth output end of the high-level active 3-8 decoder based on hybrid logic, and is used to output the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 The output end of the fourth AND gate serves as the fifth output end of the high-level effective type 3-8 decoder based on the hybrid logic, which is used to output the 5th decoded data Y4 of the 8-bit decoded data Y0Y1 Y2 Y3 Y4 Y5 Y6 Y7, the output end of the fifth AND gate serves as the sixth output end of the high-level effective type 3-8 decoder based on the hybrid logic, which is used to output the 6th decoded data Y5 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7, the output end of the sixth AND gate serves as the seventh output end of the high-level effective type 3-8 decoder based on the hybrid logic,The output terminal of the seventh AND gate is used as the eighth output terminal of the high-level effective 3-8 decoder based on mixed logic, and is used to output the eighth-bit decoded data Y7 of the 8-bit decoded data Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7.

2. The high level active 3-8 decoder based on hybrid logic according to claim 1, characterized in that The AND gate based on transmission gate logic includes a first transmission gate, a second transmission gate, a first NMOS tube and a second NMOS tube. The first transmission gate includes a first PMOS tube and a third NMOS tube. The source of the first PMOS tube is connected to the drain of the third NMOS tube, and the connection end thereof is the first input end of the first transmission gate. The gate of the third NMOS tube is the second input end of the first transmission gate. The gate of the first PMOS tube is the third input end of the first transmission gate. The drain of the first PMOS tube is connected to the source of the third NMOS tube, and the connection end thereof is the output end of the first transmission gate. The second transmission gate includes a second PMOS tube and a fourth NMOS tube. The source of the second PMOS tube is connected to the drain of the fourth NMOS tube, and the connection end thereof is the first input end of the second transmission gate. The gate of the fourth NMOS tube is the second input end of the second transmission gate. The gate of the second PMOS tube is the third input end of the second transmission gate. The drain of the second PMOS tube is connected to the source of the third NMOS tube, and the connection end thereof is the output end of the first transmission gate. The source of the NMOS tube is connected, and its connection end is the output end of the second transmission gate, the first input end of the first transmission gate is the first input end of the AND gate based on the transmission gate logic, the second input end of the first transmission gate is the second input end of the AND gate based on the transmission gate logic, the third input end of the first transmission gate is connected to the gate of the second NMOS tube, and its connection end is the fourth input end of the AND gate based on the transmission gate logic, the output end of the first transmission gate is connected to the first input end of the second transmission gate, the second input end of the second transmission gate is the third input end of the AND gate based on the transmission gate logic, the third input end of the second transmission gate is connected to the gate of the first NMOS tube, and its connection end is the fifth input end of the AND gate based on the transmission gate logic, the output end of the second transmission gate, the drain of the first NMOS tube and the drain of the second NMOS tube are connected, and their connection ends serve as the output end of the AND gate based on the transmission gate logic, and the source of the first NMOS tube and the source of the second NMOS tube are both grounded GND.

3. The high level active 3-8 decoder based on hybrid logic according to claim 1, characterized in that The AND gate based on transmission tube logic includes a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, the source of the fourth PMOS tube is the third input terminal of the AND gate based on transmission tube logic, the drain of the fourth PMOS tube is connected to the source of the third PMOS tube, the drain of the third PMOS tube, the drain of the fifth NMOS tube, the drain of the sixth NMOS tube and the drain of the seventh NMOS tube are connected, and their connection ends are the output terminals of the AND gate based on transmission tube logic. The source of the fifth NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are all grounded GND, the gate of the third PMOS tube is connected to the gate of the seventh NMOS tube, and the connection end thereof serves as the first input end of the AND gate based on the transmission tube logic, the gate of the fourth PMOS tube is connected to the gate of the sixth NMOS tube, and the connection end thereof serves as the second input end of the AND gate based on the transmission tube logic, and the gate of the fifth NMOS tube serves as the fourth input end of the AND gate based on the transmission tube logic.

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