Electric leakage adjusting circuit and adjusting method of delay phase-locked loop

Abstract

The invention relates to an electric leakage adjusting circuit and method of a delay phase-locked loop, and the electric leakage adjusting circuit is used for adjusting the subthreshold electric leakage power consumption of the delay phase-locked loop during an aging test, and comprises an operational amplifier module, a window comparison module and an adjusting module. The operational amplifier module is configured to output a first voltage value based on the sub-threshold leakage current of the delay-locked loop; the window comparison module is configured to output a comparison result based on the first voltage value; the adjustment module is configured to provide a substrate bias voltage to the delay-locked loop based on the comparison result. When an aging test is carried out, the electric leakage adjusting circuit can be used for adjusting the sub-threshold electric leakage power consumption of the delay phase-locked loop, and the inaccuracy of an aging test result and the increase of test cost caused by the increase of the sub-threshold electric leakage power consumption are prevented.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing, and in particular to a leakage adjustment circuit and an adjustment method for a delay locked loop. Background Art

[0002] Aging test is an important part of the chip production process for potential failure analysis. It usually requires accelerated aging of the chip in a high-temperature environment, so that the defects of the chip are exposed in advance during the aging test stage. The chip generally includes a delay locked loop (DLL) and a dynamic random access memory (DRAM). The DLL is the source synchronous clock generation module of the DRAM, which is used for signal delay compensation and clock adjustment. However, during the aging test, the power consumption caused by the subthreshold leakage in the delay locked loop in the low-frequency switching mode increases, resulting in inaccurate aging test results and increased testing costs. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a leakage adjustment circuit and an adjustment method for a delay locked loop.

[0004] According to some embodiments, the leakage adjustment circuit provided in the first aspect of the embodiment of the present disclosure is used to adjust the subthreshold leakage power consumption of a delay phase-locked loop during an aging test, and the leakage adjustment circuit includes:

[0005] An operational amplifier module, wherein a first input terminal of the operational amplifier module is connected to the delay locked loop, a second input terminal of the operational amplifier module is connected to a first common ground terminal, and the operational amplifier module is configured to output a first voltage value based on a subthreshold leakage current of the delay locked loop;

[0006] a window comparison module, wherein an input terminal of the window comparison module is connected to an output terminal of the operational amplifier module, and the window comparison module is configured to output a comparison result based on the first voltage value;

[0007] An adjustment module is connected to the output end of the window comparison module and the delay locked loop respectively, and the adjustment module is configured to provide a bias voltage to the delay locked loop based on the comparison result.

[0008] In some embodiments of the present disclosure, the window comparison module includes a plurality of window comparators arranged in an array, each of the window comparators has a continuous threshold level range, and the input end of each of the window comparators is connected to the output end of the operational amplifier module.

[0009] In some embodiments of the present disclosure, the window comparator includes a first operational amplifier and a first diode connected in series, and a second operational amplifier and a second diode connected in series, the first input terminal of the first operational amplifier is connected to a first reference voltage, the second input terminal of the second operational amplifier is connected to a second reference voltage, the second input terminal of the first operational amplifier is connected to the first input terminal of the second operational amplifier as the input terminal of the window comparator, and the first diode is connected to the second diode as the output terminal of the window comparator;

[0010] The multiple window comparators are configured such that when the first voltage value falls within the threshold level range of one of the window comparators, the output end of the window comparator outputs a second voltage value, and the output ends of the remaining window comparators output a third voltage value, and the third voltage value is different from the second voltage value.

[0011] In some embodiments of the present disclosure, the adjustment module includes:

[0012] A voltage dividing circuit, the voltage dividing circuit comprising a plurality of voltage dividing resistors connected in series, with a voltage dividing point between each two adjacent voltage dividing resistors;

[0013] A plurality of switch transistors, each of the switch transistors corresponds to a voltage dividing point, a gate of each of the switch transistors is connected to an output end of a corresponding window comparator, a source of each of the switch transistors is connected to a corresponding voltage dividing point, and a drain of each of the switch transistors is connected to a substrate of the delay locked loop; or, a drain of each of the switch transistors is connected to a corresponding voltage dividing point, and a source of each of the switch transistors is connected to the substrate of the delay locked loop.

[0014] In some embodiments of the present disclosure, the adjustment range of the voltage divider circuit is -0.7 to -0.1V.

[0015] In some embodiments of the present disclosure, the delay locked loop includes a plurality of complementary metal oxide semiconductor (CMOS) inverters connected in series in sequence, the CMOS inverter includes a substrate and an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS) disposed on the substrate, the gate of the NMOS and the gate of the PMOS serve as input terminals of the CMOS inverter, and the drain of the NMOS and the drain of the PMOS serve as output terminals of the CMOS inverter;

[0016] The source of the PMOS is connected to the power supply terminal, the source of the NMOS is connected to the first input terminal of the operational amplifier module, and the source of the NMOS is connected to the second common ground terminal through an interconnection resistor.

[0017] In some embodiments of the present disclosure, the leakage regulation circuit further includes an access transistor, which is disposed between the operational amplifier module and the delay locked loop, and the access transistor is configured to be turned on when an aging test is performed.

[0018] According to some embodiments, a leakage adjustment method for a delay locked loop provided in the second aspect of the embodiments of the present disclosure is implemented by a leakage adjustment circuit as described in the first aspect, wherein the leakage adjustment circuit includes an operational amplifier module, a window comparison module, and an adjustment module, and the leakage adjustment method includes:

[0019] The operational amplifier module outputs a first voltage value based on the subthreshold leakage current of the delay locked loop;

[0020] The window comparison module outputs a comparison result based on the first voltage value;

[0021] The adjustment module provides a bias voltage to the delay locked loop based on the comparison result.

[0022] In some embodiments of the present disclosure, the window comparison module includes a plurality of window comparators arranged in an array, and the step of the window comparison module outputting a comparison result based on the first voltage value includes:

[0023] Inputting the first voltage value to the input terminal of each of the window comparators;

[0024] When the first voltage value falls within the threshold level range of one of the window comparators, the output end of the window comparator outputs a second voltage value, and the output ends of the remaining window comparators output a third voltage value.

[0025] In some embodiments of the present disclosure, the adjustment module includes a voltage divider circuit and a plurality of switching transistors, the voltage divider circuit includes a plurality of voltage divider resistors connected in series, a voltage divider point is provided between each two adjacent voltage divider resistors, and each of the voltage divider points is connected to an output end of a corresponding window comparator through a switching transistor;

[0026] The step of the adjustment module providing a bias voltage to the delay locked loop based on the comparison result includes:

[0027] Inputting the second voltage value or the third voltage value output by each of the window comparators into the gates of the plurality of switch transistors, so that the switch transistors having the second voltage value input to the gates are turned on;

[0028] Through the turned-on switch transistor, the voltage at the voltage dividing point connected thereto is applied to the delay locked loop as a bias voltage.

[0029] In some embodiments of the present disclosure, the delay locked loop includes a CMOS inverter;

[0030] Before the operational amplifier module outputs a first voltage value based on the subthreshold leakage current of the delay locked loop, the leakage adjustment method further includes:

[0031] A fourth voltage value is input to the input terminal of the CMOS inverter, so that the NMOS in the CMOS inverter generates a subthreshold leakage current.

[0032] The disclosed embodiment has at least the following beneficial effects: through the connection between the operational amplifier module, the window comparison module and the adjustment module in the leakage regulation circuit, the first voltage value can be output, the comparison result can be output and the corresponding bias voltage can be provided to the delay locked loop based on the subthreshold leakage current of the delay locked loop, so as to achieve the regulation and control of the subthreshold leakage power consumption of the delay locked loop during the aging test, and prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption. In addition, the operational amplifier module is selected to be connected with the delay locked loop, and the voltage of the second input terminal of the operational amplifier module is stabilized by the characteristic that the input terminal of the operational amplifier module is not affected by temperature, so that the first voltage value corresponding to the subthreshold leakage current can be output more accurately during the aging test, thereby improving the stability and accuracy of the leakage regulation.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0035] Figure 1 The figure is a schematic diagram of a leakage regulation circuit and a delay locked loop according to an exemplary embodiment of the present disclosure.

[0036] Figure 2 The circuit structure diagram of an operational amplifier module is shown as an exemplary embodiment of the present disclosure.

[0037] Figure 3 The figure is a schematic diagram of an operational amplifier module according to an exemplary embodiment of the present disclosure.

[0038] Figure 4 This is a schematic diagram of input and output voltages of a window comparator according to an exemplary embodiment of the present disclosure.

[0039] Figure 5 The circuit structure diagram of a window comparator is shown as an exemplary embodiment of the present disclosure.

[0040] Figure 6 It is a circuit structure diagram of an adjustment module, a window comparison module and a delay locked loop according to an exemplary embodiment of the present disclosure.

[0041] Figure 7 The diagram is a schematic diagram of a CMOS inverter and a leakage adjustment circuit according to an exemplary embodiment of the present disclosure.

[0042] Figure 8 The diagram is a schematic diagram of interconnect resistance in a local semiconductor structure of a chip according to an exemplary embodiment of the present disclosure.

[0043] Fig. 9 The present invention is a flowchart of a leakage current regulation method according to an exemplary embodiment of the present invention.

[0044] Description of reference numerals:

[0045] 10-delay phase-locked loop; 20-operational amplifier module;

[0046] 30-window comparison module; 40-adjustment module;

[0047] 41-voltage dividing resistor; 42-voltage dividing point;

[0048] 43-switching transistor; 50-CMOS inverter;

[0049] 61-a second common ground terminal; 62-a power supply terminal;

[0050] 70-interconnection resistor; 80-access transistor;

[0051] 91-first op amp; 92-second op amp;

[0052] 93-a first diode; 94-a second diode;

[0053] 100-substrate; M1-metal layer;

[0054] C1, CD-contact plug. DETAILED DESCRIPTION

[0055] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0056] In the related art, aging test is an important part of the potential failure analysis of products in the chip production process. It is usually necessary to accelerate the aging of the chip in a high-temperature environment, so that the defects of the chip are exposed in advance during the aging test stage. The chip generally includes a delay locked loop (DLL) and a dynamic random access memory (DRAM). The delay locked loop is a source synchronous clock generation module of the dynamic random access memory, which is used for signal delay compensation and clock adjustment. It is an important part of the clock control of the dynamic random access memory. At the aging test site, the delay locked loop is actually an idle module, but in order to protect the delay locked loop from the negative bias temperature instability (NBTI) effect, it is necessary to keep the delay locked loop signal switched (toggle DLL).

[0057] However, due to the limitation of the machine, the switching frequency of the delay locked loop during the aging test is low, and the automatic refresh frequency is usually used as the switching signal frequency. In the low-frequency switching mode, the power consumption generated by the subthreshold leakage in the delay locked loop is significant and changes exponentially with temperature, resulting in inaccurate aging test results and increased testing costs.

[0058] Based on this, the exemplary embodiment of the present disclosure provides a leakage regulation circuit of a delay locked loop. Through the connection between the operational amplifier module, the window comparison module and the adjustment module in the leakage regulation circuit, the first voltage value can be output, the comparison result can be output and the corresponding bias voltage can be provided to the delay locked loop based on the subthreshold leakage current of the delay locked loop, so as to achieve the regulation and control of the subthreshold leakage power consumption of the delay locked loop during the aging test, and prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption. In addition, the operational amplifier module is selected to be connected to the delay locked loop, and the voltage of the second input terminal of the operational amplifier module is stable through the characteristic that the input terminal of the operational amplifier module is not affected by temperature, so that the first voltage value corresponding to the subthreshold leakage current can be output more accurately during the aging test, thereby improving the stability and accuracy of the leakage regulation.

[0059] In an exemplary embodiment, Figure 1As shown, the leakage regulation circuit provided by the embodiment of the present disclosure is used to regulate the subthreshold leakage power consumption of the delay locked loop 10 during the aging test. The leakage regulation circuit includes an operational amplifier module 20, a window comparison module 30 and an adjustment module 40. The first input end of the operational amplifier module 20 is connected to the delay locked loop 10, and the second input end of the operational amplifier module 20 is connected to the first common ground end. The operational amplifier module 20 is configured to output a first voltage value based on the subthreshold leakage current of the delay locked loop 10; the input end of the window comparison module 30 is connected to the output end of the operational amplifier module 20, and the window comparison module 30 is configured to output a comparison result based on the first voltage value; the adjustment module 40 is respectively connected to the output end of the window comparison module 30 and the delay locked loop 10, and the adjustment module 40 is configured to provide a bias voltage to the delay locked loop 10 based on the comparison result.

[0060] The specific circuit structure of the operational amplifier module is, for example, Figure 2 As shown in the figure, PCS and NCS represent process control system and network control system respectively, operational amplifier module 20 is an amplifying circuit capable of performing mathematical operations on signals, BL and BL / are input terminals of the operational amplifier module, usually one of BL and BL / is a ground terminal, and the other is a power supply terminal. Its input terminal is usually a gate, and because the gate is a special tunneling mechanism rather than a thermal activation mechanism, its input terminal is not sensitive to temperature changes, and can maintain the voltage at the ground voltage (VSS) when connected to the ground terminal.

[0061] Operational amplifier module 20 Figure 3 As shown, the first input terminal and the second input terminal are provided, wherein the first input terminal is, for example, a "-" input terminal, and the second input terminal is, for example, a "+" input terminal. The operational amplifier module 20 calculates the difference between the voltage values ​​input from the second input terminal and the voltage values ​​input from the first input terminal, and multiplies the difference by a preset amplification factor, and outputs the calculation result V from the output terminal. out =(R2 / R1)(V2-V1). The operational amplifier module 20 can make a difference between the voltage value at the second input terminal connected to the first common ground terminal and the voltage value at the first input terminal connected to the delay locked loop 10, and multiply the difference by a preset amplification factor to obtain a first voltage value. The voltage value at the first input terminal of the operational amplifier module 20 corresponds to the subthreshold leakage current of the delay locked loop 10.

[0062] The output end of the operational amplifier module 20 is connected to the input end of the window comparison module 30, that is, the first voltage value output by the output end of the operational amplifier module 20 is input to the input end of the window comparison module 30. The window comparison module 30 compares the threshold level range of the window comparator therein with the input first voltage value, and outputs different comparison results according to the size of the first voltage value.

[0063] The output end of the window comparison module 30 is connected to the adjustment module 40, that is, the comparison result output by the output end of the window comparison module 30 is input to the input end of the adjustment module 40. The adjustment module 40 is also connected to the delay locked loop 10. The adjustment module 40 can provide the delay locked loop 10 with a bias voltage corresponding to different comparison results according to the input comparison result. When the bias voltage is applied to the delay locked loop 10, it can reduce or eliminate the subthreshold leakage current in the delay locked loop 10, thereby realizing the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10.

[0064] In this embodiment, by setting the operational amplifier module 20, the window comparison module 30 and the adjustment module 40 in the leakage regulation circuit, the first voltage value can be outputted, the comparison result can be outputted and the corresponding bias voltage can be provided to the delay locked loop 10 based on the subthreshold leakage current of the delay locked loop 10, so as to realize the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10 during the aging test, and prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption. In addition, the operational amplifier module 20 is selected to be connected to the delay locked loop 10, and the voltage of the second input terminal is stabilized by the characteristic that the input terminal of the operational amplifier module 20 is not affected by temperature, so that the first voltage value corresponding to the subthreshold leakage current can be outputted more accurately during the aging test, and the stability and accuracy of the leakage regulation are improved.

[0065] In some embodiments, the window comparison module 30 includes a plurality of window comparators arranged in an array, each window comparator has a continuous threshold level range, and an input terminal of each window comparator is connected to an output terminal of the operational amplifier module 20 .

[0066] The window comparison module 30 includes a plurality of window comparators arranged in an array, such as Figure 4 As shown in the figure, u i Indicates the voltage value of the input window comparator, u o Represents the voltage value output by the window comparator. Each window comparator has two threshold levels U RL and U RH The input end of each window comparator is connected to the output end of the operational amplifier module 20, so that the first voltage value outputted from the output end of the operational amplifier module 20 is inputted into each window comparator, and each window comparator can detect whether the input first voltage value is within the range between two threshold levels, and output different comparison results according to whether the first voltage value is within the range between the two threshold levels.

[0067] The threshold level range of each window comparator is set to be continuous, that is, the U RL with U RHThe threshold level ranges determined are continuous with each other. In addition to the window comparator with minimum and maximum threshold level ranges, when the threshold level range of a window comparator is U RL ~U RH When there is a window comparator with a threshold level range smaller than U RL ~U RH And the larger threshold level of the window comparator is RL equal, and there is a window comparator with a threshold level range greater than U RL ~U RH And the smaller threshold level of the window comparator is RH equal.

[0068] In this embodiment, by setting a plurality of window comparators in the window comparison module 30, a comparison result can be output according to the first voltage value input from the output end of the operational amplifier module 20 to the input end of each window comparator, and the comparison result can indicate whether the first voltage value is within the threshold level range of each window comparator. By setting the threshold level range of each window comparator to be continuous, the first voltage value can be within the threshold level range of only one window comparator, so that the comparison results output by the window comparator and other window comparators are different, and different comparison results are output according to the size of the first voltage value, providing a basis for the subsequent determination of the bias voltage, and realizing the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10 during the aging test, so as to prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption.

[0069] In some embodiments, the window comparator includes a first operational amplifier 91 and a first diode 93 connected in series and a second operational amplifier 92 and a second diode 94 connected in series, the first input terminal of the first operational amplifier 91 is connected to a first reference voltage, the second input terminal of the second operational amplifier 92 is connected to a second reference voltage, the second input terminal of the first operational amplifier 91 is connected to the first input terminal of the second operational amplifier 92 as the input terminal of the window comparator, and the first diode 93 and the second diode 94 are connected as the output terminal of the window comparator; the multiple window comparators are configured such that when the first voltage value falls within the threshold level range of a window comparator among the multiple window comparators, the output terminal of the window comparator outputs the second voltage value, and the output terminals of the remaining window comparators output a third voltage value, and the third voltage value is different from the second voltage value.

[0070] The internal circuit structure of the window comparator is as follows: Figure 5 As shown in the figure, u i and u oThe window comparator comprises a first operational amplifier 91 and a first diode 93 connected in series, and a second operational amplifier 92 and a second diode 94 connected in series. The first input terminal of the first operational amplifier 91, i.e., the “+” input terminal, is connected to a first reference voltage U RL The second input terminal of the second operational amplifier 92, i.e., the “-” input terminal, is connected to the second reference voltage U RH The second input terminal of the first operational amplifier 91, i.e., the "-" input terminal, is connected to the first input terminal of the second operational amplifier 92, i.e., the "+" input terminal, as the input terminal of the window comparator. The first voltage value is input into each window comparator from the input terminal. The first diode 93 and the second diode 94 are connected as the output terminal of the window comparator to output the comparison result.

[0071] Each window comparator is set up in a circuit structure and has a continuous threshold level range of each window comparator, so that when a first voltage value falls within the threshold level range of a certain window comparator, the output end of the window comparator outputs a second voltage value, and the remaining window comparators all output a third voltage value different from the second voltage value because the first voltage value does not fall within the threshold level range of each window comparator. Exemplarily, the second voltage value is a low level and the third voltage value is a high level.

[0072] In this embodiment, by setting the first operational amplifier 91, the second operational amplifier 92, the first diode 93 and the second diode 94 in the window comparator, each window comparator can determine whether the first voltage value inputted at the input end is within the threshold level range formed by the first reference voltage and the second reference voltage, and make the window comparator whose first voltage value falls within the threshold level range output the second voltage value, and make the remaining window comparators whose first voltage values ​​do not fall within the threshold level range all output the third voltage value, so that when the first voltage value changes and is within the threshold level range of different window comparators, the window comparator that outputs the second voltage value also changes accordingly, so that the window comparison module 30 outputs different comparison results based on the size of the first voltage value, provides a basis for the subsequent determination of the bias voltage, and realizes the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10 during the aging test, so as to prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption.

[0073] In some embodiments, the adjustment module 40 includes: a voltage divider circuit and multiple switching transistors 43, the voltage divider circuit includes multiple voltage divider resistors 41 connected in series in sequence, and there is a voltage divider point 42 between each two adjacent voltage divider resistors 41; each switching transistor 43 corresponds to a voltage divider point 42, the gate of each switching transistor 43 is connected to the output end of a corresponding window comparator, the source of each switching transistor 43 is connected to a corresponding voltage divider point 42, and the drain of each switching transistor 43 is connected to the substrate 100 of the delay locked loop 10; or, the drain of each switching transistor 43 is connected to a corresponding voltage divider point 42, and the source of each switching transistor 43 is connected to the substrate 100 of the delay locked loop 10.

[0074] Adjustment module 40 as Figure 6 As shown, the adjustment module 40 includes a voltage divider circuit, which includes a plurality of voltage divider resistors 41 connected in series in sequence. The number of the voltage divider resistors 41 is greater than the number of window comparators in the window comparison module 30. There is a voltage divider point 42 between each two adjacent voltage divider resistors 41. The voltage at each voltage divider point 42 varies according to the position of the voltage divider point 42. The resistance values ​​of the voltage divider resistors 41 may be the same or different. When the resistance values ​​of the voltage divider resistors 41 are the same, the voltage difference between the adjacent voltage divider points 42 is the same. When the resistance values ​​of the voltage divider resistors 41 are different, the voltage difference between the adjacent voltage divider points 42 is different.

[0075] Each voltage dividing point 42 corresponds to a switch-on transistor. In some embodiments, the gate of each switch transistor 43 is connected to the output end of a corresponding window comparator to receive the comparison result output by each window comparator, i.e., the second voltage value or the third voltage value. The source of each switch transistor 43 is connected to a corresponding voltage dividing point 42, and the drain is connected to the substrate 100 of the delay locked loop 10, so that when the switch transistor 43 is turned on, the voltage at the corresponding voltage dividing point 42 can be applied to the substrate 100 of the delay locked loop 10 as a bias voltage, so as to reduce or eliminate the subthreshold leakage current in the delay locked loop 10, thereby realizing the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10.

[0076] In other embodiments, the gate of each switching transistor 43 is also connected to the output end of a corresponding window comparator to receive the comparison result output by each window comparator, i.e., the second voltage value or the third voltage value. The drain of each switching transistor is connected to the corresponding first voltage dividing point 42, and the source is connected to the substrate 100 of the delay locked loop 10, so that when the switching transistor 43 is turned on, the voltage at the corresponding voltage dividing point 42 can be applied to the substrate 100 of the delay locked loop 10 as a bias voltage, so as to reduce or eliminate the subthreshold leakage current in the delay locked loop 10, thereby realizing the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10.

[0077] It should be noted that when the second voltage value is a low level and the third voltage value is a high level, each switching transistor 43 should be turned on when a low level voltage is input to the gate and not turned on when a high level voltage is input to the gate, that is, the switching transistor 43 in this case should be a P-type transistor.

[0078] In this embodiment, by setting the voltage-dividing resistor 41 and the voltage-dividing point 42 connected in series in the voltage-dividing circuit, different voltage values ​​can be provided at each voltage-dividing point 42, which is a prerequisite for realizing that the adjustment module 40 applies different substrate bias voltages to the substrate 100 of the delay-locked loop 10 under different comparison results input by the window comparison module 30. By setting the switch transistor 43, and the connection relationship between the gate, source, and drain of the switch transistor 43 and the output terminals of each window comparator, the voltage dividing point 42, and the substrate 100 of the delay locked loop 10, the switch transistor 43 corresponding to the window comparator that outputs the second voltage value can be turned on according to the comparison result output by the output terminal of the window comparator, and then the voltage at the voltage dividing point 42 corresponding to the switch transistor 43 is applied to the substrate 100 of the delay locked loop 10, so that the entire leakage adjustment circuit can provide the corresponding bias voltage to the final delay locked loop 10 according to the initial subthreshold leakage current of the delay locked loop 10, and the subthreshold leakage power consumption of the delay locked loop 10 is regulated and controlled during the aging test, so as to prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption.

[0079] In some embodiments, the adjustment range of the voltage divider circuit is -0.7 to -0.1V.

[0080] like Figure 6 As shown, the two ends of the voltage divider circuit have two different voltage values ​​as the lower limit and upper limit of the adjustment range of the voltage divider circuit, the voltage value of one end is -0.7V, and the voltage value of the other end is -0.1V. Then, the voltage values ​​at each voltage dividing point 42 in the voltage divider circuit are all within the range of -0.7 to -0.1V, so that the substrate bias voltage applied to the substrate 100 of the delay locked loop 10 after a switch transistor 43 is turned on is also within the range of -0.7 to -0.1V.

[0081] In this embodiment, by setting the adjustment range of the voltage divider circuit to -0.7 to -0.1V, the voltage value at each voltage dividing point 42 in the voltage divider circuit, i.e., the bias voltage applied to the substrate 100 of the delay locked loop 10 after a switch transistor 43 is turned on, is also within the range of -0.7 to -0.1V, thereby limiting the bias voltage applied to the substrate 100 of the delay locked loop 10, ensuring that the bias voltage can reduce or eliminate the subthreshold leakage current in the delay locked loop 10, and preventing the bias voltage from being too large to affect the opening and closing speed of the dynamic random access memory, thereby interfering with the normal operation of the dynamic random access memory.

[0082] In some embodiments, the delay locked loop 10 includes a plurality of complementary metal oxide semiconductor (CMOS) inverters 50 connected in series in sequence, the CMOS inverter 50 includes a substrate 100 and an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS) disposed on the substrate 100, the gate of the NMOS and the gate of the PMOS serve as input terminals of the CMOS inverter 50, the drain of the NMOS and the drain of the PMOS serve as output terminals of the CMOS inverter 50; the source of the PMOS is connected to the power supply terminal 62, the source of the NMOS is connected to the first input terminal of the operational amplifier module 20, and the source of the NMOS is connected to the second common ground terminal 61 through an interconnect resistor 70.

[0083] like Figure 1 As shown, the delay locked loop 10 includes a plurality of complementary metal oxide semiconductor (CMOS) inverters 50 connected in series in sequence. The number of the CMOS inverters 50 is, for example, 2, 3, ..., N, where N is a positive integer greater than 3. The plurality of CMOS inverters connected in series form a part of the delay locked loop 10.

[0084] like Figure 7 As shown, S, D, and G in the figure represent the source, drain, and gate in NMOS or CMOS, respectively, and the arrow represents the flow direction of the subthreshold leakage current in NMOS. The CMOS inverter 50 includes a substrate 100 and an N-type metal oxide semiconductor NMOS and a P-type metal oxide semiconductor PMOS arranged on the substrate 100. The gate of the NMOS and the gate of the PMOS serve as the input terminal of the CMOS inverter 50, and the drain of the NMOS and the drain of the PMOS serve as the output terminal of the CMOS inverter 50. The source of the PMOS is connected to the power supply terminal 62, and the voltage value is the working voltage (VDD). The source of the NMOS is connected to the first input terminal of the operational amplifier module 20, and the source of the NMOS is connected to the second common ground terminal 61 through the interconnection resistor 70, and the voltage value is the ground voltage (VSS). The PMOS power supply terminal 62 and the second common ground terminal 61 refer to the leads that the chip directly contacts with the tester when performing the aging test, for example, the metal layer (M4) located at the top in the semiconductor structure of the chip.

[0085] The semiconductor local structure of the chip is as follows Figure 8 As shown, M1 represents a metal layer, and C1 and CD represent contact plugs. The interconnect resistor 70 may be a contact plug C1 and CD connecting the NMOS source of the COMS inverter with the upper metal layer in the semiconductor structure of the chip. The contact plug can realize the electrical connection between the NMOS source and the second common ground terminal 61, and the contact plug has a certain resistance value.

[0086] When a low-level voltage is applied to the input terminal of the COMS inverter, the PMOS is turned on and a subthreshold leakage current is generated in the NMOS channel. The subthreshold leakage current flows from the drain of the NMOS to the source and flows to the interconnection resistor 70, so that the voltage at the interconnection resistor 70 changes, and then the voltage at the source of the NMOS changes. The source of the NMOS is also connected to the first input terminal of the operational amplifier module 20. When the voltage at the source of the NMOS changes due to the subthreshold leakage current, the voltage input to the first input terminal of the operational amplifier module 20 changes accordingly, so that the voltages of the first input terminal and the second input terminal of the operational amplifier module 20 are different, and the corresponding first voltage value can be output after the operational amplification calculation.

[0087] In the present embodiment, a subthreshold leakage current is generated in the NMOS in the CMOS inverter 50. Due to the setting of the interconnect resistor 70, a voltage change can occur at the source of the NMOS corresponding to the subthreshold leakage current, so that the voltage of the second input terminal of the operational amplifier module 20, which is also connected to the source of the NMOS, changes, and then the operational amplifier module 20 outputs a first voltage value when the voltages at the first input terminal and the second input terminal are different, thereby realizing that the operational amplifier module 20 outputs a corresponding first voltage value based on the subthreshold leakage current, which is a prerequisite for the subsequent window comparison module 30 to output a comparison result according to the first voltage value, and can regulate and control the subthreshold leakage power consumption of the delay locked loop 10 during the aging test, thereby preventing inaccurate aging test results and increased testing costs caused by an increase in subthreshold leakage power consumption. In addition, the second input terminal of the operational amplifier module 20 is connected to the first common ground terminal. The voltage of the second input terminal is stabilized by the characteristic that the input terminal of the operational amplifier module 20 is not affected by temperature, and the voltage value of the first input terminal of the operational amplifier module 20 is used to represent the size of the subthreshold leakage current. During the aging test, the first voltage value corresponding to the subthreshold leakage current can be output more accurately, thereby improving the stability and accuracy of the leakage regulation.

[0088] It can be understood that the present embodiment is a circuit connection relationship when detecting the subthreshold leakage current generated in NMOS as an example. The leakage adjustment circuit can also be applied to detect the subthreshold leakage current generated in PMOS and perform corresponding adjustment control. When detecting and adjusting the subthreshold leakage current generated in PMOS, it is only necessary to change the voltage passed into the input terminal of the CMOS inverter 50 to a high level and change the first input terminal of the operational amplifier module 20 to be connected to the source of the PMOS.

[0089] In some embodiments, the leakage regulation circuit further includes an access transistor 80 , which is disposed between the operational amplifier module 20 and the delay locked loop 10 , and the access transistor 80 is configured to be turned on when an aging test is performed.

[0090] like Figure 1 As shown, the leakage regulation circuit also includes an access transistor 80, which is arranged between the operational amplifier module 20 and the delay locked loop 10, and the source and drain of the access transistor 80 are respectively connected to the source of the NMOS in the CMOS inverter 50 and the first input terminal of the operational amplifier module 20.

[0091] When performing an aging test, a voltage is applied to the gate of the access transistor 80, so that the access transistor 80 is turned on and the entire leakage adjustment circuit is activated, that is, the leakage adjustment circuit is only in a connected and conductive state with the delay locked loop 10 when performing an aging test, and is disconnected and cut off with the delay locked loop 10 when not performing an aging test.

[0092] In this embodiment, an access transistor 80 is provided between the operational amplifier module 20 and the delay locked loop 10, and the access transistor 80 is turned on only when the aging test is performed, so that the leakage regulation circuit is connected to the delay locked loop 10 only when the aging test is performed, thereby realizing that the leakage regulation circuit regulates and controls the subthreshold leakage power consumption of the delay locked loop 10 only when the aging test is performed, that is, the delay locked loop 10 is in a low-frequency switching state, thereby preventing the regulation effect of the leakage regulation circuit from affecting the opening and closing speed of the dynamic random access memory when the aging test is not performed, that is, the delay locked loop 10 is in a normal working state, thereby preventing interference with the reading and writing process of the dynamic random access memory.

[0093] In an exemplary embodiment, the leakage adjustment method provided by the embodiment of the present disclosure is implemented by the leakage adjustment circuit as described above. Figure 1 As shown, it includes an operational amplifier module 20, a window comparison module 30 and an adjustment module 40, and the leakage adjustment method is as follows Fig. 9 As shown, including:

[0094] S100, the operational amplifier module outputs a first voltage value based on the subthreshold leakage current of the delay locked loop;

[0095] S200, the window comparison module outputs a comparison result based on the first voltage value;

[0096] S300: The adjustment module provides a bias voltage to the delay locked loop based on the comparison result.

[0097] In step S100, since the signal switching frequency of the delay locked loop 10 is low during the aging test, the power consumption generated by the subthreshold leakage current in the delay locked loop 10 is significant. Exemplarily, the first input terminal of the operational amplifier module 20 having the function of performing mathematical operation amplification on the signal is connected to the delay locked loop 10, and the second input terminal of the operational amplifier module 20 is connected to the first common ground terminal. The voltage value at the second input terminal connected to the first common ground terminal of the operational amplifier module 20 is subtracted from the voltage value at the first input terminal connected to the delay locked loop 10, and the first voltage value is obtained after multiplying the difference with the preset amplification factor. The obtained first voltage value can characterize the magnitude of the subthreshold leakage current in the delay locked loop 10.

[0098] In step S200, illustratively, the output end of the operational amplifier module 20 is connected to the input end of the window comparison module 30, that is, the first voltage value output by the output end of the operational amplifier module 20 is input to the input end of the window comparison module 30, and the window comparison module 30 compares the threshold level range of the window comparator therein with the input first voltage value, and outputs different comparison results according to the size of the first voltage value.

[0099] In step S300, exemplarily, the output end of the window comparison module 30 is connected to the adjustment module 40, that is, the comparison result output by the output end of the window comparison module 30 is input to the input end of the adjustment module 40, and the adjustment module 40 is also connected to the delay locked loop 10. The adjustment module 40 can provide the delay locked loop 10 with a bias voltage corresponding to different comparison results according to the input comparison result. When the bias voltage is applied to the delay locked loop 10, it can reduce or eliminate the subthreshold leakage current in the delay locked loop 10, thereby realizing the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10.

[0100] In this embodiment, the operational amplifier module 20 first outputs a first voltage value based on the subthreshold leakage current of the delay locked loop 10, and then the window comparison module 30 outputs a comparison result based on the first voltage value, and finally the adjustment module 40 provides a bias voltage to the delay locked loop 10 based on the comparison result, so that the leakage adjustment method can provide a corresponding bias voltage to the delay locked loop 10 based on the initial subthreshold leakage current to reduce or eliminate the subthreshold leakage current in the delay locked loop 10, thereby realizing the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10 during the aging test, and preventing the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption.

[0101] In some embodiments, the window comparison module 30 includes a plurality of window comparators arranged in an array, and the step of the window comparator module outputting a comparison result based on the first voltage value includes:

[0102] S210, inputting a first voltage value to an input terminal of each window comparator;

[0103] S220: When the first voltage value falls within a threshold level range of one window comparator among the multiple window comparators, the output end of the window comparator outputs a second voltage value, and the output ends of the remaining window comparators output a third voltage value.

[0104] In step S210, illustratively, the input end of each window comparator is connected to the output end of the operational amplifier module 20, and the first voltage value outputted from the output end of the operational amplifier module 20 is inputted into each window comparator. The circuit structure of each window comparator is as follows: Figure 5 As shown, the window comparator can detect whether the input first voltage value is within the range between two threshold levels, and output different comparison results according to whether the first voltage value is within the range between the two threshold levels.

[0105] In step S220, illustratively, the threshold level range of each window comparator is set to be continuous, and each window comparator can output the second voltage value when the first voltage value is within the range between the two threshold levels, and output the third voltage value when the first voltage value is outside the range between the two threshold levels. The first voltage value can only fall within the threshold level range of one of the window comparators, so that only one window comparator can output the second voltage value, and the remaining window comparators all output the third voltage value, and the second voltage value and the third voltage value output by each window comparator are used as the comparison result output by the window comparison module 30.

[0106] In this embodiment, the first voltage value output by the operational amplifier module 20 is first input into the input end of each window comparator in the window comparison module 30, and then each window comparator outputs a second voltage value and a third voltage value according to the size of the first voltage value. The output second voltage value and the third voltage value are the comparison results finally output by the window comparison module 30. The change of the window comparator that outputs the second voltage value represents different comparison results, and different comparison results are output according to the size of the first voltage value, which provides a basis for the subsequent determination of the bias voltage, and realizes the regulation and control of the subthreshold leakage power consumption of the delay locked loop 10 during the aging test, so as to prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption.

[0107] In some embodiments, the adjustment module 40 is as follows Figure 6 As shown, the voltage divider circuit includes a voltage divider circuit and a plurality of switch transistors 43, the voltage divider circuit includes a plurality of voltage divider resistors 41 connected in series, a voltage divider point 42 is provided between each two adjacent voltage divider resistors 41, and each voltage divider point 42 is connected to an output end of a corresponding window comparator through a switch transistor 43; the adjustment module 40 provides a bias voltage to the delay locked loop 10 based on the comparison result, including:

[0108] S310, inputting the second voltage value or the third voltage value output by each window comparator into the gates of a plurality of switch transistors, so that the switch transistors having the second voltage value input to the gates are turned on;

[0109] S320 , applying the voltage at the voltage dividing point connected to the turned-on switch transistor as a bias voltage to the delay locked loop.

[0110] In step S310, illustratively, the adjustment module 40 Figure 6 As shown, each voltage dividing point 42 corresponds to a switch transistor, and the gate of each switch transistor 43 is connected to the output end of a corresponding window comparator to receive the comparison result output by each window comparator, that is, the second voltage value or the third voltage value. The source and drain of each switch transistor 43 are respectively connected to a corresponding voltage dividing point 42 and the substrate 100 of the delay locked loop 10. The second voltage value or the third voltage value output by each window comparator is input to the gates of multiple switch transistors 43, so that the switch transistors 43 with the second voltage value input to the gate are turned on. Since only one window comparator among the window comparators outputs the second voltage value as the comparison result, only the switch transistor 43 corresponding to the window comparator among the switch transistors 43 is turned on, and the other switch transistors 43 are not turned on.

[0111] In step S320, exemplarily, the source and drain of the turned-on switching transistor 43 are respectively connected to the voltage dividing point 42 corresponding to the switching transistor 43 and the delay locked loop 10, and the corresponding voltage dividing point 42 has a voltage corresponding to the position of the voltage dividing point 42 in the voltage dividing circuit. After the switching transistor 43 is turned on, the voltage at the voltage dividing point 42 is applied to the delay locked loop 10 through the turned-on switching transistor 43 as a bias voltage to reduce or eliminate the subthreshold leakage current in the delay locked loop 10, thereby achieving regulation and control of the subthreshold leakage power consumption of the delay locked loop 10.

[0112] In this embodiment, the second voltage value or the third voltage value output by each window comparator is first input into the gate of multiple switch transistors 43, so that the switch transistors 43 whose gates are input with the second voltage value are turned on, and then the voltage at the voltage dividing point 42 connected thereto is applied to the delay locked loop 10 as the bias voltage through the turned-on switch transistors 43, so that the adjustment module 40 can provide the corresponding bias voltage to the delay locked loop 10 based on the comparison result. The complete leakage adjustment method can provide the corresponding bias voltage to the final delay locked loop 10 according to the subthreshold leakage current of the initial delay locked loop 10, so that the subthreshold leakage power consumption of the delay locked loop 10 is regulated and controlled during the aging test, so as to prevent the inaccurate aging test results and the increase of the test cost caused by the increase of the subthreshold leakage power consumption.

[0113] In some embodiments, the delay locked loop 10 is as follows Figure 1 The CMOS inverter 50 is shown; the operational amplifier module 20 outputs the first voltage value based on the subthreshold leakage current of the delay locked loop 10, and the leakage adjustment method also includes:

[0114] S400 , inputting a fourth voltage value to the input terminal of the CMOS inverter, so that the NMOS in the CMOS inverter generates a subthreshold leakage current.

[0115] In step S400, illustratively, Figure 7 As shown, the CMOS inverter 50 includes a substrate 100 and an N-type metal oxide semiconductor NMOS and a P-type metal oxide semiconductor PMOS arranged on the substrate 100. When a low-level voltage is applied to the input end of the inverter, the PMOS can be turned on and a subthreshold leakage current can be generated in the NMOS channel. Therefore, a fourth voltage value is input to the input end of the CMOS inverter 50, so that the NMOS in the CMOS inverter 50 generates a subthreshold leakage current.

[0116] The subthreshold leakage current flows from the drain of the NMOS to the source and flows to the interconnect resistor 70, causing the voltage at the interconnect resistor 70 to change, thereby causing the voltage at the source of the NMOS to change. The source of the NMOS is also connected to the first input terminal of the operational amplifier module 20. When the voltage at the source of the NMOS changes due to the subthreshold leakage current, the voltage input to the first input terminal of the operational amplifier module 20 changes accordingly, making the voltages at the first input terminal and the second input terminal of the operational amplifier module 20 different, and the corresponding first voltage value can be output after the operational amplification calculation.

[0117] In this embodiment, before the operational amplifier module 20 outputs the first voltage value based on the subthreshold leakage current of the delay locked loop 10, the fourth voltage value is first input to the input terminal of the CMOS inverter 50, so that the NMOS in the CMOS inverter 50 generates a subthreshold leakage current, which is a prerequisite for the operational amplifier module 20 to output the first voltage value based on the subthreshold leakage current of the delay locked loop 10. By inputting the low-level fourth voltage value to the input terminal of the CMOS inverter 50, the voltage at the source of the NMOS can be changed, and the voltage of the first input terminal of the operational amplifier module 20 is changed, so that the voltage of the first input terminal and the second input terminal of the operational amplifier module 20 are different, and the corresponding first voltage value is output after operational amplification.

[0118] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the present disclosure. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0119] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A leakage regulation circuit for a delay locked loop, characterized in that: The leakage regulating circuit is used to regulate the subthreshold leakage power consumption of the delay phase-locked loop during the aging test, and the leakage regulating circuit includes: An operational amplifier module, wherein a first input terminal of the operational amplifier module is connected to the delay locked loop, a second input terminal of the operational amplifier module is connected to a first common ground terminal, and the operational amplifier module is configured to output a first voltage value based on a subthreshold leakage current of the delay locked loop; a window comparison module, wherein an input terminal of the window comparison module is connected to an output terminal of the operational amplifier module, and the window comparison module is configured to output a comparison result based on the first voltage value; An adjustment module is connected to the output end of the window comparison module and the delay locked loop respectively, and the adjustment module is configured to provide a bias voltage to the delay locked loop based on the comparison result.

2. The leakage regulating circuit according to claim 1, characterized in that: The window comparison module includes a plurality of window comparators arranged in an array, each of the window comparators has a continuous threshold level range, and the input end of each of the window comparators is connected to the output end of the operational amplifier module.

3. The leakage regulating circuit according to claim 2, characterized in that: The window comparator comprises a first operational amplifier and a first diode connected in series, and a second operational amplifier and a second diode connected in series, the first input terminal of the first operational amplifier is connected to a first reference voltage, the second input terminal of the second operational amplifier is connected to a second reference voltage, the second input terminal of the first operational amplifier is connected to the first input terminal of the second operational amplifier as the input terminal of the window comparator, and the first diode is connected to the second diode as the output terminal of the window comparator; The multiple window comparators are configured such that when the first voltage value falls within the threshold level range of one of the window comparators, the output end of the window comparator outputs a second voltage value, and the output ends of the remaining window comparators output a third voltage value, and the third voltage value is different from the second voltage value.

4. The leakage regulating circuit according to claim 3, characterized in that: The adjustment module comprises: A voltage dividing circuit, the voltage dividing circuit comprising a plurality of voltage dividing resistors connected in series, with a voltage dividing point between each two adjacent voltage dividing resistors; A plurality of switch transistors, each of the switch transistors corresponds to a voltage dividing point, a gate of each of the switch transistors is connected to an output end of a corresponding window comparator, a source of each of the switch transistors is connected to a corresponding voltage dividing point, and a drain of each of the switch transistors is connected to a substrate of the delay locked loop; or, a drain of each of the switch transistors is connected to a corresponding voltage dividing point, and a source of each of the switch transistors is connected to the substrate of the delay locked loop.

5. The leakage regulating circuit according to claim 4, characterized in that: The adjustment range of the voltage divider circuit is -0.7 to -0.1V.

6. The leakage regulating circuit according to claim 1, characterized in that: The delay locked loop comprises a plurality of complementary metal oxide semiconductor (CMOS) inverters connected in series in sequence, wherein the CMOS inverter comprises a substrate and an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS) arranged on the substrate, wherein the gate of the NMOS and the gate of the PMOS serve as input terminals of the CMOS inverter, and the drain of the NMOS and the drain of the PMOS serve as output terminals of the CMOS inverter; The source of the PMOS is connected to the power supply terminal, the source of the NMOS is connected to the first input terminal of the operational amplifier module, and the source of the NMOS is connected to the second common ground terminal through an interconnection resistor.

7. The leakage regulating circuit according to any one of claims 1 to 6, characterized in that: The leakage regulating circuit further includes an access transistor, which is arranged between the operational amplifier module and the delay locked loop, and is configured to be turned on when an aging test is performed.

8. A method for regulating leakage of a delay-locked loop, characterized in that: The leakage adjustment method is implemented by the leakage adjustment circuit according to any one of claims 1 to 7, wherein the leakage adjustment circuit comprises an operational amplifier module, a window comparison module and an adjustment module, and the leakage adjustment method comprises: The operational amplifier module outputs a first voltage value based on the subthreshold leakage current of the delay locked loop; The window comparison module outputs a comparison result based on the first voltage value; The adjustment module provides a bias voltage to the delay locked loop based on the comparison result.

9. The leakage current adjustment method according to claim 8, characterized in that: The window comparison module includes a plurality of window comparators arranged in an array, and the step of the window comparison module outputting a comparison result based on the first voltage value includes: Inputting the first voltage value to the input terminal of each of the window comparators; When the first voltage value falls within the threshold level range of one of the window comparators, the output end of the window comparator outputs a second voltage value, and the output ends of the remaining window comparators output a third voltage value.

10. The leakage current adjustment method according to claim 9, characterized in that: The adjustment module includes a voltage divider circuit and a plurality of switch transistors, wherein the voltage divider circuit includes a plurality of voltage divider resistors connected in series in sequence, a voltage divider point is provided between each two adjacent voltage divider resistors, and each of the voltage divider points is connected to an output end of a corresponding window comparator through a switch transistor; The step of the adjustment module providing a bias voltage to the delay locked loop based on the comparison result includes: Inputting the second voltage value or the third voltage value output by each of the window comparators into the gates of the plurality of switch transistors, so that the switch transistors having the second voltage value input to the gates are turned on; Through the turned-on switch transistor, the voltage at the voltage dividing point connected thereto is applied to the delay locked loop as a bias voltage.

11. The leakage current adjustment method according to claim 8, characterized in that: The delay locked loop includes a CMOS inverter; Before the operational amplifier module outputs a first voltage value based on the subthreshold leakage current of the delay locked loop, the leakage adjustment method further includes: A fourth voltage value is input to the input terminal of the CMOS inverter, so that the NMOS in the CMOS inverter generates a subthreshold leakage current.

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