Sampling error code correction method, sampling error code correction device and time-to-digital converter with sampling error code correction device

Abstract

The invention relates to a sampling error code correction method, a sampling error code correction device and a time-to-digital converter with the sampling error code correction device. The method comprises the following steps: receiving a sampling code of a trigger; a verification bit is added to each of the first bit and the last bit of the sampling code; whether the first bit and the last bit of the sampling code are correct or not is judged according to the phase relation between the two verification bits and the first bit and the last bit of the sampling code; and when the first bit and the last bit of the sampling code are correct, filtering the sampling code, correcting an error code according to a preset correction logic, and inputting a correction result into a decoder. According to the method, before a sampling code is input into a decoder, error code processing is carried out, a verification bit is additionally arranged at each of the first bit and the last bit of the sampling code to verify whether the last bit and the first bit of the sampling code are correct or not, and after it is confirmed that the first bit and the last bit of the sampling code are correct, other sampling codes are detected and corrected. Therefore, the problem of signal error codes caused by inconsistent signal delay is solved.

Description

Technical Field

[0001] The present invention and the field of time measurement technology particularly relate to a sampling error correction method and device and a time-to-digital converter with the same. Background Art

[0002] TDC (Time to digital converter) is mainly used for ultra-short time interval measurement, which requires a time resolution of nanoseconds (ns) or even picoseconds (ps). It is widely used in medical imaging, lidar, fluorescence spectroscopy, industrial density / thickness testing and other fields.

[0003] At present, the commonly used TDC structure includes a delay loop composed of a set of inverters / buffers (including 2N-stage delay units R 0 ,R 1 ,R 2 …R 2N-1 ), N-level signal sampling trigger (J 0 ,J 1 ,J 2 …J N-1 ) and an N-bit decoder. Figure 1 As shown, generally speaking, for a 2N-stage delay unit chain, only any N bits of adjacent phase information need to be sampled to calculate a complete 2N time state. Figure 2 The results of a 32-stage linear delay unit are shown. Only the bold box (R 7 ,R 8 ,R 9 …R 22 ) A total of 16 phase states can calculate the corresponding 32 time states. After the TDC time recording starts, first, at the rising edge of the start (Start) signal, the trigger samples the N-level signal states of the delay loop respectively. After the required measurement time interval, at the rising edge of the end (End) signal, the trigger samples the N-level signal states of the delay loop respectively. The two sampling codes are decoded by the decoder and subtracted, which is the delay time required to be tested between Start and End. In theory, it is required that the sampling value of each trigger has no bit errors, and the same transmission path is maintained before the signal is transmitted into the decoder, so as not to introduce ranging errors.

[0004] However, in actual circuits, due to layout routing, parasitics and other issues, the delay time of each delay loop phase signal transmitted to the sampling circuit is not the same, and due to the influence of PVT (Process, Voltage, Temperature), the threshold of each signal buffer and the sampling speed of the trigger are also different. The above problems will give the signal group (J) entering the trigger different 0 ,J 1 ,J2 …J N-1 ) will generate bit errors. Especially for devices with high time resolution requirements, if these bit errors are not processed, they will be directly input into the decoder, causing serious ranging errors.

[0005] At present, the solutions to existing problems mainly include the following:

[0006] 1. According to the error bubble characteristics of Johnson Code, add corresponding detection circuits, such as searching for data arrangements with characteristics such as (101, 1001, 10001, 010, 0110, 01110), and modify the calculation results accordingly (+1, +2, +3, -1, -2, -3...). The circuit implementation of this solution is relatively complex. For each additional error detection type, the corresponding circuit channel needs to be added, and the implementation cost is relatively high;

[0007] 2. For the same set of Johnson codes, change the weights and perform two calculations, then perform an average or other weighted algorithm. This method assumes that errors in positions other than the weights will have little impact on the final calculation results, so after changing the weights and performing two calculations, there will always be one calculation result that is closest to the true value. This solution has a low hardware cost and relies on an algorithm to solve the problem, but it can only reduce errors and cannot avoid bit errors;

[0008] 3. Take samples multiple times at fixed intervals. Compare the results of multiple samples to eliminate bit errors. Although this solution can perfectly solve the problem of bit errors, it requires adding multiple sets of sampling circuits, the amount of data increases many times, and the area and power consumption of the circuit also increase proportionally. Summary of the invention

[0009] In view of this, the present application proposes a sampling error correction method, device and a time-to-digital converter with the same.

[0010] In one aspect, the present application provides a sampling error correction method, comprising the following steps:

[0011] A sampling code of a receiving trigger is received; and a verification bit is added to the first bit and the last bit of the sampling code respectively;

[0012] Determine whether the first and last bits of the sampling code are correct by using the phase relationship between the two verification bits and the first and last bits of the sampling code respectively;

[0013] When the first bit and the last bit of the sampling code are correct, the sampling code is filtered, and the error code is corrected according to a preset correction logic, and the correction result is input into the decoder.

[0014] As an optional implementation scheme of the present application, optionally, the preset correction logic includes:

[0015] Determine whether the first digit of the sampling code is 0 or 1;

[0016] If the first digit of the sampling code is 0, determining whether there is a falling edge in the remaining sampling codes, and correcting the determined falling edge;

[0017] If the first digit of the sampling code is 1, it is determined whether there is a rising edge in the remaining sampling codes, and the determined rising edge is corrected.

[0018] As an optional implementation scheme of the present application, optionally, the determining whether the first bit and the last bit of the sampling code are correct by respectively using the phase relationship between the two verification bits and the first bit and the last bit of the sampling code includes:

[0019] Determining whether the last bit of the sampling code is correct according to whether the phase relationship between the verification bit added relative to the first bit of the sampling code and the last bit of the sampling code is opposite;

[0020] Whether the first bit of the sampling code is correct is determined based on whether the phase relationship between the verification bit added relative to the last bit of the sampling code and the first bit of the sampling code is opposite.

[0021] As an optional implementation scheme of the present application, optionally, judging whether the last bit of the sampling code is correct according to whether the phase relationship between the verification bit added relative to the first bit of the sampling code and the last bit of the sampling code is opposite includes:

[0022] If the phase relationship is opposite, the last bit of the sampling code is correct;

[0023] If the phase relationship is not opposite, the last bit of the sampling code is wrong and an error result is output.

[0024] As an optional implementation scheme of the present application, optionally, judging whether the first bit of the sampling code is correct according to whether the phase relationship between the verification bit added relative to the last bit of the sampling code and the first bit of the sampling code is opposite includes:

[0025] If the phase relationship is opposite, the first bit of the sampling code is correct;

[0026] If the phase relationship is not opposite, the first bit of the sampling code is wrong, and an error result is output.

[0027] In another aspect, the present application provides a sampling error correction device, which is used to implement any of the above sampling error correction methods, including:

[0028] A sampling code receiving module is configured to receive a sampling code of a trigger; and a verification bit is added to the first bit and the last bit of the sampling code respectively;

[0029] A sampling code judgment module is configured to judge whether the first bit and the last bit of the sampling code are correct by using the phase relationship between the two verification bits and the first bit and the last bit of the sampling code respectively;

[0030] The sampling code correction module is configured to filter the sampling code when the first bit and the last bit of the sampling code are correct, correct the error code according to the preset correction logic, and input the correction result into the decoder.

[0031] In another aspect, the present application provides a time-to-digital converter, comprising:

[0032] Delay unit;

[0033] A trigger connected to the delay unit and sampling the signal state of the delay unit to obtain a sampling code;

[0034] The sampling error correction device is connected to the trigger, receives the sampling code of the trigger, and performs error correction on the sampling code to obtain a correction result;

[0035] The decoder is connected to the sampling error correction device, receives the correction result, and calculates the delay time according to the correction result.

[0036] Technical effects of the present invention:

[0037] 1. The present application provides a sampling error correction method, which specifically includes: receiving a sampling code of a trigger; and adding a verification bit to the first and last bits of the sampling code respectively; using the phase relationship between the two verification bits and the first and last bits of the sampling code to determine whether the first and last bits of the sampling code are correct; when the first and last bits of the sampling code are correct, filtering the sampling code, and correcting the error according to a preset correction logic, and inputting the correction result into a decoder. The method of the present application performs error processing before inputting the sampling code into the decoder, and adds a verification bit to the first and last bits of the sampling code to verify whether the last bit and the first bit of the sampling code are correct, and after confirming that the first and last bits of the sampling code are correct, other sampling codes are detected and corrected, thereby solving the signal error problem caused by inconsistent signal delays. And the method of the present application can detect and correct multiple discontinuous errors in a single call, and can detect and correct continuous errors in multiple calls.

[0038] 2. The time-to-digital converter provided by the present application adds a sampling error correction device between the trigger and the decoder, so that the signal is first error-processed by the sampling error correction device before entering the decoder, thereby effectively solving the signal error problem caused by inconsistent signal delays in existing time-to-digital converters, and can improve the time resolution of the time-to-digital converter at a lower power consumption and area cost.

[0039] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0041] Figure 1 It is shown as a schematic diagram of the TDC structure;

[0042] Figure 2 Shown is a state cycle table of 32-order phase delay varying with time and a time result line graph based on 16-bit phase array calculation;

[0043] Figure 3 The figure shows a flow chart of a sampling error correction method according to an embodiment of the present application;

[0044] Figure 4 The following is an implementation flow of the sampling error correction method according to an embodiment of the present application and the corresponding example RTL code;

[0045] Figure 5 The state cycle table of the 18-bit array changing with time and the state cycle table after non-continuous bit error correction are shown in the embodiment of the present application;

[0046] Figure 6 A comparison diagram showing the time result of calculating the original data of non-continuous bit errors and the time result of calculating the data after correction once in an embodiment of the present application is shown;

[0047] Figure 7 The state cycle table of the 18-bit array according to the embodiment of the present application that changes with time and the state cycle table after three consecutive bit error corrections are shown;

[0048] Figure 8 A comparison diagram showing the time result of calculating the original data of continuous bit errors and the time result of calculating the data after correction three times according to an embodiment of the present application is shown;

[0049] Fig. 9 FIG. 4 is a schematic diagram of the structure of a time-to-digital converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0051] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0052] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0053] like Figure 3 As shown, on one hand, the present application proposes a sampling error correction method, comprising the following steps:

[0054] S100, receiving a sampling code of a trigger; and adding a verification bit to the first and last bits of the sampling code respectively;

[0055] In this step, you first need to receive the trigger sampling code (J 0 J 1 ,J 2 …J N+1 ), where N+2 sampling codes are the 2Nth order phase signal (R 0 ,R 1 ,R 2 …R 2N-1 ) to obtain the N+2 order phase state (J 0 ,J 1 ,J 2 …J N+1 ). Considering that the delay unit of some delay loops is an inverter, it is necessary to convert the sampled N+2 order phase signal into Johnson Code (Johnson Code, keep the data at the even positions of the array unchanged, and invert the data at the odd positions, that is, obtain Johnson Code). It should be noted that in order to ensure that the first and last bits of the sampling code are correct, sampling needs to add one bit at the first and last bits of the sampling code as a verification bit, that is, J 0 / J N+1 , so the number of sampling phases in this step increases by 2, that is, the input phase group is: {verification bit J 0 ,J 1 ,J 2 ,J 3 ,…J N , verification bit J N+1}.

[0056] S200, judging whether the first and last bits of the sampling code are correct by using the phase relationship between the two verification bits and the first and last bits of the sampling code respectively;

[0057] In this step, according to the two verification bits J 0 / J N+1 Respectively with sampling code J N / J 1 Phase relationship judgment of phase 1 , J N Is it correct? It should be noted that for a delayed ring oscillator with a period of 2N, the phase polarity of a half period N must be opposite. Therefore, J 0 and J N The phase relationship is opposite, J 1 and J N+1 The phase relationship is opposite. Based on the above rules, it can be judged that the received J 0 and J N , J 1 and J N+1 The polarity relationship of is correct, and since the probability of two sampling values ​​half a cycle apart being wrong at the same time is very small, if J 1 / J N and verification bit J N+1 / Verification bit J 0 After verification, the logic is opposite, so it is determined that J 1 / J N The sampling result is correct.

[0058] S300, when the first and last bits of the sampling code are correct, the sampling code is filtered, and the bit error is corrected according to a preset correction logic, and the correction result is input into the decoder.

[0059] In this step, if the first and last digits of the sampling code are correct, the sampling code (J 1 ,J 2 …J N ) filtering, and after correcting the bit errors, the correction result (P 0 ,P 1 …P N-1 ), that is, the sampling code is error-processed before inputting into the decoder, thereby solving the signal error problem caused by inconsistent signal delay in the existing time-to-digital converter. It should be noted that a single call of this method can detect and correct multiple discontinuous errors. At the same time, in practical applications, continuous errors may also occur. The above process can be repeated, and a continuous error can be detected and corrected each time. Multiple repeated calls can detect and correct continuous errors, so that the corrected time result is basically consistent with the real time.

[0060] As an optional implementation scheme of the present application, optionally, the correction logic is preset, including: determining whether the first digit of the sampling code is 0 or 1; if the first digit of the sampling code is 0, determining whether there is a falling edge in the remaining sampling codes, and correcting the determined falling edge; if the first digit of the sampling code is 1, determining whether there is a rising edge in the remaining sampling codes, and correcting the determined rising edge.

[0061] It should be noted that after determining that the first and last bits of the sampling code are correct, the error bits are detected and corrected according to the preset correction logic. Specifically, it is necessary to first determine the first bit J of the sampling code. 1 Is it 0 or 1, and for the first J 1 0 and the first J 1 When the first bit in the array is J, the error code is detected and corrected in different ways. 1 is 0, then the array (J 1 ,J 2 ,J 3 ,…J N ) There is no falling edge of

[10] . If

[10] appears, it needs to be changed to

[00] . If the first position of the array is J 1 is 1, then the array (J 1 ,J 2 ,J 3 ,…J N ) does not have a rising edge of

[01] . If

[01] appears, it needs to be changed to

[11] . The RTL code example of this logic implementation is as follows Figure 4 As shown, "#Default first and last position J 1 ,J N is correct, and each of the N bits is corrected once; if the first bit is 1, 01 is abnormal, and 0 is set to 1, otherwise it is kept; if the first bit is 0, 10 is abnormal, and 1 is set to 0, otherwise it is kept. It should also be noted that the above correction logic assumes that the bit error caused by line delay will not exceed 2 delay units.

[0062] As an optional implementation scheme of the present application, optionally, the phase relationship between the two verification bits and the first and last bits of the sampling code is used to determine whether the first and last bits of the sampling code are correct, including: determining whether the last bit of the sampling code is correct based on whether the phase relationship between the verification bit added relative to the first bit of the sampling code and the last bit of the sampling code is opposite; determining whether the first bit of the sampling code is correct based on whether the phase relationship between the verification bit added relative to the last bit of the sampling code and the first bit of the sampling code is opposite.

[0063] It should be noted that this embodiment uses two verification bits J 0 / J N+1 Respectively with J N and J 1Phase logically opposite relationship judgment at any time J 1 , J N Is it correct? Since the probability of two sampling values ​​half a cycle apart being wrong at the same time is very small, if J 1 ( / J N ) and verification bit J N+1 (Verification Bit J 0 ) After verification, it is indeed logically opposite, and it is determined that J 1 ( / J N )’s sampling result is correct.

[0064] As an optional implementation scheme of the present application, optionally, whether the last bit of the sampling code is correct is judged based on whether the phase relationship between the verification bit added relative to the first bit of the sampling code and the last bit of the sampling code is opposite, including: if the phase relationship is opposite, the last bit of the sampling code is correct; if the phase relationship is not opposite, the last bit of the sampling code is wrong, and an error result is output.

[0065] As an optional implementation scheme of the present application, optionally, whether the first bit of the sampling code is correct is judged based on whether the phase relationship between the verification bit added relative to the last bit of the sampling code and the first bit of the sampling code is opposite, including: if the phase relationship is opposite, the first bit of the sampling code is correct; if the phase relationship is not opposite, the first bit of the sampling code is wrong, and an error result is output.

[0066] It should be noted that, in this embodiment, based on the relatively increased verification bit at the first and last bits of the sampling code and the logical opposite phase of the last and first bits of the sampling code at any time, it is determined whether the first and last bits of the sampling code have errors. If there are errors in the first and last bits, the process is stopped immediately, an error is reported and an error Flag is output; if there are no errors in the first and last bits, the errors are corrected for the remaining sampling codes according to the preset correction logic, and the results are input into the decoder.

[0067] It should also be noted that the sampling error correction method of the present application is implemented based on a sampling error correction device, wherein the input end of the sampling error correction device is connected to the output end of the trigger, and the output end of the sampling error correction device is connected to the input end of the decoder. That is, in order to solve the problem of signal errors, the present application first adds the signal to the error signal correction device before the signal enters the decoder, and the sampling code is error-processed before being input into the decoder. It should also be noted that the device implements the correction function based on a simple algorithm of a digital circuit. A single call can detect and correct multiple discontinuous errors, for example, an 8-bit array containing discontinuous two-bit errors: 1101 0100 and 0010 1011 detection and correction; multiple repeated calls can detect and correct continuous errors, for example, an 8-bit array containing continuous multi-bit errors: 1100 0100 and 0001 1011 detection and correction.

[0068] The following examples 1 and 2 are provided to illustrate the method of the present application in detail.

[0069] Example 1

[0070] The input end of the sampling error correction device of this embodiment is connected to an 18-bit trigger, and the output end is connected to a 16-bit data decoder, wherein the trigger samples the delay loop data in real time and inputs the 18-bit array into the correction device, after the correction device corrects the data, the 16-bit data is output to the decoder, and finally the calculation result is obtained. The specific processing steps are as follows:

[0071] First, if Figure 5 As shown, it is shown as a set of 18 bits {J 0 ,J 1 ,J 2 …J 15 ,J 16 ,J 17}The state cycle table of the signal array changing over time, which contains 16 bits of continuous data {J 1 ,J 2 ,J 3 …J 14 ,J 15 ,J 16} and two verification bits {J 0 ,J 17 Some discontinuous bit errors are randomly marked in the dotted box in the figure. It should be noted here that the signal bit errors caused by inconsistent signal delays will only appear near the 0-1 boundary of the value jump, and the time delay occurs from top to bottom. The data table simulates the trigger sampling results and inputs them into the correction device in this application;

[0072] Then, first determine the verification bit J 0 and J 16 Whether the status is different; J 1 and verification bit J 17 If the two phases are different, the data J is considered 1 and J 16 The data is correct; otherwise, an error flag is output;

[0073] Furthermore, if data J1 and J16 are correct, the remaining 14 data (J 2 J 3 ,…J 15 ) screen and verify in sequence, correct the error data and output a 16-bit continuous array {P 1 ,P 2 ,P 3 …P 14 ,P 15 ,P16}, the output result is as follows Figure 5 As shown in FIG. 1 , the state cycle table after the error correction device corrects the error once. It can be seen that after one correction, the non-continuous error randomly marked in the dotted box is completely eliminated.

[0074] like Figure 6 As shown, the calculation result of the 16-bit array containing non-continuous bit errors is input into the decoder after one correction. It can be seen that the calculation result before correction has obvious errors, and the time result calculated after correction is completely consistent with the real event.

[0075] Example 2

[0076] The error correction device of this embodiment corrects the data three times in a row according to the above processing flow, and then outputs the 16-bit data to the decoder to finally obtain the calculation result. The specific processing steps are as follows:

[0077] First, if Figure 7 As shown, Figure 7 The upper left shows a set of 18 {J 0 ,J 1 ,J 2 …J 15 ,J 16 ,J 17}The state cycle table of the signal array changing over time includes a 16-bit array and 2-bit verification bit data. Some continuous bit errors are randomly marked in the dotted box in the figure. It should be noted that the signal bit errors caused by inconsistent signal delays will only appear near the 0-1 boundary of the value jump, and the time delay occurs from top to bottom. The data table simulates the trigger sampling results and is input into the error correction device of this application.

[0078] Then, the data J is judged 1 and J 16 Is the data correct? If not, output an error flag; if correct, continue with the following steps;

[0079] Further, the correction (J 2 ,J 3 ,…J 15 ), output the 16-bit continuous array obtained by the first correction {P 1 ,P 2 ,P 3 …P 14 ,P 15 ,P 16},like Figure 7 The upper right shows the state cycle table after being corrected once by the error correction device;

[0080] Furthermore, the result obtained by the first correction {P1 ,P 2 ,P 3 …P 14 ,P 15 ,P 16} as the data source, the result of the analog trigger sampling is continuously input into the error correction device of the present application, and the above steps are repeated to obtain the data result of the second correction {P' 1 ,P' 2 ,P' 3 …P' 14 ,P' 15 ,P' 16 The second correction can correct two consecutive bit errors, such as Figure 7 The lower left shows the state cycle table after being corrected twice by the error correction device;

[0081] The result obtained by the second correction above {P' 1 ,P' 2 ,P' 3 …P' 14 ,P' 15 ,P' 16} as the data source, simulate the trigger sampling result, continue to input the error correction device of the present application, repeat the above steps again, and obtain the data result of the third correction {P" 1 ,P” 2 ,P” 3 …P” 14 ,P” 15 ,P” 16 The third correction can correct three consecutive bit errors, such as Figure 7 The lower right corner shows the state cycle table after the error correction device corrects three times.

[0082] like Figure 8 As shown, the calculation result of the 16-bit array containing continuous bit errors after three corrections is input into the decoder. The figure shows the time result calculated by the original data containing continuous bit errors and the time result calculated by the data after three corrections. Figure 8 The results show that after three corrections, the corrected time result is closer to the real time, and after three corrections, the time result is basically consistent with the real time.

[0083] In summary, the present application provides a method with simple algorithm logic and friendly circuit implementation, which solves the problem of signal error caused by inconsistent signal delay in the event digital converter, and can improve the time resolution of the time digital converter at a lower power consumption and area cost.

[0084] Obviously, those skilled in the art should understand that all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned control methods. The modules or steps of the present invention can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by computing devices, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules respectively, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.

[0085] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned control methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0086] Furthermore, in another aspect, the present application provides a sampling error correction device, which is used to implement any of the above sampling error correction methods, including:

[0087] A sampling code receiving module is configured to receive a sampling code of a trigger; and a verification bit is added to the first bit and the last bit of the sampling code respectively;

[0088] A sampling code judgment module is configured to judge whether the first bit and the last bit of the sampling code are correct by using the phase relationship between the two verification bits and the first bit and the last bit of the sampling code respectively;

[0089] The sampling code correction module is configured to filter the sampling code when the first bit and the last bit of the sampling code are correct, correct the error code according to the preset correction logic, and input the correction result into the decoder.

[0090] like Fig. 9 As shown, on the other hand, the present application provides a time-to-digital converter, comprising:

[0091] Delay unit;

[0092] A trigger connected to the delay unit and sampling the signal state of the delay unit to obtain a sampling code;

[0093] The sampling error correction device is connected to the trigger, receives the sampling code of the trigger, and performs error correction on the sampling code to obtain a correction result;

[0094] The decoder is connected to the sampling error correction device, receives the correction result, and calculates the delay time according to the correction result.

[0095] It should be noted that an error correction device is added to the time-to-digital converter of this embodiment, which aims to solve the signal error problem caused by inconsistent signal delays in existing time-to-digital converters, and can improve the time resolution of the time-to-digital converter at a lower power consumption and area cost. Specifically, in order to solve the signal error problem, an error correction device is added between the trigger and the decoder, so that before the sampling code enters the decoder, the error correction device first performs error processing on the sampling code. Among them, the error correction device of this embodiment implements the correction function based on a simple algorithm of a digital circuit. A single call can realize multiple discontinuous errors, and multiple repeated calls can realize the detection and correction of continuous errors. The input end of the error correction device of this embodiment is connected to the output end of the trigger, and the output end of the error correction device is connected to the input end of the decoder. The trigger is connected to the 2N-order phase signal (R 0 ,R 1 ,R 2 …R 2N-1 ) to obtain the N+2 order phase state (J 0 ,J 1 ,J 2 …J N+1 ). And considering that the delay unit of some delay loops is an inverter, it is necessary to convert the sampled N+2 order phase signal into Johnson code. N+2 sampling codes (J 0 ,J 1 ,J 2 …J N+1 ) After the bit error correction device is input, the bit error is processed according to the sampling error correction method described in any of the above items, which solves the signal error problem caused by inconsistent signal delay in the time-to-digital converter, and can improve the time resolution of the time-to-digital converter at a lower power consumption and area cost.

[0096] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A sampling error correction method, It is characterized in that The steps include: A sampling code of a receiving trigger is received; and a verification bit is added to the first bit and the last bit of the sampling code respectively; Determine whether the first and last bits of the sampling code are correct by using the phase relationship between the two verification bits and the first and last bits of the sampling code respectively; When the first bit and the last bit of the sampling code are correct, the sampling code is filtered, and the error code is corrected according to a preset correction logic, and the correction result is input into the decoder.

2. The sampling error correction method according to claim 1, It is characterized in that The preset correction logic includes: Determine whether the first digit of the sampling code is 0 or 1; If the first digit of the sampling code is 0, determining whether there is a falling edge in the remaining sampling codes, and correcting the determined falling edge; If the first digit of the sampling code is 1, it is determined whether there is a rising edge in the remaining sampling codes, and the determined rising edge is corrected.

3. The sampling error correction method according to any one of claims 1 or 2, It is characterized in that The method of judging whether the first bit and the last bit of the sampling code are correct by respectively using the phase relationship between the two verification bits and the first bit and the last bit of the sampling code comprises: Determining whether the last bit of the sampling code is correct according to whether the phase relationship between the verification bit added relative to the first bit of the sampling code and the last bit of the sampling code is opposite; Whether the first bit of the sampling code is correct is determined based on whether the phase relationship between the verification bit added relative to the last bit of the sampling code and the first bit of the sampling code is opposite.

4. The sampling error correction method according to claim 3, It is characterized in that The step of judging whether the last bit of the sampling code is correct according to whether the phase relationship between the verification bit added relative to the first bit of the sampling code and the last bit of the sampling code is opposite comprises: If the phase relationship is opposite, the last bit of the sampling code is correct; If the phase relationship is not opposite, the last bit of the sampling code is wrong and an error result is output.

5. The sampling error correction method according to claim 3, It is characterized in that The step of judging whether the first bit of the sampling code is correct according to whether the phase relationship between the verification bit added relative to the last bit of the sampling code and the first bit of the sampling code is opposite comprises: If the phase relationship is opposite, the first bit of the sampling code is correct; If the phase relationship is not opposite, the first bit of the sampling code is wrong, and an error result is output.

6. A sampling error correction device, used to implement the sampling error correction method according to any one of claims 1 to 5, It is characterized in that include: A sampling code receiving module is configured to receive a sampling code of a trigger; and a verification bit is added to the first bit and the last bit of the sampling code respectively; A sampling code judgment module is configured to judge whether the first bit and the last bit of the sampling code are correct by using the phase relationship between the two verification bits and the first bit and the last bit of the sampling code respectively; The sampling code correction module is configured to filter the sampling code when the first bit and the last bit of the sampling code are correct, correct the error code according to the preset correction logic, and input the correction result into the decoder.

7. A time-to-digital converter, It is characterized in that include: Delay unit; A trigger connected to the delay unit and sampling the signal state of the delay unit to obtain a sampling code; The sampling error correction device of claim 6 is connected to the trigger, receives the sampling code of the trigger, and performs error correction on the sampling code to obtain a correction result; The decoder is connected to the sampling error correction device, receives the correction result, and calculates the delay time according to the correction result.

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