Memory structure and forming method thereof

Abstract

The invention discloses a memory structure and a forming method thereof. The method comprises the following steps: providing a substrate; forming a floating gate precursor layer on the substrate; providing a ligand material to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal organic framework. The derivative of the metal organic framework has a periodic topological structure with complex micropores, so that the charge trapping structure has porosity, high defect state density and high carrier trapping capability, charge storage can be realized under low operating voltage, and the reliability of the memory structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a memory structure and a forming method thereof. Background Art

[0002] There are many types of memory. According to the storage material, it can be divided into magnetic surface memory and semiconductor memory. Semiconductor memory can be divided into volatile memory and non-volatile memory according to whether the data storage depends on external power supply. Volatile memory will lose all stored data after power failure, such as dynamic random access memory (DRAM) and static random access memory (SRAM). On the contrary, non-volatile memory can retain stored data even when power is off, such as embedded flash (EFlash) and charge trapping memory (CTM). Charge trapping memory has the characteristics of low power consumption, good fatigue characteristics and strong data retention ability. It is one of the mainstream non-volatile memories currently used. By applying different voltages on the storage layer to control the tunneling of charges in and out of the storage layer, data writing, erasing and storage can be achieved.

[0003] However, current charge trap memories still face many challenges. Summary of the invention

[0004] The problem solved by the present invention is how to optimize the charge trapping layer to improve the performance of the charge trapping memory.

[0005] To solve the above problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate; providing a ligand material to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal organic framework.

[0006] Optionally, in the step of forming a floating gate precursor layer on the substrate, the floating gate precursor layer is formed by atomic deposition.

[0007] Optionally, in the step of forming a floating gate precursor layer on the substrate, the thickness of the floating gate precursor layer ranges from 300 angstroms to 600 angstroms.

[0008] Optionally, the step of providing a ligand material to react with the floating gate precursor layer to form the charge trapping structure includes:

[0009] Depositing a ligand material to react with the floating gate precursor layer to form an initial charge trapping structure;

[0010] The initial charge trapping structure is annealed to form the charge trapping structure.

[0011] Optionally, in the step of depositing the ligand material, the ligand material is deposited by chemical vapor deposition.

[0012] Optionally, in the step of depositing the ligand material by chemical vapor deposition, the reaction parameters include: reaction time range: 2h to 4h; reaction temperature range: 100°C to 150°C.

[0013] Optionally, in the step of annealing the initial charge trapping structure to form the charge trapping structure, the annealing parameters include: an annealing temperature range of 250° C. to 300° C.; and an annealing time range of 2 h to 3 h.

[0014] Optionally, the material of the floating gate precursor layer includes metal oxide.

[0015] Optionally, the metal oxide includes zinc oxide.

[0016] Optionally, the ligand material includes an organic ligand material.

[0017] Optionally, the organic ligand material includes terephthalic acid and naphthalene dicarboxylic acid.

[0018] Optionally, also include:

[0019] After providing a substrate and before forming the floating gate precursor layer, a tunneling layer is formed on the substrate; after forming the charge trapping structure, a dielectric layer is formed on the charge trapping structure;

[0020] After forming the dielectric layer, forming source and drain regions in the substrate on both sides of the charge trapping structure;

[0021] After forming the source and drain regions, a control gate is formed on the dielectric layer.

[0022] Optionally, the method further includes: performing patterning between any two of the steps of forming a tunneling layer on the substrate, forming a floating gate precursor layer on the substrate, forming an initial charge trapping structure, annealing the initial charge trapping structure and forming a dielectric layer on the charge trapping structure.

[0023] Optionally, in the step of forming the dielectric layer on the charge trapping structure, the dielectric layer is formed on the charge trapping structure by chemical vapor deposition.

[0024] Correspondingly, the technical solution of the present invention further provides a memory structure, and the memory structure is formed by the method for forming a memory structure as described in any of the above technical solutions.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the method for forming a memory structure of the technical solution of the present invention, a ligand material is provided to react with the floating gate precursor layer to form a charge trapping structure. The material of the charge trapping structure is a derivative of a metal organic framework. The derivative of the metal organic framework has a periodic topological structure with complex micropores, so that the charge trapping structure has porosity and a large defect state density, and has a strong ability to capture carriers. Charge storage can be achieved at a low operating voltage, thereby improving the reliability of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a process flow chart of a process of forming a memory structure according to an embodiment of the present invention;

[0028] Figures 2 to 6 It is a schematic cross-sectional structure diagram of each step of the formation process of the memory structure of an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As can be seen from the background art, with the advent of advanced technology nodes, the use of silicon nitride crystals as charge trapping layers in conventional charge trap memory has limited the performance of the charge trap memory.

[0030] To solve the technical problem, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate; providing a ligand material to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal organic framework.

[0031] In the method for forming a memory structure of the technical solution of the present invention, a ligand material is provided to react with the floating gate precursor layer to form a charge trapping structure. The material of the charge trapping structure is a derivative of a metal organic framework. The derivative of the metal organic framework has a periodic topological structure with complex micropores, so that the charge trapping structure has porosity and a large defect state density, and has a strong ability to capture carriers. Charge storage can be achieved at a low operating voltage, thereby improving the reliability of the memory structure.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Please refer to Figure 1 , and combined with reference Figures 2 to 6 ,in Figure 1is a process flow chart of a formation process of a memory structure according to an embodiment of the present invention, Figures 2 to 6 It is a schematic cross-sectional structure diagram of each step of a formation process of a memory structure according to an embodiment of the present invention.

[0034] The forming process of the memory structure includes:

[0035] Step S10, providing a substrate 100;

[0036] Step S11, forming a tunneling layer 101 on the substrate 100;

[0037] Step S12, forming a floating gate precursor layer 102 on the substrate 100;

[0038] Step S13, providing a ligand material to react with the floating gate precursor layer 102 to form a charge trapping structure 104, wherein the charge trapping structure has a metal organic framework pore structure;

[0039] Step S14, after forming the charge trapping structure 104, forming a dielectric layer 105 on the charge trapping structure 104;

[0040] Step S15, after forming the dielectric layer 105, forming source and drain regions in the substrate 100 on both sides of the charge trapping structure 104;

[0041] Step S16 , after forming the source and drain regions, forming a control gate 108 on the dielectric layer 105 .

[0042] The following will describe in detail the steps of the memory structure formation process.

[0043] Please refer to Figure 2 , in step S10 , a substrate 100 is provided.

[0044] The material of the substrate 100 includes: silicon, silicon carbide, silicon germanium, silicon on insulator (SOI) or germanium on insulator (GOI).

[0045] The substrate 100 provides a structural foundation for forming a floating gate precursor layer 102 .

[0046] Please continue to refer to Figure 2 In step S11 , a tunneling layer 101 is formed on the substrate 100 .

[0047] The material of the tunneling layer 101 includes silicon oxide.

[0048] Please continue to refer to Figure 2 In step S12 , a floating gate precursor layer 102 is formed on the substrate 100 .

[0049] In the step of forming the floating gate precursor layer 102 on the substrate 100, the floating gate precursor layer 102 is formed by atomic deposition. The floating gate precursor layer 102 formed by atomic deposition has high quality and good uniformity.

[0050] In the step of forming a floating gate precursor layer 102 on the substrate 100 , the thickness of the floating gate precursor layer 102 is in the range of 300 angstroms to 600 angstroms.

[0051] The material of the floating gate precursor layer 102 includes metal oxide. Specifically, in some embodiments of the present invention, the metal oxide includes zinc oxide (ZnO). In other embodiments, the metal oxide also includes other metal oxides except zinc oxide.

[0052] Specifically, in some embodiments of the present invention, the chemical reaction equation for preparing the floating gate precursor layer 102 of zinc oxide (ZnO) material includes:

[0053] Zn(C2H5)2(g)+H2O(g)→ZnO(s)+2C2H6(g).

[0054] Please refer to Figure 3 to Figure 4 In step S13, a ligand material is provided to react with the floating gate precursor layer 102 to form a charge trapping structure 104, wherein the material of the charge trapping structure 104 is a derivative of a metal organic framework.

[0055] The step of providing a ligand material to react with the floating gate precursor layer to form the charge trapping structure comprises: Figure 3 As shown, a ligand material is deposited, and the ligand material reacts with the floating gate precursor layer 102 to form an initial charge trapping structure 103; Figure 4 As shown, the initial charge trapping structure 103 is annealed to form the charge trapping structure 104 .

[0056] In the step of depositing the ligand material, the ligand material is deposited by chemical vapor deposition. The ligand material is deposited by chemical vapor deposition so that the surface of the initial charge trapping structure 103 formed by the reaction is smooth and flat with good uniformity. The material of the initial charge trapping structure 103 is a metal organic framework (MOF), which is a crystalline material with a periodic topological structure of complex micropores. The metal organic framework material has a porous structure that can be systematically designed and can be synthesized at the nanoscale. The initial charge trapping structure 103 of the metal organic framework material provides a basis for forming a charge trapping structure 104 having a structure with metal organic framework pores. In some specific embodiments, the material of the floating gate precursor layer 102 includes zinc oxide (ZnO), and the initial charge trapping structure 103 formed by the reaction is a Zn-MOF material.

[0057] The ligand material includes an organic ligand material. Specifically, in some embodiments of the present invention, the organic ligand material includes terephthalic acid (H2BDC) and naphthalene dicarboxylic acid (H2NDC). In other embodiments, the ligand material also includes other organic materials. According to the needs of the actual process, the ligand material can be selected to obtain the initial charge trapping structure of the metal organic framework material that meets the requirements, and the performance of the memory structure can be adjusted.

[0058] Specifically, in some embodiments of the present invention, terephthalic acid (H2BDC) is used as a ligand material, and the chemical reaction equation for preparing the initial charge trapping structure 103 includes:

[0059] ZnO(s)+H2BDC(g)→H2O(g)+Zn-BDC(s).

[0060] In the step of depositing the ligand material by chemical vapor deposition, the reaction parameters include: reaction time range: 2h~4h; reaction temperature range: 100℃~150℃.

[0061] The initial charge trapping structure 103 is annealed so that the annealed derivative of the initial charge trapping structure 103 (i.e., the charge trapping structure 104) retains the porosity of the metal organic framework pore structure, so that the charge trapping structure 104 has a large defect state density and a strong carrier capture ability, and charge storage can be achieved at a lower operating voltage, thereby improving the reliability of the storage device.

[0062] In the step of performing annealing on the initial charge trapping structure 103 to form the charge trapping structure 104, the annealing parameters include: an annealing temperature range of 250° C. to 300° C.; and an annealing time range of 2 h to 3 h.

[0063] The thickness of the charge trapping structure 104 is less than 10 nm. Specifically, in some embodiments of the present invention, the material of the charge trapping structure 104 is zinc oxide (ZnO).

[0064] Please refer to Figure 5 In step S14 , after forming the charge trapping structure 104 , a dielectric layer 105 is formed on the charge trapping structure 104 .

[0065] The material of the dielectric layer 105 includes silicon oxide.

[0066] Specifically, in some embodiments of the present invention, after forming the dielectric layer 105, the charge trapping structure 104, the tunneling layer 101, and the dielectric layer 105 are patterned to form a floating gate with the patterned tunneling layer 101, the charge trapping structure 104, and the dielectric layer 105.

[0067] In other embodiments, patterning is performed between any two steps of forming a tunneling layer on the substrate, forming a floating gate precursor layer on the substrate, forming an initial charge trapping structure, annealing the initial charge trapping structure, and forming a dielectric layer on the charge trapping structure to form a floating gate.

[0068] Please refer to Figure 6 In step S15 , after forming the dielectric layer 105 , source and drain regions are formed in the substrate 100 on both sides of the charge trapping structure 104 .

[0069] The source-drain region includes a source electrode 106 and a drain electrode 107. The source electrode 106 and the drain electrode 107 are formed by ion implantation.

[0070] Please continue to refer to Figure 6 In step S16 , after forming the source and drain regions, a control gate 108 is formed on the dielectric layer 105 .

[0071] In the step of forming the control gate 108 on the dielectric layer 105 , polysilicon is deposited by chemical vapor deposition, and the polysilicon is doped to form the control gate 108 .

[0072] Correspondingly, an embodiment of the present invention further provides a memory structure, and the memory structure is formed by the above-mentioned method for forming the memory structure, which will not be described in detail here.

[0073] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a memory structure, characterized in that: include: providing a substrate; forming a floating gate precursor layer on the substrate; A ligand material is provided to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal organic framework.

2. The method for forming a memory structure according to claim 1, wherein: In the step of forming a floating gate precursor layer on the substrate, the floating gate precursor layer is formed by atomic deposition.

3. The method for forming a memory structure according to claim 1 or 2, characterized in that: In the step of forming a floating gate precursor layer on the substrate, the thickness of the floating gate precursor layer ranges from 300 angstroms to 600 angstroms.

4. The method for forming a memory structure according to claim 1, wherein: The step of providing a ligand material to react with the floating gate precursor layer to form the charge trapping structure comprises: Depositing a ligand material to react with the floating gate precursor layer to form an initial charge trapping structure; The initial charge trapping structure is annealed to form the charge trapping structure.

5. The method for forming a memory structure according to claim 4, wherein: In the step of depositing the ligand material, the ligand material is deposited by chemical vapor deposition.

6. The method for forming a memory structure according to claim 5, wherein: In the step of depositing the ligand material by chemical vapor deposition, the reaction parameters include: reaction time range: 2h~4h; reaction temperature range: 100℃~150℃.

7. The method for forming a memory structure according to claim 4, wherein: In the step of performing annealing on the initial charge trapping structure to form the charge trapping structure, the annealing parameters include: an annealing temperature range of 250° C. to 300° C.; and an annealing time range of 2 h to 3 h.

8. The method for forming a memory structure according to claim 1, wherein: The material of the floating gate precursor layer includes metal oxide.

9. The method for forming a memory structure according to claim 8, wherein: The metal oxide includes zinc oxide.

10. The method for forming a memory structure according to claim 1, wherein: The ligand material includes an organic ligand material.

11. The method for forming a memory structure according to claim 10, wherein: The organic ligand material includes terephthalic acid and naphthalene dicarboxylic acid.

12. The method for forming a memory structure according to claim 4, wherein: Also includes: After providing a substrate and before forming the floating gate precursor layer, forming a tunneling layer on the substrate; After forming the charge trapping structure, forming a dielectric layer on the charge trapping structure; After forming the dielectric layer, forming source and drain regions in the substrate on both sides of the charge trapping structure; After forming the source and drain regions, a control gate is formed on the dielectric layer.

13. The method for forming a memory structure according to claim 12, wherein: Also includes: Patterning is performed between any two steps of forming a tunneling layer on the substrate, forming a floating gate precursor layer on the substrate, forming an initial charge trapping structure, annealing the initial charge trapping structure and forming a dielectric layer on the charge trapping structure.

14. The method for forming a memory structure according to claim 12, wherein: In the step of forming a dielectric layer on the charge trapping structure, the dielectric layer is formed on the charge trapping structure by chemical vapor deposition.

15. A memory structure, characterized in that: The memory structure is formed by the method for forming a memory structure according to any one of claims 1 to 14.

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