Chip technology with double piezoelectric layers

Abstract

The invention relates to the technical field of semiconductor processes, in particular to a process for a chip with double piezoelectric layers, which comprises the following steps of: S1, preparing a wafer as a substrate, growing a first metal layer on the front surface of the substrate, growing a first piezoelectric layer by adopting a radio frequency magnetron sputtering method, and growing a second metal layer on the plane of one side, far away from the substrate, of the first piezoelectric layer; s2, patterning the second metal layer; s3, integrally growing a second piezoelectric layer by adopting a sol-gel method, growing a third metal layer on one side surface, far away from the substrate, of the second piezoelectric layer, and patterning the third metal layer; s4, patterning the second piezoelectric layer; s5, forming a through hole; and S6, forming a cavity in the back surface of the substrate to form the vibrating diaphragm. The first layer of piezoelectric PZT film is prepared by adopting a radio frequency magnetron sputtering method, and on the basis, the second layer of piezoelectric PZT film is prepared by adopting a sol-gel method, so that the size of the MEMS chip is reduced on the premise of keeping the performance of the MEMS chip.

Description

Technical Field

[0001] One or more embodiments of the present specification relate to the field of semiconductor process technology, and in particular, to a chip process with a double piezoelectric layer. Background Art

[0002] Existing piezoelectric MEMS chips usually adopt a single-layer piezoelectric structure design, while a double-layer piezoelectric structure can make the piezoelectric MEMS chip more flexible in structural design and have better chip performance. However, due to the difficulty of the process, the double-layer piezoelectric structure can only be realized on a very few piezoelectric materials such as aluminum nitride. For the widely used lead zirconate titanate (PZT) piezoelectric material, it is very difficult to manufacture a double-layer piezoelectric layer.

[0003] The commonly used methods for preparing piezoelectric PZT films are the sol-gel method and the radio frequency magnetron sputtering method. If the sol-gel method is used to manufacture a double-layer PZT structure, it is difficult to manufacture two thin layers of highly consistent piezoelectric films by the sol-gel method, and the manufactured double-layer PZT structure is thick and has poor performance. If the magnetron sputtering method is used to manufacture a double-layer PZT structure, since the PZT film contains volatile lead metal, the high temperature environment required for magnetron sputtering will cause the lead metal in the first layer of the PZT film to evaporate when the second layer of PZT is grown, which will greatly reduce the performance of the MEMS chip.

[0004] In summary, the present application now proposes a chip process with a double piezoelectric layer to solve the above-mentioned problems. Summary of the invention

[0005] The present invention aims to solve the problems raised in the background technology. The purpose of one or more embodiments of this specification is to propose a chip process with a double piezoelectric layer, which reduces the space occupied by the chip while ensuring the chip performance.

[0006] Based on the above purpose, one or more embodiments of the present specification provide a chip process with a double piezoelectric layer, including the following steps: S1, preparing a wafer as a substrate, the substrate having a relative front and back side, growing a first metal layer on the front side of the substrate, growing the first piezoelectric layer by radio frequency magnetron sputtering on a plane side of the first metal layer away from the substrate, and growing the second metal layer on a plane side of the first piezoelectric layer away from the substrate; S2, patterning the second metal layer; S3, using a sol-gel method to grow the second piezoelectric layer integrally on the side of the first piezoelectric layer and the second metal layer away from the substrate, growing a third metal layer on the side of the second piezoelectric layer away from the substrate, and patterning the third metal layer; S4, patterning the second piezoelectric layer; S5, opening a through hole in the non-patterned area of ​​the first piezoelectric layer and the second piezoelectric layer to expose the first metal layer; S6, opening a cavity on the back side of the substrate to form a final diaphragm area.

[0007] The chip process with a double piezoelectric layer proposed in the embodiment of the present invention adopts a radio frequency magnetron sputtering method to prepare a first layer of piezoelectric PZT film, and on this basis, a sol-gel method is used to prepare a second layer of piezoelectric PZT film, thereby reducing the size of the MEMS chip while maintaining the performance of the MEMS chip.

[0008] According to the chip process with a double piezoelectric layer proposed in an embodiment of the present invention, the substrate is a substrate made of silicon material.

[0009] According to the chip process with double piezoelectric layers proposed in an embodiment of the present invention, the substrate is a substrate composed of SOI.

[0010] According to the chip process with double piezoelectric layers proposed in the embodiment of the present invention, a transition layer is grown on the surface of the substrate.

[0011] The beneficial effects of the present invention are described in detail below with reference to the embodiments and drawings of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate one or more embodiments of the present specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 A flowchart of a chip process with a double piezoelectric layer proposed in an embodiment of the present invention;

[0014] Figure 2 for Figure 1 Schematic diagram of step S1 in FIG.

[0015] Figure 3 for Figure 1 Schematic diagram of step S2 in FIG.

[0016] Figure 4 for Figure 1 Schematic diagram of step S3 in FIG.

[0017] Figure 5 for Figure 1 Schematic diagram of step S4;

[0018] Figure 6 for Figure 1 Schematic diagram of step S5;

[0019] Figure 7 for Figure 1 Schematic diagram of step S6;

[0020] Figure 8 for Figure 1 A schematic diagram of another embodiment of a substrate in FIG.

[0021] In the figure numerals: 1. substrate; 1a. bottom silicon; 1b. buried oxide layer; 1c. top silicon; 2. transition layer; 3a. first metal layer; 3b. second metal layer; 3c. third metal layer; 4a. first piezoelectric layer; 4b. second piezoelectric layer. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments.

[0023] Example

[0024] See also Figure 1-Figure 8 , a chip process with a double piezoelectric layer proposed in an embodiment of the present invention includes the following steps:

[0025] S1, prepare a wafer as a substrate 1, the substrate 1 has a front side and a back side opposite to each other, grow a first metal layer 3a on the front side of the substrate, grow a first piezoelectric layer 4a by radio frequency magnetron sputtering on a side plane of the first metal layer 3a away from the substrate 1, and grow a second metal layer 3b on a side plane of the first piezoelectric layer 4a away from the substrate 1. Optionally, the substrate 1 is a substrate made of silicon material. Optionally, the substrate 1 is a substrate made of SOI, which is composed of bottom silicon 1a and top silicon 1c connected by a buried oxide layer 1b, such as Figure 8 Optionally, a transition layer 2 is grown on the surface of the substrate, such as Figure 8 The radio frequency magnetron sputtering method is to place the prepared target material and substrate 1 in a vacuum sputtering chamber, introduce argon gas into the vacuum sputtering chamber, perform magnetron sputtering, complete the coating, and keep the temperature in the chamber after sputtering. The coated substrate 1 can be annealed (the radio frequency magnetron sputtering method is a direct conversion of the existing technology). Figure 2 shown.

[0026] S2, patterning the second metal layer 3b, such as Figure 3 shown.

[0027] S3, using a sol-gel method to integrally grow a second piezoelectric layer 4b on a side of the first piezoelectric layer 4a and the second metal layer 3b away from the substrate 1, grow a third metal layer 3c on a side of the second piezoelectric layer 4b away from the substrate 1, and pattern the third metal layer 3c. Optionally, the sol-gel method is to dissolve the main raw materials in a suitable solvent to form a stable sol sol, and to make the sol undergo a series of hydrolysis and polycondensation reactions to form a PZT precursor solution, and to apply the precursor solution on the substrate 1 to form a wet film by spin coating, dipping or spraying, and to thermally decompose the organic matter to form an amorphous inorganic medium by low-temperature heat treatment, and to densify and crystallize the film by high-temperature heat treatment, and finally to form a perovskite structure ferroelectric film (the sol-gel method is a direct conversion of the prior art), such as Figure 4 shown.

[0028] S4, patterning the second piezoelectric layer 4b, such as Figure 5 shown.

[0029] S5, through holes are formed in the non-patterned areas of the first piezoelectric layer 4a and the second piezoelectric layer 4b to expose the first metal layer 3a, such as Figure 6 shown.

[0030] S6, a cavity is opened on the back of the substrate 1 to form the final diaphragm area, such as Figure 7 shown.

[0031] The chip process with a double piezoelectric layer proposed in the embodiment of the present invention adopts a radio frequency magnetron sputtering method to prepare a first layer of piezoelectric PZT film, and on this basis, a sol-gel method is used to prepare a second layer of piezoelectric PZT film, thereby reducing the size of the MEMS chip while maintaining the performance of the MEMS chip.

[0032] One or more embodiments of this specification are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of this disclosure.

Claims

1. A chip process with a double piezoelectric layer, characterized in that: The following steps are involved: S1, preparing a wafer as a substrate (1), the substrate (1) having a front side and a back side opposite to each other, growing a first metal layer (3a) on the front side of the substrate (1), growing a first piezoelectric layer (4a) on a side plane of the first metal layer (3a) away from the substrate (1) by using a radio frequency magnetron sputtering method, and growing a second metal layer (3b) on a side plane of the first piezoelectric layer (4a) away from the substrate (1); S2, patterning the second metal layer (3b); S3, using a sol-gel method to integrally grow a second piezoelectric layer (4b) on a side of the first piezoelectric layer (4a) and the second metal layer (3b) away from the substrate (1), grow a third metal layer (3c) on a side of the second piezoelectric layer (4b) away from the substrate (1), and pattern the third metal layer (3c); S4, patterning the second piezoelectric layer (4b); S5, through-holes are formed in the non-patterned areas of the first piezoelectric layer (4a) and the second piezoelectric layer (4b) to expose the first metal layer (3a); S6, opening a cavity on the back side of the substrate (1) to form a final diaphragm area.

2. The chip process with double piezoelectric layers according to claim 1, characterized in that: The substrate (1) is a substrate made of silicon material.

3. The chip process with double piezoelectric layers according to claim 1, characterized in that: The substrate (1) is a substrate composed of SOI.

4. The chip process with double piezoelectric layers according to claim 2 or 3, characterized in that: A transition layer (2) is grown on the surface of the substrate.

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