Device preparation method

Abstract

The invention discloses a device preparation method, which is characterized in that a groove is processed on a substrate to increase the distance between the substrate and a device, so that when a first sacrificial layer is etched to separate a device layer from the substrate, a relatively large etching channel is provided, the etching rate of the first sacrificial layer is improved, the stripping speed of the device layer is accelerated, and the device preparation efficiency is improved. Damage to the device layer caused by the etching process condition is reduced, so that the device yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a device preparation method. Background Art

[0002] The micro-coaxial structure device prepared by the micro-electromechanical system (MEMS) process is a device used to transmit and process high-frequency and high-speed signals. It has the advantages of low loss, small dispersion, large operating frequency range, and extremely high digital signal transmission rate.

[0003] like Figure 1 As shown, the micro-coaxial structure device generally includes a rectangular outer conductor metal frame 101, an inner conductor 102 located in the outer conductor metal frame 101, and a support bar 103 for supporting the inner conductor 102. The preparation of the micro-coaxial structure device generally involves: processing a silicon oxide layer on a substrate, then processing a device on the silicon oxide layer, and etching the silicon oxide layer to separate the device from the substrate.

[0004] In the prior art, the process conditions for etching the silicon oxide layer will inevitably cause damage to the device itself. The longer the etching time, the greater the damage to the device. Summary of the invention

[0005] In view of the above problems, the present application is proposed to provide a device preparation method that overcomes the above problems or at least partially solves the above problems.

[0006] Provided is a device preparation method, comprising:.

[0007] forming a groove on one side of the substrate and filling the groove with a first sacrificial layer;

[0008] forming a second sacrificial layer on a side of the first sacrificial layer away from the groove, wherein the orthographic projection of the first sacrificial layer on the bottom surface of the substrate is within the range of the orthographic projection of the second sacrificial layer on the bottom surface of the substrate;

[0009] forming a device layer on a side of the second sacrificial layer away from the groove, wherein an orthographic projection of the device layer on the substrate is at least partially located in the groove;

[0010] The first sacrificial layer and the second sacrificial layer are etched to peel the device layer from the substrate.

[0011] Optionally, in a direction perpendicular to the bottom surface of the substrate, a height of the first sacrificial layer is the same as a depth of the groove.

[0012] Optionally, etching the first sacrificial layer and the second sacrificial layer to peel the device layer from the substrate includes:

[0013] Etching at least the second sacrificial layer not covered by the device layer to expose a partial area of ​​the first sacrificial layer;

[0014] The first sacrificial layer is etched to peel the device layer from the substrate.

[0015] Optionally, after the device layer is peeled off from the substrate, the method further comprises:

[0016] The first sacrificial layer remaining on the bottom surface of the device layer is removed to obtain a device.

[0017] Optionally, etching the first sacrificial layer includes:

[0018] Etching the first sacrificial layer using an etching solution;

[0019] Wherein, the material of the first sacrificial layer includes at least one of a simple substance, oxide and hydroxide of magnesium, aluminum, zinc, iron, nickel or calcium, and the etching solution includes a non-oxidizing acid solution;

[0020] Alternatively, the material of the first sacrificial layer includes at least one of a simple substance, an oxide, and a hydroxide of aluminum or zinc, and the etching solution includes an alkaline solution;

[0021] Alternatively, the material of the first sacrificial layer includes silicon oxide, and the etching solution includes hydrofluoric acid.

[0022] Optionally, the orthographic projection of the device layer on the bottom surface of the substrate is a first projection area, the orthographic projection of the groove on the bottom surface of the substrate is a second projection area, the first projection area is located within the range of the second projection area, and there is a spacing area between the boundary of the first projection area and the boundary of the second projection area; the ratio of the width of the spacing area to the width of the first projection area is 1% to 10%.

[0023] Optionally, along a direction perpendicular to the bottom surface of the substrate, the depth of the groove is greater than or equal to 8 micrometers and less than the thickness of the substrate.

[0024] Optionally, the width of the groove increases or remains unchanged along the direction from the substrate to the device layer.

[0025] Optionally, the side wall of the groove is stepped.

[0026] Optionally, before etching the first sacrificial layer and the second sacrificial layer, the method further includes:

[0027] forming a protective layer outside the device layer on a side away from the substrate, wherein the protective layer covers the side of the device layer and the side of the device layer on a side away from the substrate;

[0028] After the sacrificial layer is removed by wet etching process, the method further includes:

[0029] Remove the protective layer.

[0030] The technical solution provided by this application has at least the following technical effects or advantages:

[0031] The device preparation method provided in the present application increases the distance between the substrate and the device by processing a groove on the substrate, so that when the first sacrificial layer is etched to separate the device layer and the substrate, there is a larger etching channel, so as to increase the etching rate of the first sacrificial layer, accelerate the stripping speed of the device layer, reduce the damage to the device layer caused by the etching process conditions, and thus improve the device yield.

[0032] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0034] Figure 1 This is a schematic diagram of the existing PolyStrata structure;

[0035] Figure 2 A schematic diagram of a system module that integrates a variety of thick copper high-frequency and high-speed devices;

[0036] Figure 3 This is a schematic diagram of the preparation of thick copper high-frequency and high-speed devices on silicon wafers;

[0037] Figure 4 This is a flow chart of the device preparation method in the embodiment of this application;

[0038] Figure 5 The device preparation process in the embodiment of this application Figure 1 ;

[0039] Figure 6 The device preparation process in the embodiment of this application Figure 2 ;

[0040] Figure 7 The device preparation process in the embodiment of this application Figure 3 ;

[0041] Figure 8 The device preparation process in the embodiment of this application Figure 4 ;

[0042] Fig. 9 The device preparation process in the embodiment of this application Figure 5 ;

[0043] Fig.10 The device preparation process in the embodiment of this application Figure 6 ;

[0044] Fig.11 This is a schematic diagram of the first projection area and the second projection area in an embodiment of the present application;

[0045] Fig.12 This is the relationship curve between the extension amplitude and the peeling time in the embodiment of the present application;

[0046] Fig.13 This is a curve showing the relationship between groove depth and peeling time in the embodiment of the present application;

[0047] Fig.14 This is a schematic diagram of a trapezoidal groove in an embodiment of the present application;

[0048] Fig.15 The device preparation process in the embodiment of this application Figure 7 ;

[0049] Fig.16 This is a schematic diagram of a tapered groove in an embodiment of the present application. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0051] Various structural schematic diagrams according to embodiments of the present application are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0052] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element therebetween. Additionally, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed. In the context of the present disclosure, similar or identical components may be denoted by the same or similar reference numerals.

[0053] In order to better understand the above-mentioned technical scheme, the above-mentioned technical scheme will be described in detail below in combination with specific implementation methods. It should be understood that the embodiments of the present disclosure and the specific features in the embodiments are detailed descriptions of the technical scheme of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0054] The micro-electromechanical system (MEMS) process is used to manufacture a rectangular coaxial transmission line by adding an inner conductor 102 and a dielectric support structure 103 supporting the inner conductor 102 to a rectangular outer conductor metal frame 101, and filling the surrounding with air. This is called the micro-coaxial technology of the PolyStrata structure. The micro-coaxial technology can be used to manufacture thick copper high-frequency and high-speed devices, such as Figure 1 , which is a schematic diagram of an existing PolyStrata structure, and the PolyStrata structure is suitable for thick copper high-frequency and high-speed devices.

[0055] Based on micro-coaxial technology, a large number of MEMS passive devices can be developed, such as log-periodic antennas, resonators, couplers, mixers, power synthesizers, antenna arrays and other high-frequency signal transmission structures and high-speed digital signal transmission structures.

[0056] like Figure 2 As shown, it is a schematic diagram of a system module that integrates a variety of thick copper high-frequency and high-speed devices. The module is suitable for the transmission and processing of high-frequency and high-speed signals. The frequency band of the signal transmitted by such high-frequency and high-speed devices can be as high as 300GHz, and the data transmission rate can be as high as 150Gbps. It has the advantages of low loss, small dispersion, large operating frequency range, and extremely high digital signal transmission rate. For example, the devices framed in the figure include DC Interconnects, Filters, Capacitors, power combiners, Resistors, Waveguides, and Power Dividers, which can be prepared by the preparation method provided by the present disclosure.

[0057] In the disclosed technology, this type of thick copper high-frequency and high-speed device is manufactured on a semiconductor wafer and connected to other microelectronic devices to form an integrated functional module, transmitting high-frequency and high-speed signals, expanding in two dimensions and stacking in three dimensions. It is the equipment solution required for high-speed information networks.

[0058] In the prior art, a micrometer-sized silicon oxide layer 302 is usually formed on a silicon or glass substrate 301, and then a thick copper high-frequency, high-speed device 303 is formed on the silicon oxide layer 302. The structure of the thick copper high-frequency, high-speed device 303 prepared on the substrate 301 is as follows: Figure 3After the device 303 is prepared, it needs to be completely peeled off from the substrate 301, and the peeled device 303 and the substrate are subjected to surface mounting, bonding interconnection, packaging testing and other operations to complete the board-level packaging integration.

[0059] Taking wet etching of silicon oxide layer 302 to peel device 303 from substrate 301 as an example, substrate 301 on which device 303 is processed is immersed in an etching solution, and the etching solution first etches away the exposed silicon oxide in a direction perpendicular to substrate 301, and then etches away silicon oxide layer 302 between substrate 301 and device 303. However, the thickness of silicon oxide layer 302 is only about 1 micron, and the reaction channel between etching solution and silicon oxide is only 1 micron, which means that it is necessary to soak in a strong acid etching solution such as hydrofluoric acid for more than 4 hours to completely etch away silicon oxide at the bottom of device 303, so as to completely peel device 303 from substrate 301. The process time of this peeling method is too long, and device 303 is immersed in hydrofluoric acid solution for a long time, which is prone to over-corrosion damage, resulting in a decrease in yield, affecting the structural integrity and device design performance of thick copper high-frequency and high-speed devices.

[0060] In view of this, the present application provides a device preparation method, please refer to Figure 4 , Figure 4 This is a flow chart of the device preparation method in the embodiment of the present application, including:

[0061] S401, forming a groove on one side of the substrate, and filling the groove with a first sacrificial layer. The substrate may be made of silicon, glass, etc., which is not limited here.

[0062] S402 , forming a second sacrificial layer on a side of the first sacrificial layer away from the groove, wherein the orthographic projection of the first sacrificial layer on the bottom surface of the substrate is within the range of the orthographic projection of the second sacrificial layer on the bottom surface of the substrate.

[0063] S403 , forming a device layer on a side of the second sacrificial layer away from the groove, wherein an orthographic projection of the device layer on the substrate is at least partially located in the groove.

[0064] S404 , etching the first sacrificial layer and the second sacrificial layer to peel the device layer off the substrate.

[0065] The device preparation method provided in the embodiment of the present application increases the distance between the substrate and the device by processing a groove on the substrate, so that when the first sacrificial layer is etched to separate the device layer and the substrate, there is a larger etching channel, so as to increase the etching rate of the first sacrificial layer, speed up the stripping speed of the device layer, reduce the damage to the device layer caused by the etching process conditions, and thus improve the device yield.

[0066] Take the wet etching process to remove the sacrificial layer as an example. Figure 3In the prior art shown, there is only a layer of silicon oxide of about 1 micron between the device and the substrate. It takes more than 4 hours to wet-etch the silicon oxide using hydrofluoric acid. Too long a time will also reduce the device yield.

[0067] By adopting the method provided in the embodiment of the present application, the distance between the device layer and the substrate is increased by filling the first sacrificial layer in the groove. When wet etching is used to remove the first sacrificial layer, a wider reaction channel is provided between the device layer and the substrate, thereby accelerating the peeling speed of the device layer and the substrate and reducing the damage to the device layer caused by the etching process conditions.

[0068] For example, when performing S401, dry etching, such as plasma etching, can be used to form a layer such as Figure 5 The groove 502 shown in the figure is used to extend the distance between the device and the substrate 501, so as to increase the reaction channel of the S404 etching process and accelerate the device stripping speed. Then, a first sacrificial layer 601 is filled in the groove 502 by a chemical vapor deposition process, as shown in FIG. Figure 6 When S402 is executed, a second sacrificial layer 701 is deposited on a side of the first sacrificial layer 601 away from the groove 502 by using a chemical vapor deposition process, as shown in FIG. Figure 7 When S403 is executed, a device layer 801 is formed on a side of the second sacrificial layer 701 away from the groove 502 by using a chemical vapor deposition process, as shown in FIG. Figure 8 shown.

[0069] In some optional implementations, the operation of performing S304 specifically includes: firstly etching at least the second sacrificial layer 701 not covered by the device layer 801 to expose a partial area of ​​the first sacrificial layer 601, such as Fig. 9 Then, the first sacrificial layer 601 is etched to peel the device layer 801 from the substrate 501 , as shown in FIG10 .

[0070] It can be understood that the purpose of etching the second sacrificial layer 701 not covered by the device layer 801 is to expose the second sacrificial layer 701, so there is no need to etch the second sacrificial layer 701 covered by the device layer 801, otherwise it will take a long time and the device layer 801 will be easily damaged by hydrofluoric acid. Finally, the first sacrificial layer 601 adhered to the device layer 801 is etched to obtain the device layer 801.

[0071] Compared with the prior art, the present application increases the distance between the device layer 801 and the substrate 501 by providing the groove 502 and the first sacrificial layer 601. When the first sacrificial layer 601 is etched with an etching solution, compared with the prior art, the first sacrificial layer 601 is etched with an etching solution. Figure 3As shown in the silicon oxide layer 302 , the etching solution of the present application has a larger contact area with the first sacrificial layer 601 , thereby shortening the etching time, reducing the time the device is immersed in the etching solution, and improving the yield of the device layer 801 .

[0072] The material of the second sacrificial layer 701 includes silicon oxide, which is not limited here. Exemplarily, the second sacrificial layer 701 is silicon oxide, and a 1-micron-thick silicon oxide film, i.e., the second sacrificial layer 701, is deposited on the side of the first sacrificial layer 601 away from the groove 502 by a chemical vapor deposition process. When performing the operation of S304, hydrofluoric acid is used as an etching solution to etch the second sacrificial layer 701 that is not covered by the device layer 801. For a 1-micron-thick silicon oxide film as the second sacrificial layer 701, it can be completely etched by the hydrofluoric acid solution in about 5 to 10 minutes. After the device layer 801 is separated from the substrate 501, hydrofluoric acid is still used to etch the second sacrificial layer 701 adhered to the device to obtain a complete device layer. After washing with deionized water, drying can complete the complete stripping of high-frequency and high-speed devices, and then the subsequent processes such as surface mounting, bonding interconnection, and packaging testing of board-level packaging can be carried out to complete the board-level packaging integration of high-frequency and high-speed modules.

[0073] In some optional embodiments, an etching solution is used to etch the first sacrificial layer 601. The first sacrificial layer 601 may be made of silicon oxide, and the corresponding etching solution may be hydrofluoric acid. Although the prior art also uses hydrofluoric acid to etch the silicon oxide between the device and the substrate, the present application increases the reaction channel of hydrofluoric acid and silicon oxide by providing a groove 502 structure, thereby increasing the etching efficiency to a certain extent, shortening the etching time, and further shortening the time the device is immersed in hydrofluoric acid, thereby improving the yield of the device.

[0074] In some other embodiments, the material of the first sacrificial layer 601 includes at least one of simple substances, oxides and hydroxides of magnesium, aluminum, zinc, iron, nickel and calcium, and the etching solution includes a non-oxidizing acid solution.

[0075] The first sacrificial layer 601 uses an active metal, and the etching solution uses a non-oxidizing acid. The two have a faster reaction speed. The non-oxidizing acid can be dilute hydrochloric acid, dilute sulfuric acid, acetic acid, oxalic acid, etc., which are dilute acids that do not have strong oxidizing properties for metals, and are less damaging to the device than hydrofluoric acid. Therefore, compared with the prior art, the present application shortens the time for separating the device layer 801 and the substrate 501, and improves the yield of the device.

[0076] It is understandable that the material of the substrate is not limited to silicon wafers, but should also include various types of substrates such as glass, PCB, ceramic substrates, etc., and the stripping process only needs to be appropriately changed according to the changes in the substrate material.

[0077] When performing the operation of S404, after etching the second sacrificial layer 701 not covered by the device layer 801, the device is immersed in the above-mentioned dilute acid, and the metal filled in the groove 502 is dissolved by the dilute acid, and the fast device layer 801 is completely peeled off from the substrate 501. The metal reacts quickly with the dilute acid, and the device layer 801 and the substrate 501 can be separated in about 20 minutes. In addition to the time for removing the second characteristic layer, compared with the prior art, the time required for device layer peeling can still be shortened to less than 30% of the prior device peeling time.

[0078] Alternatively, the material of the first sacrificial layer 601 includes at least one of a simple substance, oxide and hydroxide of aluminum and zinc, and the etching solution includes an alkaline solution.

[0079] The alkaline solution may also be a weak alkaline solution, and the first sacrificial layer 601 may be made of a neutral metal, so as to reduce damage to the device while ensuring efficient peeling of the device from the substrate 501 .

[0080] It is understandable that the etching solution can be a new solution that is less damaging to the device instead of the traditional strong acid solution, and the corresponding configuration can be a material that can react with the new solution or is easily soluble in the new solution as the first sacrificial layer 601. Exemplarily, the first sacrificial layer 601 can be made of sodium chloride, and the etching solution can be water, which can greatly reduce the damage of the etching solution to the device.

[0081] In the prior art, when using hydrofluoric acid etching such as Figure 3 When the silicon oxide layer 302 is hydrogenated as shown, the generated by-products are discharged from the channels that have been etched, and the unreacted hydrofluoric acid needs to contact the unreacted silicon oxide layer 302 through the channels that have been etched. Since there is only a gap of about 1 micron between the device 303 and the substrate 301, the by-products are blocked by the hydrofluoric acid and the discharge speed is very slow. The hydrofluoric acid is blocked by the by-products and it is difficult to contact the unreacted silicon oxide. Therefore, it takes a long time to completely peel off the device 303 and the substrate 301.

[0082] In the embodiment of the present application, the distance between the device layer 801 and the substrate 501 is widened by machining the groove 502 on the substrate 501. Even if the first sacrificial layer 601 and the second sacrificial layer 701 are both made of silicon oxide, during the process of etching the silicon oxide with hydrofluoric acid, the by-products can be discharged faster from the wider channel, and the hydrofluoric acid can enter from the wider channel. Even if the two block each other, the widened channel can ensure that enough hydrofluoric acid and silicon oxide are in full contact and react, so the time for separating the device layer 801 from the substrate 501 can be shortened, thereby ensuring the yield of the device layer 801.

[0083] In some optional embodiments, such as Fig.11As shown, the orthographic projection of the device layer 801 on the bottom surface of the substrate 501 is the first projection area 1101, the orthographic projection of the groove 502 on the bottom surface of the substrate 501 is the second projection area 1102, the first projection area 1101 is located within the range of the second projection area 1102, and there is a spacing area between the boundary of the first projection area 1101 and the boundary of the second projection area 1102.

[0084] It is understandable that the groove structure is a geometric extension of the bottom pattern of the device layer on the substrate. Therefore, the pattern of the second projection area 1102 is extended with the shape of the first projection area 1101, and is not limited to rectangles such as rectangles or squares, but also includes various geometric shapes, such as trapezoids, triangles, circles, etc.

[0085] Exemplarily, the first projection area 1101 is a rectangular area, whose width in the X direction is X0 and whose width in the Y direction is Y0, wherein the X direction is the short axis direction and the Y direction is the long axis direction. The second projection area 1102 is based on the first projection area 1101, and is expanded by ΔX in the X direction and ΔY in the Y direction to form a ring-shaped spacing area. It can be understood that Fig.15 The shapes of the first projection area 1101, the second projection area 1102 and the spacing area are for illustration only and are not intended to be limiting.

[0086] The ratio of the width of the spacing area to the width of the first projection area 1101, that is, the extension width, is 1% to 10%. Fig.15 As shown, the extension amplitude of the second projection area 1102 compared with the first projection area 1101 is the ratio of ΔX to X0, and the extension amplitude of the second projection area 1102 compared with the first projection area 1101 is the ratio of ΔY to Y0.

[0087] The width of the spacing area represents the extension of the groove 502 compared to the device layer 801. Through comparative experiments, it is determined that when the depth of the groove 502 is fixed, the time required to peel the device layer 801 and the substrate 501 by using a wet etching process when the width of the groove 502 is different. The results are as follows: Fig.12 shown. Fig.12 The curve of the relationship between the extension amplitude and the stripping time given is conducive to optimizing the lateral widening size of the groove and implementing it in the layout production, photolithography mask production and manufacturing process, which is conducive to exploring the shortest stripping process time for thick copper high-frequency and high-speed devices.

[0088] Taking the first sacrificial layer 601 as an example, in which a metal is used and the first sacrificial layer 601 is etched with a dilute acid solution, in the range of 1% to 4% of the extension amplitude, the shortest process time is required to completely peel the device layer 801 from the substrate 501, which is 25.5 minutes. When the extension amplitude is other than 25.5 minutes, the process time required to completely peel the device layer 801 from the substrate 501 is greater than 25.5 minutes.

[0089] It can be explained that when the extension amplitude is less than 4%, the chemical reaction channel between the metal and the dilute acid solution is small, and the transport speed of the dissolution reaction is limited by the size of the reaction channel, rather than the chemical reaction speed. When the extension amplitude is greater than 4%, the reaction channel becomes larger, and the transport speed of the dissolution reaction is no longer limited by the size of the reaction channel, but by the chemical reaction speed.

[0090] In some optional embodiments, in a direction perpendicular to the bottom surface of the substrate 501, the height of the first sacrificial layer 601 is the same as the depth of the groove 502. Exemplarily, the first sacrificial layer 601 is deposited by physical vapor deposition to fill the groove 502. Then, the first sacrificial layer 601 is polished by chemical mechanical polishing technology until the top of the groove 502 is flush with the top surface of the substrate 501, so that the first sacrificial layer 601 is embedded in the groove 502.

[0091] In some optional embodiments, along a direction perpendicular to the bottom surface of the substrate 501 , the depth of the groove 502 is greater than or equal to 8 micrometers and less than the thickness of the substrate 501 .

[0092] The depth of the groove 502 determines the thickness of the second sacrificial layer 701, and thus affects the wet etching rate to a certain extent. The depth of the groove 502 is smaller than the thickness of the substrate 501 to ensure that the substrate 501 can be reused. If the groove 502 penetrates the substrate 501, after the device layer 801 is peeled off, the groove 502 lacks the required bottom, and it is difficult to directly form the first sacrificial layer 601 again in the groove 502, but it is necessary to increase the process and increase the cost. Still taking the first sacrificial layer 601 as a metal and etching the first sacrificial layer 601 with a dilute acid solution as an example, a comparative experiment is conducted to determine the time required to peel the device layer 801 and the substrate 501 using a wet etching process when the depth of the groove 502 is different under the condition that the outward extension amplitude of the groove 502 is fixed.

[0093] like Fig.13 As shown, when the extension amplitude x% is a fixed value of 4%, when the depth Z of the groove 502 is 12 microns, the process time required for the device layer 801 to be completely peeled off from the substrate 501 is 24.1 minutes. When the depth Z of the groove 502 is larger or smaller than 12 microns, the process time required for the device layer 801 to be completely peeled off from the substrate 501 is longer than 24.1 minutes.

[0094] Understandably, Fig.13 The relationship curve between groove attempt and stripping time is helpful to optimize the longitudinal depth dimension of the groove and implement it into the manufacturing process (as long as it is the etching depth of the substrate), which is conducive to exploring the shortest stripping process time for thick copper high-frequency and high-speed devices.

[0095] This indicates that when the depth Z of the groove 502 is less than 12 microns, the chemical reaction channel between the metal and the dilute acid solution is small, and the transport speed of the dissolution reaction is limited by the size of the reaction channel, rather than the chemical reaction speed. When the depth Z of the groove 502 is greater than 12 microns, the reaction channel becomes larger, and the transport speed of the dissolution reaction is no longer limited by the size of the reaction channel, but by the chemical reaction speed.

[0096] According to the above comparative experimental results, in the embodiment of the present application, the outer extension amplitude of the groove 502 is preferably 4%, and the depth is 12 microns, that is, the ratio of the width of the spacing area to the width of the first projection area is 4%. At this time, the process time required for the device layer 801 to be completely peeled off from the substrate 501 is about 25 minutes. Compared with the prior art, the peeling time of more than 4 hours required to prepare thick copper high-frequency and high-speed devices on a silicon oxide film with a thickness of about 1 micron and then completely peel off from the silicon wafer substrate is greatly shortened, thereby avoiding damage to the device and improving the device yield.

[0097] It can be understood that the technical solution provided in the embodiment of the present application is that under the condition that the first sacrificial layer 601 is made of metal and the corresponding etching solution is made of dilute acid solution, the immersion process in the hydrofluoric acid solution is divided into two times, the first time is that the hydrofluoric acid dissolves the silicon oxide film (second sacrificial layer 701) with a thickness of about 1 micron exposed on the substrate 501, and the second time is that after the device layer 801 is stripped from the substrate 501, the hydrofluoric acid dissolves the residual silicon oxide film (second sacrificial layer 701) with a thickness of about 1 micron adhered to the bottom of the device layer 801. In this way, the total time that the device layer 801 needs to be immersed in hydrofluoric acid is less than 20 minutes, and the silicon oxide film (i.e., the second sacrificial layer 701) with a thickness of 1 micron can be completely removed. When the metal sacrificial layer (i.e., the first sacrificial layer 601) is dissolved and removed in dilute acid, the process time can be optimized to within 25 minutes, thereby optimizing the process time for completely stripping the device layer 801 from the substrate 501 to within 1 hour, which not only shortens the process time, but also improves the yield of the device layer.

[0098] The device layer 801 is immersed in hydrofluoric acid solution twice. For a silicon oxide layer with a thickness of about 1 micron, the immersion time only takes 5 to 10 minutes. Therefore, the total immersion time of the device layer 801 in hydrofluoric acid is less than 20 minutes, and the 1 micron thick silicon oxide film can be completely removed. When the first metallic sacrificial layer 601 is dissolved and removed in dilute acid, the process time can be optimized to less than 25 minutes due to the fast reaction speed between the dilute acid and the metal and the large reaction channel.

[0099] In this way, the device can be completely peeled off from the silicon substrate within a total immersion time of no more than 45 minutes in hydrofluoric acid and dilute acid solution. This is more than 2 hours shorter than the prior art, which requires immersion in highly active hydrofluoric acid for more than 4 hours, or more than 240 minutes, to completely peel the device off from the silicon substrate.

[0100] In some optional embodiments, the width of the groove 502 increases or remains unchanged along the direction from the substrate 501 to the device layer 801. When the device preparation method provided in the embodiment of the present application is applied to the preparation of thick copper high-frequency and high-speed devices, the core is to add a groove structure filled with a metal sacrificial layer at the bottom of the thick copper high-frequency and high-speed devices. The groove filled with the metal sacrificial layer is characterized in that the groove is two-dimensionally expanded on the surface of the silicon wafer substrate along the size of the bottom structure of the thick copper high-frequency and high-speed device on the wafer.

[0101] In some optional embodiments, the sidewall of the groove 502 is stepped. The stepped groove 502 further increases the reaction rate, accelerates the release, and shortens the reaction time.

[0102] like Fig.14 As shown, the stepped groove 502 includes a first shallow groove 1401, a second shallow groove 1402, and a third shallow groove 1403 which are arranged in sequence along a direction perpendicular to the bottom surface of the substrate 501 and from the device layer 801 to the substrate 501. When performing the S401 operation, the first shallow groove 1401 is first processed from a position flush with the surface of the substrate 501, and then the second shallow groove 1402 is processed at the bottom of the first shallow groove 1401, and finally the third shallow groove 1403 is processed at the bottom of the second shallow groove 1402.

[0103] When the groove is Fig.14 When the step-shaped structure is shown in FIG. 1 , after executing the operation of S403, the structure shown in FIG. 1 is formed. Fig.15 In the structure shown in FIG. 1 , when executing the operation of S404, first Fig.15 The second sacrificial layer 701 not covered by the device layer 801 is etched to expose a partial area of ​​the first sacrificial layer 601 in the first shallow groove 1401, and then the first sacrificial layer 601 is etched to peel the device layer 801 from the substrate 501, and finally the first sacrificial layer 601 remaining on the bottom surface of the device layer 801 is removed to obtain a device.

[0104] The widths of the first shallow groove 1401, the second shallow groove 1402, and the third shallow groove 1403 decrease in sequence, forming a gradient groove structure that becomes narrower as it goes deeper, formed by stacking multiple shallow grooves with decreasing bottom areas. Fig.15As shown, the orthographic projection of the first shallow groove 1401 on the bottom surface of the substrate 501 is extended by a width ΔX1 and a depth Z1 compared to the orthographic projection of the device layer 801 on the bottom surface of the substrate 501; the orthographic projection of the second shallow groove 1402 on the bottom surface of the substrate 501 is extended by a width ΔX2 and a depth Z2 compared to the orthographic projection of the device layer 801 on the bottom surface of the substrate 501; the orthographic projection of the third shallow groove 1403 on the bottom surface of the substrate 501 is extended by a width ΔX3 and a depth Z3 compared to the orthographic projection of the device layer 801 on the bottom surface of the substrate 501. Among them, ΔX1>ΔX2>ΔX3.

[0105] It can be understood that the specific sizes of ΔX1, ΔX2, and ΔX3 can be determined according to the extension amplitude of the groove compared to the device layer 801. For example, if the size of the device layer 801 is 8 microns and the extension amplitude is 4%, then ΔX1 is 0.32 microns, ΔX2 can be 0.30 microns, and ΔX3 can be 0.26 microns. The sum of Z1, Z2, and Z3 is equivalent to the depth of the groove 502. When the depth Z of the groove 502 is 9 microns, the inner wall of the groove 4 can be divided into three steps in height, that is, Z1 is 3 microns, Z2 is 3 microns, and Z3 is 3 microns.

[0106] The sidewall of the groove 502 may also be Fig.16 As shown in the cone. Or Figure 5 As shown, the sidewall and bottom of the groove 502 are vertical, and the width of the groove 502 is constant. Fig.14 When the step-shaped structure is shown, the stripping rate is faster than the structure with a constant width of the groove 502. This is because when the width of the groove 502 is constant, it is in a rectangular shape. Compared with the step-shaped structure, the rectangular groove 502 is filled with more first sacrificial layer. When the first sacrificial layer is removed by etching solution, the reaction time required is longer. Experiments have shown that under the conditions of the same depth and opening area, the step-shaped groove can reduce the process time by at least 1 minute compared with the rectangular groove.

[0107] In some optional implementations, before etching the first sacrificial layer and the second sacrificial layer, the process further includes: forming a protective layer outside the side of the device layer 801 away from the substrate 501, the protective layer covering the side of the device layer 801 and the side of the device layer 801 away from the substrate 501. After removing the sacrificial layer by wet etching, the process further includes: removing the protective layer.

[0108] By protecting the device layer 801 with the protective layer, it is possible to prevent the etching solution from damaging the device layer 801 during the etching process, thereby further ensuring the yield of the device layer 801 .

[0109] The device layer 801 can be prepared using a micro-electromechanical system (MEMS) process, and its structure can be as follows: Figure 1In the structure shown, an inner conductor 102 and a dielectric support structure 103 supporting the inner conductor 102 are added to a rectangular outer conductor metal frame 101. The outer conductor and the inner conductor can be made of copper, which is not limited here.

[0110] In summary, the technical solution provided by the present application is applicable to the field of board-level packaging technology. On the basis of substrate materials such as substrate silicon wafers, grooves filled with metal sacrificial materials are made, and then thick copper high-frequency and high-speed devices are prepared. After the thick copper high-frequency and high-speed devices are completed, the metal sacrificial materials are wet-etched to release the groove structure, and the thick copper high-frequency and high-speed devices made of the substrate material as the base are completely peeled off from the substrate. After the peeling is completed, the detached thick copper high-frequency and high-speed devices need to be cleaned of residues and dried. After that, the thick copper high-frequency and high-speed devices can be surface mounted, bonded, interconnected, and packaged and integrated into the board-level system to realize the preparation of integrated modules of board-level high-frequency and high-speed systems. In the era of system integration module technology for large models such as AI and high-speed processing of big data, in the era of 6G communication and ultra-high frequency interconnection and intercommunication of electromagnetic signals, the substrate peeling technology of thick copper high-frequency and high-speed devices for board-level packaging provides technical possibilities for the free combination of thick copper high-frequency and high-speed devices, thereby realizing system integration, and has important practical value.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0112] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

Claims

1. A device preparation method, It is characterized in that include: forming a groove on one side of the substrate and filling the groove with a first sacrificial layer; forming a second sacrificial layer on a side of the first sacrificial layer away from the groove, wherein the orthographic projection of the first sacrificial layer on the bottom surface of the substrate is within the range of the orthographic projection of the second sacrificial layer on the bottom surface of the substrate; forming a device layer on a side of the second sacrificial layer away from the groove, wherein an orthographic projection of the device layer on the substrate is at least partially located in the groove; The first sacrificial layer and the second sacrificial layer are etched to peel the device layer from the substrate.

2. The device preparation method according to claim 1, It is characterized in that In a direction perpendicular to the bottom surface of the substrate, a height of the first sacrificial layer is the same as a depth of the groove.

3. The device preparation method according to claim 2, It is characterized in that The etching of the first sacrificial layer and the second sacrificial layer to peel the device layer off the substrate includes: Etching at least the second sacrificial layer not covered by the device layer to expose a partial area of ​​the first sacrificial layer; The first sacrificial layer is etched to peel the device layer from the substrate.

4. The device preparation method according to claim 3, It is characterized in that After the device layer is peeled off from the substrate, the method further comprises: The first sacrificial layer remaining on the bottom surface of the device layer is removed to obtain a device.

5. The device preparation method according to claim 3, It is characterized in that The etching of the first sacrificial layer comprises: Etching the first sacrificial layer using an etching solution; Wherein, the material of the first sacrificial layer includes at least one of a single substance, oxide and hydroxide of magnesium, aluminum, zinc, iron, nickel or calcium, and the etching solution includes a non-oxidizing acid solution; Alternatively, the material of the first sacrificial layer includes at least one of a simple substance, an oxide, and a hydroxide of aluminum or zinc, and the etching solution includes an alkaline solution; Alternatively, the material of the first sacrificial layer includes silicon oxide, and the etching solution includes hydrofluoric acid.

6. The device preparation method according to claim 1, It is characterized in that The orthographic projection of the device layer on the bottom surface of the substrate is a first projection area, the orthographic projection of the groove on the bottom surface of the substrate is a second projection area, the first projection area is located within the range of the second projection area, and there is a spacing area between the boundary of the first projection area and the boundary of the second projection area; the ratio of the width of the spacing area to the width of the first projection area is 1% to 10%.

7. The device preparation method according to claim 1, It is characterized in that Along a direction perpendicular to the bottom surface of the substrate, the depth of the groove is greater than or equal to 8 micrometers and less than the thickness of the substrate.

8. The device preparation method according to claim 1, It is characterized in that The width of the groove increases or remains unchanged along the direction from the substrate to the device layer.

9. The device preparation method according to claim 1, It is characterized in that The side wall of the groove is stepped.

10. The device preparation method according to claim 1, It is characterized in that Before etching the first sacrificial layer and the second sacrificial layer, the method further includes: forming a protective layer outside the device layer on a side away from the substrate, wherein the protective layer covers the side of the device layer and the side of the device layer on a side away from the substrate; After removing the sacrificial layer by a wet etching process, the method further comprises: The protective layer is removed.

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