MEMS chip preparation process based on double piezoelectric layers

Abstract

The invention relates to the technical field of semiconductor processes, in particular to an MEMS (Micro Electro Mechanical System) chip preparation process based on double piezoelectric layers, which comprises the following steps of: preparing a substrate, and sequentially growing metal layers and piezoelectric layers at intervals; etching the uppermost metal layer and the uppermost piezoelectric layer; growing a first isolation layer on the surfaces of the middle metal layer and the uppermost metal layer; etching the first isolation layer; etching the middle metal layer, the lowermost piezoelectric layer and the lowermost metal layer; growing a second isolation layer on the surface of the substrate and the surface of the lowermost metal layer; etching the second isolation layer; the first isolation layer is etched, so that the metal layer needing to be electrically connected and communicated is exposed; and growing a metal connecting layer on the surface of the metal layer, etching the metal connecting layer, patterning the metal connecting layer, and isolating the metal connecting layer through an isolating layer, so that the metal layers are mutually communicated in pairs, and circuits are independent and are not associated with each other. According to the invention, on a chip with double piezoelectric layers, the three metal layers can be independently interconnected in pairs, the device configuration is enriched, and the application range of the chip is expanded.

Description

Technical Field

[0001] One or more embodiments of the present specification relate to the field of semiconductor process technology, and in particular, to a MEMS chip preparation process based on a double piezoelectric layer. Background Art

[0002] At present, wafers with double piezoelectric layers have greatly enriched the structural design of piezoelectric MEMS devices. In the double piezoelectric layer structure, there are two piezoelectric layers and three metal layers. In some special structural designs, these three metal layers need to be independently interconnected to achieve the required device configuration. Therefore, a MEMS chip preparation process based on a double piezoelectric layer is proposed to achieve the above requirements and solve the above problems. Summary of the invention

[0003] The present invention aims to solve the problems raised in the background technology. The purpose of one or more embodiments of this specification is to propose a MEMS chip preparation process based on a double-layer piezoelectric layer, which can realize independent interconnection of three metal layers in pairs on a double-layer piezoelectric layer chip, enrich the device configuration, and expand the application scope of the chip.

[0004] Based on the above purpose, one or more embodiments of the present specification provide a MEMS chip preparation process based on a double-layer piezoelectric layer, including the following steps: preparing a substrate, the substrate having a relative front and back side, and growing a metal layer and a piezoelectric layer in sequence on the front side of the substrate; etching the top metal layer to pattern the top metal layer; etching the top piezoelectric layer to pattern the top piezoelectric layer; growing a first isolation layer on the surface of the middle metal layer and the top metal layer; etching the first isolation layer to pattern the first isolation layer; etching the middle metal layer The method comprises the following steps: etching the bottom piezoelectric layer to pattern the bottom piezoelectric layer; etching the bottom metal layer to pattern the bottom metal layer; growing a second isolation layer on the surface of the substrate and the surface of the bottom metal layer; etching the second isolation layer to pattern the second isolation layer, etching the first isolation layer to expose the metal layer that needs to be electrically connected; growing a metal connection layer on the surface of the metal layer, etching the metal connection layer to pattern the metal connection layer, and isolating the metal layers through the isolation layer so that the metal layers are interconnected and the circuits are independent and unrelated to each other.

[0005] According to the MEMS chip preparation process based on double piezoelectric layers described in the embodiment of the present invention, the isolation layer includes one or a combination of silicon nitride, silicon oxide or aluminum oxide.

[0006] According to the MEMS chip preparation process based on double piezoelectric layers described in the embodiment of the present invention, the substrate is a silicon substrate.

[0007] According to the MEMS chip preparation process based on double piezoelectric layers described in the embodiment of the present invention, the substrate is an SOI substrate.

[0008] The beneficial effects of the present invention are described in detail below with reference to the embodiments and drawings of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate one or more embodiments of the present specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 A schematic diagram of step S1 in a MEMS chip preparation process based on a double-layer piezoelectric layer proposed in an embodiment of the present invention;

[0011] Figure 2-3 A schematic diagram of step S2 in the MEMS chip preparation process based on a double-layer piezoelectric layer proposed in an embodiment of the present invention;

[0012] Figure 4 A schematic diagram of step S3 in the MEMS chip preparation process based on a double-layer piezoelectric layer proposed in an embodiment of the present invention;

[0013] Figure 5-7 A schematic diagram of step S4 in the MEMS chip preparation process based on a double-layer piezoelectric layer proposed in an embodiment of the present invention;

[0014] Figure 8 A schematic diagram of step S5 in the MEMS chip preparation process based on a double-layer piezoelectric layer proposed in an embodiment of the present invention;

[0015] Fig. 9 This is a schematic diagram of step S6 in the MEMS chip preparation process based on a double piezoelectric layer proposed in an embodiment of the present invention.

[0016] In the figure numerals: 1. substrate; 2. first metal layer; 3. first piezoelectric layer; 4. second metal layer; 5. second piezoelectric layer; 6. third metal layer; 7. first isolation layer; 8. second isolation layer; 9. metal connection layer. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments.

[0018] According to the following Figure 1-Figure 6 The specific process of the MEMS chip preparation process based on the double piezoelectric layer in the embodiment of the present invention is described.

[0019] The MEMS chip manufacturing process based on the double piezoelectric layer proposed in the embodiment of the present invention includes the following steps:

[0020] S1, such as Figure 1 As shown, a substrate 1 is prepared, the substrate 1 has a relative front side and a back side, a first metal layer 2 is grown on the front side of the substrate, a first piezoelectric layer 3 is grown on a plane of the first metal layer 2 away from the substrate, a second metal layer 4 is grown on a plane of the first piezoelectric layer 3 away from the substrate 1, a second piezoelectric layer 5 is grown on a plane of the second metal layer 4 away from the substrate 1, and a third metal layer 6 is grown on a plane of the second piezoelectric layer 5 away from the substrate 1. Optionally, the substrate 1 is a silicon substrate. Optionally, the substrate 1 is an SOI substrate consisting of bottom silicon and top silicon connected by a buried oxide layer.

[0021] S2-1, such as Figure 2 As shown, the third metal layer 6 is etched to pattern the third metal layer 6 to form structures 6a and 6b.

[0022] S2-2, such as Figure 3 As shown, the second piezoelectric layer 5 is etched to be patterned to form a structure 5a corresponding to the structure 6a and a structure 5b corresponding to the structure 6b.

[0023] S3, such as Figure 4 As shown, a first isolation layer 7 is grown on a plane of the second metal layer 4 away from the substrate and a plane of the third metal layer 6 away from the substrate, and the first isolation layer 7 is etched to be patterned to form a structure 7c grown on the surface of the second metal layer 4, a structure 7b that completely wraps the structure 5b and the structure 6b, and a structure 7a that completely wraps the structure 5a and the structure 6a.

[0024] S4-1, such as Figure 5 As shown, the second metal layer 4 is etched to be patterned to form a structure 4a corresponding to the structure 5a, a structure 4b corresponding to the structure 5b, and a structure 4c corresponding to the structure 5c.

[0025] S4-2, such as Figure 6 As shown, the first piezoelectric layer 3 is etched to be patterned to form a structure 3a corresponding to the structure 4a, a structure 3b corresponding to the structure 4b, and a structure 3c corresponding to the structure 4c.

[0026] S4-3, such as Figure 7 As shown, the first metal layer 2 is etched to pattern the first metal layer 2 to form a structure 2a corresponding to the structure 3a, a structure 2b corresponding to the structure 3b, and a structure 2c corresponding to the structure 3c.

[0027] S5-1, such as Figure 8As shown, the second isolation layer 8 is grown in the gaps generated by the patterning in steps S1-S4, and the second isolation layer 8 is etched to pattern the second isolation layer 8, so that the second isolation layer 8 forms structures 8a, 8b, 8c, 8d and 8e.

[0028] S5-2, such as Figure 8 As shown, structure 7a is etched to expose part of the area of ​​structure 6a and part of the area of ​​structure 4a, structure 7b and structure 8c are etched to expose part of the area of ​​structure 6b and part of the area of ​​structure 2b, and structure 7a is etched to expose part of the area of ​​structure 6a and part of the area of ​​structure 5a.

[0029] S6, such as Fig. 9 As shown, a metal connection layer 9 is grown on the surfaces of the first metal layer 2, the second metal layer 4 and the third metal layer 6, and the metal connection layer 9 is etched to pattern the metal connection layer 9 to form a structure 9c electrically connecting the structure 4c and the structure 2c, a structure 9b electrically connecting the structure 6b and the structure 2b, and a structure 9a electrically connecting the structure 6a and the structure 4a. The structures 9a, 9b and 9c are independent of each other, and the circuits are not related to each other.

[0030] One or more embodiments of this specification are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of this disclosure.

Claims

1. A MEMS chip preparation process based on a double piezoelectric layer, characterized in that: The following steps are involved: A substrate (1) is prepared, wherein the substrate (1) has a front side and a back side opposite to each other, and metal layers (2, 4, 6) and piezoelectric layers (3, 5) are sequentially grown at intervals on the front side of the substrate (1); Etching the uppermost metal layer (6) to pattern the uppermost metal layer (6); Etching the uppermost piezoelectric layer (5) to pattern the uppermost piezoelectric layer (5); Growing a first isolation layer (7) on the surfaces of the middle metal layer (4) and the uppermost metal layer (6); Etching the first isolation layer (7) to pattern the first isolation layer (7); Etching the intermediate metal layer (4) to pattern the intermediate metal layer (4); Etching the bottom piezoelectric layer (3) to pattern the bottom piezoelectric layer (3); Etching the bottom metal layer (2) to pattern the bottom metal layer (2); Growing a second isolation layer (8) on the surface of the substrate (1) and the surface of the bottom metal layer (2); Etching the second isolation layer (8) to pattern the second isolation layer (8), and etching the first isolation layer (7) to expose the metal layers (2, 4, 6) that need to be electrically connected; A metal connection layer (9) is grown on the surface of the metal layer (2, 4, 6), and the metal connection layer (9) is etched to pattern the metal connection layer (9), and the metal connection layer (9) is isolated by isolation layers (7, 8) so that the metal layers (2, 4, 6) are interconnected in pairs and the circuits are independent and unrelated to each other.

2. The MEMS chip preparation process based on double piezoelectric layers according to claim 1 is characterized in that: The isolation layer (7, 8) comprises one or a combination of silicon nitride, silicon oxide or aluminum oxide.

3. The MEMS chip preparation process based on double piezoelectric layers according to claim 1 is characterized in that: The substrate (1) is a silicon substrate.

4. The MEMS chip preparation process based on double piezoelectric layers according to claim 1 is characterized in that: The substrate (1) is an SOI substrate.

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