Capacitance detection circuit based on peak detection and measurement method thereof

Abstract

The invention provides a capacitance detection circuit based on peak detection and an operation method thereof. The circuit comprises a signal generation circuit (101), a signal conversion circuit (102), a peak detection circuit (103) and an analog-to-digital conversion circuit (104), the input end of the signal generation circuit is used for receiving a capacitor to be detected, the output end of the signal generation circuit is connected with the input end of the signal conversion circuit through the capacitor to be detected, the output end of the signal conversion circuit is connected with the input end of the peak detection circuit, and the output end of the peak detection circuit is connected with the input end of the analog-to-digital conversion circuit. And the digital-to-analog conversion circuit outputs a capacitance detection result. The capacitance detection circuit designed by the invention is simple in circuit structure, convenient and easy to construct, visual in circuit connection and low in overall power consumption of the system. Meanwhile, the circuit is easy to realize physically, and the analog-to-digital converter and the upper computer can be interconnected conveniently, so that the circuit can be applied to various occasions for measuring the capacitance conveniently.

Description

Technical Field

[0001] The invention relates to a capacitance detection circuit based on peak value detection and a measurement method thereof, belonging to the technical field of capacitance detection interface circuits. Background Art

[0002] The technical background of capacitance detection circuit involves many aspects, mainly including the working principle, application field, technical challenges and corresponding measurement circuit design and development of capacitance sensors. Capacitance sensors have important applications in many fields, including but not limited to: Industrial automation: used to detect the position, speed, acceleration and other parameters of mechanical parts to achieve precise control. Aerospace: plays a key role in the attitude control and navigation systems of aircraft, rockets and other equipment. Environmental monitoring: used to measure environmental parameters such as liquid level, humidity, gas concentration, etc. Biomedicine: used in medical equipment to detect physiological parameters of organisms, such as heartbeat, breathing, etc.

[0003] Although capacitive sensors have many advantages, they also face some technical challenges in practical applications: parasitic capacitance. In actual circuits, in addition to the capacitance of the sensor itself, there are various parasitic capacitances, which will interfere with the measurement results and reduce the measurement accuracy. Power supply voltage stability. The accuracy of the measurement results also depends on the stability of the power supply voltage. The fluctuation of the power supply voltage will directly affect the accuracy of the measurement results. Small capacitance detection. For the detection of small capacitance, high-precision measurement circuits and signal processing technologies are required to achieve high-sensitivity and high-resolution measurements.

[0004] In order to overcome the above technical challenges, researchers have designed a variety of capacitance detection circuits and continuously improved and optimized the performance of these circuits. Common capacitance detection circuits include: operational amplifier circuits, which use the high amplification factor and low noise characteristics of operational amplifiers to amplify and process capacitance signals. Bridge circuits, which convert capacitance changes into voltage or current changes by building a bridge circuit, making it easier to measure and record. Frequency modulation circuits, which convert capacitance changes into frequency changes, use the high precision of frequency measurement to improve measurement accuracy. Resonant circuits, which use a resonant circuit composed of a capacitor and an inductor to indirectly measure capacitance changes by measuring changes in the resonant frequency.

[0005] In addition, with the development of microelectronics technology and digital signal processing technology, capacitance detection circuits are also developing towards digitalization and intelligence. For example, digital intelligent capacitance sensors combine the measurement component technology with the calculation function of the microprocessor, making the measuring instrument to the control instrument a fully digital system, greatly improving the measurement accuracy and stability.

[0006] In short, the technical background of capacitance detection circuit involves many aspects, including the working principle of capacitance sensor, application field, technical challenges and the design and development of measurement circuit. With the continuous advancement and innovation of science and technology, the performance of capacitance detection circuit will continue to improve and perfect, providing more reliable and accurate technical support for various industrial measurement and automation control systems. The performance of capacitance sensor detection circuit determines the performance of the entire capacitance sensor link from natural signal to final signal processing, display and other results. It is one of the bottlenecks that capacitance sensor technology often needs to solve for its continued development. Therefore, people have always attached great importance to the design of capacitance sensor detection circuit.

[0007] To address this issue, this patent proposes a capacitance detection circuit based on peak detection and a measurement method thereof. Compared with other capacitance sensor interface circuits, it can not only complete capacitance detection, but also has excellent characteristics such as simple principle, small area, low power consumption and low noise. Summary of the invention

[0008] The present invention aims to solve the technical problems that the existing capacitance sensor cannot overcome the parasitic capacitance and has low measurement accuracy, and further proposes a capacitance detection circuit based on peak detection and a measurement method thereof.

[0009] The technical solution adopted by the present invention to solve the above problems is: the present invention proposes a capacitance detection circuit based on peak detection, comprising:

[0010] A signal generating circuit (101), a signal converting circuit (102), a peak value detecting circuit (103) and an analog-to-digital converting circuit (104);

[0011] The input end of the signal generating circuit (101) is used to receive the capacitance to be measured, the output end of the signal generating circuit (101) is connected to the input end of the signal conversion circuit (102) through the capacitance to be measured, the output end of the signal conversion circuit (102) is connected to the input end of the peak detection circuit (103), the output end of the peak detection circuit (103) is connected to the input end of the analog-to-digital conversion circuit (104), and the digital-to-analog conversion circuit outputs the capacitance detection result.

[0012] Optionally, the signal generating circuit (101) includes a sine wave module and an excitation signal module;

[0013] The sine wave module is used to obtain sine waves;

[0014] The excitation signal module obtains a sinusoidal excitation signal based on the obtained sinusoidal wave.

[0015] Optionally, the signal conversion circuit (102) is a low-noise charge transfer device including a three-stage amplification structure, which is used to amplify the sinusoidal excitation signal according to the conversion ratio of the capacitance value;

[0016] The first stage of the three-stage amplification structure is a five-tube OTA, the second stage is a folded common source and common gate structure, and the third stage is a common source stage.

[0017] Optionally, the peak detection circuit (103) is a transistor-level circuit, and the structure is a five-transistor OTA structure, which is used to collect voltage peak values ​​in real time.

[0018] Optionally, the analog-to-digital conversion circuit (104) includes: a sampling and holding circuit, a DAC capacitor array circuit, a comparator circuit and a SAR logic circuit;

[0019] The sample-and-hold circuit is a bootstrap switch circuit used to accurately sample the input signal under the control of a sampling clock;

[0020] The DAC capacitor array circuit is a fully differential segmented structure, which is used to store sampled information and is controlled by the SAR logic circuit to perform a successive approximation process;

[0021] The comparator circuit is a structure of pre-amplification plus latch dynamic comparator, which is used to compare the voltage levels at both ends of the input, thereby obtaining a quantized result through repeated comparisons.

[0022] The SAR logic circuit is composed of combinational logic and sequential logic circuits, which are used to store the comparison results of each time and control the potential conversion of the upper plate of the capacitor array according to the appropriate switching strategy.

[0023] A method for measuring a capacitance detection circuit based on peak detection, comprising:

[0024] Step 1: The signal generating circuit (101) outputs a sinusoidal excitation signal, and the output end of the signal generating circuit (101) is connected to the input end of the signal conversion circuit (102) via a capacitor to be measured;

[0025] Step 2: The signal conversion circuit (102) amplifies the input sinusoidal excitation signal according to the ratio of the capacitance value, connects the input end of the peak detection circuit (103) through the buffer circuit, and inputs the amplified sinusoidal excitation signal into the peak detection circuit (103);

[0026] Step 3: The voltage peak value of the amplified sinusoidal excitation signal is collected in real time through the peak detection circuit (103), the capacitance value of the capacitor to be measured is calculated based on the voltage peak value, and the capacitance value is transmitted to the analog-to-digital conversion circuit (104);

[0027] Step 4: The analog-to-digital conversion circuit (104) performs high-precision digitization on the input capacitance value and outputs the capacitance detection result;

[0028] The expression for amplifying the sinusoidal excitation signal according to the capacitance ratio is:

[0029]

[0030] In formula (1), V x is the amplified sinusoidal excitation signal, C f is the reference capacitor, V in is the peak value of the input sine wave, C x is the capacitance value of the capacitor to be tested;

[0031] The expression of the capacitance value of the capacitor to be measured is:

[0032]

[0033] In formula (2), V peakout is the peak value of the known sinusoidal excitation signal, V cm is a known common-mode level.

[0034] Optionally, in step 1, the frequency range of the sine wave in the sine excitation signal is 1 Hz-120 MHz, the frequencies of the sine excitation signal are 100 Hz, 1 KHz, 10 KHz and 100 KHz, and the frequency accuracy is 0.02%.

[0035] Optionally, the real-time acquisition of the sine peak value of the amplified sine excitation signal input in step 3 specifically includes:

[0036] The amplified sinusoidal excitation signal is used as the input voltage value Vip. When the input voltage value Vip is equal to the output voltage Vpeak, the current of NM2 flows equally through NM0 and NM1, and Vpeak charges the load capacitor Co to make the output voltage reach the Vpeak value; if Vip becomes larger, the current value of the NM0 branch will increase, and the excess current will be obtained from the PM2 branch. Through the current mirror effect, a downward current is generated in PM5, and the downward current charges Co, causing the Co voltage to increase. When the voltage value is equal to the input voltage Vip, the charging stops, the circuit returns to the equilibrium state, and the voltage peak value of the amplified sinusoidal excitation signal is obtained.

[0037] Optionally, the step of outputting the capacitance detection result in step 4 includes:

[0038] Step 4.1: Input the capacitance value of the capacitor as the input signal Vin into the analog-to-digital conversion circuit (104). The input signal Vin reaches the positive input terminal of the comparator circuit through the sampling and holding circuit. The highest bit MSB of the digital control SAR logic circuit is set to 1, and the remaining bits are cleared. Under the control of the SAR logic circuit and the reference voltage Vref, the DAC capacitor array circuit outputs 1 / 2Vref and sends it to the negative input terminal of the comparator. If Vin>1 / 2Vref, the output of the comparator circuit is 1, and the highest bit of the digital code is also 1; if Vin<1 / 2Vref, the output of the comparator circuit is 0, and the highest bit of the digital code is also 0;

[0039] Step 4.2: Set the second highest bit MSB of the numerical control SAR logic circuit to 1. If MSB = 1, the DAC capacitor array circuit output is 3 / 4Vref, and the second highest bit is determined by comparing Vin with 3 / 4Vref. If MSB = 0, the DAC capacitor array circuit output is 1 / 4Vref, and the second highest bit is determined by comparing Vin with 1 / 4Vref.

[0040] Step 4.3: Follow the logic of step 4.1 and step 4.2 until all digital codes of SAR are determined, the voltage peak is digitized, and the capacitance detection result is output.

[0041] The beneficial effects of the present invention are:

[0042] 1. The capacitance detection circuit designed in the present invention has high measurement accuracy and a resolution of more than 12 bits. The measurement accuracy is mainly restricted by the operational amplifier offset and the accuracy of the analog-to-digital conversion circuit.

[0043] 2. The high gain of the low-noise three-stage operational amplifier in the capacitance detection circuit designed by the present invention makes the closed-loop amplification high in precision, and the comparator in the final analog-to-digital converter uses offset storage technology to reduce offset, and redundant bits are added to the capacitor array to increase the final effective number of bits.

[0044] 3. The capacitance detection circuit designed by the present invention has a simple circuit structure, is easy to build, and has intuitive circuit connection, and has low power consumption for the entire system. At the same time, the circuit is easy to physically implement, and the final analog-to-digital converter and the host computer can be conveniently interconnected, which is convenient for application in a variety of capacitance measurement occasions.

[0045] 4. The analog-to-digital conversion circuit in the present invention has low power consumption and high speed, and can reach a sampling rate of 1MSPS. The frequency measured by the sensor at the front end of the general capacitor is relatively low. The rate of the analog-to-digital converter can digitize the output of the peak detection with high precision, and the measurement frequency range is wide, which can meet the Nyquist sampling theorem. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A logic block diagram of a capacitance detection circuit based on peak detection provided by the present invention;

[0047] Figure 2 A logic block diagram of a peak detection circuit provided by the present invention;

[0048] Figure 3 A logic block diagram of the analog-to-digital conversion circuit provided by the present invention;

[0049] Figure 4 A logic block diagram of a DAC capacitor array circuit in an analog-to-digital conversion circuit provided by the present invention;

[0050] Figure 5 The present invention provides a flow chart of a method for measuring a capacitance detection circuit based on peak detection. DETAILED DESCRIPTION

[0051] Specific implementation method 1: Combination Figure 1 The present embodiment is described. The structure of a capacitance detection circuit based on peak detection described in the present embodiment includes:

[0052] A signal generating circuit (101), a signal converting circuit (102), a peak value detecting circuit (103) and an analog-to-digital converting circuit (104);

[0053] The input end of the signal generating circuit (101) is used to receive the capacitance to be measured, the output end of the signal generating circuit (101) is connected to the input end of the signal conversion circuit (102) through the capacitance to be measured, the output end of the signal conversion circuit (102) is connected to the input end of the peak detection circuit (103), the output end of the peak detection is connected to the input end of the analog-to-digital conversion circuit (104), and the digital-to-analog conversion circuit outputs the capacitance detection result.

[0054] The capacitance detection circuit designed by the present invention has a simple structure, is easy to build, and has intuitive circuit connection, and has low power consumption for the entire system. At the same time, the circuit is easy to physically implement, and the final analog-to-digital converter and the host computer can be conveniently interconnected, which is convenient for application in a variety of capacitance measurement occasions.

[0055] The signal generating circuit (101) is implemented by an AD9854 board-level high-speed DDS module, and is capable of generating a sine wave in a frequency range of 1 Hz to 120 MHz, and using the sine wave to generate excitation signals of 100 Hz, 1 KHz, 10 KHz, and 100 KHz, with a frequency accuracy of 0.02%.

[0056] The signal conversion circuit (102) includes a low-noise charge amplifier, which amplifies the sinusoidal excitation signal according to the conversion ratio of the capacitance value, uses a three-stage amplification structure, and crosses the proportional capacitor to form a capacitance proportional amplification structure. The first stage of the three-stage operational amplifier is a five-tube OTA, the second stage is a folded common source and common gate structure, and the last stage is a common source stage. The input end of the capacitor voltage conversion circuit is connected to the output end of the signal generating circuit (101), and the output voltage of the capacitor voltage conversion circuit is connected to the input of the peak detection circuit (103) through a buffer circuit.

[0057] The peak detection circuit (103) is implemented by a transistor-level circuit, the main structure is similar to a five-transistor OTA structure, the input is fully differential, and the tail current is implemented by a current mirror replica current, and is used to collect the voltage peak in real time.

[0058] The analog-to-digital conversion circuit (104) is composed of a sampling and holding circuit, a comparator circuit, a SAR logic circuit and a DAC capacitor array circuit. The sampling and holding circuit is a bootstrap switch circuit, which is used to accurately sample the input signal under the control of a sampling clock; the DAC capacitor array circuit is a fully differential segmented structure, which is used to store the sampled information and to perform a successive approximation process under the control of the SAR logic circuit; the comparator circuit is a structure of a pre-amplifier plus a latch dynamic comparator, which is used to compare the voltage levels at both ends of the input, thereby obtaining a quantized result through repeated comparisons; the SAR logic circuit is composed of a combinational logic circuit and a sequential logic circuit, which is used to store each comparison result and control the conversion of the potential of the upper plate of the capacitor array according to a suitable switching strategy.

[0059] Specific implementation method 2: Combination Figure 2-5 This embodiment is described as follows. Figure 5 As shown, the steps of a measurement method of a capacitance detection circuit based on peak detection described in this embodiment include:

[0060] S1: the signal generating circuit (101) outputs a sinusoidal excitation signal, and the output end of the signal generating circuit (101) is connected to the input end of the signal conversion circuit (102) via a capacitor to be measured;

[0061] S101: The frequency range of the sine wave in the sine excitation signal is 1 Hz-120 MHz, the frequencies of the sine excitation signal are 100 Hz, 1 KHz, 10 KHz and 100 KHz, and the frequency accuracy is 0.02%.

[0062] S2: the signal conversion circuit (102) amplifies the input sinusoidal excitation signal according to the ratio of the capacitance value, connects the input end of the peak detection circuit (103) through the buffer circuit, and inputs the amplified sinusoidal excitation signal into the peak detection circuit (103);

[0063] The expression for amplifying the sinusoidal excitation signal according to the capacitance ratio is:

[0064]

[0065] In formula (1), V x is the amplified sinusoidal excitation signal, C f is the reference capacitor, V in is the peak value of the input sine wave, C x is the capacitance value of the capacitor to be tested;

[0066] S3: collecting the voltage peak value of the amplified sinusoidal excitation signal in real time through the peak detection circuit (103), calculating the capacitance value of the capacitor to be measured based on the voltage peak value, and transmitting the capacitance value to the analog-to-digital conversion circuit (104);

[0067] Since the cross-connected reference capacitor Cf, the common mode level Vcm and the peak value Vpeakin of the input sine are known, the linear relationship between the measured capacitor Cx and the peak value Vpeakout of the output sine is as shown in formula (2). The expression of the capacitance value of the measured capacitor is:

[0068]

[0069] In formula (2), V peakout is the peak value of the known sinusoidal excitation signal, V cm is a known common-mode level;

[0070] S301: Figure 2 As shown, the amplified sinusoidal excitation signal is used as the input voltage value Vip. When the input voltage value Vip is equal to the output voltage Vpeak, the current of NM2 flows equally through NM0 and NM1, and Vpeak charges the load capacitor Co, so that the output voltage reaches the Vpeak value; if Vip becomes larger, the current value of the NM0 branch will become larger, and the excess current will be obtained from the PM2 branch. Through the current mirror effect, a downward current is generated in PM5, and the downward current charges Co, so that the voltage of Co increases. When the voltage value is equal to the input voltage Vip, the charging stops, and the circuit returns to the equilibrium state, and the voltage peak value of the amplified sinusoidal excitation signal is obtained. The large resistor can be realized by the MOS tube in the cut-off area, and the capacitor Co is directly integrated on the chip.

[0071] The peak detection circuit (103) is constructed with a transistor-level structure. The peak voltage detection circuit is mainly used to track the peak value of the constantly fluctuating voltage in the circuit. Generally, the voltage peak in the circuit can be used to make logical judgments, thereby realizing the control and regulation of the circuit. The peak detector is usually composed of a diode and a capacitor to complete the measurement of the peak voltage. While using the capacitor to store the peak voltage in the circuit, due to the forward conduction effect of the diode, the voltage can be stably stored on the capacitor. The principle of the peak detection circuit (103) used in this embodiment is that when the circuit is in a balanced state, the voltages at both ends of the circuit input are equal. At this time, the current signals flowing through the two branches are equal, and the voltages at both ends of the capacitor CL will track the voltage value of one end input. At this time, if the input voltage at one end increases, the current flowing through the branch will increase, and the extra current will charge CL through the mirror effect of the current mirror until the potential of CL is equal to the potential of the increased input voltage. When the input voltage at one end decreases, since the current in the current mirror can only flow from the power supply to the ground, the voltage value on the capacitor remains unchanged, that is, the peak detection function is realized. Due to various non-ideal effects in the circuit, the voltage of the capacitor CL needs to be reset every once in a while to ensure that the voltage across the capacitor always follows the peak value of the input voltage. A large resistor is connected in parallel between the output and the ground to establish a DC operating point, and a switch is connected in parallel to provide a reset refresh circuit to ensure the normal operation of the circuit.

[0072] S4: the analog-to-digital conversion circuit (104) performs high-precision digitization on the input capacitance value and outputs the capacitance detection result;

[0073] The capacitance detection circuit designed in the present invention has high measurement accuracy, and its resolution can reach more than 12 bits. The measurement accuracy is mainly restricted by the operational amplifier offset and the accuracy of the analog-to-digital conversion circuit (104).

[0074] S401: The sampling and holding circuit is a bootstrap switch circuit. When the sampling clock CLK is at a low level, the bootstrap switch works in the holding stage, and Vboost is pulled to GND; when CLK is at a high level, the bootstrap switch works in the sampling stage, and the bootstrap clock signal Vboost voltage is VDD+Vin. The VGS of the sampling switch M1 is fixed to VDD, which significantly reduces the nonlinearity of the M1 equivalent resistance RON and improves the linearity of the sampling switch M1. When the actual circuit is designed, the capacitance value is selected as 0.5p, and the charge pump of the three capacitors can realize the function of raising the gate voltage of the switch tube to VDD+Vin. The size of the last switch tube should be designed to be relatively large, in order to improve the establishment accuracy of the gate voltage bootstrap switch, so that the deviation between Vs and Vin is smaller, so that the potential of each part of the capacitor array can be established more accurately, so that the capacitor array can be established more accurately. The comparator of this embodiment combines the open-loop amplifier structure and the latch, and uses the advantages of these two structures for complementary design. Taking advantage of the open-loop amplifier, the difference of the input signal can be increased, and then added to the latch structure. This structure can improve the speed and accuracy of the comparator. The pre-amplifier stage uses a fully differential unipolar amplifier. On the basis of the five-tube OTA, a cross-coupled load pair is added to introduce appropriate positive feedback. The gain of the operational amplifier can be effectively improved by using the principle of current cancellation. Latch uses a traditional dynamic comparator structure. The gate of the tail current tube is connected to the comparator clock, and a reset tube is used to reset the comparison result. The output of the latch is connected to an inverter to enhance the driving ability of the comparator output and improve the waveform quality. The power consumption of this structure is low. The latch has no static power consumption but only dynamic power consumption, and only uses one level of pre-amplification, which can maintain a certain accuracy while maintaining a fast enough speed. The offset of the comparator will affect the comparison result. After amplification, the offset of the latch equivalent to the input has been greatly reduced. The main offset comes from the offset of the pre-amplifier input pair tube, and then the input offset is reduced by the offset storage technology of OOS or IOS.

[0075] S402: Figure 4As shown in the figure, the capacitor array in the DAC adopts a fully differential segmented structure. The fully differential input has a certain inhibitory effect on temperature drift mismatch compared to the single-ended input. The Vcm-based switching strategy is adopted. Through the conservation of the node capacitance of the capacitor, in conjunction with the action of the appropriate capacitor lower plate switch, the upper plate of the capacitor array will change the correct voltage value due to the conservation of capacitance, so that the comparison of the voltage at the upper plate of the capacitor array can be converted into the difference of the differential input and compared with the corresponding value of each conversion in the successive approximation logic. The value of the unit capacitance is very particular. If it is too large, the chip area will be increased and the establishment time of each conversion voltage will be increased, but the establishment accuracy can be relatively improved; if the unit capacitance value is too small, the establishment accuracy will be poor. It is necessary to iterate and compromise the value to select the appropriate unit capacitance value. The segmented structure can reduce the size of the overall capacitor array and save area. At the same time, redundant bits and digital combinational logic modules are set to calculate the output code back to binary, which improves the fault tolerance rate. The SAR logic circuit is used to control the process of successive approximation. The SAR logic in this design can realize the generation of each clock rising edge of the shift register output through the traditional logic process based on the shift register, and can store the two results of each comparison in the DFF respectively, and output them in combination with appropriate digital circuits. At the same time, the correct control timing of the DAC array switch is obtained after reasonable processing of each comparison result. The redundancy technology in the SAR DAC performs internal fault tolerance correction by increasing the number of quantization times. It is used to solve the establishment problem in the SAR DAC and the comparison error caused by limited resolution, and a non-binary DAC array is used to achieve redundancy.

[0076] S403: Figure 3 As shown, the capacitance value is input as the input signal Vin into the analog-to-digital conversion circuit (104), the input signal Vin passes through the sampling and holding circuit to reach the positive input end of the comparator circuit, the highest bit MSB of the digital control SAR logic circuit is set to 1, and the remaining bits are cleared to zero. Under the control of the SAR logic circuit and the reference voltage Vref, the DAC capacitor array circuit outputs 1 / 2Vref and sends it to the negative input end of the comparator. If Vin>1 / 2Vref, the output of the comparator circuit is 1, and the highest bit of the digital code is also 1; if Vin<1 / 2Vref, the output of the comparator circuit is 0, and the highest bit of the digital code is also 0; the second highest bit MSB of the numerical control SAR logic circuit is set to 1, if MSB=1, the DAC capacitor array circuit output is 3 / 4Vref, and the size of Vin and 3 / 4Vref is compared to determine the second highest bit, if MSB=0, the DAC capacitor array circuit output is 1 / 4Vref, and the size of Vin and 1 / 4Vref is compared to determine the second highest bit; repeat the logic of the above content and make analogy until all the digital codes of the SAR are determined, the digitization of the voltage peak is completed, and the capacitance detection result is output.

[0077] The high gain of the low-noise three-stage operational amplifier in the present invention enables high precision of closed-loop amplification, and the comparator in the final analog-to-digital converter adopts offset storage technology to reduce offset, and redundant bits are added to the capacitor array to increase the final effective number of bits. The analog-to-digital conversion circuit (104) has low power consumption and high speed, and can reach a sampling rate of 1MSPS. The frequency measured by the sensor at the front end of the general capacitor is relatively low, and the rate of the analog-to-digital converter can digitize the output of the peak detection with high precision, and the measurement frequency range is wide, which can meet the Nyquist sampling theorem.

[0078] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A capacitance detection circuit based on peak detection, characterized in that: The structure of the capacitance detection circuit based on peak detection includes: A signal generating circuit (101), a signal converting circuit (102), a peak value detecting circuit (103) and an analog-to-digital converting circuit (104); The input end of the signal generating circuit (101) is used to receive the capacitance to be measured, the output end of the signal generating circuit (101) is connected to the input end of the signal conversion circuit (102) through the capacitance to be measured, the output end of the signal conversion circuit (102) is connected to the input end of the peak detection circuit (103), the output end of the peak detection circuit (103) is connected to the input end of the analog-to-digital conversion circuit (104), and the analog-to-digital conversion circuit (104) outputs the capacitance detection result.

2. A capacitance detection circuit based on peak detection according to claim 1, characterized in that: The signal generating circuit (101) comprises a sine wave module and an excitation signal module; The sine wave module is used to obtain a sine wave; The excitation signal module acquires a sinusoidal excitation signal based on the acquired sinusoidal wave.

3. A capacitance detection circuit based on peak detection according to claim 1, characterized in that: The signal conversion circuit (102) is a low-noise charge transfer device including a three-stage amplification structure, and is used to amplify the sinusoidal excitation signal according to the conversion ratio of the capacitance value; The first stage of the three-stage amplification structure is a five-tube OTA, the second stage is a folded common source and common gate structure, and the third stage is a common source stage.

4. A capacitance detection circuit based on peak detection according to claim 1, characterized in that: The peak detection circuit (103) is a transistor-level circuit with a five-transistor OTA structure, and is used for real-time collection of voltage peak values.

5. The capacitance detection circuit based on peak detection according to claim 1, characterized in that: The analog-to-digital conversion circuit (104) comprises: a sampling and holding circuit, a DAC capacitor array circuit, a comparator circuit and a SAR logic circuit; The sample-and-hold circuit is a bootstrap switch circuit, which is used to accurately sample the input signal under the control of a sampling clock; The DAC capacitor array circuit is a fully differential segmented structure, which is used to store sampled information and is controlled by the SAR logic circuit to perform a successive approximation process; The comparator circuit is a structure of pre-amplification plus latch dynamic comparator, which is used to compare the voltage levels at both ends of the input, thereby obtaining a quantized result through repeated comparisons; The SAR logic circuit is composed of a combinational logic circuit and a sequential logic circuit, and is used to store each comparison result and control the potential conversion of the upper plate of the capacitor array according to a suitable switching strategy.

6. A method for measuring a capacitance detection circuit based on peak detection, applied to a capacitance detection circuit based on peak detection according to any one of claims 1 to 5, characterized in that: include: Step 1: the signal generating circuit (101) outputs a sinusoidal excitation signal, and the output end of the signal generating circuit (101) is connected to the input end of the signal conversion circuit (102) via a capacitor to be measured; Step 2: the signal conversion circuit (102) amplifies the input sinusoidal excitation signal in proportion to the capacitance value, connects the input end of the peak detection circuit (103) through the buffer circuit, and inputs the amplified sinusoidal excitation signal into the peak detection circuit (103); Step 3: The peak value of the voltage of the amplified sinusoidal excitation signal is collected in real time by the peak detection circuit (103), the capacitance value of the capacitor to be measured is calculated based on the peak value of the voltage, and the capacitance value is transmitted to the analog-to-digital conversion circuit (104); Step 4: the analog-to-digital conversion circuit (104) performs high-precision digitization on the input capacitance value and outputs the capacitance detection result; The expression for amplifying the sinusoidal excitation signal according to the capacitance ratio is: In formula (1), V x is the amplified sinusoidal excitation signal, C f is the reference capacitor, V in is the peak value of the input sine wave, C x is the capacitance value of the capacitor to be tested; The expression of the capacitance value of the capacitor to be measured is: In formula (2), V peakout is the peak value of the known sinusoidal excitation signal, V cm is a known common-mode level.

7. The method for measuring a capacitance detection circuit based on peak detection according to claim 6, characterized in that: The frequency range of the sine wave in the sine excitation signal in step 1 is 1 Hz-120 MHz, the frequencies of the sine excitation signal are 100 Hz, 1 KHz, 10 KHz and 100 KHz, and the frequency accuracy is 0.02%.

8. The method for measuring a capacitance detection circuit based on peak detection according to claim 6, characterized in that: The real-time acquisition of the sine peak value of the amplified sine excitation signal input in step 3 specifically includes: The amplified sinusoidal excitation signal is used as the input voltage value Vip. When the input voltage value Vip is equal to the output voltage Vpeak, the current of NM2 flows equally through NM0 and NM1, and Vpeak charges the load capacitor Co, so that the output voltage reaches the Vpeak value; if Vip becomes larger, the current value of the NM0 branch will become larger, and the excess current will be obtained from the PM2 branch. Through the current mirror effect, a downward current is generated in PM5, and the downward current charges Co, so that the voltage of Co increases. When the voltage value is equal to the input voltage Vip, the charging is stopped, the circuit returns to the equilibrium state, and the voltage peak value of the amplified sinusoidal excitation signal is obtained.

9. The method for measuring a capacitance detection circuit based on peak detection according to claim 6, characterized in that: The steps of outputting the capacitance detection result in step 4 include: Step 4.1: Input the capacitance value of the capacitor as the input signal Vin into the analog-to-digital conversion circuit (104). The input signal Vin reaches the positive input terminal of the comparator circuit through the sampling and holding circuit. The highest bit MSB of the digital control SAR logic circuit is set to 1, and the remaining bits are cleared. Under the control of the SAR logic circuit and the reference voltage Vref, the DAC capacitor array circuit outputs 1 / 2Vref and sends it to the negative input terminal of the comparator. If Vin>1 / 2Vref, the output of the comparator circuit is 1, and the highest bit of the digital code is also 1; if Vin<1 / 2Vref, the output of the comparator circuit is 0, and the highest bit of the digital code is also 0; Step 4.2: Set the second highest bit MSB of the numerical control SAR logic circuit to 1. If MSB = 1, the DAC capacitor array circuit output is 3 / 4Vref, and the second highest bit is determined by comparing Vin with 3 / 4Vref. If MSB = 0, the DAC capacitor array circuit output is 1 / 4Vref, and the second highest bit is determined by comparing Vin with 1 / 4Vref. Step 4.3: Follow the logic of step 4.1 and step 4.2 until all digital codes of SAR are determined, the voltage peak is digitized, and the capacitance detection result is output.

Images