Equipment upgrading method and device, electronic equipment and storage medium

Abstract

The invention provides an equipment upgrading method and device, electronic equipment and a storage medium, and relates to the technical field of equipment upgrade.The method comprises the steps that upgrading sub-data corresponding to an offset address in obtained upgrading data is modified, and target data is constructed; target data is sent to the FPGA chip, and the target data is used for indicating the FPGA chip to start a backup program when it is determined that the equipment upgrading state is the abnormal upgrading state; the upgrading sub-data is used for upgrading the equipment according to the backup program. According to the method, the equipment upgrading failure caused by the fact that the equipment is stuck in a certain link when the equipment is in the abnormal upgrading state can be avoided, and the universality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of device upgrading, and in particular to a device upgrading method, device, electronic device and storage medium. Background Art

[0002] During the device upgrade process, the data in the FLASH is usually erased first, and then the upgrade data is written. After the upgrade data is completely written, the upgrade is performed. The upgrade process generally includes two parts: verifying the integrity of the upgrade data and upgrading according to the upgrade data. For FPGA-related devices, since the verification data is set at the end of the upgrade data, if the device upgrade fails due to misoperation or abnormal power failure during the upgrade data writing process, after the device system is restarted, the written upgrade data is incomplete, which will cause the device to be stuck at a certain link during the upgrade process, causing the device to be in an upgrade failure state and unable to recover automatically.

[0003] In the prior art, the MD5 value of the data written in FLASH is generally calculated, and the MD5 value is matched with the MD5 value of the upgrade data. If they are inconsistent, a backup program is started, or a new partition is opened in FLASH and a flag is written in the partition. The flag is used to represent the upgrade status to avoid the upgrade failure due to the device being unable to automatically recover.

[0004] However, in the case of large amounts of data, the above two methods increase the overhead of components such as device memory and CPU, affecting the startup speed of the device. Secondly, the default backup program in the device does not support the above two methods, and the above methods can only be executed after the backup program is upgraded. Therefore, how to successfully upgrade the device without affecting the performance of the device is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a device upgrading method, apparatus, electronic device and storage medium, which are used to solve the defects in the prior art of successfully upgrading a device without affecting the performance of the device, avoid the device being stuck in a certain link when in an abnormal upgrading state, resulting in the failure of the device upgrading, and improve universality.

[0006] The present invention provides a device upgrading method, comprising:

[0007] Modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device;

[0008] Sending the target data to the FPGA chip, wherein the target data is used to instruct the FPGA chip to start a backup program when determining that the device upgrade state is an abnormal upgrade state;

[0009] The device is upgraded according to the backup program.

[0010] According to the device upgrade method provided by the present invention, the upgrade sub-data corresponding to the offset address in the acquired upgrade data is modified to construct the target data, including:

[0011] Obtaining verification information stored in the FPGA chip;

[0012] Based on the verification information, determine the offset address corresponding to the FPGA chip and the abnormal data corresponding to the offset address;

[0013] The upgrade sub-data corresponding to the offset address in the upgrade data is modified into the abnormal data to construct the target data.

[0014] According to the device upgrade method provided by the present invention, the step of modifying the upgrade sub-data corresponding to the offset address in the upgrade data into the abnormal data to construct the target data includes:

[0015] Starting from the initial position of the upgrade data, reading a preset amount of first sub-data in the upgrade data into a cache;

[0016] replacing the upgraded sub-data corresponding to the offset address in the first sub-data with the abnormal data to obtain second sub-data;

[0017] writing the other sub-data in the upgrade data except the first sub-data into the cache in sequence;

[0018] The target data is constructed based on the second sub-data and the other sub-data.

[0019] According to the device upgrade method provided by the present invention, determining the offset address corresponding to the FPGA chip and the abnormal data corresponding to the offset address based on the verification information includes:

[0020] In a case where the verification information includes a verification flag and offset data, based on a matching result between the verification flag and a first threshold, determining an offset address corresponding to the FPGA chip, and determining the offset data as abnormal data corresponding to the offset address;

[0021] In the case where the verification information only includes a verification flag, the offset address corresponding to the FPGA chip is determined based on the matching result between the verification flag and the first threshold, and the second threshold is determined as the abnormal data corresponding to the offset address.

[0022] According to the device upgrade method provided by the present invention, determining the offset address corresponding to the FPGA chip based on the matching result between the check flag and the first threshold includes:

[0023] When the check flag matches the first threshold, a third threshold corresponding to the first threshold is determined as the offset address corresponding to the FPGA chip;

[0024] When the check flag does not match the first threshold, the offset address corresponding to the FPGA chip is determined based on the check flag.

[0025] According to the device upgrading method provided by the present invention, the method further includes:

[0026] When receiving feedback information sent by the FPGA chip, the upgrade sub-data is sent to the FPGA chip, and the FPGA chip is used to modify the target data into the upgrade data based on the upgrade sub-data, and when the upgrade data is successfully verified, perform device upgrade based on the upgrade data, and the feedback information is used to indicate that the FPGA chip has written the target data into the memory.

[0027] According to the device upgrade method provided by the present invention, in the case of receiving feedback information sent by the FPGA chip, sending the upgrade sub-data to the FPGA chip includes:

[0028] In case of receiving feedback information sent by the FPGA chip, sending an offset instruction to the FPGA chip, wherein the offset instruction is used to instruct the FPGA chip to offset to an offset address corresponding to the second sub-data;

[0029] The upgraded sub-data is sent to the FPGA chip, and the FPGA chip is used to update the abnormal data corresponding to the offset address in the second sub-data to the upgraded sub-data to obtain the upgraded data.

[0030] According to the device upgrading method provided by the present invention, the method further includes:

[0031] When it is determined that the upgrade state of the device is an abnormal upgrade state, obtaining an original version number corresponding to the FPGA chip;

[0032] Matching the original version number with the upgraded version number corresponding to the upgraded data;

[0033] When the original version number does not match the upgraded version number, the target data and upgraded sub-data are repeatedly sent to the FPGA chip to upgrade the device again, until the original version number matches the upgraded version number, and the device upgrade is terminated.

[0034] The present invention also provides a device upgrading apparatus, comprising:

[0035] A construction module, used to modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device;

[0036] A first sending module, used for sending the target data to the FPGA chip, wherein the target data is used for instructing the FPGA chip to start a backup program when determining that the upgrade state of the device is an abnormal upgrade state;

[0037] An upgrade module is used to upgrade the device according to the backup program.

[0038] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the device upgrade method described in any one of the above methods is implemented.

[0039] The device upgrade method, apparatus, electronic device and storage medium provided by the present invention modify the upgrade sub-data corresponding to the offset address in the upgrade data, construct the target data, and send the target data to the FPGA chip. The upgrade sub-data causes the FPGA chip to be in an abnormal upgrade state when the target data is not all written into the memory, that is, the FPGA chip starts the backup program in the abnormal upgrade state to avoid directly starting the written target data, resulting in a stuck machine and an upgrade failure that cannot be recovered. At the same time, for the target data as a whole, the data volume of the written target data and the upgrade data is extremely small, which has little impact on the overhead of components such as the device memory and CPU and the device performance such as the boot speed of the device, thereby improving universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is one of the flow charts of the equipment upgrading method provided by the prior art;

[0042] Figure 2This is the second flow chart of the device upgrade method provided by the prior art;

[0043] Figure 3 This is one of the flow charts of the device upgrading method provided by the embodiment of the present invention;

[0044] Figure 4 This is a second flow chart of the device upgrade method provided by an embodiment of the present invention;

[0045] Figure 5 This is a third flow chart of the device upgrade method provided by an embodiment of the present invention;

[0046] Figure 6 It is a structural schematic diagram of a device upgrading apparatus provided by an embodiment of the present invention;

[0047] Figure 7 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Figure 1 It is one of the flow charts of the device upgrade method provided by the prior art, such as Figure 1 As shown, the device includes a CPU and an FPGA chip, and the CPU and the FPGA chip are connected in communication. The FPGA chip is equipped with an external FLASH memory. FLASH is a non-volatile memory used to store data in electronic devices. The characteristics of FLASH memory are that it can be electrically erased and programmable, so data can be erased and programmed through electronic operations without removing the memory chip. FLASH memory is widely used in various electronic devices, including computers, smart phones, embedded systems, and other electronic devices. It is usually used to store operating systems, firmware, BIOS, applications, and other types of data.

[0050] In the prior art, the CPU continuously sends instructions to the FPGA chip to implement device upgrades. Figure 2 This is the second flow chart of the device upgrade method provided by the prior art. Figure 2As shown, when the device is upgraded, first, the CPU sends an erase instruction to the FPGA chip. The FPGA chip erases the data in the FLASH memory through the erase instruction. After the erasure is completed, the FPGA chip sends feedback information to the CPU, indicating that all the data in the FLASH memory has been erased. After receiving the feedback information, the CPU sends a start upgrade instruction to the FPGA chip to adjust the FPGA chip to the upgrade state. After that, the CPU sends the acquired upgrade data to the FPGA chip one by one through the PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) bus, so that the FPGA chip writes the upgrade data to the FLASH in sequence. However, if an erroneous operation or abnormal power failure occurs at this time, some of the data written in the FLASH will be saved. After the FPGA chip is restarted, it will be initialized and some of the data written in the FLASH will be started. Since the written data is correct but incomplete, the FPGA chip will be stuck in a certain link and cannot be recovered, resulting in the failure of the device upgrade.

[0051] Combine the following Figure 3-Figure 5 A device upgrading method provided by an embodiment of the present invention is described.

[0052] In view of the above problems, an embodiment of the present invention provides a device upgrading method. Figure 3 is one of the flow charts of the device upgrade method provided by the embodiment of the present invention, such as Figure 3 As shown, the method includes:

[0053] Step 310: Modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device.

[0054] Specifically, in order to avoid the problem of increasing device memory and CPU overhead by two methods, such as comparing the MD5 value of the written data and the MD5 value of the upgraded data, and starting the backup program if they are inconsistent, or creating a new partition in the FLASH, writing a flag in the partition, and using the flag to represent the upgrade status, in an embodiment of the present invention, the upgrade sub-data corresponding to the offset address in the upgrade data is modified, and the upgrade sub-data is modified from correct data to incorrect data, so that the FPGA chip verifies the data corresponding to the offset address before receiving the target data and upgrading. If the data is correct, a normal upgrade is performed. If the data is incorrect, a backup program is started to avoid the problem that the device is stuck and cannot be restored due to misoperation or abnormal power failure during the device upgrade process.

[0055] Optionally, the above-mentioned upgrade data may be mirror data, which refers to binary data containing device firmware or software, and is used to characterize a specific version of the device or the content of the upgrade. During the upgrade process, the mirror data is new data used to replace the current firmware or software version of the device. The CPU may obtain the mirror data from a flash memory, a hard disk, or a solid-state drive, and may also download the mirror data from a server or other device through a network protocol such as HTTP, FTP, etc., and may also read the mirror data from an external storage device such as a USB flash drive, an SD card, etc. The embodiment of the present invention is not limited to this.

[0056] In addition to the image data, the above-mentioned upgrade data may also include: patch files, configuration files, scripts or instruction sets, and resource files, etc. Among them: patch files contain fixes, updates or improvements to the existing software or firmware in the device. Patch files usually only contain the parts that need to be modified, rather than the complete image data. Configuration files can modify the behavior, functions or performance of the device. Scripts or instruction sets can be used to perform specific operations, such as installing new software packages, configuring device parameters, or performing other system tasks. Resource files can be image data, audio data, video data, etc. Upgrading resource files can improve the media functions of the device.

[0057] Optionally, Figure 4 FIG. 2 is a flow chart of a device upgrade method provided by an embodiment of the present invention. Figure 4 As shown, the upgrade sub-data corresponding to the offset address in the acquired upgrade data is modified to construct the target data, including:

[0058] Obtaining verification information stored in the FPGA chip;

[0059] Based on the verification information, determine the offset address corresponding to the FPGA chip and the abnormal data corresponding to the offset address;

[0060] The upgrade sub-data corresponding to the offset address in the upgrade data is modified into the abnormal data to construct the target data.

[0061] Specifically, the FPGA chip includes two registers for providing the verification information. The verification information is not a fixed value, and will adapt to different addresses and data as the model of the FPGA chip is different, so as to adapt to all FPGA chips and improve the universality of the embodiment of the present invention. After obtaining the verification information, the offset address corresponding to the FPGA chip and the abnormal data corresponding to the offset address can be further determined according to the verification information, and the correct upgrade sub-data corresponding to the offset address in the upgrade data can be modified to the wrong abnormal data, so as to construct the target data, so that the FPGA chip first verifies the abnormal data corresponding to the offset address when upgrading. Since the data is abnormal data, it can avoid the FPGA from starting the local target data when the target data is not written, thereby avoiding the problem that the device is always in a stuck state and cannot be recovered due to incomplete data.

[0062] Optionally, modifying the upgrade sub-data corresponding to the offset address in the upgrade data into the abnormal data to construct the target data includes:

[0063] Starting from the initial position of the upgrade data, reading a preset amount of first sub-data in the upgrade data into a cache;

[0064] replacing the upgraded sub-data corresponding to the offset address in the first sub-data with the abnormal data to obtain second sub-data;

[0065] writing the other sub-data in the upgrade data except the first sub-data into the cache in sequence;

[0066] The target data is constructed based on the second sub-data and the other sub-data.

[0067] Specifically, since the upgrade adopts a positive upgrade method, and the FLASH memory performs erase and write operations in units of blocks, rather than bytes. Therefore, when constructing the target data, the CPU starts from the initial position of the upgrade data, reads the first sub-data of the preset data amount each time, and writes the first sub-data into the cache, and the preset data amount is about 1 block in the FLASH storage. After that, it offsets to the offset address in the first sub-data, and writes the abnormal data starting from the offset address. Since the writing method is overwriting, it is equivalent to replacing the upgrade sub-data corresponding to the offset address with the abnormal data. Then, a new memory is applied in the cache, and the other sub-data in the upgrade data except the first sub-data are written into the cache in sequence, and the other sub-data are not modified. Therefore, based on the second sub-data and other sub-data obtained after the modification, the target data can be constructed. Compared with the upgrade data, the target data only has the data corresponding to the offset address. Therefore, the device memory and CPU overhead occupied are extremely small, and the impact on the boot speed of the device is extremely small and negligible. The device can be successfully upgraded without affecting the performance of the device, while avoiding the problem that the device is always in a stuck state and cannot be restored.

[0068] It should be noted that the data volume of the abnormal data is the same as the data volume of the upgraded sub-data.

[0069] Optionally, determining the offset address corresponding to the FPGA chip and abnormal data corresponding to the offset address based on the verification information includes:

[0070] In a case where the verification information includes a verification flag and offset data, based on a matching result between the verification flag and a first threshold, determining an offset address corresponding to the FPGA chip, and determining the offset data as abnormal data corresponding to the offset address;

[0071] In the case where the verification information only includes a verification flag, the offset address corresponding to the FPGA chip is determined based on the matching result between the verification flag and the first threshold, and the second threshold is determined as the abnormal data corresponding to the offset address.

[0072] Optionally, determining the offset address corresponding to the FPGA chip based on a matching result between the check flag and a first threshold value includes:

[0073] When the check flag matches the first threshold, a third threshold corresponding to the first threshold is determined as the offset address corresponding to the FPGA chip;

[0074] When the check flag does not match the first threshold, the offset address corresponding to the FPGA chip is determined based on the check flag.

[0075] Specifically, in the FPGA chip, one of the registers is a 0x100 register, which is used to store a check mark. Another register is a 0x101 register, which is used to store the offset data corresponding to the offset address. The above check mark is used to identify which address writes abnormal data. If the check mark obtained from the 0x100 register matches the first threshold, the third threshold corresponding to the first threshold can be determined as the offset address corresponding to the FPGA chip. Taking the first threshold as 0 and the third threshold as 0x40 as an example, if the check mark is 0, the offset address can be determined as 0x40, and if the check mark is not 0, for example, when the check mark is 30, the offset address can be constructed as 0x30 based on the read data 30. In addition, if the offset data obtained from the 0x101 register is 0xbb112233, 0xbb112233 can be determined as abnormal data. If the offset data is not obtained from the 0x101 register, the abnormal data corresponding to the offset address may be determined as the second threshold 0xFFFFFFFF, and the upgrade sub-data 0xaa995566 may be replaced with 0xbb112233 or 0xFFFFFFFF.

[0076] Step 320: Send the target data to the FPGA chip, where the target data is used to instruct the FPGA chip to start a backup program when it is determined that the upgrade status of the device is an abnormal upgrade status.

[0077] Specifically, the FLASH memory is divided into two partitions, one for storing the Golden program and the other for storing the Update program. The Golden program includes the initialization startup program and the backup program of the FPGA chip, and the Update program includes the normal running programs in the FPGA chip except the Golden program, that is, after receiving the target data, the FPGA chip will store the target data in the partition where the Update program is located. This means that when the FPGA chip is started and upgraded, it first calls the Golden program to initialize the system, and then checks whether the data corresponding to the offset address is consistent with the offset data in the 0x101 register. If they are inconsistent, it indicates that the data is correct, and the target data in the partition where the Update program is located can be called for upgrading. If they are consistent, it indicates that the data is wrong, and the backup program in the Golden program is called, and the target data in the partition where the Update program is located is no longer called for upgrading, so as to avoid the problem that the device is always in a stuck state and cannot be recovered.

[0078] Step 330: Upgrade the device according to the backup program.

[0079] The FPGA chip verifies the target data. If the device upgrade status is abnormal, it will not call the target data written into the partition where the Update program is located for upgrade. Instead, it will call the backup program in the Golden program for upgrade. The backup program is complete and correct, and the device will not be stuck and cannot be restored.

[0080] Optionally, the method further includes: upon receiving feedback information sent by the FPGA chip, sending the upgrade sub-data to the FPGA chip, the FPGA chip being used to modify the target data into upgrade data based on the upgrade sub-data, and performing a device upgrade based on the upgrade data when the upgrade data verification is successful, and the feedback information is used to indicate that the FPGA chip has written the target data into the memory.

[0081] Specifically, in order to prevent the FPGA chip from being unable to upgrade normally due to the need to call backup data continuously due to target data errors, in an embodiment of the present invention, after all the target data are written into the partition where the Update program of the FPGA chip is located, the CPU may send the upgrade sub-data to the FPGA chip, so that the FPGA chip replaces the abnormal data corresponding to the offset address in the target data with the correct upgrade sub-data to correct the target data.

[0082] Optionally, in the case of receiving feedback information sent by the FPGA chip, sending the upgrade sub-data to the FPGA chip includes:

[0083] In case of receiving feedback information sent by the FPGA chip, sending an offset instruction to the FPGA chip, wherein the offset instruction is used to instruct the FPGA chip to offset to an offset address corresponding to the second sub-data;

[0084] The upgraded sub-data is sent to the FPGA chip, and the FPGA chip is used to update the abnormal data corresponding to the offset address in the second sub-data to the upgraded sub-data to obtain the upgraded data.

[0085] Specifically, after all the target data is written into the partition where the Update program of the FPGA chip is located, the FPGA chip sends feedback information to the CPU to confirm that all the target data is written into the FLASH memory. After that, the CPU sends an offset instruction to the FPGA chip to control the FPGA chip to offset to the offset address corresponding to the second sub-data. Next, the CPU sends the upgrade sub-data to the FPGA chip, that is, starting from the offset address, writes the upgrade sub-data to overwrite the abnormal data, so that the obtained upgrade data is correct and complete, so that the FPGA chip can successfully verify the upgrade data and perform device upgrade based on the upgrade data.

[0086] In the device upgrade process of the prior art, after the corresponding upgrade data is sent to the FPGA chip, the FPGA chip will first erase the data in the Flash, and then write the corresponding upgrade data into the corresponding storage area. After the upgrade data is completely written into the above storage area, the integrity of the upgrade data is verified and the upgrade is performed according to the upgrade data. If an abnormal interruption such as a power failure of the device occurs during the writing of the upgrade data, the upgrade data is not completely written. Since the verification data at the end of the upgrade data is not written, there is no verification error for this abnormality. At the same time, the existence of upgrade data without errors is detected, that is, the upgrade will be performed according to the incomplete upgrade data, and the upgrade system is disordered at this time.

[0087] In the embodiment of the present invention, when writing the upgrade data, the corresponding upgrade sub-data is intentionally modified into erroneous abnormal data to construct the target data, and the corresponding abnormal data is corrected after the target data is completely written, so as to perform the upgrade. If a sudden abnormality occurs and the writing of the target data is interrupted, since the abnormal data is at the head position of the target data, the corresponding abnormal data will be found after the device is restarted, and the backup program will be called according to the abnormal data, so as to avoid the disorder of the upgrade system and perform the normal upgrade of the device.

[0088] Optionally, Figure 5 FIG. 3 is a flow chart of a device upgrade method provided by an embodiment of the present invention. Figure 5 As shown, the method also includes:

[0089] When it is determined that the upgrade state of the device is an abnormal upgrade state, obtaining an original version number corresponding to the FPGA chip;

[0090] Matching the original version number with the upgraded version number corresponding to the upgraded data;

[0091] When the original version number does not match the upgraded version number, the target data and upgraded sub-data are repeatedly sent to the FPGA chip to upgrade the device again, until the original version number matches the upgraded version number, and the device upgrade is terminated.

[0092] Specifically, if an erroneous operation or abnormal power failure occurs during the process of the CPU sending the target data to the FPGA chip, resulting in the device upgrade status being an abnormal upgrade status, since the abnormal data is located at the first data block of the target data, the FPGA chip can automatically start the backup program in the Golden program when it detects that the abnormal data corresponding to the offset address is consistent with the offset data stored in the 0x101 register or the default second threshold. Before the upgrade, the CPU can obtain the original version number corresponding to the backup program. Since the last upgrade of the FPGA chip failed, the original version number in the FPGA chip is inconsistent with the upgrade version number corresponding to the upgrade data. At this time, the CPU can repeat the device upgrade method of steps 310-340 and start the upgrade again until the version number of the FPGA chip obtained is consistent with the upgrade version number of the upgrade data. At this time, it means that the FPGA chip has been successfully upgraded and has jumped to the Update program. At this time, the upgrade can be ended.

[0093] The device upgrade method provided by the embodiment of the present invention modifies the upgrade sub-data corresponding to the offset address in the upgrade data, constructs the target data, and sends the target data to the FPGA chip until the FPGA chip writes all the target data into the storage, and then uses the upgrade sub-data to modify the target data in the FPGA chip, so that the FPGA chip is in an abnormal upgrade state when the target data is not fully written into the memory, that is, the FPGA chip starts the backup program in the abnormal upgrade state to avoid directly starting the written target data, resulting in the machine being stuck and the upgrade failing and being unable to recover. At the same time, for the target data as a whole, the data volume of the written target data and the upgrade data is very small, and the impact on the overhead of components such as the device memory and CPU and the device boot speed and other device performance is very small. At the same time, there is no need to upgrade the Golden program first and then execute the device upgrade method provided by the embodiment of the present invention, which improves universality.

[0094] The device upgrade apparatus provided by the present invention is described below. The device upgrade apparatus described below and the device upgrade method described above can be referenced to each other.

[0095] The embodiment of the present invention also provides a device upgrading apparatus, Figure 6 is a schematic diagram of the structure of a device upgrade apparatus provided by an embodiment of the present invention, such as Figure 6 As shown, the device upgrade apparatus 600 includes: a construction module 610, a first sending module 620 and an upgrade module 630, wherein:

[0096] A construction module 610 is used to modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device;

[0097] A first sending module 620 is used to send the target data to the FPGA chip, where the target data is used to instruct the FPGA chip to start a backup program when determining that the device upgrade state is an abnormal upgrade state;

[0098] The upgrade module 630 is used to upgrade the device according to the backup program.

[0099] The device upgrade apparatus provided by the embodiment of the present invention modifies the upgrade sub-data corresponding to the offset address in the upgrade data, constructs the target data, and sends the target data to the FPGA chip, so that the FPGA chip is in an abnormal upgrade state when the target data is not fully written into the memory, that is, the FPGA chip starts the backup program in the abnormal upgrade state to avoid directly starting the written target data, resulting in a stuck machine and upgrade failure and inability to recover. At the same time, for the target data as a whole, the data volume of the written target data and the upgrade data is very small, and the impact on the device performance such as the overhead of the device memory and CPU and the boot speed of the device is very small. At the same time, there is no need to upgrade the Golden program first and then execute the device upgrade method provided by the embodiment of the present invention, which improves universality.

[0100] Optionally, the construction module 610 is specifically configured to:

[0101] Obtaining verification information stored in the FPGA chip;

[0102] Based on the verification information, determine the offset address corresponding to the FPGA chip and the abnormal data corresponding to the offset address;

[0103] The upgrade sub-data corresponding to the offset address in the upgrade data is modified into the abnormal data to construct the target data.

[0104] Optionally, the construction module 610 is specifically configured to:

[0105] Starting from the initial position of the upgrade data, reading a preset amount of first sub-data in the upgrade data into a cache;

[0106] replacing the upgraded sub-data corresponding to the offset address in the first sub-data with the abnormal data to obtain second sub-data;

[0107] writing the other sub-data in the upgrade data except the first sub-data into the cache in sequence;

[0108] The target data is constructed based on the second sub-data and the other sub-data.

[0109] Optionally, the construction module 610 is specifically configured to:

[0110] In a case where the verification information includes a verification flag and offset data, based on a matching result between the verification flag and a first threshold, determining an offset address corresponding to the FPGA chip, and determining the offset data as abnormal data corresponding to the offset address;

[0111] In the case where the verification information only includes a verification flag, the offset address corresponding to the FPGA chip is determined based on the matching result between the verification flag and the first threshold, and the second threshold is determined as the abnormal data corresponding to the offset address.

[0112] Optionally, the construction module 610 is specifically configured to:

[0113] When the check flag matches the first threshold, a third threshold corresponding to the first threshold is determined as the offset address corresponding to the FPGA chip;

[0114] When the check flag does not match the first threshold, the offset address corresponding to the FPGA chip is determined based on the check flag.

[0115] Optionally, the device upgrading apparatus 600 further includes: a second sending module, the second sending module being specifically configured to:

[0116] When receiving feedback information sent by the FPGA chip, the upgrade sub-data is sent to the FPGA chip, and the FPGA chip is used to modify the target data into the upgrade data based on the upgrade sub-data, and when the upgrade data is successfully verified, perform device upgrade based on the upgrade data, and the feedback information is used to indicate that the FPGA chip has written the target data into the memory.

[0117] Optionally, the second sending module is specifically configured to:

[0118] In case of receiving feedback information sent by the FPGA chip, sending an offset instruction to the FPGA chip, wherein the offset instruction is used to instruct the FPGA chip to offset to an offset address corresponding to the second sub-data;

[0119] The upgraded sub-data is sent to the FPGA chip, and the FPGA chip is used to update the abnormal data corresponding to the offset address in the second sub-data to the upgraded sub-data to obtain the upgraded data.

[0120] Optionally, the device upgrading apparatus 600 further includes: a matching module, which is specifically used to:

[0121] When it is determined that the upgrade state of the device is an abnormal upgrade state, obtaining an original version number corresponding to the FPGA chip;

[0122] Matching the original version number with the upgraded version number corresponding to the upgraded data;

[0123] When the original version number does not match the upgraded version number, the target data and upgraded sub-data are repeatedly sent to the FPGA chip to upgrade the device again, until the original version number matches the upgraded version number, and the device upgrade is terminated.

[0124] Figure 7 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 7 As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the device upgrade method, which includes:

[0125] Modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device;

[0126] Sending the target data to the FPGA chip, wherein the target data is used to instruct the FPGA chip to start a backup program when determining that the device upgrade state is an abnormal upgrade state;

[0127] The device is upgraded according to the backup program.

[0128] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0129] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the device upgrade method provided by the above methods, the method includes:

[0130] Modify the upgrade sub-data corresponding to the offset address in the upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device;

[0131] Sending the target data to the FPGA chip, wherein the target data is used to instruct the FPGA chip to start a backup program when determining that the device upgrade state is an abnormal upgrade state;

[0132] The device is upgraded according to the backup program.

[0133] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the device upgrade method provided by the above methods is implemented, and the method includes:

[0134] Modify the upgrade sub-data corresponding to the offset address in the upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device;

[0135] Sending the target data to the FPGA chip, wherein the target data is used to instruct the FPGA chip to start a backup program when determining that the device upgrade state is an abnormal upgrade state;

[0136] The device is upgraded according to the backup program.

[0137] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0138] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A device upgrading method, characterized in that: include: Modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device; Sending the target data to the FPGA chip, wherein the target data is used to instruct the FPGA chip to start a backup program when determining that the device upgrade state is an abnormal upgrade state; The device is upgraded according to the backup program.

2. The device upgrade method according to claim 1, characterized in that: The step of modifying the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct the target data includes: Obtaining verification information stored in the FPGA chip; Based on the verification information, determine the offset address corresponding to the FPGA chip and the abnormal data corresponding to the offset address; The upgrade sub-data corresponding to the offset address in the upgrade data is modified into the abnormal data to construct the target data.

3. The device upgrade method according to claim 2, characterized in that: The step of modifying the upgrade sub-data corresponding to the offset address in the upgrade data into the abnormal data to construct the target data includes: Starting from the initial position of the upgrade data, reading a preset amount of first sub-data in the upgrade data into a cache; replacing the upgraded sub-data corresponding to the offset address in the first sub-data with the abnormal data to obtain second sub-data; writing the other sub-data in the upgrade data except the first sub-data into the cache in sequence; The target data is constructed based on the second sub-data and the other sub-data.

4. The device upgrading method according to claim 2 or 3, characterized in that: The step of determining, based on the verification information, an offset address corresponding to the FPGA chip and abnormal data corresponding to the offset address includes: In a case where the verification information includes a verification flag and offset data, based on a matching result between the verification flag and a first threshold, determining an offset address corresponding to the FPGA chip, and determining the offset data as abnormal data corresponding to the offset address; In the case where the verification information only includes a verification flag, the offset address corresponding to the FPGA chip is determined based on a matching result between the verification flag and a first threshold, and the second threshold is determined as abnormal data corresponding to the offset address.

5. The device upgrade method according to claim 4, characterized in that: The step of determining the offset address corresponding to the FPGA chip based on the matching result between the check flag and the first threshold comprises: When the check flag matches the first threshold, a third threshold corresponding to the first threshold is determined as the offset address corresponding to the FPGA chip; When the check flag does not match the first threshold, the offset address corresponding to the FPGA chip is determined based on the check flag.

6. The device upgrade method according to claim 3, characterized in that: The method further comprises: When receiving feedback information sent by the FPGA chip, the upgrade sub-data is sent to the FPGA chip, and the FPGA chip is used to modify the target data into the upgrade data based on the upgrade sub-data, and when the upgrade data is successfully verified, perform device upgrade based on the upgrade data, and the feedback information is used to indicate that the FPGA chip has written the target data into the memory.

7. The device upgrading method according to claim 6, characterized in that: The step of sending the upgrade sub-data to the FPGA chip upon receiving feedback information sent by the FPGA chip comprises: In case of receiving feedback information sent by the FPGA chip, sending an offset instruction to the FPGA chip, wherein the offset instruction is used to instruct the FPGA chip to offset to an offset address corresponding to the second sub-data; The upgraded sub-data is sent to the FPGA chip, and the FPGA chip is used to update the abnormal data corresponding to the offset address in the second sub-data to the upgraded sub-data to obtain the upgraded data.

8. The device upgrading method according to any one of claims 1 to 3, characterized in that: The method further comprises: When it is determined that the upgrade state of the device is an abnormal upgrade state, obtaining an original version number corresponding to the FPGA chip; Matching the original version number with the upgraded version number corresponding to the upgraded data; When the original version number does not match the upgraded version number, the target data and upgraded sub-data are repeatedly sent to the FPGA chip to upgrade the device again, until the original version number matches the upgraded version number, and the device upgrade is terminated.

9. A device upgrading apparatus, characterized in that: include: A construction module, used to modify the upgrade sub-data corresponding to the offset address in the acquired upgrade data to construct target data, wherein the upgrade sub-data is used to represent the upgrade status of the device; A first sending module, used for sending the target data to the FPGA chip, wherein the target data is used for instructing the FPGA chip to start a backup program when determining that the upgrade state of the device is an abnormal upgrade state; An upgrade module is used to upgrade the device according to the backup program.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the device upgrading method according to any one of claims 1 to 7 is implemented.

Images