Soft error injection system

Abstract

The invention relates to the technical field of integrated circuits, and discloses a soft error injection system which comprises an upper computer and an FPGA chip, the FPGA chip comprises error injection logic, a configuration circuit and an SRAM, and the configuration circuit is provided with an internal configuration interface and an ECC interface; the upper computer generates configurable bit information and expected injection dislocation information of the FPGA chip; the error injection logic is configured as follows: judging whether the ECC in the FPGA chip is running or not through the ECC interface; if it is determined that the ECC does not run, the configuration frame of the SRAM is read back and stored through an internal configuration interface; according to the expected injection misplacement information, carrying out negation on corresponding position bits in the configuration frame to obtain an injection misplacement configuration frame; calculating the CRC of the error injection configuration frame, and generating a new configuration frame according to the write instruction, the error injection configuration frame and the CRC; and a new configuration frame is written into the SRAM through the internal configuration interface via the configuration circuit, and an error injection completion instruction is sent to an upper computer. The invention further provides the FPGA chip, and soft error injection is carried out through the error injection logic.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a soft error injection system and an FPGA chip. Background Art

[0002] Field Programmable Gate Array (FPGA) chips based on static random access memory (SRAM) are widely used in many fields due to their advantages such as reconfigurability and high integration. However, SRAM-based FPGA chips are extremely sensitive to the interference caused by single event upset (SEU), which can cause the logic state of the digital circuit to change, which is manifested as a change in the storage state of one or more SRAM storage bits (for example, from 1 to 0 or from 0 to 1), thus causing problems with the reliability of the application. For the SEU problem, there are technologies such as logical use of triple modular redundancy (TMR) design, timed refresh through the configuration interface, and configurable bit detection by the SRAM soft error correction circuit (ECC) of the FPGA chip. However, it is very difficult to perform flexible and reliable error injection on the configurable bits, evaluate the impact of soft errors on user functions, and the effectiveness of anti-SEU methods.

[0003] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of the present application. Summary of the invention

[0004] The purpose of this application is to provide a soft error injection system to perform soft error injection on FPGA chips. On the one hand, the flexibility of the soft error injection method is improved, and on the other hand, different user functions are provided to provide the applicability of soft error insertion for different FPGA chips, while ensuring the stability and security of the FPGA chip itself during the soft error injection process.

[0005] The present application discloses a soft error injection system, including a host computer and an FPGA chip, wherein the FPGA chip includes an error injection logic, a configuration circuit and an SRAM, and the configuration circuit has an internal configuration interface and an ECC interface;

[0006] The host computer generates configurable bit information and expected misalignment information of the FPGA chip;

[0007] The error injection logic determines whether the soft error correction circuit inside the FPGA chip is running through the ECC interface;

[0008] If it is determined that the soft error correction circuit is not operating, the error injection logic reads back and stores the configuration frame of the SRAM through the internal configuration interface;

[0009] The error injection logic inverts the corresponding position bits in the configuration frame according to the expected error injection position information to obtain an error injection configuration frame;

[0010] The error injection logic calculates a CRC of the error injection configuration frame, and generates a new configuration frame according to a write instruction, the error injection configuration frame, and the CRC; and

[0011] The error injection logic writes the new configuration frame to the SRAM via the configuration circuit through the internal configuration interface, and sends an error injection completion indication to the host computer.

[0012] In a preferred example, the configurable bit information includes frame address information, and the expected misalignment information is a subset of the configurable bit information selected by a user.

[0013] In a preferred example, if it is determined that the soft error correction circuit is running, the error injection logic writes an ECC stop configuration instruction to the configuration circuit through the internal configuration interface.

[0014] In a preferred example, the host computer uses EDA software to generate the configurable bit information and expected misalignment information of the FPGA chip.

[0015] In a preferred example, the soft error correction circuit is arranged inside the configuration circuit.

[0016] In a preferred example, generating a new configuration frame according to a write instruction, the error injection configuration frame and the CRC includes: combining the write instruction, the error injection configuration frame and the CRC to generate a new configuration frame.

[0017] The present application also discloses an FPGA chip including an error injection logic, a configuration circuit and an SRAM, wherein the configuration circuit has an internal configuration interface and an ECC interface; the error injection logic is configured to perform the following steps:

[0018] Receiving configurable bit information and expected misalignment information of the FPGA chip from a host computer;

[0019] Determining whether a soft error correction circuit inside the FPGA chip is running through the ECC interface;

[0020] If it is determined that the soft error correction circuit is not operating, reading back and storing the configuration frame of the SRAM through the internal configuration interface;

[0021] Inverting the corresponding position bits in the configuration frame according to the expected error injection information to obtain an error injection configuration frame;

[0022] Calculating the CRC of the error-injection configuration frame, and generating a new configuration frame according to a write instruction, the error-injection configuration frame, and the CRC; and

[0023] The new configuration frame is written into the SRAM via the configuration circuit through the internal configuration interface, and an error injection completion indication is sent to the host computer.

[0024] In a preferred example, if it is determined that the soft error correction circuit is running, the error injection logic writes an ECC stop configuration instruction to the configuration circuit through the internal configuration interface.

[0025] In the implementation of the present application, all configurable bit information and expected error injection information of the FPGA chip are generated based on the EDA software. After determining that the internal ECC of the FPGA chip is not running, the configuration frame is read back through the internal configuration interface, and then the configuration frame data is stored. The expected error injection position is reversed, and after the error injection frame CRC is calculated, the reorganized configuration information is rewritten through the internal configuration interface to complete the error injection. On the one hand, the present application improves the flexibility of the soft error injection method, and on the other hand, provides different user functions, provides the applicability of soft error insertion of different FPGA chips, and at the same time ensures the stability and security of the FPGA chip itself during the soft error injection process.

[0026] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flowchart of soft error injection according to an embodiment of the present application.

[0028] Figure 2It is a structural diagram of a soft error injection system according to an embodiment of the present application.

[0029] Figure 3 It is a detailed flowchart of soft error injection according to an embodiment of the present application.

[0030] Figure 4 It is a schematic diagram of a combined configuration frame according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0032] Description of some concepts:

[0033] FPGA (Field-Programmable Gate Array) is a digital integrated circuit that can be programmed and configured by the user on site (not during manufacturing) to implement various logic functions. The biggest feature of FPGA is its high flexibility and can be reconfigured according to application requirements.

[0034] Soft Error Injection (SEI) is a technical means to test and verify the behavior and response of electronic devices (such as microprocessors, memories, ASICs, etc.) when they are affected by soft errors. Soft errors refer to instantaneous changes in internal data of electronic devices caused by external factors (such as cosmic rays, alpha particle radiation, etc.), which usually do not cause physical damage to the hardware, but can cause the data in the device to be incorrectly flipped or abnormal operation.

[0035] ICAP (Internal Configuration Access Port) is a configuration interface inside the FPGA chip that allows users to access and modify its configuration data during normal operation of the FPGA. The data in the FPGA's internal configuration memory defines its logical functions and interconnection configuration. ICAP provides a path to access this configuration memory. Usually, the FPGA's configuration data is loaded into the FPGA through an external interface (such as JTAG, SPI, serial flash, etc.), but through ICAP, the FPGA's internal logic can also directly access these configuration data. ICAP is the key interface inside the FPGA for accessing and controlling its configuration memory. It can be used to implement advanced functions such as dynamic partial reconfiguration, error repair, and debugging. With the help of ICAP, the flexibility and adaptability of the FPGA are enhanced, especially for high-performance, high-reliability and flexible resource allocation application scenarios.

[0036] ECC (Error Correction Circuit) is a technology used to detect and correct errors in memory or communication data. It is widely used in memory, cache, registers and communication systems. ECC soft error correction circuit is designed to detect and correct instantaneous data bit flips caused by soft errors (such as cosmic rays, radiation, etc.) to ensure the reliability of system data.

[0037] Cyclic Redundancy Check (CRC) is a verification technology used to detect errors in data transmission or storage. CRC is an error detection method based on binary division. It generates a checksum and appends it to the data by performing polynomial operations on the data. When the data is received or read, the receiver recalculates the checksum and compares it with the appended CRC checksum to detect errors in the data.

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0039] The first embodiment of the present application relates to a soft error injection system, which includes a host computer and an FPGA chip, and the host computer and the FPGA chip are communicatively connected. The FPGA chip includes an error injection logic, a configuration circuit and an SRAM. The error injection logic is communicatively coupled to the configuration circuit, and the configuration circuit has an internal configuration interface (ICAP) and a soft error correction circuit (ECC) interface. The configuration circuit is communicatively coupled to the SRAM, and the user stores the user-configured code stream in the SRAM. The ECC interface is used to determine and return the operating status of the ECC circuit inside the FPGA chip.

[0040] The host computer generates the configurable bit information and expected misalignment information of the FPGA chip. In one embodiment, the host computer uses EDA (Electronics Design Automation, Electronic Design Automation) software to generate the configurable bit information and expected misalignment information of the FPGA chip. Through the design of EDA outputting all configuration bit information, the configurable bits of the entire chip can be misaligned, which has a wider coverage for the evaluation of user logic impact and error detection, and is more adaptable to the evaluation of different user designs and different FPGA chips.

[0041] In one embodiment, the configurable bit information includes frame address information, and the expected error bit information is a subset of the configurable bit information selected by the user. The generated configurable bit information and the expected error bit information are sent to the error injection logic. The error injection logic performs soft error injection via the configuration circuit according to the configurable bit information and the expected error bit information, and stores it in the SRAM.

[0042] In this embodiment, the design of arbitrary frame, arbitrary bit, and arbitrary bit error injection based on the expected error information can effectively evaluate the impact of various error types on user logic and the effectiveness of anti-SEU methods under various error types.

[0043] Figure 2 A flowchart of a method in which the error injection logic is configured to perform soft injection is shown. The soft error injection method comprises the following steps:

[0044] Step 101, the error injection logic determines whether the soft error correction circuit ECC inside the FPGA chip is running through the ECC interface.

[0045] In one embodiment, the soft error correction circuit is disposed inside the configuration circuit.

[0046] Step 102: If it is determined that the soft error correction circuit is not running, the error injection logic reads back and stores the configuration frame of the SRAM through the internal configuration interface.

[0047] The ECC interface is used to determine whether the ECC inside the FPGA chip is running. If the ECC is not running, soft errors are injected. Both the ICAP and ECC circuits can read and write the SRAM circuit of the FPGA chip. If the ECC is not judged to be running, it is easy to cause simultaneous reading and writing of the SRAM, causing large-scale soft errors and causing application failure.

[0048] In one embodiment, if it is determined that the soft error correction circuit is running, the error injection logic writes an ECC stop configuration instruction to the configuration circuit through the internal configuration interface. Writing the ECC stop configuration instruction through the internal configuration interface can stop the ECC that is already running on the FPGA chip and avoid simultaneous reading and writing of the SRAM.

[0049] Step 103: the error injection logic inverts the corresponding position bits in the configuration frame according to the expected error injection position information to obtain an error injection configuration frame.

[0050] Step 104, the error annotation logic calculates a cyclic redundancy check (CRC) of the error annotation configuration frame, and generates a new configuration frame according to the write instruction, the error annotation configuration frame and the CRC.

[0051] In one embodiment, generating a new configuration frame according to a write instruction, an error-notation configuration frame, and a CRC includes: combining the write instruction, the error-notation configuration frame, and the CRC to generate a new configuration frame. For example, combining a write instruction segment, an error-notation configuration frame segment, and a CRC segment into a new configuration frame in the order of the write instruction, the error-notation configuration frame, and the CRC.

[0052] In the present invention, CRC calculation is performed on the error-injected configuration frame, and then the write instruction, the error-injected frame, and the CRC are combined into new configuration information and written through ICAP. This can avoid the direct failure of the FPGA chip function due to configuration information verification failure caused by error injection, and can also avoid unexpected error injection caused by errors during the ICAP writing process.

[0053] Step 105 , the error injection logic writes a new configuration frame to the SRAM via the internal configuration interface via the configuration circuit, and sends an error injection completion indication to the host computer.

[0054] The present invention mainly judges the ECC interface signal, under the premise of ensuring that the internal SRAM of the FPGA chip will not be read and written at the same time, combines the configurable bit information and the expected error injection bit information generated by the EDA software, reads back and stores the configuration frame through the internal configuration interface, then inverts the expected error injection bit to obtain the error injection configuration frame, recalculates the CRC for the error injection configuration frame, recombines the error injection configuration frame, CRC and write instructions into new configuration information, and finally writes the new configuration information to the SRAM through the internal configuration interface and outputs an error injection completion indication signal.

[0055] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0056] The structure of the entire soft error injection system is as follows: Figure 2As shown, it includes a host computer system and an FPGA system, and the host computer system generates configurable bit information and expected error bit information. The FPGA system includes an internal configuration circuit module. The configuration circuit has ICAP and ECC interfaces, the internal configuration interface completes the reading and writing of the configuration frame, and the ECC interface completes the ECC status indication. The FPGA system also includes error injection logic, the error injection logic completes the judgment of the ECC status, the ECC stops the configuration instruction writing, the configuration frame reads back, the readback frame data storage, the expected error bit inversion, the configuration frame reorganization, the error injection configuration frame writing and other functions.

[0057] The specific detailed process of soft error injection in one embodiment of the present application is as follows Figure 2 As shown. Combined Figure 2 and Figure 3 As shown, the specific steps of soft error injection are:

[0058] 1. The EDA software outputs the configurable bit information and expected error position information of the FPGA chip. The configurable bit information must be accurate to the bit and contain the frame address information. The expected error position information is a subset of the configurable bit information selected by the user.

[0059] 2. Determine whether the ECC inside the FPGA chip is running through the ECC interface. If it is determined that the ECC inside the FPGA chip is running, proceed to step 3. If it is determined that the ECC inside the FPGA chip is not running, proceed to step 4.

[0060] 3. Write the ECC stop configuration instruction through the internal configuration interface ICAP, and then proceed to step 2.

[0061] 4. Read back the configuration frame through the internal configuration interface ICAP.

[0062] 5. Store data for the read-back configuration frame.

[0063] 6. Invert the expected error-injection bits of the stored configuration frame to obtain an error-injection configuration frame.

[0064] 7. Calculate the CRC of the error-injected configuration frame.

[0065] 8. Combine the write instruction, error-notation frame, and CRC into new configuration information.

[0066] refer to Figure 4 As shown, the write instruction segment, the error frame segment, and the CRC segment are sequentially combined to form a new configuration frame, wherein the number of bytes of the write instruction segment is, for example, 4 bytes, the number of bytes of the error frame segment is, for example, 324 bytes, and the number of bytes of the CRC segment is, for example, 4 bytes.

[0067] 9. Write new configuration information through the internal configuration interface ICAP.

[0068] 10. Output the error completion indication.

[0069] The second embodiment of the present application relates to an FPGA chip, the FPGA chip includes an error injection logic, a configuration circuit and an SRAM. The configuration circuit has an internal configuration interface and an ECC interface. The error injection logic is configured to perform the following steps:

[0070] Step 1: Receive the configurable bit information and expected misalignment information of the FPGA chip from the host computer.

[0071] Step 2: Determine whether the ECC inside the FPGA chip is running through the ECC interface.

[0072] Step 3: If it is determined that the ECC is not running, read back and store the configuration frame of the SRAM through the internal configuration interface.

[0073] Step 4: invert the bits at corresponding positions in the configuration frame according to the expected error injection information to obtain an error injection configuration frame.

[0074] Step 5, calculate the CRC of the error-injected configuration frame, and generate a new configuration frame based on the write instruction, the error-injected configuration frame and the CRC.

[0075] Step 6: Write a new configuration frame to the SRAM via the configuration circuit through the internal configuration interface, and send an error injection completion indication to the host computer.

[0076] In one embodiment, if it is determined that the ECC is running, the error injection logic writes an ECC stop configuration instruction to the configuration circuit through the internal configuration interface.

[0077] The first implementation manner is a method implementation manner corresponding to the present implementation manner. The technical details in the first implementation manner can be applied to the present implementation manner, and the technical details in the present implementation manner can also be applied to the first implementation manner.

[0078] Accordingly, the embodiments of the present application also provide a computer-readable storage medium, in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition herein, computer-readable storage media do not include transient computer-readable media (transitory media), such as modulated data signals and carriers.

[0079] In addition, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and when the computer executable instructions are executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0080] It should be noted that, in the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means at least the meaning of performing the action according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Multiple, multiple, multiple, etc. expressions include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0081] The serial numbers used in describing the steps of the method do not themselves constitute any limitation on the order of these steps. For example, the step with a larger serial number does not necessarily have to be executed after the step with a smaller serial number. The step with a larger serial number may be executed first and then the step with a smaller serial number. They may also be executed in parallel, as long as this execution order is reasonable for those skilled in the art. For another example, multiple steps with consecutive serial numbers (e.g., step 101, step 102, step 103, etc.) do not limit other steps that can be executed in between. For example, there may be other steps between step 101 and step 102.

[0082] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0083] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0084] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A soft error injection system, characterized in that: It includes a host computer and an FPGA chip, wherein the FPGA chip includes an error injection logic, a configuration circuit and an SRAM, and the configuration circuit has an internal configuration interface and an ECC interface; The host computer generates configurable bit information and expected misalignment information of the FPGA chip; The error injection logic determines whether the soft error correction circuit inside the FPGA chip is running through the ECC interface; If it is determined that the soft error correction circuit is not operating, the error injection logic reads back and stores the configuration frame of the SRAM through the internal configuration interface; The error injection logic inverts the corresponding position bits in the configuration frame according to the expected error injection position information to obtain an error injection configuration frame; The error injection logic calculates a CRC of the error injection configuration frame, and generates a new configuration frame according to a write instruction, the error injection configuration frame, and the CRC; and The error injection logic writes the new configuration frame to the SRAM via the configuration circuit through the internal configuration interface, and sends an error injection completion indication to the host computer.

2. The soft error injection system according to claim 1, characterized in that: The configurable bit information includes frame address information, and the expected offset bit information is a subset of the configurable bit information selected by a user.

3. The soft error injection system according to claim 1, characterized in that: If it is determined that the soft error correction circuit is operating, the error injection logic writes an ECC stop configuration instruction to the configuration circuit through the internal configuration interface.

4. The soft error injection system according to claim 1, characterized in that: The host computer uses EDA software to generate the configurable bit information and expected misalignment information of the FPGA chip.

5. The soft error injection system according to claim 1, characterized in that: The soft error correction circuit is arranged inside the configuration circuit.

6. The soft error injection system according to claim 1, characterized in that: Generating a new configuration frame according to a write instruction, the error annotation configuration frame and the CRC includes: combining the write instruction, the error annotation configuration frame and the CRC to generate a new configuration frame.

7. An FPGA chip, characterized in that: The invention comprises an error injection logic, a configuration circuit and an SRAM, wherein the configuration circuit has an internal configuration interface and an ECC interface; the error injection logic is configured to perform the following steps: Receiving configurable bit information and expected misalignment information of the FPGA chip from a host computer; Determining whether a soft error correction circuit inside the FPGA chip is running through the ECC interface; If it is determined that the soft error correction circuit is not operating, reading back and storing the configuration frame of the SRAM through the internal configuration interface; Inverting the corresponding position bits in the configuration frame according to the expected error injection information to obtain an error injection configuration frame; Calculating the CRC of the error-injected configuration frame, and generating a new configuration frame according to a write instruction, the error-injected configuration frame and the CRC; as well as The new configuration frame is written into the SRAM via the configuration circuit through the internal configuration interface, and an error injection completion indication is sent to the host computer.

8. The FPGA chip as claimed in claim 7, characterized in that: If it is determined that the soft error correction circuit is operating, the error injection logic writes an ECC stop configuration instruction to the configuration circuit through the internal configuration interface.

Images