Processor with pipeline processing design and execution path prediction method

Abstract

The present invention proposes a processor with pipeline processing design and an execution path prediction method. The processor with pipeline processing design includes a memory controller, an instruction cache module, a sending unit, a scheduler and an execution unit; the execution path prediction method includes: taking the execution of the instruction as the predicted satisfied condition of the conditional jump; when the instruction with a jump request is read, detecting whether the satisfied condition of the conditional jump corresponding to the conditional jump prediction instruction occurs; when the satisfied condition of the conditional jump does not occur, the pipeline continues to execute the next instruction; when the satisfied condition of the conditional jump occurs, the program pointer moves to the specified position requested by the satisfied conditional jump instruction, and the pipeline continues to execute the instruction from the specified position requested by the conditional jump instruction. The present invention can reduce the effect loss due to incorrect prediction by designing the cache column with a jump address, thereby improving the execution efficiency of the program.

Description

Technical Field

[0001] The present invention provides a processor with pipeline processing design and an execution path prediction method, which relate to the technical field of data prediction, and in particular to the technical field of a processor with pipeline processing design and an execution path prediction method. Background Art

[0002] Generally, the execution of an instruction in a processor (CPU) usually requires the following steps: fetch (get instruction), decode (decode instruction), execute (execute instruction) and write-back (write back data). When all the steps in each stage are fully executed, it means that an instruction is completed.

[0003] The pipeline processing of the processor can execute the above steps simultaneously and in stages. For example, when the previous instruction A is executed to the decoding instruction, the next instruction B can start to execute the fetch instruction. In this way, the time required to execute all instructions can be shortened through this execution method.

[0004] However, for certain instructions, such as the "if" instruction, the next instruction must be determined based on whether the result of the "if" formula is "true" or "false", so you must wait until the "if" instruction is executed before you know what the next instruction is. At this point, the execution efficiency of the processor is undoubtedly reduced. Therefore, today's processors are designed with a branch prediction mechanism for this situation. This is for this kind of if instruction. Before it is executed, it first predicts whether the execution result may be true or false, and then puts the corresponding conditional instructions into the pipeline.

[0005] The use of branch prediction ranges from methods that simply generate the same prediction each time to methods that maintain a complex record of previous branches in the program to generate a record-based prediction. Branch prediction can be facilitated by hardware optimizations, compiler optimizations, or both. Based on the predictions provided by the branch prediction mechanism, instructions can be accessed and executed predictively. When the branch instruction is finally evaluated, the branch prediction can be confirmed. If the prediction is incorrect, any instructions that were predicted to be executed based on the incorrect prediction can be undone. However, high branch prediction accuracy means more complex algorithms and also affects the CPU cycle time. Summary of the invention

[0006] The present invention provides a processor with pipeline processing design and an execution path prediction method to solve the problem that incorrect prediction may cause effect loss.

[0007] The present invention proposes a processor with pipeline processing design and an execution path prediction method. The processor with pipeline processing design includes a memory controller, an instruction cache module, a sending unit, a scheduler and an execution unit; wherein the memory controller is electrically connected to the instruction cache module; the instruction cache module is electrically connected to the sending unit; the sending unit is electrically connected to the scheduler; and the scheduler is electrically connected to the execution unit.

[0008] Furthermore, the scheduler is electrically connected to the execution unit including a first electrical connection channel and a second electrical connection channel; wherein the first electrical connection channel is used to send operation data to the scheduler; and the second electrical connection channel is used to confirm that the operation data is resent to the scheduler.

[0009] Furthermore, the memory controller is electrically connected to a system memory of a system in which the processor is located.

[0010] Furthermore, the processor with pipeline processing design also includes a branch prediction unit and a data cache module; wherein the branch prediction unit is electrically connected to the execution unit, and the branch prediction unit is electrically connected to the instruction cache module; the data cache module is electrically connected to the execution unit and the memory controller respectively.

[0011] Furthermore, the processor with pipeline processing design also includes a bus; wherein the bus is electrically connected to the execution unit.

[0012] Furthermore, the execution path prediction method of the processor with pipeline processing design includes:

[0013] The execution of the instruction is regarded as the prediction that the condition of the conditional jump is satisfied;

[0014] When an instruction with a jump request is read, it is detected whether the satisfying condition of the conditional jump corresponding to the conditional jump prediction instruction occurs;

[0015] When the satisfying condition of the conditional jump does not occur, the pipeline continues to execute the next instruction;

[0016] When the condition of the conditional jump is satisfied, the program pointer moves to the specified position requested by the conditional jump instruction that satisfies the condition, and the pipeline continues to execute instructions from the specified position requested by the conditional jump instruction.

[0017] Furthermore, when the instruction with the jump request is executed for the first time, regardless of whether the previous instruction has been executed, it is regarded that the condition of the conditional jump is not satisfied.

[0018] Furthermore, when the condition of the conditional jump is satisfied, when the instruction with the jump request is executed again, the program pointer moves to the position specified by the jump request.

[0019] Furthermore, the position corresponding to the conditional jump is recorded in a conditional jump record table, and each position corresponding to the conditional jump can be marked as valid or invalid.

[0020] Further, the instruction weight coefficient and weight update coefficient of the instruction are calculated, and then the weight adjustment coefficient is calculated to adjust the weight of the instruction, including:

[0021] Acquire historical execution data of the instruction, and calculate the instruction weight coefficient of the instruction according to the historical execution data of the instruction;

[0022] The calculation formula of the instruction weight coefficient is:

[0023]

[0024] Among them, Q zli is the instruction weight coefficient of the ith instruction, j is the number of instruction execution records in the data collection period, S i is the time decay factor of the i-th record, which is used to reduce the impact of old execution records on the current weight. i is the number of successful executions of the instruction in the i-th record, L vi is the preset weight of the instruction in the i-th record, Z i is the total number of executions of the instructions in the i-th record;

[0025] Generate an execution prediction path based on the instruction execution order combined with the instruction weight order;

[0026] Comparing the instruction weight coefficient of each instruction with the preset weight range to obtain a weight comparison result;

[0027] The weight comparison result includes out-of-range instructions and in-range instructions;

[0028] Eliminate out-of-range instructions in the execution prediction path to obtain the execution update path;

[0029] Acquire instruction execution dynamic change data, and update historical execution data of the instruction according to the instruction execution dynamic change data to obtain instruction update data;

[0030] Calculating a weight update coefficient of the instruction based on the weight comparison result, the instruction weight coefficient and the instruction update data;

[0031] The calculation formula of the weight update coefficient is:

[0032]

[0033] Among them, G zli is the weight update coefficient of the ith instruction, ΔC i is the increase in the number of successful executions of the instruction in the i-th record, ∇C i is the number of successful executions of the instruction in the i-th record;

[0034] The instruction weight coefficient of the instruction is updated according to the weight update coefficient, and then the execution update path is updated to obtain the execution change path;

[0035] When the instruction weight coefficient is outside the preset weight range and the weight update coefficient is within the preset weight range, the weight adjustment coefficient is calculated according to the instruction weight coefficient, the weight update coefficient and the preset weight range;

[0036] The calculation formula of the weight adjustment coefficient is:

[0037]

[0038] Among them, T ys is the weight adjustment coefficient, X x is the lower limit of the preset weight range, S x is the upper limit of the preset weight range;

[0039] The weight of the corresponding instruction is adjusted according to the weight adjustment coefficient until the weight of the instruction is within a preset weight range.

[0040] Beneficial effects of the present invention: By designing the cache column with a jump address, the effect loss due to incorrect prediction can be reduced, thereby improving the execution efficiency of the program. Through instruction caching and branch prediction technology, the number of accesses and delays to the system memory are reduced, and the execution efficiency of instructions is improved. Pipeline processing allows instructions to be executed in parallel, further improving the throughput of the processor. The design of dual electrical connection channels (the first channel is used for normal transmission and the second channel is used for retry) makes the processor more flexible and reliable when handling abnormal situations. The bus interface provides the ability to communicate with external devices, enhancing the scalability and compatibility of the processor. The scheduler performs intelligent scheduling based on the dependency relationship and resource availability of instructions, ensuring the effective use of resources and avoiding unnecessary conflicts. The data cache module reduces the delay and bandwidth consumption of data access, and improves the overall performance of the system. Efficient instruction execution and data management capabilities enable the processor to respond to user requests more quickly, improving the user experience. Reliable error handling and retry mechanisms ensure the stability and reliability of the system, and reduce the risk of system crashes and data loss caused by hardware failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of the prediction method of the present invention;

[0042] Figure 2 is a block diagram of the processor architecture of the present invention;

[0043] Figure 3 It is a schematic diagram of the structure of the branch prediction unit of the processor architecture of the present invention. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0045] One embodiment of the present invention proposes a processor with pipeline processing design and an execution path prediction method, wherein the processor with pipeline processing design includes a memory controller, an instruction cache module, a sending unit, a scheduler and an execution unit; wherein the memory controller is electrically connected to the instruction cache module; the instruction cache module is electrically connected to the sending unit; the sending unit is electrically connected to the scheduler; and the scheduler is electrically connected to the execution unit.

[0046] The scheduler is electrically connected to the execution unit through a first electrical connection channel and a second electrical connection channel; wherein the first electrical connection channel is used to send operation data to the scheduler; and the second electrical connection channel is used to confirm that the operation data is resent to the scheduler.

[0047] The memory controller is electrically connected to the system memory of the system where the processor is located.

[0048] The processor with pipeline processing design also includes a branch prediction unit and a data cache module; wherein the branch prediction unit is electrically connected to the execution unit, and the branch prediction unit is electrically connected to the instruction cache module; the data cache module is electrically connected to the execution unit and the memory controller respectively.

[0049] The processor with pipeline processing design also includes a bus; wherein the bus is electrically connected to the execution unit.

[0050] The working principle of the above technical solution is as follows: the processor 100 shown in the embodiment of the present invention includes a sending unit 101 which can be configured to receive instructions from an instruction cache 102, and the sending unit 101 can send instructions to a scheduler 103, and the instruction cache 102 is connected to a memory controller 104. The scheduler 103 can be connected to an execution unit 105, and the scheduler 103 is used to store operation information waiting for decision. The execution unit 105 can be configured as a load / store unit for executing access to a data cache 106, and the result generated by the execution unit 105 can be output to a bus 107, and the data stream from the bus 107 can enter the execution unit 105; further, the data cache 106 is connected to the memory controller 104, and the execution unit 105 can provide a replay indication 108 to confirm that the operation is resent to the scheduler 103.

[0051] Secondly, the processor 100 has a branch prediction unit 109 connected to the execution unit 105 and the instruction cache 102. The memory controller 104 is connected to the system memory 110.

[0052] In one embodiment, the processor 100 may be designed to be compatible with the x86 architecture. It should be noted that the processor 100 includes a branch prediction unit 109. The branch prediction unit 109 is used to temporarily store information including program locations.

[0053] This embodiment points out a specific embodiment. Figure 3 As shown, the branch prediction unit 109 includes a conditional jump record table 120. The fields of the conditional jump record table 120 include but are not limited to a tag column 121, an address column 122, and a status column 123. It is understandable that the conditional jump record table 120 is used to record the high byte or tag of the address of the conditional jump instruction, the target jump position of the jump instruction, and whether the data or program is currently valid or invalid.

[0054] The information in the conditional jump record table 120 can be automatically loaded and updated. For example, when a jump instruction is executed for the first time, it is still executed in sequence according to the program line, and the jump address required in the jump instruction is recorded in the conditional jump record table 120 and recorded as invalid. After one or more execution results, in particular, when the jump instruction is executed again under the preset jump condition, the program pointer (program counter) can be moved to the jump position according to the required jump address, and the status in the jump record table 120 is changed to valid. In addition, when the jump position has not been executed for too long, the status in the jump record table 120 will also be changed to invalid.

[0055] The above-mentioned preset jump condition includes but is not limited to the execution of an instruction. The situation where the preset jump condition is satisfied can be that if a non-jump previous instruction is executed, and the content executed by the non-jump previous instruction matches the default jump condition set in the jump instruction, it can be regarded as satisfying the preset jump condition, so when the jump instruction is executed, the program pointer (program counter) moves to the jump position.

[0056] Therefore, predicting which branch will be executed before the jump instruction is executed can be used to improve the performance of the processor's instruction pipeline. An embodiment of the present invention discloses a method for performing prediction, such as Figure 1 As shown, when executing the program, the instruction list is read one by one and in sequence, and an instruction with a conditional jump is read (such as block 301); then, a judgment is performed to check whether the jump address that is the jump condition is met has been moved to the buffer as data (such as block 302); if the data data position obtained by the instruction from the conditional jump record table is invalid, the pipeline continues to execute the next instruction, such as block 303. If the data position obtained by the instruction from the conditional jump record table is valid, the program pointer (program counter) moves to the default jump position, such as block 304; then the execution of the program continues to execute instructions from the position pointed to by the program pointer (program counter), such as block 305.

[0057] According to the above description, the processor and prediction method disclosed in the embodiments of the present invention can reduce the effect loss due to incorrect prediction, thereby improving the execution efficiency of the program.

[0058] When the processor needs to execute a new instruction, the memory controller first reads the instruction data from the system memory and passes it to the instruction cache module. The instruction cache module is responsible for caching these instructions for fast access. The instructions in the instruction cache module are then sent to the sending unit, which is responsible for preparing these instructions in a certain order and format for subsequent processing. The sending unit sends the prepared instructions to the scheduler. The scheduler sorts and schedules the instructions according to the dependency relationship and resource availability of the instructions to ensure that they can be executed in the correct order and timing. The scheduler and the execution unit send operation data through the first electrical connection channel. The execution unit receives the instructions from the scheduler and performs the corresponding operation. If a situation that requires retry or resending is encountered during the execution process (such as cache miss, resource conflict, etc.), the execution unit will send a confirmation signal to the scheduler through the second electrical connection channel to request the resending of the relevant instructions or data. The branch prediction unit predicts the branch path to be executed by analyzing the historical execution mode and the current instruction stream to reduce the delay caused by branch jumps. It is connected to the instruction cache module and the execution unit to obtain and update the prediction information in a timely manner. The data cache module is used to cache the data required by the execution unit to reduce the number of accesses to the system memory. It is connected to the execution unit and the memory controller to ensure that data can be transferred to the execution unit quickly and accurately. The bus is connected to the execution unit and provides a communication interface between the processor and external devices or other parts of the system. Through the bus, the execution unit can exchange data and control information with other processors, memory or other I / O devices.

[0059] The effects of the above technical solution are as follows: through instruction cache and branch prediction technology, the number of accesses and delays to the system memory are reduced, and the execution efficiency of instructions is improved. Pipeline processing allows instructions to be executed in parallel, further improving the throughput of the processor. The design of dual electrical connection channels (the first channel is used for normal transmission and the second channel is used for retry) makes the processor more flexible and reliable when handling abnormal situations. The bus interface provides the ability to communicate with external devices, enhancing the scalability and compatibility of the processor. The scheduler performs intelligent scheduling based on the dependency of instructions and resource availability, ensuring the effective use of resources and avoiding unnecessary conflicts. The data cache module reduces the delay and bandwidth consumption of data access, and improves the overall performance of the system. Efficient instruction execution and data management capabilities enable the processor to respond to user requests more quickly, improving the user experience. Reliable error handling and retry mechanisms ensure the stability and reliability of the system, and reduce the risk of system crashes and data loss caused by hardware failures.

[0060] In one embodiment of the present invention, the execution path prediction method of the processor with pipeline processing design includes:

[0061] The execution of the instruction is regarded as the prediction that the condition of the conditional jump is satisfied;

[0062] When an instruction with a jump request is read, it is detected whether the satisfying condition of the conditional jump corresponding to the conditional jump prediction instruction occurs;

[0063] When the satisfying condition of the conditional jump does not occur, the pipeline continues to execute the next instruction;

[0064] When the condition of the conditional jump is satisfied, the program pointer moves to the specified position requested by the conditional jump instruction that satisfies the condition, and the pipeline continues to execute instructions from the specified position requested by the conditional jump instruction.

[0065] The working principle of the above technical solution is as follows: during the instruction execution process, the processor uses the execution results of certain instructions (especially conditional jump instructions) as the basis for subsequent jump prediction. This prediction is based on the historical execution mode and the current context information, and attempts to determine in advance whether the conditional jump will occur. When a conditional jump instruction is encountered in the instruction stream, the processor reads the instruction and recognizes that it is an instruction that requires a jump judgment. At this time, the processor checks the prediction information associated with the conditional jump instruction. The processor checks the current state or register value, etc. according to the specific conditions of the conditional jump instruction to determine whether the condition is met. This step is the key to determining whether the jump needs to be actually executed. If the condition is not met (that is, the prediction does not occur or the actual detection does not occur), the processor will continue to execute the next instruction along the current pipeline without changing the execution path. If the condition is met (that is, the prediction occurs and the actual detection also occurs), the processor will update the program pointer (PC) to point it to the specified position requested by the conditional jump instruction. Subsequently, the pipeline will continue to execute instructions from the new position to achieve the jump of the execution path.

[0066] The effect of the above technical solution is that through conditional jump prediction, the processor can make a decision in advance whether to jump, thereby reducing the delay caused by waiting for the conditional judgment result. This is crucial to improving the execution efficiency and response speed of the program. When the prediction is accurate, the processor can continuously execute multiple instructions in the instruction stream without interruption due to conditional jumps. This helps to improve the instruction throughput of the processor, enabling it to handle more workloads. The prediction and jump mechanism enables the processor to use pipeline resources more efficiently. When it is predicted that a conditional jump will occur, the processor can prepare instructions and data at the jump target in advance, thereby reducing waste caused by resource conflicts or waiting. Overall, the method improves the execution efficiency and performance of the program by optimizing the processing flow of conditional jumps. This is particularly important for programs that need to process a large number of conditional branches and complex control flows. For users, faster program response and higher execution efficiency represent a better user experience. Whether it is handling daily tasks or running large applications, users can feel a significant performance improvement.

[0067] In one embodiment of the present invention, when the instruction with the jump request is executed for the first time, no matter whether the previous instruction has been executed or not, it is considered that the condition of the conditional jump is not satisfied.

[0068] The working principle of the above technical solution is as follows: when parsing the instruction stream, the processor tracks the execution status of each instruction. When encountering an instruction with a jump request and this is the first execution of the instruction in the current context, the processor will specifically mark this. Due to the lack of historical execution data or context information to accurately predict whether the conditional jump will actually occur, the processor takes a conservative assumption that the condition of the conditional jump is not satisfied. This means that the processor will not risk changing the current execution path if there is not enough evidence to support that the conditional jump will occur. Based on the above assumption, the processor will continue to execute subsequent instructions along the current pipeline without performing a jump operation. Doing so can ensure the stability of the program flow and avoid execution errors or performance degradation caused by incorrect jump predictions. When the conditional jump instruction is actually executed and its condition is determined to be satisfied or not satisfied, the processor will update the prediction information associated with the instruction. This information will be used in future executions to more accurately predict the behavior of the conditional jump.

[0069] The effect of the above technical solution is that by adopting a conservative prediction strategy at the first execution, the processor reduces the risk of execution path errors caused by incorrect predictions. This helps to improve the execution stability and reliability of the program. In the absence of sufficient information to support complex predictions, choosing a simple conservative strategy can simplify the prediction logic of the processor and reduce the difficulty and cost of implementation. As the program is executed and the prediction information is accumulated, the processor can gradually improve the prediction accuracy of conditional jumps. This gradual optimization process helps to improve performance while maintaining stability. By avoiding risky jump predictions at the first execution, the processor reduces performance fluctuations caused by prediction errors. This is particularly important for applications that require stable performance. During the program or system startup phase, many instructions are executed for the first time. Adopting a conservative prediction strategy can ensure that these instructions can be executed smoothly, thereby supporting a fast startup and initialization process.

[0070] According to an embodiment of the present invention, when the condition of the conditional jump is satisfied and the instruction with the jump request is executed again, the program pointer moves to the position specified by the jump request.

[0071] The working principle of the above technical solution is as follows: when the processor encounters a conditional jump instruction, it first evaluates the conditional expression associated with the instruction. This usually involves checking a specific register, memory location, or the execution result of a previous instruction. The processor determines whether the condition is satisfied based on the evaluation result of the conditional expression. If the condition is true (i.e. satisfied), the processor decides to execute the jump operation. Once the decision to execute the jump is made, the processor looks for the jump target address specified in the conditional jump instruction. This address is a specific location in the program, usually a label or memory address, which identifies the sequence of instructions that should be executed after the jump. The processor updates the current program pointer (PC) to the jump target address. This step is key to changing the execution path because it indicates where the instructions should be read and executed next. Due to the update of the program pointer, the processor's instruction pipeline is redirected to load instructions from the new address. Subsequent instruction acquisition, decoding, and execution operations will be based on the new execution path. Once the instruction pipeline is redirected, the processor will continue to execute instructions starting from the jump target address. Some instructions that were originally on the current execution path are skipped and directly jump to another code block for execution.

[0072] The effect of the above technical solution is: conditional jump allows the program to selectively execute code blocks based on conditions, thereby avoiding the execution of unnecessary instructions. This helps to reduce the execution time and resource consumption of the program and improve overall efficiency. Through conditional jumps, the program can control the execution flow more flexibly and implement complex control logic and decision-making processes. This is essential for developing applications with complex functions and behaviors. Conditional jumps enable programmers to organize code to express logical structures in a more natural and intuitive way. For example, control flow structures such as loops and conditional statements can be implemented based on conditional jump instructions, making the code clearer and easier to understand. In modular programming, conditional jumps can help implement the call and return of functions or subroutines. By jumping to a specific code block and executing the instructions in that block, the program can reuse and share code, reduce redundancy and improve maintainability. In applications that require fast response, conditional jumps can reduce processing time and speed up decision-making.

[0073] In one embodiment of the present invention, the position corresponding to the conditional jump is recorded in a conditional jump record table, and each position corresponding to the conditional jump can be marked as valid or invalid.

[0074] The working principle of the above technical solution is as follows: when the compiler or assembler processes the source code or assembly code, it generates an entry for each conditional jump instruction and adds it to the conditional jump record table. This entry contains at least two key information: the identifier of the conditional jump instruction (such as a label or address) and the address of the target location. In some cases, the location of the jump target may become invalid. For example, if the jump target is located in a deleted or reconstructed code block, or the jump is no longer needed due to changes in the conditional logic. In these cases, the processor or related software will update the conditional jump record table and mark the corresponding jump location as invalid. When the processor executes a conditional jump instruction, it will first look up the conditional jump record table to obtain the target address and check the validity of the address. If the target address is marked as valid, the processor will perform the jump operation normally; if the target address is marked as invalid, the processor may take specific error handling measures, such as throwing an exception, executing an alternate code path, or continuing to execute the next instruction. During program execution, if changes in the validity of jump target locations are detected (e.g., through runtime analysis or dynamic code generation), the processor or associated software can dynamically update the conditional jump record table to reflect these changes.

[0075] The effect of the above technical solution is: by marking the validity of the jump position in the conditional jump record table, the processor can avoid executing to invalid or deleted code areas, thereby improving the stability and reliability of the program. The conditional jump record table provides a way to centrally manage jump information, making it easier to track and update the validity of the jump target when modifying or refactoring the code. This helps to reduce errors caused by missing or erroneous updates to jump information. At runtime, the processor or related software can dynamically update the conditional jump record table according to the actual execution of the program to optimize the execution path and performance. For example, if a conditional jump is not satisfied in most cases, the processor may choose to skip the prediction and checking process of the jump to reduce overhead. The conditional jump record table provides a structured way to organize and represent jump information, making the logical structure and control flow of the code clearer and easier to understand. This helps other developers become familiar with and modify the code faster. In modular programming, the conditional jump record table can help achieve decoupling and independent updates between modules. By updating the jump record table instead of modifying the jump logic inside the module, it is easier to replace or upgrade the module without affecting other parts of the program.

[0076] In one embodiment of the present invention, the instruction weight coefficient and the weight update coefficient of the instruction are calculated, and then the weight adjustment coefficient is calculated to adjust the weight of the instruction, including:

[0077] Acquire historical execution data of the instruction, and calculate the instruction weight coefficient of the instruction according to the historical execution data of the instruction;

[0078] The calculation formula of the instruction weight coefficient is:

[0079]

[0080] Among them, Q zli is the instruction weight coefficient of the ith instruction, j is the number of instruction execution records in the data collection period, S i is the time decay factor of the i-th record, which is used to reduce the impact of old execution records on the current weight. i is the number of successful executions of the instruction in the i-th record (conditional jumps are satisfied), L vi is the preset weight of the instruction in the i-th record, Z i is the total number of executions of the instruction in the i-th record (regardless of whether the conditional jump is met);

[0081] Generate an execution prediction path based on the instruction execution order combined with the instruction weight order;

[0082] Comparing the instruction weight coefficient of each instruction with the preset weight range to obtain a weight comparison result;

[0083] The weight comparison result includes out-of-range instructions and in-range instructions;

[0084] Eliminate out-of-range instructions in the execution prediction path to obtain the execution update path;

[0085] Acquire instruction execution dynamic change data, and update historical execution data of the instruction according to the instruction execution dynamic change data to obtain instruction update data;

[0086] Calculating a weight update coefficient of the instruction based on the weight comparison result, the instruction weight coefficient and the instruction update data;

[0087] The calculation formula of the weight update coefficient is:

[0088]

[0089] Among them, G zli is the weight update coefficient of the ith instruction, ΔC i is the increase in the number of successful executions (conditional jumps) of the instruction in the i-th record, ∇C i is the number of successful executions of the instruction in the i-th record (jump conditionally satisfied);

[0090] The instruction weight coefficient of the instruction is updated according to the weight update coefficient, and then the execution update path is updated to obtain the execution change path;

[0091] When the instruction weight coefficient is outside the preset weight range and the weight update coefficient is within the preset weight range, the weight adjustment coefficient is calculated according to the instruction weight coefficient, the weight update coefficient and the preset weight range;

[0092] The calculation formula of the weight adjustment coefficient is:

[0093]

[0094] Among them, T ys is the weight adjustment coefficient, X x is the lower limit of the preset weight range, S x is the upper limit of the preset weight range;

[0095] The weight of the corresponding instruction is adjusted according to the weight adjustment coefficient until the weight of the instruction is within a preset weight range.

[0096] The working principle of the above technical solution is as follows: the system obtains the historical execution data of each instruction, including the number of execution records of the instruction, the time decay factor of each record (to reduce the influence of old data), the number of successful executions of each record, the preset weight and the total number of executions. The instruction weight coefficient of each instruction is calculated using these historical data. This method takes into account time decay, the number of successful executions, the preset weight and the total number of executions to ensure that the influence of old data gradually weakens, while highlighting the importance of the number of successful executions. The system generates an execution prediction path based on the execution order of the instructions and the instruction weight order. This path reflects the instruction execution order predicted based on the current weight coefficient. The instruction weight coefficient of each instruction is compared with the preset weight range, and the instructions with weights outside the range are regarded as abnormal or adjusted instructions, so as to eliminate these instructions and obtain the updated execution path. The system obtains the dynamic change data of instruction execution, updates the historical execution data, and calculates the weight update coefficient of each instruction. This coefficient takes into account the increase in the number of successful executions to reflect the improvement or deterioration of instruction performance. The instruction weight coefficient is updated using the weight update coefficient, and the execution path is updated accordingly to obtain the execution change path. This step ensures that the path can be adjusted according to the latest changes in instruction performance. For instructions with weights outside the preset range, if their weight update coefficients are within the preset range, the system calculates the weight adjustment coefficient and uses it to adjust the instruction weight until the weight returns to the preset range. This step ensures the stability and rationality of instruction weights.

[0097] The effect of the above technical solution is: by dynamically adjusting the instruction weights, the system can predict and execute instructions more accurately, reduce unnecessary execution overhead, and improve overall execution efficiency. The system can update the weights in real time according to the dynamic changes in instruction execution, adapt to different execution environments and conditions, and enhance the adaptability and robustness of the system. Through weight adjustment, the system can more reasonably allocate resources to important instructions, ensure that key tasks are given priority, and improve resource utilization. The improvement of the accuracy and efficiency of instruction execution, as well as the optimization of resource allocation, will ultimately enhance the overall user experience and enable users to complete tasks more efficiently. Through automated weight calculation and adjustment, the system reduces the need for manual intervention and reduces the maintenance cost of the system.

[0098] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for predicting an execution path of a processor with a pipeline processing design, characterized in that: The execution path prediction method of the processor with pipeline processing design includes: The execution of the instruction is regarded as the prediction that the condition of the conditional jump is satisfied; When an instruction with a jump request is read, it is detected whether the satisfying condition of the conditional jump corresponding to the conditional jump prediction instruction occurs; When the satisfying condition of the conditional jump does not occur, the pipeline continues to execute the next instruction; When the satisfying condition of the conditional jump occurs, the program pointer moves to the specified position requested by the conditional jump instruction that satisfies the condition, and the pipeline continues to execute instructions from the specified position requested by the conditional jump instruction; Obtain historical execution data of instructions, calculate instruction weight coefficients of instructions, generate execution prediction paths, update historical execution data of instructions, obtain instruction update data, calculate weight update coefficients of instructions, update instruction weight coefficients of instructions, obtain execution change paths, calculate weight adjustment coefficients, and adjust weights of corresponding instructions; wherein historical execution data of the instruction is obtained, and an instruction weight coefficient of the instruction is calculated according to the historical execution data of the instruction; The calculation formula of the instruction weight coefficient is: Among them, Q zli is the instruction weight coefficient of the ith instruction, j is the number of instruction execution records in the data collection period, S i is the time decay factor of the i-th record, which is used to reduce the impact of old execution records on the current weight. i is the number of successful executions of the instruction in the i-th record, L vi is the preset weight of the instruction in the i-th record, Z i is the total number of executions of the instructions in the i-th record; Generate an execution prediction path based on the instruction execution order combined with the instruction weight order; Compare the instruction weight coefficient of each instruction with the preset weight range to obtain a weight comparison result; The weight comparison result includes out-of-range instructions and in-range instructions; Eliminate out-of-range instructions in the execution prediction path to obtain the execution update path; Acquire instruction execution dynamic change data, and update historical execution data of the instruction according to the instruction execution dynamic change data to obtain instruction update data; The weight update coefficient of the instruction is calculated based on the weight comparison result, the instruction weight coefficient and the instruction update data.

2. The execution path prediction method of a processor with pipeline processing design according to claim 1, characterized in that: When the instruction with the jump request is executed for the first time, regardless of whether the instruction has been executed before, it is considered that the condition of the conditional jump is not satisfied.

3. The execution path prediction method of a processor with pipeline processing design according to claim 1, characterized in that: When the condition of the conditional jump is satisfied, when the instruction with the jump request is executed again, the program pointer moves to the position specified by the jump request.

4. The execution path prediction method of a processor with pipeline processing design according to claim 1, characterized in that: The positions corresponding to the conditional jumps are recorded in a conditional jump record table, and each position corresponding to the conditional jump can be marked as valid or invalid.

5. The execution path prediction method of a processor with pipeline processing design according to claim 1, characterized in that: Obtain historical execution data of instructions, calculate instruction weight coefficients of instructions, generate execution prediction paths, update historical execution data of instructions, obtain instruction update data, calculate weight update coefficients of instructions, update instruction weight coefficients of instructions, obtain execution change paths, calculate weight adjustment coefficients, and adjust the weights of corresponding instructions, including: The calculation formula of the weight update coefficient is: Among them, G zli is the weight update coefficient of the ith instruction, ΔC i is the increase in the number of successful executions of the instruction in the i-th record, ∇C i is the number of successful executions of the instruction in the i-th record; The instruction weight coefficient of the instruction is updated according to the weight update coefficient, and then the execution update path is updated to obtain the execution change path; When the instruction weight coefficient is outside the preset weight range and the weight update coefficient is within the preset weight range, the weight adjustment coefficient is calculated according to the instruction weight coefficient, the weight update coefficient and the preset weight range; The calculation formula of the weight adjustment coefficient is: Among them, T ys is the weight adjustment coefficient, X x is the lower limit of the preset weight range, S x is the upper limit of the preset weight range; The weight of the corresponding instruction is adjusted according to the weight adjustment coefficient until the weight of the instruction is within a preset weight range.

6. A processor with pipeline processing design, the processor with pipeline processing design comprising a memory controller, an instruction cache module, a sending unit, a scheduler and an execution unit; wherein, The memory controller is electrically connected to the instruction cache module; the instruction cache module is electrically connected to the sending unit; the sending unit is electrically connected to the scheduler; the scheduler is electrically connected to the execution unit, and the processor includes an execution path prediction method as described in any one of claims 1-5.

7. The processor with pipeline processing design according to claim 6, characterized in that: The scheduler is electrically connected to the execution unit through a first electrical connection channel and a second electrical connection channel; wherein the first electrical connection channel is used to send operation data to the scheduler; and the second electrical connection channel is used to confirm that the operation data is resent to the scheduler.

8. The processor with pipeline processing design according to claim 6, characterized in that: The memory controller is electrically connected to the system memory of the system where the processor is located.

9. The processor with pipeline processing design according to claim 6, characterized in that: The processor with pipeline processing design also includes a branch prediction unit and a data cache module; wherein the branch prediction unit is electrically connected to the execution unit, and the branch prediction unit is electrically connected to the instruction cache module; the data cache module is electrically connected to the execution unit and the memory controller respectively.

10. The processor with pipeline processing design according to claim 6, characterized in that: The processor with pipeline processing design also includes a bus; wherein the bus is electrically connected to the execution unit.

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