A memory sharing interaction method and device between BIOS and BMC

Abstract

The invention relates to a memory sharing interaction method and device between BIOS and BMC, the method comprising: after the BMC firmware is burned or updated for the first time, the BMC executes an internal code instruction to read the uplink flag bit information of the uplink domain in the shared memory; after the BIOS firmware is burned or updated for the first time, the BIOS executes a hardware initialization code to read the downlink flag bit information of the downlink domain in the shared memory; the configuration information of the server is obtained and written into the shared memory; after the BMC detects that the boot is completed, the shared memory data interaction of the first boot is completed, all flag bits of the uplink domain are traversed and detected, if there is an item with a flag bit of 1, the data of the uplink data area corresponding to the flag bit Flag is read; if the basic input and output system BIOS is not booted for the first time, the downlink flag bit of the downlink domain in the shared memory is read, if there is a downlink flag bit of 1, the BIOS reads and processes the data of the downlink data area corresponding to the downlink flag bit, and feeds the result back to the baseboard management controller BMC.

Description

Technical Field

[0001] The present invention relates to the field of servers, and in particular to an interactive method and device for memory sharing between a BIOS and a BMC. Background Art

[0002] With the rapid development of the server industry, the demand for server BIOS and BMC is also increasing day by day. The increase in demand will inevitably lead to an increase in the boot time of BIOS, which will also increase the response time of BMC. The traditional Redfish (Redfish is a modern, open standard RESTful API used to manage and monitor hardware devices in data centers, such as servers, storage and network devices) specification can bring good demand expansion, but its transmission method has caused several shortcomings of BIOS: it takes a long time to configure USB Driver, USB LAN, etc.; it uses network transmission and sends in the form of packets, which is slower than memory transmission and is prone to downtime caused by excessive packet size; BMC virtual USB devices are prone to downtime risks. Downtime is caused by interruptions during use. Summary of the invention

[0003] The present invention provides an interactive method and device for memory sharing between BIOS and BMC, aiming to solve at least one of the technical problems existing in the prior art.

[0004] The technical solution of the present invention is a memory sharing interaction method between BIOS and BMC, which is used for communication between a baseboard management controller BMC and a basic input and output system BIOS in a server. The memory sharing interaction method between BIOS and BMC includes the following steps:

[0005] S100, based on the preset shared memory, after the baseboard management controller BMC firmware is burned or updated for the first time, the server is powered on, and the baseboard management controller BMC executes internal code instructions to read the uplink flag bit information of the uplink domain (Host->BMC) in the shared memory;

[0006] S200, after the basic input and output system BIOS firmware is burned or updated for the first time, when the server is powered on for the first time, the basic input and output system BIOS executes the hardware initialization code and reads the downlink flag bit information of the downlink domain (BMC->Host) in the shared memory;

[0007] S300, obtaining the configuration information of the server and writing it into the shared memory, and after the writing is completed, setting the first address flag of the shared memory to 1;

[0008] S400: After the baseboard management controller BMC detects that the boot is completed, the shared memory data interaction of the first boot is completed, and all flags Flag of the upstream domain (Host->BMC) are traversed and detected. If there is an item with the flag Flag as 1, the data in the upstream data area corresponding to the flag Flag is read;

[0009] S500, if the basic input and output system BIOS is not started for the first time, read the downstream flag Flag of the downstream domain (BMC->Host) in the shared memory, if there is a downstream flag Flag that is 1, the basic input and output system BIOS reads and processes the data in the downstream data area corresponding to the downstream flag Flag, and feeds the result back to the baseboard management controller BMC.

[0010] Further, in step S100 and step S200,

[0011] The initial values ​​of all uplink flag information and all downlink flag information are 0.

[0012] Furthermore, the step S300 also includes: converting the configuration information of the acquired server into a Json data format.

[0013] Furthermore, the shared memory is used for the baseboard management controller BMC to communicate with the basic input and output system BIOS of the host through the Host To BMC mechanism, and the shared memory includes an upstream domain (Host->BMC) for storing communication from the host Host to the baseboard management controller BMC and a downstream domain (BMC->Host) for storing communication from the baseboard management controller BMC to the host Host.

[0014] Further, the shared memory includes an uplink flag bit area, a downlink flag bit area, an uplink data storage area and a downlink data storage area, the physical addresses of which are sequentially continuous;

[0015] The uplink domain includes the uplink flag bit area and the uplink data storage area, and the downlink domain includes the downlink flag bit area and the downlink data storage area.

[0016] Further, the uplink flag bit area includes a plurality of uplink flag bits, the storage address of the first uplink flag bit is a base address, and the physical address of the subsequent uplink flag bits is the base address plus an offset byte;

[0017] The downlink flag area includes multiple downlink flags, the storage address of the first downlink flag is the next physical address of the physical address of the last uplink flag in the uplink flag area, and the physical address of the subsequent downlink flag is the storage address of the first downlink flag plus an offset byte.

[0018] Further, the uplink data storage area includes a plurality of uplink data areas, each of which corresponds to a corresponding uplink flag bit, and each of which includes an uplink data starting address and an uplink data size, wherein the uplink data starting address is used to identify a physical starting position of the uplink data, and the uplink data size is used to identify a placeholder size of the uplink data;

[0019] The downlink data storage area includes multiple downlink data areas, each of which corresponds to a corresponding downlink flag bit, and each downlink data area includes a downlink data starting address and a downlink data size. The downlink data starting address is used to identify the physical starting position of the downlink data, and the downlink data size is used to identify the occupied size of the downlink data.

[0020] Further, the base address is obtained in the following manner:

[0021] First, use the UEFI standard function LocateHandleBuffer to locate all EFI standard Pci protocol interfaces gEfiPciIoProtocolGuid;

[0022] Then, traverse the handles Handles and use the UEFI standard function Pci.Read to read the device's VendorId and DeviceId (VendorId and DeviceId are configuration space fields defined by the PCI specification, which store the basic information of the device: VendorId represents the manufacturer ID, such as 0x8086 for Intel, and DevcieId represents a device of the manufacturer), and find the VendorId and DeviceId corresponding to the PCIE (PCI-Express, peripheral component interconnect express, a high-speed serial computer expansion bus standard) device (H2b);

[0023] Finally, the BAR value at 0x10 of the PCIE device (H2b) is read through Pci.Read. The BAR value is the base address of the shared memory address. The base address is stored and transferred in the form of Protocol (in UEFI, Protocol is a data structure that defines specific functions or services. Each Protocol has a globally unique identifier (GUID) that uniquely identifies the Protocol. Protocol can contain data, function pointers, or any other type of information) to facilitate the use of the base address in the startup phase of different basic input and output systems BIOS.

[0024] Furthermore, the present invention also proposes an interactive device for memory sharing between BIOS and BMC, the interactive device for memory sharing between BIOS and BMC is used to implement the interactive method for memory sharing between BIOS and BMC, the interactive device for memory sharing between BIOS and BMC is arranged on a mainboard of a server, and the interactive device for memory sharing between BIOS and BMC at least comprises:

[0025] A baseboard management controller BMC, wherein the baseboard management controller BMC is connected to a central processing unit CPU and a memory DDR on a server mainboard;

[0026] The basic input and output system BIOS is connected to the baseboard management controller BMC and the central processing unit CPU on the server mainboard.

[0027] The beneficial effects of the present invention are:

[0028] The memory sharing interaction method and device between BIOS and BMC can optimize the BIOS boot time, reduce the risk of downtime, increase stability, make address planning clear, adopt flag bit form, and reduce unnecessary running time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is an overall circuit diagram of the memory sharing interaction method between BIOS and BMC according to the present invention.

[0030] Figure 2 It is a schematic diagram of hardware connection of the memory sharing interaction device between BIOS and BMC according to the present invention.

[0031] Figure 3 FIG. 1 is a running example of the memory sharing interaction method between BIOS and BMC according to the present invention.

[0032] Figure 4 Shown is a structural block diagram of a shared memory in the memory sharing interaction method between BIOS and BMC according to the present invention.

[0033] Figure 5 It is a schematic diagram showing the address planning of the shared memory in the memory sharing interaction method between BIOS and BMC according to the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the embodiments and drawings to clearly and completely describe the concept, specific structure and technical effects of the present invention, so as to fully understand the purpose, scheme and effect of the present invention. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0035] It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature, or it may be indirectly fixed or connected to the other feature. In addition, the descriptions of up, down, left, right, top, bottom, etc. used in the present invention are only relative to the relative positional relationship of the components of the present invention in the drawings.

[0036] In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art. The terms used in this specification are only for describing specific embodiments, not for limiting the present invention. The term "and / or" used herein includes any combination of one or more related listed items.

[0037] It should be understood that, although the terms first, second, third, etc. may be used to describe various elements in the present disclosure, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of the present disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0038] Reference Figures 1 to 5 In some embodiments, the present invention proposes a method and device for interactive memory sharing between BIOS and BMC, referring to Figure 1 The memory sharing interaction method between BIOS and BMC is used for communication between baseboard management controller BMC and basic input and output system BIOS in a server. The memory sharing interaction method between BIOS and BMC includes the following steps:

[0039] S100, based on the preset shared memory, after the baseboard management controller BMC firmware is burned or updated for the first time, the server is powered on, the baseboard management controller BMC executes internal code instructions, and reads the upstream flag information Flag of the upstream domain (Host->BMC) in the shared memory;

[0040] S200, after the basic input and output system BIOS firmware is burned or updated for the first time, when the server is powered on for the first time, the basic input and output system BIOS executes the hardware initialization code and reads the downstream flag information Flag of the downstream domain (BMC->Host) in the shared memory;

[0041] S300, obtaining the configuration information of the server and writing it into the shared memory, and after the writing is completed, setting the first address flag of the shared memory to 1;

[0042] S400: After the baseboard management controller BMC detects that the boot is completed, the shared memory data interaction of the first boot is completed, and all flags Flag of the upstream domain (Host->BMC) are traversed and detected. If there is an item with the flag Flag as 1, the data in the upstream data area corresponding to the flag Flag is read;

[0043] S500, if the basic input and output system BIOS is not started for the first time, read the downstream flag Flag of the downstream domain (BMC->Host) in the shared memory, if there is a downstream flag Flag that is 1, the basic input and output system BIOS reads and processes the data in the downstream data area corresponding to the downstream flag Flag, and feeds the result back to the baseboard management controller BMC.

[0044] The beneficial effects of the present invention are:

[0045] The memory sharing interaction method and device between BIOS and BMC can optimize the BIOS boot time, reduce the risk of downtime, increase stability, make address planning clear, adopt flag bit form, and reduce unnecessary running time.

[0046] In a specific embodiment, the baseboard management controller BMC is an AST2600 chip system, the shared memory is a PCIE (Host To BMC) device shared memory in the AST2600 chip of the BMC, and 17MB of memory is allocated for use by both the baseboard management controller BMC and the basic input and output system BIOS.

[0047] Specifically, when configuring shared memory, the allocated memory is planned; the USB LAN physical transmission mode of Redfish is replaced with the reading and writing of shared memory; and the transmission mode of the entire Redfish is replaced with OneByOne.

[0048] Among them, the BIOS processing needs to develop and design a complete set of H2b (Host To BMC) functional solutions, which adopt the OneByOne mode transmission through memory shared reading and writing. The interactive content at least includes BIOS asset information, BIOS password modification and BIOS startup item modification.

[0049] In a specific embodiment,

[0050] In step S100, after the BMC firmware is burned or updated for the first time, when the server is powered on, the BMC will execute its internal code instructions and read the corresponding location Flag information of Host->BMC in the shared memory (in address planning). Since the BIOS has not yet run, all Flags are 0 and no operation is performed.

[0051] In step S200, after the BIOS firmware is burned or updated for the first time, the BIOS will execute the hardware initialization code when the server is powered on for the first time. At this time, the BIOS will read the corresponding location Flag (in address planning) of BMC->Host in the shared memory. Since it is the first time to power on the server, the BMC has no operation, so all Flags are 0.

[0052] In step S300, since the BIOS is turned on for the first time, all the configuration information of this boot (PCIE, firmware version, CPU information, memory information, hard disk information, Setup information, etc.) will be obtained and constructed into a Json data format, and written into the shared memory. After writing is completed, the Post Inventory to BMC complete Flag position is set to 1, that is, offset 0 in the address planning.

[0053] In step S400, after the BMC detects that the boot is complete, it detects all the Flag bits of Host->BMC, and performs the corresponding operation when it detects that a Flag is 1. The memory address data corresponding to the Flag is read, such as Inventory data (Inventory data is asset data information, including at least PCIE asset information, CPU asset information, memory asset information, hard disk asset information, network card asset information and firmware basic information), and the shared memory data interaction of the first boot is completed.

[0054] In step S500, when the BIOS is not booting for the first time, it will still read the corresponding location Flag of BMC->Host in the shared memory. For example, if the offset 1024 is 1, the BIOS will read the memory address data corresponding to the Flag, that is, 0x500400. After receiving the data, the BIOS will process the data and feed the result back to the BMC. The subsequent restart of the BIOS will repeat step S500.

[0055] Further, refer to Figure 1 and Figure 5 In the step S100 and the step S200,

[0056] The initial values ​​of all uplink flag information and all downlink flag information are 0.

[0057] Further, refer to Figure 1 , the step S300 also includes: converting the configuration information of the acquired server into Json data format.

[0058] For example, when pushing the VendorId in the H2b Pcie device information, an instance is

[0059] {

[0060] “VendorId”: “0xFFFF”,

[0061] “DeviceId”: “0xFFFE”

[0062] }

[0063] Further, refer to Figure 4 and Figure 5 The shared memory is used for the baseboard management controller BMC to communicate with the basic input and output system BIOS of the host through the Host To BMC mechanism. The shared memory includes an upstream domain (Host->BMC) for storing the communication from the host Host to the baseboard management controller BMC and a downstream domain (BMC->Host) for storing the communication from the baseboard management controller BMC to the host Host.

[0064] Specifically, the shared memory is used for the PCIE device in the baseboard management controller BMC to communicate with the basic input and output system BIOS of the host through the Host To BMC mechanism.

[0065] Further, refer to Figure 4 and Figure 5 , the shared memory includes an uplink flag bit area, a downlink flag bit area, an uplink data storage area and a downlink data storage area whose physical addresses are sequentially continuous;

[0066] The uplink domain includes the uplink flag bit area and the uplink data storage area, and the downlink domain includes the downlink flag bit area and the downlink data storage area.

[0067] Further, refer to Figure 5 , the uplink flag bit area includes multiple uplink flag bits, the storage address of the first uplink flag bit is the base address, and the physical address of the subsequent uplink flag bits is the base address plus the offset byte;

[0068] The downlink flag area includes multiple downlink flags, the storage address of the first downlink flag is the next physical address of the physical address of the last uplink flag in the uplink flag area, and the physical address of the subsequent downlink flag is the storage address of the first downlink flag plus an offset byte.

[0069] Specifically, refer to Figure 5, the Base column is the base address 0x9f000000, and the offset column corresponds to the offset byte, including the upstream flag area and the downstream flag area, from the offset byte 0 to the offset byte 1023 (0x3FF), that is, the maximum upstream flag address is the base address 0x9f000000 plus the offset byte 511 (0x1FF, that is, 0x9f0001ff), and the maximum downstream flag address is the base address 0x9f000000 plus the offset byte 512 (0x200) + 512 (0x200) (that is, 0x9f0003ff).

[0070] Further, refer to Figure 5 , the uplink data storage area includes a plurality of uplink data areas, each of which corresponds to a corresponding uplink flag bit, and each of which includes an uplink data starting address and an uplink data size, the uplink data starting address is used to identify the physical starting position of the uplink data, and the uplink data size is used to identify the placeholder size of the uplink data;

[0071] The downlink data storage area includes multiple downlink data areas, each of which corresponds to a corresponding downlink flag bit, and each downlink data area includes a downlink data starting address and a downlink data size. The downlink data starting address is used to identify the physical starting position of the downlink data, and the downlink data size is used to identify the occupied size of the downlink data.

[0072] Specifically, refer to Figure 5 , the data starting address corresponding to the first upstream data area is 0x9f500000, and the size is 0x200000. The data starting address corresponding to the second upstream data area is 0x9F700000, and the size is 0x100, and so on.

[0073] Further, the base address is obtained in the following manner:

[0074] First, use the UEFI standard function LocateHandleBuffer to locate all UEFI standard Pci protocol interfaces gEfiPciIoProtocolGuid;

[0075] Then, traverse the handles, use the UEFI standard function Pci.Read to read the device's VendorId and DeviceId, and find the VendorId and DeviceId corresponding to the PCIE device (H2b);

[0076] Finally, the BAR value at 0x10 of the PCIE device (H2b) is read through Pci.Read. The BAR value is the base address of the shared memory address. The base address is stored and transferred in the form of Protocol, which is convenient for using the base address in the startup phase of different basic input and output system BIOS.

[0077] Specifically, the Protocol here is actually a permanent memory area, which is identified by a GUID. This is a standard operation in the UEFI specification, that is, installing a Protocol is equivalent to creating a permanent memory area.

[0078] In a specific embodiment, first, the BIOS needs to develop the required functions according to the requirements, such as shared memory address planning, and develop corresponding functions.

[0079] (1) Automatically obtain the Base Address of the H2b device (Base Address means base address, which implements the automatic acquisition of Base address in address planning): When the configuration of each server is different, the Base Address of the H2b device will be different. Therefore, it is necessary to develop a function to automatically obtain the address. Use the UEFI standard function LocateHandleBuffer to locate all gEfiPciIoProtocolGuid, then traverse the handles Handles, use the standard function Pci.Read to read the device's VendorId and DeviceId, and find the VendorId and DeviceId corresponding to H2b. Then use Pci.Read to read the BAR value at 0x10 of the device. This value is the first address of the shared memory address, that is, the Base in the shared memory address planning.

[0080] (2) The read address is stored and transferred in the form of Protocol, so that the address can be used in different BIOS startup stages: define an OemProtocol (OemProtocol actually refers to H2bHiProtocol, OEM stands for Original Equipment Manufacturer, the full name in Chinese is Original Equipment Manufacturer), name it H2bHiProtocol, and its Interface (Interface is the UEFI interface structure, which is actually a defined C language structure with members such as PciAddress and BaseAddress) member contains

[0081] a) PciAddress (PciAddress is an internal member name of H2bHiProtocol Interface. PciAddress is essentially an MMIO address. MMIO (Memory-Mapped I / O) is a technology used to access and control peripheral devices in computer architecture. In MMIO, the registers of the device are mapped to the address space of the system, so that the CPU can access these registers like accessing memory. This method simplifies the access and control of the device and improves the flexibility and efficiency of the system): the calculation formula is (UINTN)((0x80000000 | (UINT32)Bus << 20 | (UINT32)Dev << 15 | (UINT32)Fun << 12) + 4); that is, it is converted from the BDF of the H2b device. The purpose of obtaining this address is that the BAR address of the device cannot be written after each startup. The position at 0x4 in the Pci configuration space of the device needs to be written to 0x43 before it can be read and written. Write through the standard function MmioWrite8: MmioWrite8(OemH2bHiProtocolInterface->PciAddress,0x43);

[0082] b) BaseAddress (BaseAddress is the base address in (1) above): equal to the BAR value at 0x10 in the PCI configuration space.

[0083] (3) Design and develop other corresponding functional solutions:

[0084] a) In other functions, Locate H2bHiProtocol (LocateProtocol: an instance interface function in the UEFI specification. The internal implementation principle can be found in the open source project EDK2. Its function is to locate a given Protocol and use its interface function. Locata H2bHiProtocol uses the LocateProtocol interface function for positioning and uses the H2bHiProtocol interface function.) to obtain the corresponding BaseAddress, and then fill in the corresponding area content.

[0085] b) The code address is defined as follows:

[0086] typedef enum _H2B_FLAG_OFFSET{

[0087] H2bPostInventory = 0x0,

[0088] H2bBiosAttributeRegistry,

[0089] H2bBiosSD,

[0090] H2bVlan,

[0091] H2bSecureBoot,

[0092] H2bBootOption,

[0093] H2bStaticFiles

[0094] }H2B_FLAG_OFFSET;

[0095] typedef enum _B2H_FLAG_OFFSET{

[0096] B2hResetBios = 0x200,

[0097] B2hPassword,

[0098] B2hBiosSD,

[0099] B2hVlan,

[0100] B2hSecureBoot,

[0101] B2hBootOption,

[0102] B2hIscsi

[0103] }B2H_FLAG_OFFSET;

[0104] #define InventoryDataOffsetSize (0x200000)

[0105] #define BiosAttributeRegistryDataOffsetSize (0x100)

[0106] #define UpdateBiosSDOffsetSize (0x100000)

[0107] #define UpdateVlanDataOffsetSize (0x80000)

[0108] #define BiosSecureBootOffsetSize (0x40000)

[0109] #define BiosBootOptionOffsetSize (0x40000)

[0110] #define BiosStaticFilesOffsetSize (0x200000)

[0111] #define InventoryDataOffset (0x9F500000)

[0112] #define BiosAttributeRegistryDataOffset ((InventoryDataOffset) +(InventoryDataOffsetSize))

[0113] #define UpdateBiosSDOffset ((UpdateBiosPasswordOffset) +(BiosAttributeRegistryDataOffsetSize ))

[0114] #define UpdateVlanDataOffset ((UpdateBiosSDOffset) +(UpdateBiosSDOffsetSize))

[0115] #define BiosSecureBootOffset ((UpdateVlanDataOffset) +(UpdateVlanDataOffsetSize))

[0116] #define BiosBootOptionOffset ((BiosSecureBootOffset) +(BiosSecureBootOffsetSize))

[0117] #define BiosStaticFilesOffset ((BiosBootOptionOffset) +(BiosBootOptionOffsetSize))

[0118] Furthermore, the present invention also proposes an interactive device for memory sharing between BIOS and BMC, the interactive device for memory sharing between BIOS and BMC is used to implement the interactive method for memory sharing between BIOS and BMC, the interactive device for memory sharing between BIOS and BMC is arranged on a mainboard of a server, and the interactive device for memory sharing between BIOS and BMC at least comprises:

[0119] A baseboard management controller BMC, wherein the baseboard management controller BMC is connected to a central processing unit CPU and a memory DDR on a server mainboard;

[0120] The basic input and output system BIOS is connected to the baseboard management controller BMC and the central processing unit CPU on the server mainboard.

[0121] In a specific embodiment, referring to Figure 2 , including two interconnected central processing units CPU0 and CPU1, a baseboard management controller BMC connected to CPU0 through eSPI, a basic input and output system BIOS connected to CPU0 through SPI_Flash, the basic input and output system BIOS is connected to the baseboard management controller BMC through SPI_BMC, the baseboard management controller BMC is connected to the memory DDR through the BMC read and write program, and the memory DDR is connected to the central processing unit CPU0.

[0122] Among them, ESPI is a bus standard for system management, the full name is Enhanced Serial Peripheral Interface, which is used to connect various devices and sensors in the computer system, such as BIOS, power manager, temperature sensor, etc. The ESPI standard was launched by Intel to replace the original Low Pin Count (LPC) bus and provide better performance and reliability.

[0123] SPI (Serial Peripheral Interface) bus: is a high-speed full-duplex synchronous serial interface commonly used for communication between microcontrollers and peripheral devices. Its main features include synchronous transmission, serial communication, full-duplex capability and master-slave structure. The SPI protocol allows a master device (Master) to exchange data with one or more slave devices (Slave), and is usually used to connect EEPROM, FLASH, real-time clock, AD converter and other devices.

[0124] SPI_Flash refers to the connection to the BIOS flash via the SPI bus, and SPI_BMC refers to the connection to the BMC via the SPI bus.

[0125] The above is only a preferred embodiment of the present invention. The present invention is not limited to the above implementation. As long as the technical effect of the present invention is achieved by the same means, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure. All should belong to the protection scope of the present invention. Within the protection scope of the present invention, its technical scheme and / or implementation method can have various modifications and changes.

Claims

1. A memory sharing interaction method between BIOS and BMC, used for communication between baseboard management controller BMC and basic input and output system BIOS in a server, characterized in that: The memory sharing interaction method between BIOS and BMC comprises the following steps: S100, based on the preset shared memory, after the baseboard management controller BMC firmware is burned or updated for the first time, the server is powered on, and the baseboard management controller BMC executes internal code instructions to read the uplink flag bit information of the uplink domain in the shared memory; S200, after the basic input and output system BIOS firmware is burned or updated for the first time, when the server is powered on for the first time, the basic input and output system BIOS executes the hardware initialization code and reads the downlink flag bit information of the downlink domain in the shared memory; S300, obtaining the configuration information of the server and writing it into the shared memory, and after the writing is completed, setting the first address flag of the shared memory to 1; S400, after the baseboard management controller BMC detects that the boot is completed, the shared memory data interaction of the first boot is completed, and all the flags Flag of the upstream domain are traversed and detected. If there is an item with the flag Flag as 1, the data of the upstream data area corresponding to the flag Flag is read; S500, if the basic input and output system BIOS is not started for the first time, read the downlink flag Flag of the downlink domain in the shared memory, if there is a downlink flag Flag is 1, the basic input and output system BIOS reads and processes the data in the downlink data area corresponding to the downlink flag Flag, and feeds the result back to the baseboard management controller BMC; Wherein, the shared memory includes an uplink flag bit area, a downlink flag bit area, an uplink data storage area and a downlink data storage area with physical addresses being consecutive in sequence; the uplink domain includes the uplink flag bit area and the uplink data storage area, and the downlink domain includes the downlink flag bit area and the downlink data storage area; the uplink flag bit area includes a plurality of uplink flag bits, the storage address of the first uplink flag bit is a base address, and the physical addresses of subsequent uplink flag bits are the base address plus an offset byte; the downlink flag bit area includes a plurality of downlink flag bits, the storage address of the first downlink flag bit is a physical address next to the physical address of the last uplink flag bit of the uplink flag bit area, and the physical addresses of subsequent downlink flag bits are the storage address of the first downlink flag bit plus an offset byte; The base address is obtained in the following way: First, use the UEFI standard function LocateHandleBuffer to locate all UEFI standard Pci protocol interfaces gEfiPciIoProtocolGuid; Then, traverse the handles, use the UEFI standard function Pci.Read to read the device's VendorId and DeviceId, and find the VendorId and DeviceId corresponding to the PCIE device; Finally, the BAR value at 0x10 of the PCIE device is read through Pci.Read. The BAR value is the base address of the shared memory address. The base address is stored and transferred in the form of Protocol, which is convenient for using the base address in the startup phase of different basic input and output systems BIOS; The storage and transmission in the form of Protocol includes the following steps: defining an OemProtocol and naming it H2bHiProtocol, wherein the Interface member thereof includes PciAddress and BaseAddress; the PciAddress is an internal member name of the H2bHiProtocol Interface, and the BaseAddress is a BAR value at 0x10 in the Pci configuration space.

2. The memory sharing interaction method between BIOS and BMC according to claim 1, characterized in that: In the steps S100 and S200, The initial values ​​of all uplink flag information and all downlink flag information are 0.

3. The memory sharing interaction method between BIOS and BMC according to claim 1, characterized in that: The step S300 also includes: converting the configuration information of the acquired server into a Json data format.

4. The memory sharing interaction method between BIOS and BMC according to claim 1, characterized in that: The shared memory is used for the baseboard management controller BMC to communicate with the basic input and output system BIOS of the host through the Host To BMC mechanism. The shared memory includes an upstream domain for storing the communication from the host Host to the baseboard management controller BMC and a downstream domain for storing the communication from the baseboard management controller BMC to the host Host.

5. The memory sharing interaction method between BIOS and BMC according to claim 1, characterized in that: The uplink data storage area includes a plurality of uplink data areas, each of which corresponds to a corresponding uplink flag bit, and each of which includes an uplink data starting address and an uplink data size, wherein the uplink data starting address is used to identify a physical starting position of the uplink data, and the uplink data size is used to identify a placeholder size of the uplink data; The downlink data storage area includes multiple downlink data areas, each of which corresponds to a corresponding downlink flag bit, and each downlink data area includes a downlink data starting address and a downlink data size. The downlink data starting address is used to identify the physical starting position of the downlink data, and the downlink data size is used to identify the occupied size of the downlink data.

6. An interactive device for memory sharing between BIOS and BMC, characterized in that: The memory sharing interaction device between BIOS and BMC is used to implement the memory sharing interaction method between BIOS and BMC as claimed in any one of claims 1 to 5, and the memory sharing interaction device between BIOS and BMC is arranged on the mainboard of the server, and the memory sharing interaction device between BIOS and BMC at least includes: A baseboard management controller BMC, wherein the baseboard management controller BMC is connected to a central processing unit CPU and a memory DDR on a server mainboard; The basic input and output system BIOS is connected to the baseboard management controller BMC and the central processing unit CPU on the server mainboard.

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