Storage controller and electronic system

Abstract

The invention discloses a storage controller and an electronic system. The storage controller comprises a first interface, a data management module and a second interface group, the second interface group comprises N second interfaces, and N is a natural number; the first interface is used for communicating with a main control component, the second interface is used for being externally connected with a memory, and the data management module is connected between the first interface and the second interface so as to obtain a control instruction of the main control component and manage data storage of the memory based on the control instruction. The invention provides a scheme for reducing the memory capacity upgrading cost.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a storage controller and an electronic system. Background Art

[0002] With the development of electronic technology, the demand for memory capacity of various electronic products is increasing.

[0003] The upper limit of memory capacity of existing electronic products is often determined by the capacity supported by the main control components such as the motherboard chipset or CPU. When the demand reaches the maximum memory capacity supported by the main control component, it will not be able to continue to expand and can only be replaced with a higher configuration product, which results in huge hardware upgrade costs and waste of resources. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a storage controller and an electronic system that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, a storage controller is provided, comprising: A first interface, a data management module, and a second interface group, wherein the second interface group includes N second interfaces, where N is a natural number; The first interface is used to communicate with the main control component, the second interface is used for an external memory, and the data management module is connected between the first interface and the second interface to obtain control instructions from the main control component and manage data storage in the memory based on the control instructions.

[0006] Optionally, the second interface includes multiple dedicated circuits, each dedicated circuit is used to support different types of memories.

[0007] Optionally, the second interface also includes: a general circuit and an interface circuit, the multiple dedicated circuits are all connected to the general circuit to share the function of the general circuit, and the multiple dedicated circuits are all connected to the interface circuit to share the interface circuit to achieve connection with the memory.

[0008] Optionally, the storage controller further includes: an on-chip cache module connected to the first interface and used for caching communication data with the main control component.

[0009] Optionally, the on-chip cache module is connected to the data management module and stores cache data, so that the cache data can be queried according to a read instruction of the main control component.

[0010] Optionally, the storage controller further includes: a cache interface module group, the cache interface module group includes M cache interface modules, M is a natural number; the cache interface module is used for externally connecting to a cache unit.

[0011] Optionally, the cache unit and the storage controller are integrated through chip stacking technology.

[0012] Optionally, the storage controller also includes an on-chip cache module connected to the first interface; wherein the on-chip cache module and the cache interface module group are both connected to the data management module, and the on-chip cache module and the cache unit both store cache data; wherein, when the storage controller receives a read instruction from the main control component, it first queries the cache data in the on-chip cache module, and if there is no hit, it then queries the cache data in the cache unit, and if there is still no hit, it then queries the data in the memory.

[0013] Optionally, the storage controller further includes: a data protection module connected to the second interface group and used for data encryption, decryption and / or error correction.

[0014] Optionally, the storage controller further includes: a control module connected to the data management module and used to configure parameters of each module in the storage controller.

[0015] In a second aspect, an electronic system is provided, comprising: A main control component, a memory, and a storage controller as described in any one of the first aspects; The storage controller communicates with the main control component through the first interface and is connected to the memory through the second interface to expand the memory capacity of the electronic system.

[0016] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage controller and electronic system provided by the embodiment of the present invention are provided with a storage controller including a first interface, a data management module and a second interface group. Communication with the main control component is achieved through the first interface, an external memory is connected through the second interface, and data storage in the memory is managed through the data management module. This enables the main control component to remove the restrictions on memory capacity by means of an external memory, and the memory bandwidth and capacity can be expanded without replacing the main control device, greatly reducing the cost of upgrading the memory capacity. In addition, in addition to being used for expanding the memory capacity, the external memory can also be used for the functions that other memories such as hard disks and near-memory computing acceleration cards can provide, thereby improving computer performance in all aspects.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 The structure of the storage controller in the embodiment of the present invention is shown in FIG. Figure 1 ; Figure 2 is a schematic diagram of the structure of the second interface in an embodiment of the present invention; Figure 3 The structure of the storage controller in the embodiment of the present invention is shown in FIG. Figure 2 ; Figure 4 The structure of the storage controller in the embodiment of the present invention is shown in FIG. Figure 3 ; Figure 5 Schematic diagram of the structure of an electronic system in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0020] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0021] See also Figure 1The embodiment of the present application provides a storage controller 101, including: a first interface 1, a data management module 2, and a second interface group, wherein the second interface group includes N second interfaces 3, where N is a natural number. The first interface 1 is used to communicate with a main control component 102, and the second interface 3 is used to connect to an external memory 103. The data management module 2 is connected between the first interface 1 and the second interface 3 to obtain control instructions of the main control component 102, and manage data storage of the memory 103 based on the control instructions.

[0022] It should be noted that, although a portion of the capacity of the computer hard disk can be divided into virtual memory for use through the operating system to expand the memory capacity, its bandwidth and latency cannot meet the performance requirements required by the memory. Therefore, even if the memory capacity is increased through virtual memory, it cannot respond to read and write requests as quickly as the original memory, which reduces the performance of the system. However, the present application can release the coupling relationship between the main control component and the memory capacity through the storage controller 101, expand the memory bandwidth and capacity without replacing the main control component, and greatly reduce the cost of memory capacity upgrade. In addition, through the setting of the second interface group, the present application can support the flexible use of various new storage media to expand the memory, get rid of the dependence on dynamic memory DRAM, and further reduce the cost of memory.

[0023] The structure and operation mode of the storage controller 101 are described in detail below.

[0024] The first interface 1 is used to communicate with the main control component 102 such as the CPU. In an optional implementation, the first interface 1 may be a cache coherent bus interface or an open industry standard interconnect (Compute Express Link, CXL) interface module, which can be used to connect processors, accelerators, memory buffers, intelligent network interfaces, and storage devices.

[0025] Among them, the data management module 2 can obtain the control instructions of the main control component 102, and manage the data storage of the memory 103 based on the control instructions. Specifically, the data management module 2 can also perform wear leveling (i.e., control the storage amount and read and write quantity of data in each memory to be uniform, so as to avoid damage to the memory due to excessive storage or too frequent reading and writing), bad block management (i.e., it can isolate the faulty memory or the faulty storage unit in the memory to avoid the influence of the faulty part on the overall storage), data backup (it can also perform backup management on the data stored in the memory to avoid the loss of important data) and other operations on the memory 103 to improve the stability, reliability and life of the memory.

[0026] The second interface group may include multiple second interfaces 3 to be able to connect to multiple memories 103 to expand the memory capacity.

[0027] Please refer to Figure 2 In an optional embodiment, the second interface 3 includes multiple dedicated circuits 201, each dedicated circuit 201 is used to support different types of memories 103. Specifically, each dedicated circuit 201 is adapted to the communication protocol of different memories. In this way, each second interface 3 can be compatible with one or more types of memories 103 at the same time, and its compatible memory types can include volatile memories (such as dynamic memories DRAM) and non-volatile memories (such as phase change memories PCM, flash memories Flash, resistive random access memories RRAM, etc.), so as to increase the scope of application of the storage controller 101, improve the flexibility of memory expansion, get rid of the dependence on dynamic memories DRAM, and further reduce the cost of memory.

[0028] In an optional embodiment, if Figure 2 As shown, the second interface 3 can be set to include: multiple dedicated circuits 201, a general circuit 202 and an interface circuit 203. Multiple dedicated circuits 201 are connected to the general circuit 202 to share the function of the general circuit 202, and multiple dedicated circuits 201 are also connected to the interface circuit 203 to share the interface circuit 203 to achieve connection with the memory 103. Specifically, the dedicated circuits 201 are used to support different types of memories, which are mainly circuit parts related to the communication protocol of the memory. The general circuit 202 is a reusable circuit, which is mainly a circuit part related to the transmission line of the signal, such as a general high-speed bus. The interface circuit 203 is a reusable interface circuit connected to the memory. These three circuits are used in conjunction through software and / or hardware configuration to achieve data transmission of different types of memories, and the chip area and cost can be saved by sharing the general circuit 202 and the interface circuit 203.

[0029] Of course, other methods can also be used to implement access to multiple types of memories, for example, multiple second interface groups are provided, including interface modules that support different types of memories. For example, the second interface group includes 6 second interfaces 3, of which 2 support dynamic memory DRAM, 2 support phase change memory PCM, and 2 support flash memory Flash. There is no limitation here.

[0030] Of course, in the specific implementation process, the external memory 103 of the storage controller 101 can not only be used to expand the memory capacity, but also can be used for other purposes besides memory, such as hard disk, near-memory computing acceleration card, etc., depending on the type of memory 103, to improve computer performance.

[0031] Please refer to Figure 3In an optional implementation, the storage controller 101 may further include an on-chip cache module 4, which is connected to the first interface 1 and is used to cache communication data with the main control component 102. The data cached on the on-chip cache module 4 may include any one or more combinations of the following: data to be written sent by the main control component 102 to the storage controller 101, data to be read by the main control component 102, and instruction data of the main control component 102.

[0032] Taking the cache data to be written as an example, the write data received by the storage controller 101 from the first interface 1 will be first cached in the on-chip cache module 4, and when the trigger condition is met, the data management module 2 will move the write data to the memory 103 for storage through the second interface 3. The trigger condition includes any one or more of the following combinations: the time interval for accessing the memory 103 reaches a threshold, the number of accesses to the memory 103 within a period of time is less than a threshold, new data needs to be written to the on-chip cache module 4 after the capacity of the on-chip cache module 4 is full, the data management module 2 actively triggers the move operation, or the write operation to the memory 103 is triggered simultaneously when the data is written to the on-chip cache module 4.

[0033] In an optional embodiment, it is also possible to set up an on-chip cache module 4 to store some cache data. When the storage controller 101 receives a data read instruction sent by the main control component 102 from the first interface 1, it will first query in the on-chip cache module 4. If the query can hit the target data to be read, the target data is directly returned to the main control component 102. If the query does not hit, the memory 103 is accessed to read the target data, and the target data is returned to the main control component 102 through the first interface 1. This can increase the speed of reading data, improve reading efficiency, and avoid high-frequency access to the memory 103, thereby ensuring the service life of the memory 103.

[0034] Specifically, the cache data pre-stored in the on-chip cache module 4 can be data pre-acquired from the memory 103 through the data management module 2 connected thereto, or data pre-acquired from the memory 103 through software control (external device software control, or other internal module software control), or data cached in the on-chip cache module 4 through the write data received by the first interface 1, and no limitation is made here. Taking the cache data pre-acquired by the data management module 2 as an example, a pre-fetch algorithm can be preset in the data management module 2, and the number of the pre-fetch algorithms can be one or more, and any of the pre-fetch algorithms can be selected by software configuration to take effect at the same time, or multiple pre-fetch algorithms that are effective by software configuration can be combined by three logics of AND, OR, and NOT to take effect, and no limitation is made here, so as to improve the flexibility and scalability of the pre-fetch algorithm. For example, based on the pre-fetch algorithm, pre-fetch can be performed from the memory 103 according to the various features of the read instruction received previously, and the data can be stored in the on-chip cache module 4 to improve the data reading efficiency.

[0035] Please refer to Figure 4 In an optional implementation, the storage controller 101 may be configured to further include: a cache interface module group, the cache interface module group including M cache interface modules 5, where M is a natural number. The cache interface module 5 is used to connect to the external cache unit 104. The cache interface module 5 may adopt the same structural design as the second interface 3, may be configured with multiple dedicated circuits to adapt to different memory types, or may only be configured with a circuit to adapt to a single type of memory, which is not limited here.

[0036] Specifically, setting a cache interface module 5 to connect an external cache unit 104 can alleviate the problem of insufficient on-chip cache capacity. Since the on-chip cache module 4 of the storage controller 101 is often implemented by a static memory SRAM, and is limited by the chip area, its capacity cannot be very large, and the cost is very high. However, the on-chip cache module 4 can significantly improve the data reading efficiency. Therefore, a cache interface module group is set in the storage controller 101 to connect a group of external cache units 104 as an off-chip cache, which can achieve the expansion of the capacity of the on-chip cache module 4.

[0037] Among them, the cache unit 104 is an external memory, and the connection method between it and the cache interface module 5 can be realized by plugging, welding, wire connection and other connection methods between independent devices, or integrated connection through chip stacking technology, which is not limited here. Integrating the cache unit 104 with the storage controller 101 through chip stacking technology (2D interconnection technology, 2.5D interconnection technology or 3D interconnection technology) can significantly shorten the data communication time between the cache unit 104 and the storage controller 101 and improve access efficiency. In addition, the stacking technology can increase the number of connection channels, realize parallel access of the cache unit 104, and further improve the bandwidth, so as to achieve a transmission rate of not less than GB / s and a transmission delay of ns to meet the requirements of realizing the cache function.

[0038] In an optional implementation, the on-chip cache module 4 and the cache unit 104 may be combined to form a multi-level cache. Specifically, the on-chip cache module 4 and the cache interface module group may be connected to the data management module 2, and the on-chip cache module 4 and the cache unit 104 may store cache data (the method of obtaining the cache data here may be the same as the method of saving the cache data to the on-chip cache module 4). When the storage controller 101 receives the read instruction from the main control component 102, it first queries the cache data in the on-chip cache module 4. If the target data to be read is not hit, the cache data in the cache unit 104 is queried. If the target data to be read is still not hit, the data in the memory 103 is queried. Thus, on the one hand, by setting the transmission distance (for example, setting the cache unit 104 to be integrated with the storage controller 101 through chip stacking technology, and the memory 103 to be connected externally), or by setting the storage medium type (for example, setting the cache unit 104 to use a storage medium type with a faster reading speed than the memory 103), the speed of the main control component 102 accessing data is arranged from fast to slow, namely, the on-chip cache module 4, the cache unit 104, and the memory 103, so the multi-level query from fast to slow can effectively improve the speed of data reading. On the other hand, querying in the cache first can effectively reduce the number of times the memory 103 is accessed, and the life of the memory 103 is improved.

[0039] In an optional embodiment, if Figure 3As shown, the storage controller 101 may also include a data protection module 6, which is connected to the second interface group and is used for encryption, decryption and / or error correction of data. Specifically, the data protection module 6 may include any one or more of the following combinations: an encryption / decryption circuit, an error detection and correction circuit, and an encoding / decoding circuit. In this way, the data protection module 6 can perform encryption / decryption processing, error detection and correction processing, and encoding / decoding processing on the data, thereby ensuring the security and correctness of writing and reading data. The operating speed of the data protection module 6 can be pre-set to meet the bandwidth requirements when the data link is fully loaded, and its error correction capability covers the error rate of the memory 103, thereby ensuring that the uncorrectable bit error rate (UBER) of the memory 103 after error correction is better than 10 -15 .

[0040] In an optional embodiment, if Figure 3 As shown, the storage controller 101 may also include a control module 7, which is connected to the data management module 2 and is used to configure the parameters of each module in the storage controller 101. Specifically, the control module 7 is a control and calculation module integrated in the storage controller 101, which is used to execute software code and perform data calculation processing. Through it, the control and configuration of each module inside the storage controller 101 can be realized. For example, after the storage controller 101 receives the configuration instruction of the main control component 102, the configuration instruction is transmitted to the control module 7 via the first interface 1. After the control module 7 parses the configuration instruction, it obtains information such as the configuration object and configuration parameters, and performs parameter configuration on the configuration object according to the obtained information. The configuration content can be the data access frequency and trigger access conditions of the data management module 2, or it can be the update of the pre-fetch algorithm, or it can be the restriction conditions on the cache data content and cache frequency in the on-chip cache module 4, etc., which are not limited here and are not listed one by one.

[0041] Based on the same inventive concept, the embodiment of the present application also provides an electronic system, such as Figure 5 As shown, including: The main control component 102, the memory 103 and the memory controller 101 provided in the above embodiment. The memory controller 101 communicates with the main control component 102 through a first interface and is connected to the memory 103 through a second interface to expand the memory capacity of the electronic system.

[0042] Since the storage controller 101 included in the electronic system introduced in the embodiment of the present application is exactly the storage controller 101 introduced in the embodiment of the present application, the principle and structure of the storage controller 101, and the connection method between the storage controller 101 and the main control component 102 and the memory 103 have been described in detail above, so they will not be repeated here. Any electronic system including the storage controller 101 in the embodiment of the present application belongs to the scope of protection of the present invention.

[0043] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage controller and electronic system provided by the embodiment of the present invention are provided with a storage controller including a first interface, a data management module and a second interface group. Communication with the main control component is achieved through the first interface, an external memory is connected through the second interface, and data storage in the memory is managed through the data management module. This enables the main control component to remove the restrictions on memory capacity by means of an external memory, and the memory bandwidth and capacity can be expanded without replacing the main control device, greatly reducing the cost of upgrading the memory capacity. In addition, in addition to being used for expanding the memory capacity, the external memory can also be used for the functions that other memories such as hard disks and near-memory computing acceleration cards can provide, thereby improving computer performance in all aspects.

[0044] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0045] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0046] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0047] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the abstract and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0048] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0049] It should be noted that the above embodiments illustrate the present invention rather than limiting it. Any reference symbol between brackets should not be constructed as a limitation of the present invention. The word "comprising" does not exclude the presence of components or steps not listed in the present invention. The word "one" or "an" preceding a component does not exclude the presence of multiple such components. The present invention can be implemented by means of hardware including several different components and by means of appropriately programmed computers. In the embodiments in which several devices are listed, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims

1. A storage controller, characterized in that: include: A first interface, a data management module, and a second interface group, wherein the second interface group includes N second interfaces, where N is a natural number; The first interface is used to communicate with the main control component, the second interface is used for an external memory, and the data management module is connected between the first interface and the second interface to obtain control instructions from the main control component and manage data storage in the memory based on the control instructions.

2. The storage controller according to claim 1, wherein: The second interface includes a plurality of dedicated circuits, each of which is used to support different types of memories.

3. The storage controller according to claim 2, wherein: The second interface also includes: A general circuit and an interface circuit, wherein the plurality of special circuits are all connected to the general circuit to share the function of the general circuit, and the plurality of special circuits are all connected to the interface circuit to share the interface circuit to realize connection with the memory.

4. The storage controller according to claim 1, wherein: Also includes: An on-chip cache module is connected to the first interface and is used to cache communication data with the main control component.

5. The storage controller according to claim 4, wherein: The on-chip cache module is connected to the data management module and stores cache data, so as to query the cache data according to the read instruction of the main control component.

6. The storage controller according to claim 1, wherein: Also includes: A cache interface module group, wherein the cache interface module group includes M cache interface modules, where M is a natural number; The cache interface module is used for connecting to an external cache unit.

7. The storage controller according to claim 6, wherein: The cache unit and the storage controller are integrated through chip stacking technology.

8. The storage controller according to claim 6, wherein: The storage controller further includes an on-chip cache module connected to the first interface; Wherein, the on-chip cache module and the cache interface module group are both connected to the data management module, and the on-chip cache module and the cache unit both store cache data; Among them, when the storage controller receives the read instruction from the main control component, it first queries the cache data in the on-chip cache module. If there is no hit, it queries the cache data in the cache unit. If there is still no hit, it queries the data in the memory.

9. The storage controller according to claim 1, wherein: Also includes: A data protection module is connected to the second interface group and is used for data encryption, decryption and / or error correction.

10. The storage controller according to claim 1, wherein: Also includes: A control module is connected to the data management module and is used to configure parameters of each module in the storage controller.

11. An electronic system, characterized in that: include: A main control component, a memory, and a storage controller as claimed in any one of claims 1 to 10; The storage controller communicates with the main control component through the first interface and is connected to the memory through the second interface to expand the memory capacity of the electronic system.

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