Display panel manufacturing method, display panel and display panel manufacturing device

Abstract

The invention discloses a manufacturing method of a display panel, the display panel and a manufacturing device of the display panel, and generally relates to the technical field of display panels. The method comprises the following steps: carrying out first etching and second etching to enable at least one metal wiring area to be in lap joint conduction with a first metal layer and a second metal layer through two through holes formed by etching, a through hole formed in the polycrystalline silicon layer through etching is in lap joint conduction with the metal wiring area corresponding to the polycrystalline silicon layer; wherein the orthographic projection of the first metal layer on the substrate is partially overlapped with one metal wiring area, and the orthographic projection of the second metal layer on the substrate is partially overlapped with one metal wiring area, or the orthographic projection of the second metal layer on the substrate is partially overlapped with one metal wiring area.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of display devices, and in particular to a method for manufacturing a display panel, a display panel, and a device for manufacturing a display panel. Background Art

[0002] With the continuous development of display panels, the display performance of display panels is getting better and better, for example, the display panels are getting bigger and bigger.

[0003] In order to ensure that the effective display area of ​​the display panel is as large as possible without changing its volume, the non-display area is minimized as much as possible. For example, the area of ​​the display panel occupied by the frame in the orthographic projection direction is reduced, that is, the effective display area is increased by setting a narrow frame. In related technologies, the display panel is generally a stack of multiple film layers. When wiring connections are required between different film layers, wiring areas are set on two different film layers, and the position of the film layer between the two film layers in the orthographic projection direction is perforated by etching, so that the two different film layers are connected by wiring.

[0004] However, in the above scheme, in the process of etching holes from certain film layers of the display panel as the starting film layers to other film layers, if the number of holes is large and the number of layers of the corresponding spacing film layers of the holes is different, it is easy for the film layers corresponding to some holes to be over-etched or not etched in place, which will lead to poor subsequent wiring effects. Summary of the invention

[0005] In view of the above-mentioned defects or deficiencies in the related art, it is desired to provide a method for manufacturing a display panel, a display panel and a device for manufacturing a display panel, which can solve the problem that when more holes need to be etched, if the number of perforations is large and the number of layers of the corresponding spacing film layers of the perforations is different, it is easy for the film layers corresponding to some holes to be over-etched or not etched in place, which in turn leads to poor subsequent wiring effects. Thereby, the consumables required for use in the wiring process of the display panel are improved while ensuring the wiring quality of the display panel.

[0006] In a first aspect, a method for manufacturing a display panel is provided, the method comprising: The display panel comprises a display area and a non-display area in the orthographic projection direction, wherein the display area is at least partially surrounded by the non-display area; the display panel comprises a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, a PLN film layer is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged on a partial area of ​​the buffer film layer of the display area close to the substrate, and a side of the PLN film layer close to the substrate is used to arrange at least two metal wiring areas; A first metal layer is disposed on a side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is disposed on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, and the method includes: Through the first etching and the second etching, two through-holes formed by etching of at least one of the metal wiring regions are overlapped and connected with the first metal layer and the second metal layer, and one through-hole formed by etching of the polysilicon layer is overlapped and connected with the metal wiring region corresponding to the polysilicon layer; The orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0007] In the present application, the above-mentioned display panel is divided into a display area and a non-display area in the orthographic projection direction, wherein the display area is surrounded by the non-display area, the display area includes a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, and a flat film layer PLN is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged in a partial area of ​​the buffer film layer of the display area close to the substrate side, and the side of the flat film layer close to the substrate is used to set at least two metal wiring areas; a first metal layer is arranged on the side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is arranged on the side of the interlayer dielectric layer corresponding to the non-display area close to the substrate. Through two etchings (the first etching and the second etching respectively), the two perforations formed by etching of the at least one metal wiring area are overlapped and connected with the first metal layer and the second metal layer, and the polysilicon layer is overlapped and connected with the metal wiring area corresponding to the polysilicon layer by etching a perforation (the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area). In this way, through two etching processes, the three perforations between different film layers are connected in the required overlapping manner. At the same time, due to batch etching, there will be no situation where one or more of the three perforations are under-etched or over-etched, so that under the premise of ensuring etching effect and wiring effect, wiring consumables can be reduced by increasing perforations.

[0008] In a second aspect, a display panel is provided, wherein the display panel comprises a display area and a non-display area in an orthographic projection direction, wherein the display area is at least partially surrounded by the non-display area; the display panel comprises a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on a side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on a side of the GI film layer away from the substrate, a flat film layer is arranged on a side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged on a partial area of ​​the buffer film layer of the display area close to the substrate, and a side of the flat film layer close to the substrate is used to arrange at least two metal wiring areas; A first metal layer is disposed on a side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is disposed on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate; The at least one metal wiring area is overlapped and connected with the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is overlapped and connected with a through hole formed by etching and the metal wiring area corresponding to the polysilicon layer; The orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0009] In a third aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the first aspect is implemented.

[0010] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that when the program is executed by a processor, the method described in the first aspect is implemented.

[0011] In a fifth aspect, a computer program product is provided. The computer program product includes instructions, and the instructions are executed by a processor to implement the method described in the first aspect.

[0012] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 One of the schematic diagrams of a display panel in the related art; Figure 2The second schematic diagram of a display panel in the related art; Figure 3 The third schematic diagram of a display panel in the related art; Figure 4 A schematic diagram of a process for manufacturing a display panel provided in an embodiment of the present application; Figure 5 One of the structural schematic diagrams of the display panel provided in the embodiment of the present application; Figure 6 The second structural schematic diagram of the display panel provided in the embodiment of the present application; Figure 7 The third structural diagram of the display panel provided in the embodiment of the present application; Figure 8 A schematic diagram of the structure of a display panel manufacturing device provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0015] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The applicable scenarios of the present application will be described below.

[0016] In order to ensure that the effective display area of ​​the display panel is as large as possible while the volume remains unchanged, the effective display area can be increased by setting a narrow frame. The frame is often used for wiring. The display panel is generally a stack of multiple film layers. When wiring connections are required between different film layers, the wires of different film layers can be connected from the periphery of the display panel by overlapping. It is also possible to set wiring areas on different film layers and etch holes in the film layer orthographic projection direction between the above two film layers, so as to connect the two different film layers by wiring.

[0017] In the related art, the display panel includes multiple film layers, for example, 9 film layers, when viewed from the side in the orthographic projection direction. Figure 1 As shown, Figure 1It is the non-display area (Fanout area) and display area (AA area) of the display panel, separated by a dotted line 10, the left side of the dotted line is the display area, and the right side of the dotted line is the non-display area. Among them, in the display area, the LS film layer 11 is included as a light shielding layer for the thin film transistor TFT12 in the AA area, which is used to reduce the light Ioff of the thin film transistor and improve the voltage holding ability of the panel. It has been verified that when the LS film layer 11 blocks the perforation of the ILD film layer corresponding to the positive projection direction of the TFT on the substrate 13, the light LOFF is the smallest. In the non-display area, only two metal layers, the SD layer 14 and the Gate layer 15, are overlapped. In the AA area, there is an overlap between the SD film layer 16 and the polysilicon layer (Poly) 17. Both types of perforations require perforations in the ILD film layer. Therefore, in the process of making the ILD film layer 18 of the display film layer, the process is as follows: after the entire layer is coated to generate the ILD film layer, a mask is used for one etching to etch through the ILD layer 18 to the Gate layer 15, and at the same time, the ILD and GI layers 19 to the Poly layer 17.

[0018] In order to reduce the size of the frame, the overlap between different metal layers can be increased in the non-display area, thereby reducing wiring consumables and saving the space occupied by wiring, thereby greatly reducing the volume of the non-display area, that is, reducing the size of the frame. At this point, LS layer 1 and SD layer 2 can be added to the non-display area, and etching holes can be added to the ILD layer 18 in the non-display area. The newly added LS layer 1 and SD layer 2 in the non-display area are overlapped and connected. That is, three holes need to be etched in the ILD layer 18 at the same time to form a three-layer wiring setting.

[0019] To ensure the overlap between the three metal film layers, such as Figure 2 and Figure 3 As shown, the ILD layer 18 needs to be etched to the LS layer and the Gate layer in the non-display area, and there is deep and shallow hole etching. At the same time, in order to ensure that the light Ioff of the TFT device remains at a low level, the LS11 in the AA area TFT needs to block the perforation of the ILD layer 18. There is a poly layer 17 between the ILD layer 18 and the LS layer 11, which has a blocking effect on the perforation etching of the ILD layer 18, which will lead to Figure 2 Some of the SD layer 17 can be etched to the LS layer 11, while some cannot be etched to the LS layer 11. Figure 3 Some of them are over-etched to the LS layer 11, and some are not etched to the LS layer 11. For the two cases of etching to the LS layer 11 and not etching to the LS layer 11, it is actually the phenomenon of uneven and inaccurate etching of the ILD layer 18. Because there are many holes in the ILD layer in the display panel ( Figure 1 and Figure 2Only a hole of the ILD18 layer in the display area is shown in the figure) After the SD layer set in the hole of the unevenly etched ILD layer 18 is overlapped and connected with the poly layer 17, if the same brightness and the same chromaticity need to be displayed, different Vcoms need to be set for different overlapping areas, and the display panel often has one Vcom. Therefore, this uneven etching makes the Vcom of the entire display area of ​​the display panel uneven, which ultimately leads to uneven display of the display panel and poor display effect.

[0020] Based on this, the present application proposes a method, device, equipment and medium for manufacturing a display panel, which can solve the problem that when the number of holes to be etched increases, if the number of perforations is large and the number of layers of the corresponding spacing film layers of the perforations is different, it is easy for the film layers corresponding to some holes to be over-etched or not etched in place, which in turn leads to poor subsequent wiring effects. This can improve the consumables needed in the wiring process of the display panel while ensuring the wiring quality of the display panel.

[0021] Figure 4 It is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present application. The display panel includes a display area and a non-display area in the orthographic projection direction, and the display area is surrounded by the non-display area; the display panel includes a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, a flat film layer is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged on a part of the buffer film layer of the display area close to the substrate, and the side of the flat film layer close to the substrate is used to arrange at least two metal wiring areas.

[0022] In the embodiment of the present application, the display panel includes a display area and a non-display area.

[0023] In one example, the display area may be a pixel area.

[0024] In an example, the non-display area may include a wiring fan-out area. Generally, the non-display area is arranged in the area where the frame of the display panel is located, that is, the frame area includes the wiring fan-out area.

[0025] In the embodiment of the present application, the at least two metal wiring areas are respectively arranged in the display area and the non-display area.

[0026] In an example, the metal wiring region may be a SD layer.

[0027] like Figure 5 As shown, Figure 5The display film layer in the longitudinal section of the embodiment of the present application is shown in the figure. It can be seen from the display film layer that the display panel is divided into a pixel area (i.e., the above-mentioned AA area) and a Fanout area (i.e., the above-mentioned non-display area). In the above-mentioned display panel, a substrate 21 is included, a buffer film layer (buffer layer) 22 is provided on one side of the substrate, a GI film layer 23 is provided on the side of the buffer film layer 22 away from the substrate 21, an interlayer dielectric layer ILD layer 24 is provided on the side of the GI film layer 23 away from the substrate 21, and a flat film layer 25 (PLN) is provided on the side of the ILD24 away from the substrate 21. In the orthographic projection direction of the above-mentioned AA area, a polysilicon layer (Ploy) 26 is provided in a partial area of ​​the buffer film layer 22 close to the substrate 21.

[0028] In the embodiment of the present application, a first metal layer is disposed on a side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is disposed on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate.

[0029] In an example, the first metal layer may be an LS layer, and the second metal layer may be a Gate layer.

[0030] The method comprises the following steps 301: Step 301: Through the first etching and the second etching, the two through holes formed by etching of at least one of the above-mentioned metal wiring areas are overlapped and connected with the above-mentioned first metal layer and the above-mentioned second metal layer, and a through hole formed by etching of the above-mentioned polysilicon layer is overlapped and connected with the above-mentioned metal wiring area corresponding to the above-mentioned polysilicon layer.

[0031] In an embodiment of the present application, the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0032] It can be understood that since the etching process is to perform vertical penetration etching on the film layer, when it is necessary to overlap and connect the two perforations formed by etching at least one of the above-mentioned metal wiring areas with the above-mentioned first metal layer and the above-mentioned second metal layer, then at least one metal wiring area needs to at least partially overlap with the first metal layer or the second metal layer on the orthographic projection of the substrate.

[0033] In an embodiment of the present application, in order to ensure that the metal wiring area is overlapped and conductive with the first metal layer and the second metal layer through two perforations, the second metal layer can be composed of one or more overlapping areas located on the side of the interlayer dielectric layer close to the substrate. Therefore, the distribution area of ​​the second metal layer corresponds to the distribution method of the metal wiring area. Please refer to the subsequent description for details.

[0034] Furthermore, the number of the metal wiring areas also corresponds to the number of overlapping areas of the second metal layer. For example, when the number of the metal wiring areas is 3, the number of overlapping areas of the second metal layer is 1, and when the number of the metal wiring areas is 2, the number of overlapping areas of the second metal layer is 2. For details, please refer to the subsequent description, which will not be repeated here.

[0035] In the embodiment of the present application, different masks are used during the first etching and the second etching. It can be understood that in order to ensure that the etching process does not over-etch or under-etch, two masks are set and the three perforations are etched separately through the two masks, so that each perforation etched can ensure successful metal overlap and conduction between different film layers.

[0036] In the method provided in the embodiment of the present application, the display panel is divided into a display area and a non-display area in the orthographic projection direction, wherein the display area is surrounded by the non-display area, the display area includes a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, a flat film layer PLN is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged in a partial area of ​​the buffer film layer of the display area close to the substrate side, and the side of the flat film layer close to the substrate is used to set at least two metal wiring areas; a first metal layer is arranged on the side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is arranged on the side of the interlayer dielectric layer corresponding to the non-display area close to the substrate. Through two etchings (the first etching and the second etching respectively), the two perforations formed by etching of the at least one metal wiring area are overlapped and connected with the first metal layer and the second metal layer, and the polysilicon layer is overlapped and connected with the metal wiring area corresponding to the polysilicon layer by etching a perforation (the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area). In this way, through two etching processes, the three perforations between different film layers are connected in the required overlapping manner. At the same time, due to batch etching, there will be no situation where one or more of the three perforations are under-etched or over-etched, so that under the premise of ensuring etching effect and wiring effect, wiring consumables can be reduced by increasing perforations.

[0037] Optionally, in the embodiment of the present application, the three perforations may all be perforations passing through the interlayer dielectric layer. On this basis, through the first etching and the second etching, the two perforations formed by etching at least one of the metal wiring areas are overlapped and connected with the first metal layer and the second metal layer, and the one perforation formed by etching the polysilicon layer is overlapped and connected with the metal wiring area corresponding to the polysilicon layer. The manufacturing method of the display panel disclosed in the present application includes: etching the interlayer dielectric layer through a first mask to generate two perforations, and etching the interlayer dielectric layer through a second mask to generate one perforation; or etching the interlayer dielectric layer through a first mask to generate one perforation, and etching the interlayer dielectric layer through a second mask to generate two perforations.

[0038] Exemplarily, the three perforations include: a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, a perforation from the interlayer dielectric layer to the second metal layer in the non-display area, and a perforation from the interlayer dielectric layer to the first metal layer in the non-display area.

[0039] It is understandable that the above-mentioned process of opening holes through masks all requires etching holes in the interlayer dielectric layer, that is, although the three holes have different depths, they all need to be etched vertically from the interlayer dielectric layer to the substrate to open holes. Therefore, in order to ensure that the etching process does not over-etch or under-etch, two holes can be etched by setting a first mask, and then a second mask can be used to etch a hole; or a first mask can be set to generate a hole, and then two holes can be generated by setting a second mask.

[0040] Optionally, in an embodiment of the present application, a third metal layer is provided on the side of the buffer film layer corresponding to the above-mentioned display area close to the above-mentioned substrate, and the side of the PLN film layer of the above-mentioned display area close to the substrate is used to set a metal wiring area, and the above-mentioned third metal layer and the thin film transistor of the above-mentioned display area overlap in the orthographic projection direction.

[0041] Exemplarily, the third metal layer is used to block light transmission through the ILD holes in the display area for mounting thin film transistors (TFTs), thereby reducing the damage caused by light.

[0042] Exemplarily, the third metal layer may be a LS layer. like Figures 5 to 7 As shown, an LS layer 29 (ie, the third metal layer mentioned above) is disposed on a side of the display area close to the substrate.

[0043] Exemplarily, the metal wiring region of the display region may be a SD layer.

[0044] Exemplarily, the metal wiring area of ​​the display area overlaps with the polysilicon layer in the orthographic projection direction. The metal wiring area of ​​the display area overlaps with the thin film transistor in the orthographic projection direction.

[0045] It can be understood that the metal wiring area of ​​the display area can be connected to the thin film transistor and can also be connected to the polysilicon layer.

[0046] For example, in the process of etching to generate the above three perforations, the etching methods can be combined at will, and the embodiments of the present application do not limit this.

[0047] like Figure 5 As shown, Figure 5 The structure includes three perforations, which are the perforations from the interlayer dielectric layer ILD24 to the polysilicon layer 26 in the display area (hereinafter referred to as the first hole 31, the position framed by the dotted frame 31), the perforations from the interlayer dielectric layer ILD24 in the non-display area to the second metal layer GATE layer 27 in the non-display area (hereinafter referred to as the second hole 32, the position framed by the dotted frame 32), and the perforations from the interlayer dielectric layer ILD24 in the non-display area to the first metal area LS layer 28 in the non-display area (hereinafter referred to as the third hole 33, the position framed by the dotted frame 33). The first metal layer LS layer 28 is arranged on the side of the buffer film layer 22 corresponding to the non-metal area close to the substrate, and the second metal layer GATE layer 27 is arranged on the side of the interlayer dielectric layer ILD24 corresponding to the non-metal area close to the substrate. It can be seen that the perforations from the interlayer dielectric layer ILD24 in the non-display area to the second metal layer GATE layer 27 in the non-display area are single-layer perforations in the interlayer dielectric layer ILD24. It should be noted that the display area and the non-display area are divided by a dotted line 30 , the left side of the dotted line 30 is the display area, and the right side of the dotted line 30 is the non-display area.

[0048] The following are different examples to illustrate the above different perforation sequences and perforation methods: It can be understood that in the following examples, at least two metal wiring areas include three SD areas in the flat film layer PLN25 close to the display substrate, and the three SD areas overlap with the display area GI layer at the orthographic projection position of the polysilicon layer 26 on the substrate, overlap with the non-display area GATE layer 27 at the orthographic projection part of the substrate, and overlap with the non-display area LS layer 28 at the orthographic projection part of the substrate: Example 1: Figure 5As shown, after the ILD layer 24 is coated, an etching process is first performed through a first mask to etch the second hole 32 and the third hole 33 at the position corresponding to the orthographic projection position of the ILD layer in the non-display area and the two SD areas, ensuring that the second hole 32 and the third hole 33 are etched according to the overlap requirement. Afterwards, an etching process is performed using a second mask to etch the first hole 31 at the position corresponding to the orthographic projection position of the ILD layer in the display area and one SD area, ensuring that the first hole 31 is etched according to the overlap requirement.

[0049] Example 2: Figure 5 As shown, after the ILD layer 24 is coated, an etching process is first performed through a first mask to etch a first hole 31 at a position corresponding to the orthographic projection position of the ILD layer in the display area and one SD area, ensuring that the first hole 31 is etched according to the overlap requirement. Afterwards, an etching process is performed using a second mask to etch a second hole 32 and a third hole 33 at a position corresponding to the orthographic projection position of the ILD layer in the non-display area and two SD areas, ensuring that the second hole 32 and the third hole 33 are etched according to the overlap requirement.

[0050] Example 3: Figure 6 As shown, after the ILD layer 24 is coated, an etching process is first performed through a first mask, and etching is performed in the ILD layer in the non-display area. The etching position is the area corresponding to the SD area that overlaps with the orthographic projection of the GATE layer 27 in the non-display area on the substrate, that is, the second hole 32 is etched first. Afterwards, the second mask is used to etch the first hole 31 at the position where the SD area and the polysilicon layer 26 overlap on the orthographic projection of the substrate in the ILD layer in the display area, and the third hole 33 is etched at the position where the LS layer 28 overlaps on the orthographic projection of the substrate in the ILD layer in the non-display area. The first hole 31 and the third hole 33 are etched simultaneously according to the overlap requirements.

[0051] Example 4: Figure 6 As shown, after the ILD layer 24 is coated, an etching process is first performed through a first mask to etch a first hole 31 at a position in the ILD layer in the display area that overlaps with the SD area and the polysilicon layer 26 on the substrate orthographic projection, and a third hole 33 is etched at a position in the ILD layer in the non-display area that overlaps with the LS layer 28 on the substrate orthographic projection. The first hole 31 and the third hole 33 are etched simultaneously according to the overlap requirement, that is, the first hole 31 and the third hole 33 are etched first. Afterwards, the second mask is used to etch in the ILD layer in the non-display area, and the etching position is the area corresponding to the SD area that overlaps with the orthographic projection of the GATE layer 27 in the non-display area on the substrate, that is, the above-mentioned second hole 32 is etched again.

[0052] It should be noted that in the process of etching the first hole 31 and the third hole 33, both need to be etched into the buffer layer. However, since the LS layer 28 is composed of three layers of Mo / Al / Mo, the Mo layer has a relatively high hardness and is often difficult to etch through, and will not be etched into the Al layer. Therefore, although the first hole 31 is etched into the buffer layer like the third hole 33, and overlaps with the LS layer 28 in the display area and the LS layer 29 in the non-display area, the first hole 31 will actually only make the subsequent SD layer conductive with the polysilicon layer 26, but will not be conductive with the LS layer 29 in the display area.

[0053] At the same time, since the first hole 31 and the third hole 33 are both etched to the LS layer in the buffer memory, the first hole 31 will not have the problem in the prior art that some of the first holes 31 are etched to the LS layer 29 and some are not etched to the LS layer 29, which leads to uneven depth of the first hole 31, and ultimately leads to inconsistent coupling on the front of the display panel, inconsistent Vcom voltages actually required at different positions, and ultimately uneven display and poor display effect. When the etching depth of the first hole 31 is unified, the unified Vcom voltage can also ensure the display uniformity of the display panel, thereby improving the display effect of the display panel.

[0054] Optionally, the method for manufacturing a display panel provided in the embodiment of the present application further includes: during the first etching and the second etching, shielding the perforations generated corresponding to the first etching by the shielding material.

[0055] It can be understood that before the first etching begins, a shielding material can be set at the perforation generated corresponding to the second etching to protect areas other than the perforation area that needs to be generated in the first etching, thereby avoiding over-etching of other areas outside the first etching range during the first etching process; after the first etching is completed and before the second etching begins, for the holes formed at the end of the first etching, a shielding material can be set at the perforation generated corresponding to the first etching to protect the perforation generated after the first etching, thereby avoiding the perforation that has been etched from being etched again during the second etching process.

[0056] In one example, the shielding material may be PR glue.

[0057] Furthermore, the above-mentioned shielding material is applied in the process of including three perforations in the interlayer dielectric layer ILD24. It can be understood that in the case where the same film layer, that is, the interlayer dielectric layer ILD24 includes three perforations, the three perforations are not etched at the same time, but are etched through two masks in succession. Therefore, during the two etching processes, they cannot affect each other. Based on this, before the first etching and before the second etching, a shielding material needs to be set on the side of the interlayer dielectric layer ILD24 away from the substrate.

[0058] Example 5: In combination with the above Example 1, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the other areas except the areas where the second holes 32 and the third holes 33 are etched are covered with PR glue, and the first etching is performed; then after the first etching is completed, the PR glue is peeled off, and the other areas except the area of ​​the first hole 31 are covered with PR glue, and then the second etching is performed.

[0059] Example 6: In combination with the above Example 2, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the other areas except the area where the first hole 31 is etched are covered with PR glue, and the first etching is performed; then after the first etching is completed, the PR glue is peeled off, and the other areas except the areas of the second hole 32 and the third hole 33 are covered with PR glue, and then the second etching is performed.

[0060] Example 7: In combination with the above Example 3, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the other areas except the areas where the first hole 31 and the third hole 33 are etched are covered with PR glue, and the first etching is performed; then after the first etching is completed, the PR glue is peeled off, and the other areas except the area of ​​the second hole 32 are covered with PR glue, and then the second etching is performed.

[0061] Example 8: In combination with the above Example 4, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the other areas except the area where the second hole 32 is etched are covered with PR glue, and the first etching is performed; then after the first etching is completed, the PR glue is peeled off, and the other areas except the areas of the first hole 31 and the third hole 33 are covered with PR glue, and then the second etching is performed.

[0062] Optionally, in the embodiment of the present application, the perforations in the non-display area of ​​the three perforations can be holes opened successively in different film layers, so that the metal layers between different film layers are finally overlapped. Through the first etching and the second etching, the two perforations formed by etching at least one of the metal wiring areas are overlapped and connected with the first metal layer and the second metal layer, and the one perforation formed by etching the polysilicon layer is overlapped and connected with the metal wiring area corresponding to the polysilicon layer. The manufacturing method of the display panel in the embodiment of the present application includes: two second metal layers are arranged on the side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, the first second metal layer partially overlaps with the metal wiring area in the orthographic projection direction of the substrate, and the second second metal layer partially overlaps with the first metal layer in the orthographic projection direction of the substrate; the GI layer in the non-display area is etched through a third mask to generate a perforation from the GI layer in the non-display area to the first metal layer; the interlayer dielectric layer in the non-display area is etched through a fourth mask to generate two perforations.

[0063] Exemplarily, the two through-holes corresponding to the fourth mask are: a through-hole from the interlayer dielectric layer to the polysilicon layer in the display area, and a through-hole from the interlayer dielectric layer to the second metal layer in the non-display area.

[0064] It can be understood that in the embodiment of the present application, the purpose of adding the first metal layer and the second metal layer in the non-display area compared to before is to reduce the peripheral wiring in the non-display area, thereby reducing the wiring by overlapping the internal film layers.

[0065] Furthermore, in order to make the metal wiring area located in the flat film layer in the non-display area overlap and conduct between the second metal layer of the interlayer dielectric layer and the first metal layer of the buffer film layer, two second metal regions of the second metal layer can be set in the interlayer dielectric layer, wherein one second metal region overlaps with the metal wiring area in the flat film layer, and the other second metal region overlaps with the first metal layer in the buffer film layer. In this way, the above-mentioned three-layer wiring in the non-display area is realized.

[0066] like Figure 7 As shown, Figure 7 The structure includes three through holes, which are respectively a through hole from the interlayer dielectric layer ILD24 in the display area to the polysilicon layer 26 (hereinafter referred to as the first hole 31), a through hole from the interlayer dielectric layer ILD24 in the non-display area to the second metal layer GATE layer 27 in the non-display area (hereinafter referred to as the second hole 32), and a through hole from the non-display area GI film layer 23 to the first metal layer LS layer 28 in the non-display area (hereinafter referred to as the third hole 33). The first metal layer LS layer 28 is disposed on the side of the buffer film layer 22 corresponding to the non-metal region close to the substrate, and the second metal layer GATE layer 27 is disposed on the side of the interlayer dielectric layer ILD24 corresponding to the non-metal region close to the substrate. It can be seen that the perforation between the interlayer dielectric layer ILD24 in the non-display region and the second metal layer GATE layer 27 in the non-display region is a single-layer perforation in the interlayer dielectric layer ILD24.

[0067] The following are different examples to illustrate the different perforation sequences and perforation methods mentioned above: It can be understood that in the following examples, at least two metal wiring areas include two SD areas in the flat film layer PLN25 close to the display substrate, and the two SD areas overlap with the display area GI layer at the orthographic projection position of the polysilicon layer 26 on the substrate, and overlap with the non-display area GATE layer 27 at the orthographic projection part of the substrate: Example 9: Figure 7 As shown, after the GI film layer 23 is coated, the etching process is first performed using the mask of the GI layer through the first mask, and the third hole 33 is etched at the position where the GI film layer 23 in the non-display area overlaps with the LS layer 28 in the non-display area in the orthographic projection area, ensuring that the third hole 33 is etched according to the requirement that the GATE layer 27 and the LS layer 28 in the non-display area can be overlapped and connected. After that, the interlayer dielectric layer ILD layer 24 is coated, and the etching process is performed using the mask of the ILD layer using the second mask, and the first hole 31 overlapping with the polysilicon layer 26 at the orthographic projection position of the substrate is etched in the interlayer dielectric layer ILD layer 24 in the display area, and the etching is performed in the ILD layer in the non-display area, and the etching position is the area corresponding to the SD area overlapping with the orthographic projection part of the GATE layer 27 in the non-display area on the substrate, that is, the above-mentioned second hole 32 is etched again.

[0068] The present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the training rule determination method described in the present application is implemented. For example, the following can be executed: Figure 4 The individual steps of the method are shown.

[0069] The present invention provides a computer program product, which includes instructions that are executed by a processor when the processor executes the instructions. Figure 4 The individual steps of the method are shown.

[0070] It should be noted that although the operations of the method of the present invention are described in a particular order in the drawings, this does not require or imply that the operations must be performed in this particular order or that all illustrated operations must be performed to achieve desired results.

[0071] The embodiment of the present application further discloses a display panel, wherein the display panel comprises a display area and a non-display area in an orthographic projection direction, wherein the display area is at least partially surrounded by the non-display area; the display panel comprises a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, a flat film layer is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged on a partial area of ​​the buffer film layer of the display area close to the substrate, and a side of the flat film layer close to the substrate is used to arrange at least two metal wiring areas; A first metal layer is disposed on a side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is disposed on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate; The at least one metal wiring area is overlapped and connected with the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is overlapped and connected with a through hole formed by etching and the metal wiring area corresponding to the polysilicon layer; The orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0072] In one example, the three perforations include: a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, a perforation from the interlayer dielectric layer to the second metal layer in the non-display area, and a perforation from the interlayer dielectric layer to the first metal layer in the non-display area.

[0073] In one example, two second metal layers are provided on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, a first second metal layer partially overlaps with the metal wiring area in the orthographic projection direction of the substrate, and a second second metal layer partially overlaps with the first metal layer in the orthographic projection direction of the substrate; The three perforations include: a perforation from the GI layer to the first metal layer in the non-display area, a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, and a perforation from the interlayer dielectric layer to the second metal layer in the non-display area.

[0074] Figure 8The manufacturing device of the display panel disclosed in the embodiment of the present application includes an execution unit 601: the display panel includes a display area and a non-display area in the orthographic projection direction, and the display area is at least partially surrounded by the non-display area; the display panel includes a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, and a flat film layer is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged in a partial area of ​​the buffer film layer of the display area close to the substrate, and a side of the flat film layer close to the substrate is used to set at least two metal wiring areas; a first metal layer is arranged on the side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is arranged on the side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, and the execution unit 601 is used to: Through the first etching and the second etching, two through-holes formed by etching of at least one of the metal wiring regions are overlapped and connected with the first metal layer and the second metal layer, and one through-hole formed by etching of the polysilicon layer is overlapped and connected with the metal wiring region corresponding to the polysilicon layer; The orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0075] In a possible example, the execution unit 601 is specifically configured to: The interlayer dielectric layer is etched through a first mask to generate two through-holes, and the interlayer dielectric layer is etched through a second mask to generate one through-hole; or, The interlayer dielectric layer is etched through a first mask to generate a through hole, and the interlayer dielectric layer is etched through a second mask to generate two through holes; The three perforations include: a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, a perforation from the interlayer dielectric layer to the second metal layer in the non-display area, and a perforation from the interlayer dielectric layer to the first metal layer in the non-display area.

[0076] In a possible example, the execution unit 601 is specifically configured to: During the first etching and the second etching, the through-holes generated corresponding to the first etching are shielded by the shielding material.

[0077] In a possible example, the execution unit 601 is specifically configured to: The method of performing the first etching and the second etching to overlap and conduct two through-holes formed by etching at least one of the metal wiring regions with the first metal layer and the second metal layer, and overlapping and conducting one through-hole formed by etching the polysilicon layer with the metal wiring region corresponding to the polysilicon layer, comprises: Two second metal layers are arranged on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, the first of the second metal layers partially overlaps with the metal wiring area in the orthographic projection direction of the substrate, and the second of the second metal layers partially overlaps with the first metal layer in the orthographic projection direction of the substrate; etching the GI layer in the non-display area through a third mask to generate a through hole from the GI layer in the non-display area to the first metal layer; Through a fourth mask, etching the interlayer dielectric layer in the non-display area to form two through-holes; The two through-holes corresponding to the fourth mask are: a through-hole from the interlayer dielectric layer to the polysilicon layer in the display area, and a through-hole from the interlayer dielectric layer to the second metal layer in the non-display area.

[0078] In a possible example, a third metal layer is provided on the side of the buffer film layer corresponding to the display area close to the substrate, and the side of the PLN film layer of the display area close to the substrate is used to set a metal wiring area, and the third metal layer and the thin film transistor of the display area overlap in the orthographic projection direction.

[0079] It should be understood that the units recorded in the manufacturing device of the display panel correspond to the steps in the method described in the accompanying drawings. Therefore, the operations and features described above for the method are also applicable to the manufacturing device of the display panel and the units contained therein, and will not be repeated here. The manufacturing device of the display panel can be pre-implemented in the browser or other security applications of the computer device, or can be loaded into the browser or its security application of the computer device by downloading or the like. The corresponding units in the manufacturing device of the display panel can cooperate with the units in the computer device to implement the solution of the embodiment of the present application.

[0080] For the several modules or units mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0081] It should be noted that for details not disclosed in the display panel manufacturing device of the embodiment of the present application, please refer to the details disclosed in the above embodiments of the present application, which will not be repeated here.

[0082] Reference below Fig. 9 , Fig. 9 FIG. 1 is a schematic diagram showing a structure of a computer device suitable for implementing an embodiment of the present application. Fig. 9 As shown, the computer system 1700 includes a central processing unit (CPU) 1701, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1702 or the program loaded from the storage part 1708 to the random access memory (RAM) 1703. In the RAM 1703, various programs and data required for the operation instructions of the system are also stored. The CPU 1701, the ROM 1702, and the RAM 1703 are connected to each other through a bus 1704. An input / output (I / O) interface 1705 is also connected to the bus 1704.

[0083] The following components are connected to the I / O interface 1705: an input section 1706 including a keyboard, a mouse, etc.; an output section 1707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1708 including a hard disk, etc.; and a communication section 1709 including a network interface card such as a LAN card, a modem, etc. The communication section 1709 performs communication processing via a network such as the Internet. A drive 1710 is also connected to the I / O interface 1705 as needed. A removable medium 1711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1710 as needed, so that a computer program read therefrom is installed into the storage section 1708 as needed.

[0084] In particular, according to an embodiment of the present application, the above reference flow chart Figure 4 The described process can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 1709, and / or installed from a removable medium 1711. When the computer program is executed by the central processing unit (CPU) 1701, the above-mentioned functions defined in the system of the present application are executed.

[0085] It should be noted that the computer-readable medium shown in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium such as a computer-readable storage medium that can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0086] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operating instructions of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the aforementioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operating instruction, or can be implemented with a combination of dedicated hardware and computer instructions.

[0087] The units or modules involved in the embodiments described in the present application may be implemented by software or hardware. The units or modules described may also be set in a processor. For example, it may be described as: a processor includes a first receiving module, a second receiving module, and a sending module. The names of these units or modules do not, in some cases, constitute limitations on the units or modules themselves.

[0088] As another aspect, the present application further provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device. The above computer-readable storage medium stores one or more programs, and when the above programs are used by one or more processors to execute the method for manufacturing a display panel described in the present application.

[0089] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the aforementioned disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present application (but not limited to) by each other to form a technical solution.

Claims

1. A method for manufacturing a display panel, characterized in that: The display panel comprises a display area and a non-display area in the orthographic projection direction, wherein the display area is at least partially surrounded by the non-display area; the display panel comprises a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, a flat film layer is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged on a partial area of ​​the buffer film layer of the display area close to the substrate, and a side of the flat film layer close to the substrate is used to arrange at least two metal wiring areas; A first metal layer is disposed on a side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is disposed on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, and the method includes: Through the first etching and the second etching, two through-holes formed by etching of at least one of the metal wiring regions are overlapped and connected with the first metal layer and the second metal layer, and one through-hole formed by etching of the polysilicon layer is overlapped and connected with the metal wiring region corresponding to the polysilicon layer; The orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

2. The method according to claim 1, characterized in that The method of performing the first etching and the second etching to overlap and conduct two through-holes formed by etching at least one of the metal wiring regions with the first metal layer and the second metal layer, and overlapping and conducting one through-hole formed by etching the polysilicon layer with the metal wiring region corresponding to the polysilicon layer, comprises: The interlayer dielectric layer is etched through a first mask to generate two through-holes, and the interlayer dielectric layer is etched through a second mask to generate one through-hole; or, The interlayer dielectric layer is etched through a first mask to generate a through hole, and the interlayer dielectric layer is etched through a second mask to generate two through holes; The three perforations include: a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, a perforation from the interlayer dielectric layer to the second metal layer in the non-display area, and a perforation from the interlayer dielectric layer to the first metal layer in the non-display area.

3. The method according to claim 2, characterized in that The method further comprises: During the first etching and the second etching, the through-holes generated corresponding to the first etching are shielded by the shielding material.

4. The method according to claim 1, characterized in that: The method of performing the first etching and the second etching to overlap and conduct two through-holes formed by etching at least one of the metal wiring regions with the first metal layer and the second metal layer, and overlapping and conducting one through-hole formed by etching the polysilicon layer with the metal wiring region corresponding to the polysilicon layer, comprises: Two second metal layers are arranged on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, the first of the second metal layers partially overlaps with the metal wiring area in the orthographic projection direction of the substrate, and the second of the second metal layers partially overlaps with the first metal layer in the orthographic projection direction of the substrate; etching the GI layer in the non-display area through a third mask to generate a through hole from the GI layer in the non-display area to the first metal layer; Through a fourth mask, etching the interlayer dielectric layer in the non-display area to form two through-holes; The two through-holes corresponding to the fourth mask are: a through-hole from the interlayer dielectric layer to the polysilicon layer in the display area, and a through-hole from the interlayer dielectric layer to the second metal layer in the non-display area.

5. The method according to claim 1, characterized in that A third metal layer is arranged on the side of the buffer film layer corresponding to the display area close to the substrate, and a metal wiring area is arranged on the side of the PLN film layer of the display area close to the substrate. The third metal layer and the thin film transistor of the display area overlap in the orthographic projection direction.

6. A display panel, characterized in that: The display panel comprises a display area and a non-display area in the orthographic projection direction, wherein the display area is at least partially surrounded by the non-display area; the display panel comprises a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, a flat film layer is arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is arranged on a partial area of ​​the buffer film layer of the display area close to the substrate, and a side of the flat film layer close to the substrate is used to arrange at least two metal wiring areas; A first metal layer is disposed on a side of the buffer film layer corresponding to the non-display area close to the substrate, and a second metal layer is disposed on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate; The at least one metal wiring area is overlapped and connected with the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is overlapped and connected with a through hole formed by etching and the metal wiring area corresponding to the polysilicon layer; The orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

7. The display panel according to claim 6, characterized in that: The three perforations include: a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, a perforation from the interlayer dielectric layer to the second metal layer in the non-display area, and a perforation from the interlayer dielectric layer to the first metal layer in the non-display area.

8. The display panel according to claim 6, characterized in that: Two second metal layers are arranged on a side of the interlayer dielectric layer corresponding to the non-display area close to the substrate, the first of the second metal layers partially overlaps with the metal wiring area in the orthographic projection direction of the substrate, and the second of the second metal layers partially overlaps with the first metal layer in the orthographic projection direction of the substrate; The three perforations include: a perforation from the GI layer to the first metal layer in the non-display area, a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, and a perforation from the interlayer dielectric layer to the second metal layer in the non-display area.

9. A device for manufacturing a display panel, characterized in that: It comprises an execution module, which is used to execute and implement the method according to any one of claims 1 to 5.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 5 is implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

12. A computer program product, comprising instructions, characterized in that: When the instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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