Antifuse device and its memory

Abstract

The present disclosure discloses an antifuse device and its memory. The antifuse device includes: an antifuse array including: a plurality of antifuse units; a programming control circuit coupled to the antifuse array via a sensing node, including: a first transistor and a leakage suppression circuit, wherein the first terminal of the first transistor is coupled to the sensing node, the input terminal of the leakage suppression circuit is coupled to the control terminal of the first transistor, and the output terminal of the leakage suppression circuit is coupled to the second terminal of the first transistor; wherein, when a programming operation is performed on the antifuse unit, the output terminal of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the antifuse unit, the output terminal of the leakage suppression circuit is at a second voltage level; and the second voltage level is greater than the first voltage level.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuits, and in particular to an anti-fuse device and a memory thereof. Background Art

[0002] One-Time Programmable (OTP) devices include fuse devices and antifuse devices. An antifuse device consists of multiple antifuse cells. When an antifuse cell is unprogrammed, it is in a high-impedance state, which is recorded as a logic "0." When an antifuse cell is programmed, it is in a low-impedance state, which is recorded as a logic "1."

[0003] The logic information stored in the antifuse cell (e.g., logic "0" or "1") can be read by sensing the magnitude of a read electrical signal (e.g., a read voltage). However, during the read process, the antifuse cell may fail to read or experience data inversion due to leakage. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, an anti-fuse device is provided, including:

[0005] An antifuse array comprises: a plurality of antifuse units;

[0006] A programming control circuit is coupled to the anti-fuse array through a sensing node, and includes: a first transistor and a leakage suppression circuit, wherein the first end of the first transistor is coupled to the sensing node, the input end of the leakage suppression circuit is coupled to the control end of the first transistor, and the output end of the leakage suppression circuit is coupled to the second end of the first transistor; wherein, when a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; and the second voltage level is greater than the first voltage level.

[0007] In some embodiments, the leakage suppression circuit includes at least one inverter; the inverter includes:

[0008] a second transistor, wherein a first terminal of the second transistor is coupled to a power supply, a second terminal of the second transistor is coupled to the output terminal of the inverter, and a control terminal of the second transistor is coupled to the control terminal of the first transistor; wherein the power supply is configured to provide the second voltage level;

[0009] a third transistor, wherein a first terminal of the third transistor is coupled to the output terminal of the inverter, a second terminal of the third transistor is coupled to the ground terminal, and a control terminal of the third transistor is coupled to the control terminal of the first transistor; wherein the ground terminal is used to provide the first voltage level.

[0010] In some embodiments, the leakage suppression circuit includes a plurality of the inverters; wherein the plurality of inverters are connected in parallel.

[0011] In some embodiments, the type of the first transistor is the same as the type of the third transistor, and the type of the first transistor is different from the type of the second transistor.

[0012] In some embodiments, a size of the first transistor is larger than a size of the second transistor.

[0013] In some embodiments, a size of the third transistor is greater than or equal to a size of the second transistor.

[0014] In some embodiments, the anti-fuse device further includes: a comparator; wherein a first input terminal of the comparator is coupled to the anti-fuse array through the sensing node, and a second input terminal of the comparator is used to receive a reference voltage.

[0015] In some embodiments, the first voltage level is a ground level;

[0016] The second voltage level is greater than the reference voltage and less than or equal to a precharge level of the sensing node.

[0017] In some embodiments, when the programming operation is performed on the anti-fuse unit, the control terminal of the first transistor is at a third voltage level; wherein the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

[0018] According to a second aspect of the embodiments of the present disclosure, a memory is provided, comprising the anti-fuse device as described in any one of the above embodiments.

[0019] In an embodiment of the present disclosure, a leakage suppression circuit is provided in a programming control circuit, and the output end of the leakage suppression circuit is connected to the second end of the first transistor. When a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; since the second voltage level is greater than the first voltage level, when a read operation is performed on the anti-fuse unit, the high level of the output end of the leakage suppression circuit can reduce the leakage of the first transistor, which is beneficial to reducing the probability of reading failure or data inversion of the anti-fuse device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit structure diagram of an anti-fuse device according to an exemplary embodiment;

[0021] Figure 2 is a schematic diagram showing a read voltage of an anti-fuse device according to an exemplary embodiment;

[0022] Figure 3 is a circuit structure diagram of an anti-fuse device according to an embodiment of the present disclosure;

[0023] Figure 4 is a schematic diagram showing a read voltage of an anti-fuse device according to an embodiment of the present disclosure;

[0024] Figure 5 is a circuit structure diagram of another anti-fuse device according to an embodiment of the present disclosure;

[0025] Figure 6 It is a flowchart of an operating method of an anti-fuse device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0027] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0028] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0030] Figure 1 FIG. 1 is a circuit structure diagram of an anti-fuse device 100 according to an exemplary embodiment. Figure 1As shown, the antifuse device 100 includes an antifuse array 110 and a programming control circuit 120. The antifuse array 110 includes a plurality of antifuse cells, for example, an antifuse cell 111 and an antifuse cell 112. The programming control circuit 120 is configured to perform a programming operation on the antifuse array 110. The programming control circuit 120 includes a transistor 121. When a programming operation is performed on an antifuse cell selected in the antifuse array, the transistor 121 is turned on to provide a ground level to the selected antifuse cell, thereby forming a breakdown voltage difference.

[0031] The anti-fuse device 100 further includes a pre-charge circuit 130 , which can pre-charge the sensing node before the comparator 141 is enabled.

[0032] The antifuse device 100 further includes a read circuit 140, which is configured to perform a read operation on the antifuse array 110. The read circuit 140 includes a comparator 141. When a read operation is performed on a selected antifuse cell in the antifuse array 110, the transistor 121 is turned off. A first input terminal of the comparator 141 is configured to receive a read voltage, and a second input terminal of the comparator 141 is configured to receive a reference voltage.

[0033] The antifuse array 110 further includes column selection transistors, each of which is connected to a plurality of column address lines. The control terminal of the column selection transistor is used to receive a column address signal (eg, Y <0> 、Y <1> ,……Y <n>), the column selection transistor includes an N-type transistor (NMOS), and the NMOS transistor is used to select multiple column address lines through the received column address signal; in some embodiments, the column selection transistor also includes a P-type transistor (PMOS), and the PMOS transistor is used to ground the column address line where the unselected anti-fuse unit is located, thereby avoiding accidental start-up or entering a floating state, which is beneficial to reducing the power consumption of the anti-fuse device.

[0034] However, during the read operation, the transistor 121 may leak electricity, resulting in Figure 1 The leakage path shown in the figure causes charge leakage, which causes the read voltage to decrease over time and cannot maintain the target voltage. Figure 2 As shown by the middle curve L1, during the period from T1 to T2 (ie, the sensing period), when the reading voltage is lower than the fault sensing point A, the anti-fuse unit may fail to read or may experience data inversion.

[0035] In view of this, embodiments of the present disclosure provide an anti-fuse device, an operating method thereof, and a memory.

[0036] Figure 3 FIG is a circuit structure diagram of an anti-fuse device 200 according to an embodiment of the present disclosure. Figure 3 As shown, the anti-fuse device 200 includes:

[0037] An antifuse array comprises: a plurality of antifuse units;

[0038] The programming control circuit 220 is coupled to the anti-fuse array through the sensing node q, and includes: a first transistor 221 and a leakage suppression circuit 222, wherein the first end d of the first transistor 221 is coupled to the sensing node q, the input end b of the leakage suppression circuit 222 is coupled to the control end a of the first transistor 221, and the output end c of the leakage suppression circuit 222 is coupled to the second end e of the first transistor 221; wherein, when a programming operation is performed on the anti-fuse unit, the output end c of the leakage suppression circuit 222 is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end c of the leakage suppression circuit 222 is at a second voltage level; and the second voltage level is greater than the first voltage level.

[0039] The antifuse array includes a plurality of antifuse units, each of which includes a programming transistor and a selection transistor, wherein the programming transistor and the selection transistor are connected in series. Figure 1 The anti-fuse unit includes a programming transistor Fs <0> 、Fs <1> and select transistor X <0> 、X <1> , programming transistor Fs <0> and select transistor X <0> It can form an anti-fuse unit 111, a programming transistor Fs <1> and select transistor X <1> It can form an antifuse unit 112. It should be noted that the embodiment of the present disclosure has no special limitation on the number of antifuse units in the antifuse array. A plurality of antifuse units distributed in an array along the row direction and the column direction can form an antifuse array.

[0040] The antifuse device further includes a plurality of row address lines and a plurality of column address lines. Each row address line extends in a row direction and is coupled to the control terminals of a plurality of select transistors. Each column address line extends in a column direction and is coupled to a plurality of antifuse units. For example, a row address line is coupled to the control terminals of a plurality of select transistors in the same row, and a column address line is coupled to a plurality of antifuse units in the same column. Here, the direction in which the row address lines extend can be defined as the "row direction," and the direction in which the column address lines extend can be defined as the "column direction."

[0041] Reference Figure 3 As shown, the anti-fuse device further includes a plurality of column selection transistors, each connected to a plurality of column address lines. The control terminal of the column selection transistor is used to receive a column address signal (eg, Y <0> 、Y <1> ,……Y <n>), the column selection transistor includes an N-type transistor (NMOS), and the NMOS transistor is used to select multiple column address lines through the received column address signal; in some embodiments, the column selection transistor also includes a P-type transistor (PMOS), and the PMOS transistor is used to ground the column address line where the unselected anti-fuse unit is located, thereby avoiding accidental start-up or entering a floating state, which is beneficial to reducing the power consumption of the anti-fuse device.

[0042] In some embodiments, the anti-fuse device also includes multiple row selection transistors (not shown in the figure), which are respectively connected to multiple row address lines. The control end of the row selection transistor is used to receive a row address signal for selecting at least one of the multiple row address lines. The row selection transistor includes a P-type transistor; in some embodiments, the row selection transistor also includes an N-type transistor.

[0043] The program control circuit 220 is coupled to the antifuse array through the sensing node q. For example, the program control circuit 220 is coupled to the antifuse array through the column address line. The program control circuit 220 can perform a program operation on the selected antifuse unit in the antifuse array in response to a program control signal.

[0044] In some embodiments, the antifuse device includes multiple antifuse arrays and multiple programming control circuits, each of which is coupled to each antifuse array. For example, each column address line in the same antifuse array is coupled to a sensing node q via a different column select transistor, and column address lines of different antifuse arrays are coupled to different sensing nodes.

[0045] In some embodiments, an antifuse device includes multiple programming control circuits, each coupled to an antifuse array via a plurality of sensing nodes. At least one of the multiple programming control circuits includes a leakage suppression circuit. The leakage suppression circuit may be provided in some or all of the programming control circuits, thereby reducing the probability of read failure or data inversion in the antifuse device.

[0046] The first transistor 221 includes a first terminal d, a second terminal e, and a control terminal a located between the first terminal d and the second terminal e. The first terminal d is coupled to the sensing node q, the control terminal a is used to receive a programming control signal, and the second terminal e is coupled to the output terminal c of the leakage suppression circuit 222. The first transistor 221 can be a P-type transistor or an N-type transistor. The first terminal d can be the source or drain of the first transistor 221, the second terminal e can be the drain or source of the first transistor 221, and the control terminal a can be the gate of the first transistor 221. In the embodiments disclosed herein, an NMOS transistor is used as an example for description.

[0047] The leakage suppression circuit 222 includes an input terminal b and an output terminal c. The input terminal b and the control terminal a of the first transistor 221 are coupled to the input terminal p of the programming control circuit 220. The output terminal c is coupled to the second terminal e of the first transistor 221. When programming the anti-fuse cell, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a high level, turning the first transistor 221 on. The input terminal b of the leakage suppression circuit 222 receives the programming control signal and sets it to a high level, and outputs a low level, i.e., a first voltage level. When reading the anti-fuse cell, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a low level, turning the first transistor 221 off. The input terminal b of the leakage suppression circuit 222 receives the programming control signal and sets it to a low level, and outputs a high level, i.e., a second voltage level. Since the output terminal c of the leakage suppression circuit 222 is coupled to the second terminal e of the first transistor 221, the second terminal e of the first transistor 221 is in a high state during a read operation, thereby reducing charge leakage during the read operation.

[0048] In an embodiment of the present disclosure, a leakage suppression circuit is provided in a programming control circuit, and the output end of the leakage suppression circuit is connected to the second end of the first transistor. When a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; since the second voltage level is greater than the first voltage level, when a read operation is performed on the anti-fuse unit, the high level of the output end of the leakage suppression circuit can reduce the leakage of the first transistor, which is beneficial to reducing the probability of reading failure or data inversion of the anti-fuse device.

[0049] In some embodiments, reference Figure 3 As shown, the leakage suppression circuit 222 includes at least one inverter 222a; the inverter 222a includes:

[0050] a second transistor 222-1, wherein a first terminal g of the second transistor 222-1 is coupled to a power source, a second terminal h of the second transistor 222-1 is coupled to an output terminal c of the inverter 222a, and a control terminal f of the second transistor 222-1 is coupled to a control terminal a of the first transistor 221; wherein the power source is configured to provide a second voltage level;

[0051] A third transistor 222-2 has a first terminal j coupled to the output terminal c of the inverter 222a, a second terminal k coupled to the ground terminal, and a control terminal i of the third transistor 222-2 coupled to the control terminal a of the first transistor 221; wherein the ground terminal is used to provide a first voltage level.

[0052] In a specific embodiment, the input terminal b can be either the input terminal of the inverter 222 a or the input terminal of the leakage suppression circuit 222 , and the output terminal c can be either the output terminal of the inverter 222 a or the output terminal of the leakage suppression circuit 222 .

[0053] The second transistor 222-1 includes a first terminal g, a second terminal h, and a control terminal f located between the first terminal g and the second terminal h. The first terminal g is coupled to a power supply that provides a second voltage level, for example, 0.8V to 1.2V. The control terminal f is configured to receive a signal from the input terminal b of the inverter 222a, for example, a programming control signal. The second terminal h is coupled to the output terminal c of the inverter 222a. The second transistor 222-1 can be a P-type transistor or an N-type transistor. The first terminal g can be the source or drain of the second transistor 222-1, the second terminal h can be the drain or source of the second transistor 222-1, and the control terminal f can be the gate of the second transistor 222-1. In the embodiments disclosed herein, the second transistor 222-1 is described as a PMOS transistor.

[0054] The third transistor 222-2 includes a first terminal j, a second terminal k, and a control terminal i located between the first terminal j and the second terminal k. The first terminal j is coupled to the output terminal c of the inverter 222a. The control terminal i is configured to receive a signal from the input terminal b of the inverter 222a, such as a programming control signal. The second terminal k is coupled to a ground terminal, which is configured to provide a first voltage level, such as 0V. The third transistor 222-2 can be a P-type transistor or an N-type transistor. The first terminal j can be the source or drain of the third transistor 222-2, the second terminal k can be the drain or source of the third transistor 222-2, and the control terminal i can be the gate of the third transistor 222-2. In the embodiments disclosed herein, an NMOS transistor is used as an example for description.

[0055] The control terminal f of the second transistor 222-1 and the control terminal i of the third transistor 222-2 are commonly coupled to the input terminal b of the leakage suppression circuit 222, and the input terminal b of the leakage suppression circuit 222 and the control terminal a of the first transistor 221 are commonly coupled to the input terminal p of the programming control circuit 220. In this way, the control terminal f of the second transistor 222-1 can be coupled to the control terminal a of the first transistor 221 through the input terminal b of the leakage suppression circuit 222, and the control terminal i of the third transistor 222-2 can be coupled to the control terminal a of the first transistor 221 through the input terminal b of the leakage suppression circuit 222.

[0056] Since the control terminal f of the second transistor 222-1 is coupled to the control terminal a of the first transistor 221, when the control terminal a of the first transistor 221 receives a programming control signal, the control terminal f of the second transistor 222-1 can also receive the programming control signal and be turned on or off in response to the level of the programming control signal; since the control terminal i of the third transistor 222-2 is coupled to the control terminal a of the first transistor 221, when the control terminal a of the first transistor 221 receives a programming control signal, the control terminal i of the third transistor 222-2 can also receive the programming control signal and be turned off or on in response to the level of the programming control signal.

[0057] Here, the second transistor 222 - 1 and the third transistor 222 - 2 constitute an inverter 222 a .

[0058] For example, the second transistor 222-1 is a PMOS transistor and the third transistor 222-2 is an NMOS transistor. When a programming operation is performed on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a high level, turning the first transistor 221 on. The control terminal f of the second transistor 222-1 receives a programming control signal and sets it to a high level, turning the second transistor 222-1 off. The control terminal i of the third transistor 222-2 receives a programming control signal and sets it to a high level, turning the third transistor 222-2 on. In this way, the first transistor 221 is coupled to the ground terminal via the third transistor 222-2, and the second terminal e of the first transistor 221 is at a low level, i.e., the first voltage level.

[0059] When a read operation is performed on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a low level, and the first transistor 221 is turned off. The control terminal f of the second transistor 222-1 receives a programming control signal and sets it to a low level, and the second transistor 222-1 is turned on. The control terminal i of the third transistor 222-2 receives a programming control signal and sets it to a low level, and the third transistor 222-2 is turned off. In this way, the first transistor 221 can be coupled to the power supply through the second transistor 222-1, and the second terminal e of the first transistor 221 is at a high level, that is, the second voltage level.

[0060] It should be noted that when performing a read operation, the first transistor 221 may generate a leakage current, resulting in charge leakage, thereby reducing the read voltage. Here, by setting the first end g of the second transistor 222-1 to be coupled to the power supply, when performing a read operation, the first transistor 221 can be coupled to the power supply through the second transistor 222-1. The high level VDD provided by the power supply can reduce the current leakage during reading, which is beneficial to reducing the probability of anti-fuse device reading failure or data inversion due to charge leakage during the reading process.

[0061] It should be noted that the present disclosure is described by taking the second transistor 222-1 as a PMOS and the third transistor 222-2 as an NMOS as an example to facilitate communication of the present disclosure to those skilled in the art. In other embodiments, the second transistor 222-1 may be an NMOS and the third transistor may be a PMOS.

[0062] In an embodiment of the present disclosure, an inverter is set in the programming control circuit, the inverter includes a second transistor and a third transistor, and the first end of the second transistor is coupled to the power supply, the second end of the second transistor is coupled to the output end of the inverter, the first end of the third transistor is coupled to the output end of the inverter, and the second end of the third transistor is coupled to the ground end. When performing a programming operation, the first transistor can be coupled to the ground end through the third transistor, and the ground end provides a low level; when performing a reading operation, the first transistor can be coupled to the power supply through the second transistor, and the power supply provides a high level; without affecting the programming operation of the anti-fuse unit, the charge leakage of the anti-fuse unit reading process can be reduced, thereby reducing the probability of anti-fuse device reading failure or data inversion.

[0063] In some embodiments, the first transistor 221 is of the same type as the third transistor 222-2, and the first transistor 221 is of a different type than the second transistor 222-1. For example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. For another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor.

[0064] It is understood that the embodiments of the present disclosure do not impose any particular restrictions on the specific types of the first transistor 221, the second transistor 222-1, and the third transistor 222-2. It is sufficient that the first transistor 221 and the third transistor 222-2 are of the same type, and the first transistor 221 and the second transistor 222-1 are of different types. Those skilled in the art can make appropriate choices based on actual needs. The embodiments of the present disclosure are described using the example of the first transistor 221 and the third transistor 222-2 being N-type transistors and the second transistor 222-1 being a P-type transistor.

[0065] In some embodiments, the size of the first transistor 221 is larger than the size of the second transistor 222 - 1 .

[0066] In some embodiments, the size of the third transistor 222 - 2 is greater than or equal to the size of the second transistor 222 - 1 .

[0067] It should be noted that the sizes of the first transistor 221 and the third transistor 222-2 can be larger. In some embodiments, the size of the third transistor 222-2 can be equal to the size of the second transistor 222-1. In other embodiments, the size of the third transistor 222-2 can be larger than the size of the second transistor 222-1. When performing a programming operation on the anti-fuse unit, the larger sizes of the first transistor 221 and the third transistor 222-2 can increase the on-state current of the first transistor 221 and the third transistor 222-2, thereby further facilitating the operation of the anti-fuse device.

[0068] In some embodiments, reference Figure 3 As shown, the anti-fuse device 200 further includes a comparator 241 ; a first input terminal of the comparator 241 is coupled to the anti-fuse array through a sensing node q, and a second input terminal of the comparator 241 is used to receive a reference voltage.

[0069] Comparator 241 includes a first input terminal and a second input terminal. The first input terminal is coupled to the antifuse array and is configured to receive a read voltage. The second input terminal is configured to receive a reference voltage. Comparator 241 also includes an output terminal. The output voltage at the output terminal can indicate whether the read voltage at the first input terminal is greater than or less than the reference voltage at the second input terminal. For example, when the read voltage at the first input terminal is greater than the reference voltage at the second input terminal, the output voltage can be a positive voltage. When the read voltage at the first input terminal is less than the reference voltage at the second input terminal, the output voltage can be a negative voltage.

[0070] In some embodiments, the comparator 241 may be an operational amplifier for comparing the voltage read from the first input terminal with a reference voltage from the second input terminal. Here, the voltage at the output terminal of the comparator 241 may be used to determine whether the reading is normal.

[0071] In some embodiments, reference Figure 3 As shown, the anti-fuse device 200 includes: a read circuit 240 coupled to the anti-fuse array; wherein the read circuit 240 includes a comparator 241 and other circuit structures not shown, which can be configured by those skilled in the art according to actual needs.

[0072] In some embodiments, the first voltage level is a ground level; and the second voltage level is greater than a reference voltage and less than or equal to a precharge level of the sensing node q.

[0073] In one embodiment, the first voltage level is 0V; and the second voltage level ranges from 0.8V to 1.2V.

[0074] In some embodiments, the antifuse device 200 includes a precharge circuit 230 coupled to the antifuse array. For example, the precharge circuit 230 is coupled to the antifuse array via a sense node q. The precharge circuit 230 can perform a precharge operation on the sense node q in response to a precharge control signal to precharge the sense node q to a precharge level.

[0075] In some embodiments, when a programming operation is performed on the anti-fuse unit, the control terminal a of the first transistor 221 is at a third voltage level; wherein the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

[0076] In one example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and is set to a high level. The second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V. The first voltage level is lower than the high level received by the control terminal a of the first transistor 221. It will be understood that in this example, the third voltage level is a high level.

[0077] In another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and is set to a low level. The second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V. The first voltage level is lower than the low level received by the control terminal a of the first transistor 221. It will be understood that in this example, the third voltage level is a low level.

[0078] It should be noted that the second voltage level is less than or equal to the precharge level of the sensing node. Therefore, when performing a programming operation on the anti-fuse unit, the third voltage level applied to the control terminal of the first transistor is greater than the second voltage level.

[0079] Figure 4 Schematic diagram of the read voltage of an antifuse device according to an embodiment of the present disclosure. L2 represents the sensed read voltage when the programming control circuit includes a leakage suppression circuit in the embodiment of the present disclosure; L1 represents the sensed read voltage when the programming control circuit does not include a leakage suppression circuit.

[0080] Reference Figure 4 As shown, during the T1 to T2 phase (i.e., the sensing phase), when the programming control circuit does not include a leakage suppression circuit, the read voltage decreases over time and falls below the fault sensing point A, potentially leading to read failure or data inversion in the antifuse unit. When the programming control circuit includes a leakage suppression circuit, although the read voltage decreases over time, it remains greater than the reference voltage, i.e., above the fault sensing point. It can be understood that the programming control circuit including the leakage suppression circuit provided in the embodiments of the present disclosure can reduce charge leakage caused by leakage of the first transistor, thereby reducing the probability of read failure or data inversion in the antifuse device.

[0081] Figure 5 FIG. 1 is a circuit diagram of another anti-fuse device according to an embodiment of the present disclosure. Figure 5 As shown, Figure 5 The first transistor 321, the precharge circuit 330 and the read circuit 340 shown in FIG. Figure 3 The first transistor 221, the precharge circuit 230 and the read circuit 240 shown in FIG are similar and will not be described in detail here. Figure 3 The structure shown is different in that Figure 5 The leakage suppression circuit 322 includes at least two inverters; wherein, at least two inverters are connected in parallel. Figure 5 As shown, the leakage suppression circuit 322 includes an inverter 322a, an inverter 322b and an inverter 322c. It should be noted that the number of inverters in the leakage suppression circuit 322 is not limited to Figure 5 The 3 shown can also be 2, 4 or more.

[0082] Reference Figure 5 As shown, the leakage suppression circuit 322 includes an inverter 322a, an inverter 322b, and an inverter 322c. Inverter 322a includes an input terminal b and an output terminal c, inverter 322b includes an input terminal m and an output terminal n, and inverter 322c includes an input terminal u and an output terminal v. The input terminal b of inverter 322a, the input terminal m of inverter 322b, and the input terminal u of inverter 322c are all coupled to the control terminal a of the first transistor 321, and the output terminal c of inverter 322a, the output terminal n of inverter 322b, and the output terminal v of inverter 322c are all coupled to the second terminal e of the first transistor 321.

[0083] In the embodiment of the present disclosure, by setting a plurality of inverters connected in parallel in the leakage suppression circuit, when performing a programming operation on the anti-fuse unit, the conduction current of the first transistor is larger, and when performing a reading operation on the anti-fuse unit, the level of the output end of the leakage suppression circuit is higher, which can further reduce the leakage of the first transistor and is more conducive to reducing the probability of reading failure or data reversal of the anti-fuse device.

[0084] Based on the above anti-fuse device, an embodiment of the present disclosure further provides an operating method of the anti-fuse device.

[0085] Figure 6 The flowchart of the operation method of an anti-fuse device according to an embodiment of the present disclosure is shown. The anti-fuse array includes a plurality of anti-fuse units. Figure 6 As shown, the operation method includes at least the following steps:

[0086] S401: When performing a programming operation on the anti-fuse unit, turning on a first transistor and making the output terminal of the leakage suppression circuit at a first voltage level; wherein a first terminal of the first transistor is coupled to the anti-fuse array via a sensing node, a second terminal of the first transistor is coupled to the output terminal of the leakage suppression circuit, and a control terminal of the first transistor is coupled to the input terminal of the leakage suppression circuit;

[0087] S402 : When performing a read operation on the anti-fuse unit, turning off the first transistor and setting the output terminal of the leakage suppression circuit to a second voltage level; wherein the second voltage level is greater than the first voltage level.

[0088] Combine Figure 1 and Figure 3 As shown, the antifuse array 110 includes a plurality of antifuse units. Each antifuse unit is composed of a programming transistor and a selection transistor. The plurality of antifuse units are arranged in an array along row and column directions.

[0089] In step S401, when a programming operation is performed on the anti-fuse unit, the control terminal of the first transistor receives a programming control signal set to a high level, the first transistor is turned on, the input terminal of the leakage suppression circuit receives a programming control signal set to a high level, and outputs a low level, that is, a first voltage level.

[0090] In step S402, when a read operation is performed on the anti-fuse cell, the control terminal of the first transistor receives the programming control signal and is set to a low level, turning off the first transistor. The input terminal of the leakage suppression circuit receives the programming control signal and is set to a low level, and outputs a high level, i.e., a second voltage level. Because the output terminal c of the leakage suppression circuit 222 is coupled to the second terminal e of the first transistor 221, the second terminal e of the first transistor 221 is in a high state during the read operation, thereby reducing charge leakage during the read operation.

[0091] In the embodiment of the present disclosure, when performing a programming operation on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when performing a read operation on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; since the second voltage level is greater than the first voltage level, when performing a read operation on the anti-fuse unit, the high level of the output end of the leakage suppression circuit can reduce the leakage of the first transistor, which is beneficial to reducing the probability of reading failure or data inversion of the anti-fuse device.

[0092] In some embodiments, the leakage suppression circuit includes at least one inverter, and the above step S401 includes: when performing a programming operation, turning off the second transistor and turning on the third transistor; wherein, the inverter includes a second transistor and a third transistor, the first end of the third transistor is coupled to the output end of the inverter, the second end of the third transistor is coupled to the ground end, the control end of the third transistor is coupled to the control end of the first transistor, and the ground end is used to provide a first voltage level.

[0093] Combine Figure 3 As shown, when the anti-fuse unit performs a programming operation, the control terminal a of the first transistor 221 receives the programming control signal and is set to a high level, the first transistor 221 is turned on, the control terminal f of the second transistor 222-1 receives the programming control signal and is set to a high level, the second transistor 222-1 is turned off, and the control terminal i of the third transistor 222-2 receives the programming control signal and is set to a high level, the third transistor 222-2 is turned on, so that the first transistor 221 can be coupled to the ground terminal through the third transistor 222-2, and the second terminal e of the first transistor 221 is at a low level, that is, the first voltage level.

[0094] In some embodiments, the above step S402 includes: when performing a read operation, turning on the second transistor and turning off the third transistor; wherein the first end of the second transistor is coupled to the power supply, the second end of the second transistor is coupled to the output end of the inverter, the control end of the second transistor is coupled to the control end of the first transistor, and the power supply is used to provide a second voltage level.

[0095] Combine Figure 3 As shown, when the anti-fuse unit performs a read operation, the control terminal a of the first transistor 221 receives the programming control signal and is set to a low level, and the first transistor 221 is turned off. The control terminal f of the second transistor 222-1 receives the programming control signal and is set to a low level, and the second transistor 222-1 is turned on. The control terminal i of the third transistor 222-2 receives the programming control signal and is set to a low level, and the third transistor 222-2 is turned off. In this way, the first transistor 221 can be coupled to the power supply through the second transistor 222-1, and the second terminal e of the first transistor 221 is at a high level, that is, the second voltage level.

[0096] It should be noted that when performing a read operation, the first transistor 221 may generate a leakage current, resulting in charge leakage, thereby reducing the read voltage. Here, by setting the first end g of the second transistor 222-1 to be coupled to the power supply, when performing a read operation, the first transistor 221 can be coupled to the power supply through the second transistor 222-1. The high level VDD provided by the power supply can reduce the current leakage during reading, which is beneficial to reducing the probability of anti-fuse device reading failure or data inversion due to charge leakage during the reading process.

[0097] In some embodiments, the type of the first transistor is the same as the type of the third transistor, and the type of the first transistor is different from the type of the second transistor. For example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. For another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor.

[0098] In some embodiments, the above-mentioned turning off the second transistor and turning on the third transistor when performing a programming operation includes: applying a third voltage level to the control end of the first transistor when performing a programming operation; wherein the control end of the second transistor is coupled to the control end of the first transistor, and the control end of the third transistor is coupled to the control end of the first transistor; the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

[0099] Combine Figure 3 As shown, in one example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and is set to a high level. The second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V. The first voltage level is lower than the high level received by the control terminal a of the first transistor 221. It can be understood that in this example, the third voltage level is a high level.

[0100] In another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and is set to a low level. The second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V. The first voltage level is lower than the low level received by the control terminal a of the first transistor 221. It will be understood that in this example, the third voltage level is a low level.

[0101] It should be noted that the second voltage level is less than or equal to the precharge level of the sensing node. Therefore, when performing a programming operation on the anti-fuse unit, the third voltage level applied to the control terminal of the first transistor is greater than the second voltage level.

[0102] In some embodiments, the above operation method further includes: sensing the read voltage of the anti-fuse unit when performing a read operation. For example, when performing a read operation, using Figure 3 The read circuit shown senses a read voltage of the antifuse cell.

[0103] Based on the above anti-fuse device, an embodiment of the present disclosure further provides a memory, which includes the anti-fuse device as in any of the above embodiments.

[0104] In the embodiments of the present disclosure, the memory may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), and a double data rate synchronous dynamic random access memory (DDR SDRAM); or it may be a non-volatile memory, such as a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM).

[0105] Antifuse devices, as one-time programmable devices, can be used in memories such as DRAM, offering the distinct advantages of small size and simple processing. For example, they can be used in DRAM to store the address information of defective memory cells, enabling redundant replacement (row and column replacement). Antifuse devices can also be programmed to precisely adjust various parameters within the DRAM memory, such as voltage, current, or frequency.

[0106] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.< / n> < / n>

Claims

1. An anti-fuse device, characterized in that: include: An antifuse array comprises: a plurality of antifuse units; A programming control circuit is coupled to the anti-fuse array through a sensing node, and includes: a first transistor and a leakage suppression circuit, wherein the first end of the first transistor is coupled to the sensing node, the input end of the leakage suppression circuit is coupled to the control end of the first transistor, and the output end of the leakage suppression circuit is coupled to the second end of the first transistor; wherein, when a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; and the second voltage level is greater than the first voltage level.

2. The anti-fuse device according to claim 1, wherein: The leakage suppression circuit includes at least one inverter; the inverter includes: a second transistor, wherein a first terminal of the second transistor is coupled to a power supply, a second terminal of the second transistor is coupled to the output terminal of the inverter, and a control terminal of the second transistor is coupled to the control terminal of the first transistor; wherein the power supply is configured to provide the second voltage level; a third transistor, wherein a first terminal of the third transistor is coupled to the output terminal of the inverter, a second terminal of the third transistor is coupled to the ground terminal, and a control terminal of the third transistor is coupled to the control terminal of the first transistor; wherein the ground terminal is used to provide the first voltage level.

3. The anti-fuse device according to claim 2, wherein: The leakage suppression circuit includes a plurality of inverters; wherein the plurality of inverters are connected in parallel.

4. The anti-fuse device according to claim 2, wherein: The type of the first transistor is the same as that of the third transistor, and the type of the first transistor is different from that of the second transistor.

5. The anti-fuse device according to claim 2, wherein: The size of the first transistor is larger than that of the second transistor.

6. The anti-fuse device according to claim 2, wherein: The size of the third transistor is greater than or equal to the size of the second transistor.

7. The anti-fuse device according to claim 1, wherein: The antifuse device further includes: A comparator; wherein a first input terminal of the comparator is coupled to the antifuse array through the sensing node, and a second input terminal of the comparator is used to receive a reference voltage.

8. The anti-fuse device according to claim 7, wherein: The first voltage level is a ground level; The second voltage level is greater than the reference voltage and less than or equal to a precharge level of the sensing node.

9. The anti-fuse device according to claim 1, wherein: When the programming operation is performed on the anti-fuse unit, the control terminal of the first transistor is at a third voltage level; wherein the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

10. A memory, characterized in that: The anti-fuse device comprises the anti-fuse device according to any one of claims 1 to 9.

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