Mask, manufacturing method thereof and manufacturing method of Josephson junction

Abstract

The invention discloses a mask and a manufacturing method thereof, and a manufacturing method of a Josephson junction, and belongs to the technical field of integrated circuits. The mask comprises a photoresist layer which is formed on a substrate and is provided with a pattern window used for exposing the substrate; and the material deposition layer is formed on the surface, far away from the substrate, of the photoresist layer and the inner wall of the pattern window, and the material deposition layer is used for reducing the pattern window into a target pattern window with a target line width. According to the invention, the target pattern window with smaller line width is obtained based on the pattern window formed on the photoresist layer and the material deposition layer formed on the inner wall of the pattern window; the target pattern window is used for implementing subsequent processing such as an etching process, a deposition process and an ion implantation process to obtain a circuit element with the characteristic size smaller than the window size of the photoresist layer, so that the mask is low in degree of dependence on the precision of exposure equipment, is less limited by the exposure equipment and is wider in application range.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, especially the field of photolithography technology, and in particular, the present application relates to a mask and a manufacturing method thereof and a manufacturing method of a Josephson junction. Background Art

[0002] The manufacture of superconducting quantum circuits is inseparable from a mask with a graphic window, which appears as a specific pattern on a plane. For example, in the photolithography process, photoresist is usually used as a mask, and then a pattern of a specific shape and line width is obtained through exposure and development, and then etching, deposition, doping, etc. are carried out based on the pattern. The accuracy of the line width is limited by the exposure equipment and determines many characteristics of the components formed by etching, deposition, and doping.

[0003] With the development of microelectronics technology, integrated circuits are developing towards high integration. Following Moore's Law, the critical dimension is shrinking year by year, from micron-level technology to submicron, deep submicron and even nanometer-level technology. The improvement of integration has driven the continuous reform of semiconductor manufacturing equipment, and the lithography technology has developed from G-line, I-line, deep ultraviolet to immersion lithography technology. The higher-end lithography machines can achieve smaller feature sizes, but the replacement of lithography equipment is the main factor in the increase in chip manufacturing plant costs. Therefore, the application of photoresist-based masks is severely limited by the accuracy of exposure equipment, and lower-end reporting equipment cannot achieve feature sizes with small line widths. At present, it is urgent to propose a mask structure that is less dependent on exposure accuracy. Invention content

[0004] The purpose of the present application is to provide a mask and a method for manufacturing the same, and a method for manufacturing a Josephson junction, so as to overcome the dependence on high-precision exposure equipment.

[0005] An embodiment of the present application provides a mask, comprising: a photoresist layer formed on a substrate and having a graphic window formed on the photoresist layer for exposing the substrate; and a material deposition layer formed on a surface of the photoresist layer facing away from the substrate and an inner wall of the graphic window, for reducing the graphic window to a target graphic window with a target line width.

[0006] As for the mask as described above, in some embodiments, the material deposition layer is formed in a partial area of ​​the inner wall.

[0007] As for the mask as described above, in some embodiments, the photoresist layer includes a first photoresist layer formed on a substrate, and a second photoresist layer formed on the first photoresist layer, and the graphic window penetrates the second photoresist layer and the first photoresist layer.

[0008] In the mask as described above, in some embodiments, the graphic window is an undercut structure.

[0009] As for the mask described above, in some embodiments, the material deposition layer is formed on the first photoresist layer in the window.

[0010] Another embodiment of the present application provides a method for manufacturing a mask, comprising: forming a photoresist layer on a substrate; forming a graphic window for exposing the substrate in the photoresist layer, and forming a material deposition layer on a surface of the photoresist layer facing away from the substrate and an inner wall of the graphic window to reduce the graphic window to a target graphic window with a target line width.

[0011] In the method as described above, in some implementations, the photoresist layer includes a first photoresist layer located on the substrate and a second photoresist layer located on the first photoresist layer.

[0012] In the method described above, in some embodiments, the graphic window is an undercut structure.

[0013] In the method as described above, in some implementations, the inner wall of the graphic window is on the first photoresist layer located in the graphic window.

[0014] Another embodiment of the present application provides a method for manufacturing a Josephson junction, comprising: forming a mask on a substrate according to the method described above, or manufacturing the mask described above on the substrate; and forming a first superconducting layer on the substrate using the target pattern window, and partially oxidizing the first superconducting layer to form a barrier layer, and forming a second superconducting layer with at least a portion of the second superconducting layer located on the barrier layer.

[0015] The mask provided in the present application includes a photoresist layer with a graphic window formed thereon, and a material deposition layer formed on a surface of the photoresist layer away from the substrate and an inner wall of the graphic window. A desired line width is obtained based on the graphic window and the material deposition layer. Therefore, the mask structure has a low degree of dependence on the accuracy of the lithography exposure equipment and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of a mask provided in one embodiment of the present application;

[0017] FIG. 2A to FIG. 2C A schematic diagram of a method for manufacturing a mask provided in one embodiment of the present application;

[0018] Figure 3 A schematic diagram of a method for manufacturing a Josephson junction provided in accordance with an embodiment of the present application.

[0019] Description of reference numerals:

[0020] 1-Substrate

[0021] 2-photoresist layer, 21-first photoresist layer, 22-second photoresist layer;

[0022] 3 – Graphics window, 31 – First window, 32 – Second window;

[0023] 4 - Material deposition layer, 5 - Target graphic window, 6 - Josephson junction. DETAILED DESCRIPTION

[0024] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0025] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatuses.

[0026] In addition, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can also be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can also be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0027] In addition, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can also be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can also be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0028] In the integrated circuit manufacturing process, the manufacture of integrated circuit devices requires hundreds of processes. Pattern transfer technology uses masks to prepare circuits with specific patterns on substrates. Photolithography is a major method of pattern transfer technology and plays a vital role in the integrated circuit process.

[0029] The photolithography process forms a photoresist on the surface of the wafer substrate, and the photoresist is exposed and developed to form a graphic window. The surface of the wafer substrate is subsequently processed according to the graphic window. The subsequent processing can be to image the pattern on the mask on the wafer substrate through an etching step, or to complete the optional doping of the graphic area of ​​the wafer substrate by an ion implantation step. The graphic windows of various shapes and line widths in the photoresist layer determine many features of the final integrated circuit device, such as: through holes, necessary interconnection lines between layers, and silicon doped areas. Among them, etching is used to etch away the thin film material on the surface of the wafer substrate without photoresist protection to realize the patterned circuit. Specifically, a dry etching process or a wet etching process can be selected. The graphic structure formed by etching includes grooves and / or etching holes. It can be understood that the accuracy of the line width of the graphic window is limited by the accuracy of the exposure equipment, and this accuracy determines many features of the integrated circuit device. Small feature sizes need to be realized by high-end photolithography equipment (for example, an exposure machine with an exposure accuracy of several nanometers), but the replacement of photolithography equipment is the main factor in the increase in the cost of chip manufacturing plants. Therefore, the application of photoresist-based masks is restricted by the accuracy of photolithography equipment (specifically, the accuracy of exposure). At present, it is urgent to propose a mask structure that is less dependent on the exposure accuracy.

[0030] Based on the above description, the photolithography process is to dissolve some areas on the photoresist through steps such as exposure, development, fixing, and hardening, and form a graphic window with the same pattern as the layout on the photoresist mask for subsequent steps. With the expansion of the scale of components, it is inevitable to reduce the feature size, and related processes that rely on photoresist masks are often difficult to apply because the exposure equipment cannot be upgraded, which affects the preparation of circuit components and further affects the performance of integrated circuits.

[0031] To this end, the present application proposes a mask and a method for manufacturing the same, as well as a method for manufacturing a Josephson junction, which obtains the desired line width based on a graphic window formed in a photoresist layer and a material deposition layer on the inner wall of the graphic window. Therefore, the mask structure has a lower degree of dependence on the accuracy of the photolithography exposure equipment, and has a wider range of applications.

[0032] Figure 1 A schematic diagram of the structure of a mask provided in accordance with an embodiment of the present application.

[0033] FIG. 2A to FIG. 2CA schematic diagram of a method for manufacturing a mask provided in accordance with an embodiment of the present application.

[0034] Figure 3 A schematic diagram of a method for manufacturing a Josephson junction provided in accordance with an embodiment of the present application.

[0035] Combination Figure 1 , FIG. 2A to FIG. 2C and Figure 3 As shown, a mask provided in an embodiment of the present application includes: a photoresist layer 2, formed on a substrate 1 and having a graphic window 3 for exposing the substrate 1. Specifically, the photoresist layer 2 can be formed by coating the surface of the substrate 1 with photoresist through a spin coating process. The photoresist has good performance in film forming properties, imprinting properties (such as hardness and viscosity, curing speed, interface properties, etc.), and corrosion resistance. In a specific implementation, the photoresist can be a positive photoresist; and a material deposition layer 4, formed on the surface of the photoresist layer 2 that deviates from (i.e., is relatively far away from) the substrate 1 and the inner wall of the graphic window 3, and the material deposition layer 4 is used to reduce the graphic window 3 to a target graphic window 5 with a target line width. The embodiment of the present application is based on a graphic window 3 formed in a photoresist layer 2 and a material deposition layer 4 formed on the inner wall of the graphic window 3, so as to obtain a target graphic window 5 with a smaller line width. By using the target graphic window 5 to implement subsequent processing such as etching process, deposition process, ion implantation process, etc., a circuit element with a characteristic size smaller than the graphic window size of the photoresist layer 2 (i.e., higher precision) can be obtained. Therefore, the mask structure of the present application is less dependent on the precision of the photolithography exposure equipment. Therefore, it is less restricted by the photolithography exposure equipment and the application range of the mask structure is wider.

[0036] The deposition process includes, but is not limited to, electron beam evaporation (EBM), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, etc. Through the deposition processes listed above, materials can be deposited on the substrate surface exposed in the target graphic window 5.

[0037] The etching process includes a dry etching process and a wet etching process, wherein the dry etching process includes but is not limited to: ion milling etching, plasma etching, reactive ion etching, laser ablation and the like. Through the etching processes listed above, the substrate 1 and related device structures can be etched, and the exposed area of ​​the target graphic window 5 is etched, and the unexposed area is not etched. After the etching is completed, a structure that is relatively consistent with the shape and characteristic size of the target graphic window 5 is obtained.

[0038] In order to reduce or even avoid the adhesion of the material deposition layer 4 to the substrate 1, and to facilitate the removal of the mask after subsequent processing of the substrate 1 according to the target graphic window 5, during the specific implementation of the embodiment of the present application, the material deposition layer 4 is formed on a partial area of ​​the inner wall. Specifically, the partial area is close to the surface of the photoresist layer 2 away from the substrate 1, that is, the upper surface as shown in the figure.

[0039] In some embodiments, the photoresist layer 2 includes a first photoresist layer 21 formed on the substrate 1, and a second photoresist layer 22 formed on the first photoresist layer 21. The graphic window 3 penetrates the second photoresist layer 22 and the first photoresist layer 21. The graphic window 3 is constrained by both a first window 31 formed in the first photoresist layer 21 and a second window 32 formed on the second photoresist layer 22. In specific implementations, in order to facilitate the formation of the material deposition layer 4 in a partial area of ​​the inner wall, in some implementation examples, the graphic window 3 is an undercut structure (UnderCut structure), combined with Figure 1 and Figure 2B As shown, when the undercut structure is formed, the first window 31 is larger than the second window 32, that is, the second photoresist layer 22 is formed with an overhanging portion on the first photoresist layer 21. This form of undercut structure helps to distinguish the portion on the inner wall that needs to be deposited from the portion that does not need to be deposited when the material is deposited, thereby realizing the formation of the material deposition layer 4 on the first photoresist layer 21 in the graphic window 3.

[0040] Reference FIG. 2A to FIG. 2C , and combined with Figure 1 and Figure 3 As shown, another embodiment of the present application provides a method for manufacturing a mask, comprising: Figure 2A As shown, a photoresist layer 2 is formed on a substrate 1; Figure 2B As shown, a pattern window 3 for exposing the substrate 1 is formed in the photoresist layer 2, and a material is deposited on the surface of the photoresist layer 2 facing away from the substrate 1 and the inner wall of the pattern window 3 (for example, respectively according to Figure 2C Deposition is performed in two deposition directions as shown) to form a material deposition layer 4 to reduce the graphic window 3 to a target graphic window 5 with a target line width. Based on the solution provided by the present application, a graphic window 3 with a larger line width can be first formed on the photoresist layer 2 using a device with a lower line width accuracy such as a stepper exposure machine, and then a material can be deposited on the inner wall of the graphic window 3 to form a material deposition layer 4 to reduce the graphic window 3 to obtain a target graphic window 5 with a desired line width requirement. The obtained target graphic window 5 can achieve an exposure accuracy that cannot be achieved by current photolithography machines, thereby achieving the purpose of improving the patterning accuracy and reducing the line width.

[0041] Ion beam gas-assisted deposition is a method that uses a gas phase reaction activated by a finely controlled electron beam or focused ion beam to deposit the desired material deposition layer 4. It can deposit both dielectric and conductive masking materials, depending on the different precursor gases and applications. During the deposition process, the gas is introduced into a position close to the ion beam or electron beam, and the material deposition layer 4 is prepared with high reproducibility through appropriate gas flow control, electron beam or focused ion beam energy and diameter selection.

[0042] In some embodiments, the photoresist layer 2 includes a first photoresist layer 21 located on the substrate 1 and a second photoresist layer 22 located on the first photoresist layer 21. The different solubility of the double-layer photoresist in the same developer can be used to make the graphic window present an undercut structure. In some examples, the inner wall of the graphic window 3 is located on the first photoresist layer 21 in the graphic window 3.

[0043] Reference Figure 3 , and combined with Figure 1 and FIG. 2A to FIG. 2C As shown, another embodiment of the present application provides a method for manufacturing a Josephson junction, comprising: forming a mask on the substrate 1 according to the mask manufacturing method as described above, or manufacturing the mask as described above on the substrate; then, forming a first superconducting layer on the substrate 1 using the target graphic window 5, and partially oxidizing the first superconducting layer to form a barrier layer, and then forming a second superconducting layer using the target graphic window, and at least a portion of the second superconducting layer is located on the barrier layer, so as to form a three-layer structure of superconducting-barrier-superconducting (S-I-S), and the three-layer structure is the Josephson junction 6.

[0044] The line width of the Josephson junction 6 is relatively small, usually at the level of hundreds of nanometers, and a relatively advanced stepper exposure machine is usually required to form a mask with a corresponding line width. Based on the solution provided by the present application, a graphic window with a relatively large line width can be first formed on the photoresist layer using a device with a relatively low line width accuracy such as a stepper exposure machine, and then a material deposition layer 4 can be formed on the inner wall of the graphic window to reduce the graphic window to meet the desired line width requirement, thereby achieving exposure accuracy that cannot be achieved by current photolithography machines.

[0045] The applicant found that high-end lithography machines can meet the needs of small line width graphics, but the high price of high-end lithography machines increases the manufacturing cost. Therefore, the applicant proposed a mask and a manufacturing method thereof and a manufacturing method of a Josephson junction, which reduces the line width of the pattern window of the mask by adopting a line width trimming step, so as to realize the use of low-end lithography machines to manufacture integrated circuits with small line widths, which can meet the process requirements and do not need to introduce new lithography machine technology, thereby reducing manufacturing costs.

[0046] In a specific embodiment of the above-mentioned method for manufacturing a Josephson junction, a mask is formed on the substrate 1 according to the mask manufacturing method as described above, or when the mask as described above is formed on the substrate, two target pattern windows (referred to as the first target pattern window and the second target pattern window) are formed on the mask, and the first target pattern window and the second target pattern window are partially crossed (exemplarily, the two can be vertically crossed), so that the first superconducting layer in the subsequent step can be formed on the substrate surface exposed by the first target pattern window by an oblique evaporation process, and after partially oxidizing the first superconducting layer to form a barrier layer, an oblique evaporation process is performed using the second pattern window to form a second superconducting layer on the substrate surface exposed by the second target pattern window, so that a three-layer structure of superconductor-barrier-superconductor (S-I-S) can be formed in the aforementioned partially crossed area as a Josephson junction 6.

[0047] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.

Claims

1. A mask, characterized in that: include: A photoresist layer is formed on the substrate and the photoresist layer is formed with a pattern window for exposing the substrate; as well as, A material deposition layer is formed on the surface of the photoresist layer away from the substrate and the inner wall of the graphic window, and is used to reduce the graphic window to a target graphic window with a target line width.

2. The mask according to claim 1, characterized in that The material deposition layer is formed on a partial area of ​​the inner wall.

3. The mask according to claim 1, characterized in that: The photoresist layer includes a first photoresist layer formed on a substrate and a second photoresist layer formed on the first photoresist layer, and the pattern window penetrates the second photoresist layer and the first photoresist layer.

4. The mask according to claim 3, characterized in that: The graphic window is an undercut structure.

5. The mask according to claim 3 or 4, characterized in that: The material deposition layer is formed on the first photoresist layer within the pattern window.

6. A method for manufacturing a mask, characterized in that: include: forming a photoresist layer on a substrate; A pattern window for exposing the substrate is formed in the photoresist layer, and a material deposition layer is formed on the surface of the photoresist layer away from the substrate and the inner wall of the pattern window to reduce the pattern window to a target pattern window with a target line width.

7. The method according to claim 6, characterized in that The photoresist layer includes a first photoresist layer located on the substrate and a second photoresist layer located on the first photoresist layer.

8. The method according to claim 7, characterized in that The graphic window is an undercut structure.

9. The method according to claim 7, characterized in that: The inner wall of the graphic window is on the first photoresist layer in the graphic window.

10. A method for manufacturing a Josephson junction, characterized in that: include: Forming a mask on the substrate according to the method of any one of claims 1 to 5, or manufacturing the mask of any one of claims 6 to 9 on the substrate; as well as, A first superconducting layer is formed on the substrate by using the target pattern window, and the first superconducting layer is partially oxidized to form a barrier layer, and a second superconducting layer is formed at least partially on the barrier layer.

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