Semiconductor processing machine

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor processing machine table which comprises at least one process assembly which comprises a conveying cavity and a plurality of functional cavities. A plurality of stations are formed on at least one adjacent side of the conveying cavity, and the functional cavities are formed in the stations; one functional cavity is provided with a reaction processing unit, and the other functional cavity is provided with a measuring unit; the control unit is in communication connection with the conveying mechanism, controls the reaction processing unit and the measuring unit and is used for automatically iteratively executing each round of technological process, and each round of technological process comprises the steps that wafers are conveyed among the functional cavities through the conveying mechanism so as to complete wafer processing and wafer measurement before and after processing, processing result parameters are obtained according to comparison of the physical parameters of the wafer before processing and the physical parameters of the wafer after processing, and technological parameters of the target debugging reaction processing unit are obtained based on optimization of the processing result parameters. Processing, measuring and debugging processes can be automatically and circularly completed on one semiconductor processing machine table, and the working efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor processing machine. Background Art

[0002] An important part of the semiconductor manufacturing process is to etch a groove or through hole of a specific shape and depth on the wafer after masking. The development of etching equipment or etching process requires continuous adjustment of equipment parameters and process parameters. The traditional approach is to initially build equipment parameters and process parameters based on the experience of engineers, and then remove the wafer from the semiconductor processing machine for measurement after each etching by the semiconductor processing machine. According to the measurement results, the equipment or process is debugged and corrected, and then the above "etch-remove-measure-debug-remove" process is repeated until the optimal process parameters are debugged.

[0003] However, in the above process, the wafer needs to be repeatedly moved in and out of the machine, which makes the efficiency of the entire process very low. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present disclosure is to provide a semiconductor processing machine to solve the problems in the related art.

[0005] The first aspect of the present disclosure provides a semiconductor processing machine, comprising: at least one process component, the process component comprising: a transfer chamber and a plurality of functional chambers; the transfer chamber is provided with a transfer mechanism for transferring wafers; at least one side adjacent to the transfer chamber forms a plurality of workstations; the plurality of functional chambers are provided at the plurality of workstations; one of the functional chambers is at least provided with a reaction processing unit for processing wafers, and another of the functional chambers is at least provided with a measurement unit for measuring wafers before and after processing to obtain physical parameters of the wafers before and after processing; a control unit is communicatively connected and controls the transfer mechanism, the reaction processing unit and the measurement unit, and is used to automatically iterate and execute each round of process flow, wherein each round of the process flow comprises: transferring wafers between the plurality of functional chambers through the transfer mechanism to complete wafer processing and wafer measurement before and after processing, and obtaining processing result parameters according to changes between the physical parameters of the wafers before and after processing, and debugging the process parameters of the reaction processing unit based on the optimization of the processing result parameters.

[0006] In an embodiment of the first aspect, the semiconductor processing machine further includes: a wafer supply container and a wafer recovery container, which are arranged at the plurality of workstations; the wafer supply container transports the wafers to be processed to the transfer chamber; and the wafer recovery container is for recovering wafers.

[0007] In an embodiment of the first aspect, the transfer chamber and the plurality of functional chambers are provided in multiple groups and are stacked in multiple layers; at least one process component is provided in each layer.

[0008] In an embodiment of the first aspect, a wafer supply container and / or a wafer recovery container located at one of the workstations is provided with a lifting and transporting mechanism for transporting wafers between multiple process components; and / or, the transfer chambers in the multiple layers are independent of each other, or share the same transfer chamber.

[0009] In an embodiment of the first aspect, the control unit is configured with a process parameter prediction model; the process parameter prediction model inputs the processing result parameters and predicts the target process parameters of the reaction processing unit; the process parameters of the reaction processing unit are debugged based on the optimization of the processing result parameters, including: in response to the processing result parameters not reaching a preset threshold or the optimization of the processing result parameters tends to saturation, inputting the processing result parameters into the process parameter prediction model to predict the target process parameters, and setting the target process parameters for the reaction processing unit.

[0010] In an embodiment of the first aspect, the process parameters include at least one of the following: the RF power of the induction coil; the power ratio between multiple sub-coils of the induction coil; the gas volume; the gas type; the functional chamber temperature; the wafer carrier temperature of the wafer; the voltage when the wafer carrier is an electrostatic chuck; the distance between the wafer and the electrostatic chuck; and / or, the wafer processing includes etching, and the processing result parameters include at least one of the following: the etching speed of each point on the wafer; the etching uniformity value; the ratio of the mask etching speed to the wafer material etching speed; verticality; aspect ratio.

[0011] In an embodiment of the first aspect, the transfer chamber and the functional chamber are vacuum environments.

[0012] In an embodiment of the first aspect, the plurality of workstations are arranged around the outer circumference of the functional cavity.

[0013] In an embodiment of the first aspect, the functional chamber equipped with the reaction processing unit is provided with a chamber door for isolating or connecting with the transfer chamber.

[0014] In an embodiment of the first aspect, the plurality of workstations further include vacant spare workstations for setting up other functional cavities, and the other functional cavities include at least one of the following: repair; degumming; temperature adjustment.

[0015] As described above, the present disclosure relates to the field of semiconductor technology, and provides a semiconductor processing machine, including: at least one process component, the process component including: a transfer chamber and a plurality of functional chambers; the transfer chamber is provided with a transfer mechanism for transferring wafers; at least one side adjacent to the transfer chamber forms a plurality of workstations; the plurality of functional chambers are provided at the plurality of workstations; one of the functional chambers is at least provided with a reaction processing unit for processing wafers, and another of the functional chambers is at least provided with a measurement unit for measuring wafers before and after processing to obtain physical parameters of the wafers before and after processing; a control unit, which is communicatively connected and controls the transfer mechanism, the reaction processing unit and the measurement unit, and is used to automatically iterate and execute each round of process flow, wherein each round of the process flow includes: transferring wafers between the plurality of functional chambers through the transfer mechanism to complete wafer processing and wafer measurement before and after processing, and obtaining processing result parameters according to changes between the physical parameters of the wafers before and after processing, and debugging the process parameters of the reaction processing unit based on the optimization of the processing result parameters. As a result, the cycle of processing, measuring, and debugging can be automatically completed on a semiconductor processing machine, effectively improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the planar structure of a semiconductor processing machine in an embodiment of the present disclosure is shown.

[0017] Figure 2 A schematic diagram showing the process flow in an embodiment of the present disclosure.

[0018] Figure 3 A schematic diagram showing the application of the process parameter prediction model in the embodiment of the present disclosure.

[0019] Figure 4 A schematic diagram showing a process flow in another embodiment of the present disclosure.

[0020] Figure 5 A schematic side view of the structure of a semiconductor processing machine having multi-layer stacked process components according to an embodiment of the present disclosure is shown.

[0021] Figure 6 A schematic side view of the structure of a semiconductor processing machine having multi-layer stacked process components according to another embodiment of the present disclosure is shown.

[0022] Figure 7 A schematic diagram showing a process flow executed by a semiconductor processing machine in a preferred embodiment of the present disclosure.

[0023] Figure 8 A schematic diagram showing the structure of a computer device in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0025] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0026] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0028] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0029] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0030] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0031] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0032] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0033] In related technologies, the development of etching equipment or etching process requires continuous adjustment of equipment parameters and process parameters. The traditional approach is to initially build equipment parameters and process parameters based on engineer experience, and then remove the wafer from the semiconductor processing machine for measurement after each etching by the semiconductor processing machine. According to the measurement results, the equipment or process is debugged and corrected, and the above "etching-moving-measurement-debugging-moving back" process is repeated until the optimal process parameters are debugged. In the above process, the need to repeatedly move the wafer will lead to very low efficiency of the entire process.

[0034] In view of this, a semiconductor processing machine is provided in the embodiment of the present disclosure, by forming a configurable transfer chamber in the semiconductor processing machine to cooperate with a functional chamber of multiple workstations, so that a cyclic process flow (i.e., processing, measurement and debugging) can be automatically completed in one semiconductor processing machine. It should be particularly noted that the processing can be an etching process or other processes, such as deposition, etc., and is not limited to etching.

[0035] like Figure 1 , which shows a schematic diagram of the planar structure of a semiconductor processing machine in an embodiment of the present disclosure.

[0036] exist Figure 1 In FIG. 1 , the semiconductor processing tool 100 includes at least one process component 110 . The process component 110 includes a transfer chamber 111 and a plurality of functional chambers 112 .

[0037] The transfer chamber 111 is provided with a transfer mechanism 1111 for transferring wafers. In some embodiments, the transfer chamber 111 may be a vacuum environment or a non-vacuum environment. In some embodiments, the transfer mechanism 1111 may include a robot, a mechanical arm, a trolley, a conveyor belt or other mechanisms. In some embodiments, at least one side adjacent to the transfer chamber 111 forms a plurality of workstations. As an example, in Figure 1 In the embodiment, the plurality of workstations are adjacently arranged around the periphery of the transfer chamber 111, so as to save the space occupied by the plurality of workstations. In other embodiments, the plurality of workstations may also be arranged along a straight line or a curve, and are not limited to the annular arrangement around the transfer chamber 111. In some embodiments, when the transfer chamber 111 is a vacuum environment, the transfer mechanism 1111 may be a machine capable of vacuum movement, and its power supply / control circuit may be connected to a power supply / signal source outside the transfer chamber 111 through a vacuum interface.

[0038] The several functional chambers 112 are arranged at the plurality of workstations. Among them, at least one of the functional chambers 112 may be configured with at least a reaction processing unit 1121 for processing wafers, which may be referred to as a "reaction chamber". The reaction processing unit 1121 may perform an etching or deposition process on the wafer. At least another functional chamber 112 may be configured with at least a measurement unit 1122 for measuring the wafer to obtain the physical parameters of the wafer (such as the thickness of each point of the wafer, etc.), which may be referred to as a "measurement chamber". Before and after the wafer enters the reaction chamber for processing, it may enter the measurement chamber to measure the wafer to obtain the physical parameters of the wafer before and after processing.

[0039] By comparing and calculating the changes between the physical parameters of the wafer before and after the processing, the processing result parameters can be obtained, for example, the etching amount can be obtained according to the thickness change before and after etching of each point on the wafer, and the etching speed can be obtained from the etching amount / etching time in combination with the set / recorded etching time. In some embodiments, the wafer measurement can be performed based on optical instruments, electron microscopes (SEM), etc.

[0040] In some embodiments, the measurement of at least some physical parameters of the wafer (such as the etching amount, etc.) can also be completed in the reaction chamber, that is, some components in the measurement unit 1122 can also be located in the reaction chamber, so that the measurement can be performed immediately during the process. As an example, an optical-based endpoint measurement method, such as optical interferometry (IEP) or optical emission spectroscopy (OES), can be used. Taking optical interferometry as an example, when the probe light is irradiated on the surface of the thin film layer of the wafer, part of the light will be reflected by the surface of the thin film layer to form a first reflected light, while the other part passes through the thin film layer and is reflected on its lower surface to form a second reflected light. The phase difference between the first reflected light and the second reflected light depends on the thickness of the thin film layer and the wavelength of the probe light. The first reflected light and the second reflected light will interfere to form an interference signal, and the echo light contains the interference signal. Further, if the phase difference between the first reflected light and the second reflected light is an odd multiple of the wavelength, they will cancel each other, resulting in the weakening of the interference between the first reflected light and the second reflected light, so that their interference signals present dark stripes. If the phase difference is an even multiple of the wavelength, the interference between the first reflected light and the second reflected light will be enhanced, so that their interference signals present bright stripes. Therefore, by analyzing the spectral curve of the reflected light (the horizontal axis is time, the vertical axis is light intensity), the interference peaks / valleys correspond to bright fringes with enhanced interference and dark fringes with disappeared interference. By observing the number and spacing of interference peaks / valleys (i.e., interference fringes), the thickness of the film can be inferred, and the etching depth relative to the film thickness can be calculated in the etching process. The deposition process is similar. More specifically, since the second reflected light has twice the film thickness in the round trip compared to the first reflected light, the optical path difference between the first reflected light and the second reflected light can be calculated. Combined with the wavelength of the detection light, the change Δd of the film layer in each single cycle can be obtained, and the product of the number N of single etching cycles implemented within a certain period of time (i.e., the corresponding number of interference fringes) is used to obtain the etching amount. In addition, the etching rate can be obtained based on the quotient of Δd and the period of the interference fringes and the time difference δ between adjacent peaks / troughs.

[0041] Therefore, it can be understood that the reaction chamber and the measurement chamber are not strictly for performing only wafer processing and wafer measurement, and the reaction chamber may be provided with a measurement unit 1122 in addition to the reaction processing unit 1121 .

[0042] It should be noted that the plurality of workstations can be selectively equipped with the functional chamber 112 according to the requirements of the process flow, such as an etching process, a reaction chamber for the etching process and at least one measuring chamber; or a deposition process, a reaction chamber for the deposition process and at least one measuring chamber. Alternatively, a first reaction chamber for the etching process, a second reaction chamber for the deposition process and at least one measuring chamber are provided.

[0043] In some embodiments, the plurality of workstations may further be provided with a wafer supply container 120 and / or a wafer recovery container 130. The wafer supply container 120 may be provided with wafers to transport the wafers to the transfer chamber 111. The transfer mechanism 1111 may take the wafers from the wafer supply container 120 to the transfer chamber 111. The wafer recovery container 130 may receive at least one of processed, measured, and discarded wafers.

[0044] In addition, in addition to reaction chambers such as etching and deposition, measurement chambers, wafer supply containers 120, and wafer recovery containers 130, the multiple workstations may also include vacant spare workstations, and at least one of the following may be set at the workstations, such as a repair chamber (to repair wafer defects), a degumming chamber (such as removing photoresist), and a pretreatment chamber (for example, preheating or precooling the wafer).

[0045] In a preferred embodiment, by arranging different types of functional chambers 112 such as reaction chambers, measurement chambers, pretreatment chambers, repair chambers, and degumming chambers, and wafer supply and collection containers such as wafer supply containers 120 and wafer recovery containers 130 at multiple workstations surrounding the transfer chamber 111, a relatively complete semiconductor processing flow can be completed on a single machine.

[0046] In some embodiments, the functional chamber 112 (i.e., the reaction chamber) equipped with the reaction processing unit 1121 is provided with a chamber door for isolating or connecting to the transmission chamber 111. When performing wafer processing, the chamber door can be closed to isolate the reaction chamber from the transmission chamber 111. After the process is completed, the chamber door can be opened, and the wafer can be taken out of the reaction chamber to the transmission chamber 111, and the wafer is transported to the measurement chamber for measurement by the transmission mechanism 1111. The chamber door needs to be opened only when the pressure inside and outside the reaction chamber is consistent. In some examples, if the reaction chamber and the transmission chamber 111 are both vacuum environments, the pressure between the reaction chamber and the transmission chamber 111 can be the same or similar, and the chamber door can be opened directly or opened after the pressure is quickly adjusted to be consistent, thereby improving work efficiency. In other examples, if the reaction chamber is a vacuum environment and the transmission chamber 111 is a non-vacuum environment, the pressure difference between the two is large, and the reaction chamber needs a long time to adjust the pressure to be consistent with the transmission chamber 111. However, the transmission chamber 111 does not need to be provided with vacuum pumps and other related equipment for vacuuming, which can reduce costs. Therefore, the two exemplary implementations may be selected based on actual requirements of efficiency and cost, and are not intended to limit specific implementations.

[0047] The semiconductor processing machine 100 also includes a control unit 150. The control unit 150 is communicatively connected to and controls the conveying mechanism 1111, the reaction processing unit 1121 and the measuring unit 1122, and is used to automatically iterate and execute each round of the process flow. As an example, the control unit 150 can control the movement of the conveying mechanism 1111 by sending instructions, such as manipulating a robotic arm to transport the wafer between the functional chambers 112. As an example, the control unit 150 can control the reaction processing unit 1121 to perform etching, deposition and other processes by sending control instructions. Taking etching as an example, in the ICP etching process, the timing, voltage value, etc. of the RF voltage applied by the induction coil can be controlled to form a plasma with desired parameters for wafer etching.

[0048] Specifically, Figure 2 As shown, each round of the process flow can be implemented to include: Step S201: transferring wafers between the plurality of functional chambers 112 via the conveying mechanism 1111 to complete wafer processing and wafer measurement before and after processing.

[0049] Step S202: obtaining processing result parameters according to the changes between the physical parameters of the wafer before processing and the physical parameters of the wafer after processing.

[0050] In some embodiments, the processing result parameters are used to represent information about changes in physical parameters of the wafer during process treatments such as etching and deposition, and may include changes (such as etching amounts) or represented quantities calculated based on the changes, such as etching speed and etching uniformity values ​​(for example, the uniformity of thickness at each point on the wafer surface after etching, the commonly used unit is %).

[0051] Step S203: Debugging the process parameters of the reaction processing unit 1121 based on the optimization of the processing result parameters.

[0052] In some embodiments, the processing result parameters are obtained according to the changes in physical parameters before and after the wafer process. Taking the etching process as an example, the etching process refers to the process flow of etching the wafer, using an RF power supply to apply an RF electric field to a specific gas introduced into the reaction chamber under a low-pressure environment to generate plasma, and the wafer is etched with grooves or through holes through the plasma. The measurement of the wafer after etching, that is, before etching, first enters the measurement chamber to measure the pre-value, that is, the physical parameters of the wafer before processing, and after etching, enters the measurement chamber to measure the post-value, that is, the physical parameters of the wafer after processing, and outputs it.

[0053] As an example, in the etching process, the processing result parameters include at least one of the following: etching speed at each point on the wafer; etching uniformity value; selectivity, that is, the ratio of mask etching speed to wafer material etching speed; verticality (reflecting the situation of the hole wall and the bottom wall of the concave hole); aspect ratio (reflecting the etching ability of the etcher). In addition, taking the ICP etching process as an example, the process parameters include at least one of the following: the RF power of the induction coil; the power ratio between the multiple sub-coils of the induction coil; the gas volume; the gas type; the temperature of the functional cavity 112; the wafer carrier temperature of the wafer; the voltage when the wafer carrier is an electrostatic chuck; the distance between the wafer and the electrostatic chuck (related to the heat conduction speed from the electrostatic chuck to the wafer). In other embodiments, the wafer carrier can also be implemented as a hot stage, etc., and the process parameters can be changed accordingly, and are not limited to the electrostatic chuck.

[0054] In some embodiments, Figure 3As shown, the control unit 150 is configured with a process parameter prediction model 151. The process parameter prediction model 151 inputs the processing result parameters and predicts the target process parameters of the reaction processing unit 1121. In some embodiments, the process parameter prediction model 151 can be constructed based on a machine learning model and obtained through training. As an example, the machine learning model can be implemented as a neural network model. The neural network model can be implemented to include an input layer, multiple hidden layers, and an output layer. The input layer may include one or more input nodes (determined according to the number of input parameters), each of the hidden layers may include multiple hidden nodes connected to the nodes in the previous layer, and the output layer includes one or more output nodes (determined according to the number of output parameters), which are connected to the hidden nodes in the last hidden layer. The nodes from the front to the back are connected by branch lines, each branch line has a corresponding weight, each hidden node may have an offset value, the hidden node calculates the input of each branch line (such as weighted sum), and outputs it to the next level node (hidden node or output node) after adding the offset value, and finally forms an output at the output node.

[0055] As an example, the machine learning model includes, but is not limited to, a neural network (such as a generative adversarial network (GAN), a regional convolutional neural network (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), a stacked deep neural network (S-DNN), a state-space dynamic neural network (S-SDNN), a deconvolution network, a deep belief network (DBN), a restricted Boltzmann machine (RBM), a fully convolutional network, a long short-term memory (LSTM) network). Alternatively or additionally, the machine learning model may include other forms including an ensemble such as a random forest, such as, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction (such as, principal component analysis PCA) and expert systems and / or combinations thereof.

[0056] Since the process parameter prediction model 151 takes the processing result parameters as input and the target process parameters as output, in a training example, the ideal processing result parameters and the corresponding actual ideal process parameters (which can be obtained by actual experiments on the machine or according to preset data) can be used as training data and input into the machine learning model for training. The process parameter prediction model 151 predicts and outputs the predicted process parameters based on the ideal processing result parameters. The difference between the predicted process parameters and the actual process parameters, i.e., the loss, is calculated by the loss function, and the process parameter prediction model 151 is adjusted with the goal of eliminating the loss. The above process is iterated in this way, so that the predicted process parameters output by the process parameter prediction model 151 are closer and closer to the ideal process parameters, and finally the accurate target process parameters can be output. Of course, it can be understood that the training methods are different based on different machine learning models. The above only illustrates one training method, but it is not limited to this.

[0057] In some embodiments, Figure 4 As shown, step S203 may also include: Step S231: Determine whether the processing result parameter reaches a preset threshold or the optimization is saturated.

[0058] In some embodiments, the preset threshold is the target value of optimization. In other embodiments, due to hardware limitations in actual scenarios, the processing result parameters may not reach the expected preset threshold, and it can be determined whether the optimization of the processing result parameters is regionally saturated, such as the change amount or change ratio between the target process parameters obtained in the most recent multiple consecutive rounds is lower than a certain threshold.

[0059] If yes, stop the process; if no, go to step S232; Step S232 : inputting the processing result parameters into the process parameter prediction model 151 to predict target process parameters, and setting the target process parameters for the reaction processing unit 1121 .

[0060] Then, the process flow is iteratively executed according to the reset target process parameters until the process is stopped when the judgment in step S231 is yes, and the required target process parameters are obtained.

[0061] Figure 1 Only a schematic diagram of a top view of the semiconductor processing machine 100 is shown, and the semiconductor processing machine 100 may include only one single-layer process component 110, or may include multiple process components 110. The multiple process components 110 may be stacked in multiple layers in the up-and-down direction.

[0062] like Figure 5 , which shows a side structural schematic diagram of a semiconductor processing machine having multi-layer stacked process components according to an embodiment of the present disclosure.

[0063] exist Figure 5 In the figure, two process components are shown as an example, including a first process component 110a located at the bottom and a second process component 110b located at the top. It can be seen that the first process component 110a includes a first transfer chamber 111a and a first functional chamber 112a arranged adjacent to the first transfer chamber 111a. The first transfer chamber 111a is also adjacent to another first functional chamber 112a. Figure 5It is shown as a side structure and is not visible. The second process component 110b includes a second transfer chamber 111b and a second functional chamber 112b arranged adjacent to the second transfer chamber 111b. As a result, the two process components operate independently, and the first transfer mechanism 1111a in the first transfer chamber 111a can transport wafers between the first transfer chamber 111a and the first functional chamber 112a. The second transfer mechanism 1111b in the second transfer chamber 111b can transport wafers between the second transfer chamber 111b and the second functional chamber 112b. In some optional embodiments, in order to uniformly collect the wafers in the first process component 110a and the second process component 110b, the first process component 110a and the second process component 110b can share a wafer supply container 120 and / or a wafer recovery container 130. A lifting and transporting mechanism (not shown) for transporting wafers between multiple process components 110 can be set in the wafer supply container 120 and / or the wafer recovery container 130. The wafer supply container 120 may be provided with a wafer inlet on the first floor, and the lifting and conveying mechanism in the wafer supply container 120 may supply wafers from the first process component 110a to the first conveying chamber 111a, and may also be lifted to the second process component 110b to supply wafers to the second process component 110b. The wafer recovery container 130 may be provided with a wafer outlet on the first floor, and the lifting and conveying mechanism in the wafer recovery container 130 may transport the wafers in the second process component 110b (such as discarded wafers after the debugging of the machine is completed) to the first floor so that they can be sent out from the wafer outlet.

[0064] In some embodiments, multiple process components 110 may share the same transfer chamber 111 .

[0065] like Figure 6 , which shows a side structural schematic diagram of a semiconductor processing machine having multi-layer stacked process components in another embodiment of the present disclosure.

[0066] exist Figure 6, the third process component 110c below and the fourth process component 110d above are shown. The third process component 110c and the fourth process component 110d include the same third transfer chamber 111c. The third process component 110c includes a third functional chamber 112c disposed adjacent to the third transfer chamber 111c. The fourth process component 110d includes a fourth functional chamber 112d disposed adjacent to the third transfer chamber 111c. The third transfer mechanism 1111c in the third transfer chamber 111c may be liftable, for example, implemented as a robotic arm disposed on a lifting platform. The third transfer mechanism 1111c may transfer wafers between the third functional chamber 112c, the fourth functional chamber 112d and the third transfer chamber 111c. Therefore, in this embodiment, the wafers can be transferred between the third process assembly 110c and the fourth process assembly 110d, for example, the same or multiple wafers can be used to complete each round of process flow in one process assembly 110, and the wafers can be sent to another process assembly 110 through the shared third conveying mechanism 1111c to complete each round of process flow. Alternatively, the same or multiple wafers can be alternately transferred between one process assembly 110 and another process assembly 110 through the shared third conveying mechanism 1111c to complete each round of process flow.

[0067] It should be noted that the terms “first”, “second”, “third”, etc. mentioned above are only used to distinguish the descriptions and do not represent the quantities that need to be set in the embodiments.

[0068] In some other embodiments, a plurality of process components 110 may be disposed in at least one layer and arranged in parallel with each other. Optionally, a plurality of process components 110 in the same layer may share a transfer chamber 111 and / or a common functional chamber 112 .

[0069] According to the above embodiments, it can be known that between different process components 110 in upper and lower layers, and / or between different process components 110 in the same layer, a shared transfer chamber 111 and / or a shared functional chamber 112 can be considered.

[0070] To make it clear Figure 7 FIG. 1 is a schematic diagram showing a process flow executed by a semiconductor processing machine in a preferred embodiment of the present disclosure. Figure 7 An example is the execution of a process flow on a single process component basis.

[0071] exist Figure 7 The process includes: Step S701 : the control unit 150 controls the conveying mechanism 1111 to obtain wafers from the wafer supply container 120 to the conveying chamber 111 .

[0072] Step S702 : the control unit 150 controls the conveying mechanism 1111 to convey the wafer to the measuring chamber, and the physical parameters of the wafer before processing are measured by the measuring unit 1122 .

[0073] Step S703: the control unit 150 controls the conveying mechanism 1111 to take the wafer out of the measuring chamber and convey it into the reaction chamber.

[0074] Step S704: the control unit 150 controls the reaction processing unit 1121 to perform a process on the wafer.

[0075] Step S705 : the control unit 150 controls the conveying mechanism 1111 to transfer the processed wafer from the reaction chamber to the measuring chamber, and the physical parameters of the processed wafer are measured by the measuring unit 1122 .

[0076] Step S706: the control unit 150 obtains processing result parameters according to the comparison between the physical parameters of the wafer before processing and the physical parameters of the wafer after processing; Step S707: Determine whether the processing result parameter reaches a preset threshold or the optimization is saturated.

[0077] If yes, stop the process; if no, go to step S708.

[0078] Step S708 : inputting the processing result parameters into the process parameter prediction model 151 to predict target process parameters, and setting the target process parameters for the reaction processing unit 1121 .

[0079] That is, the current process parameters are adjusted to the target process parameters to complete the process parameter debugging.

[0080] After step S708, the process may return to step S704 for loop iteration (or may return to step S701 to obtain another wafer), and the current physical parameters of the processed wafer may be used as the physical parameters of the wafer before processing in the next round, and the physical parameters of the processed wafer measured after the next round of process processing may be used to calculate the processing result parameters of the next round, and then make a judgment in step S707. When a judgment result of "yes" is obtained in step S707, the process ends.

[0081] like Figure 8 FIG. 1 is a schematic diagram showing the structure of a computer device in an embodiment of the present disclosure. The control unit 150 can be implemented based on the computer device.

[0082] The computer device 800 includes a bus 801, a processor 802, and a memory 803. The processor 802 and the memory 803 can communicate with each other through the bus 801. The memory 803 may store a computer program or instruction. The processor 802 implements the functions of the control unit 150 in the previous embodiment by running the computer program or instruction in the memory 803, for example, executing the following Figure 3 , Figure 7 As an example, the memory 803 may store a control program for controlling at least one of the conveying mechanism 1111 , the reaction processing unit 1121 , and the measuring unit 1122 , and the process parameter prediction model 151 .

[0083] The bus 801 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, although only one thick line is used in the figure, it does not mean that there is only one bus or one type of bus.

[0084] In some embodiments, the processor 802 may be implemented as a central processing unit (CPU), a microprocessor 1121 (MCU), a system on chip (System On Chip), or a field programmable logic array (FPGA). The memory 803 may include a volatile memory (Volatile Memory) for temporary storage of data when running a program, such as a random access memory (Random Access Memory, RAM).

[0085] The memory 803 may also include a non-volatile memory (non-volatile memory) for data storage, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state disk (SSD).

[0086] In some embodiments, the computer device 800 may further include a communicator 804. The communicator 804 is used to communicate with the outside. In a specific example, the communicator 804 may include one or a group of wired and / or wireless communication circuit modules. For example, the communicator 804 may include one or more of a wired network card, a USB module, a serial interface module, etc. The wireless communication protocols followed by the wireless communication module include: for example, near field communication (NFC) technology, infrared (IR) technology, Global System for Mobile communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), Global Navigation Satellite System (GNSS), etc. One or more.

[0087] In an embodiment of the present disclosure, a computer-readable storage medium may be provided, storing a computer program or instructions, which, when executed, implements the method flow or functions in any of the previous embodiments.

[0088] That is, the method steps in the above embodiments are implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or are implemented as computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded via a network and to be stored in a local recording medium, so that the method represented herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA).

[0089] In the embodiments of the present disclosure, a computer program product may be provided, one or more computer programs or instructions, which, when executed, fully or partially execute the process or function in the embodiments of the present disclosure. The computer program product includes one or more computer programs or instructions.

[0090] The computer program or instructions may be stored in a readable storage medium or transmitted from one readable storage medium to another readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired or wireless means. The readable storage medium may be any available medium that can be accessed or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital video disk; it may also be a semiconductor medium, such as a solid state drive. The computer readable storage medium may be a volatile or non-volatile storage medium, or may include both volatile and non-volatile types of storage media.

[0091] In summary, the present disclosure relates to the field of semiconductor technology, and provides a semiconductor processing machine, including: at least one process component, the process component including: a transfer chamber and a plurality of functional chambers; the transfer chamber is provided with a transfer mechanism for transferring wafers; at least one side adjacent to the transfer chamber forms a plurality of workstations; the plurality of functional chambers are arranged at the plurality of workstations; one of the functional chambers is at least provided with a reaction processing unit for processing wafers, and another of the functional chambers is at least provided with a measurement unit for measuring wafers before and after processing to obtain physical parameters of the wafers before and after processing; a control unit, which is communicatively connected and controls the transfer mechanism, the reaction processing unit and the measurement unit, and is used to automatically iterate and execute each round of process flow, wherein each round of the process flow includes: transferring wafers between the plurality of functional chambers through the transfer mechanism to complete wafer processing and wafer measurement before and after processing, and obtaining processing result parameters according to changes between the physical parameters of the wafers before and after processing, and debugging the process parameters of the reaction processing unit based on the optimization of the processing result parameters. As a result, the cycle of processing, measuring, and debugging can be automatically completed on a semiconductor processing machine, effectively improving work efficiency.

[0092] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor processing machine, It is characterized in that include: At least one process component, the process component comprising: a transfer chamber and a plurality of functional chambers; The transfer chamber is provided with a transfer mechanism for transferring wafers; at least one side adjacent to the transfer chamber forms a plurality of workstations; The plurality of functional chambers are arranged at the plurality of workstations; one of the functional chambers is at least provided with a reaction processing unit for processing wafers, and another functional chamber is at least provided with a measurement unit for measuring wafers before and after processing to obtain physical parameters of the wafers before and after processing; A control unit is communicatively connected to and controls the conveying mechanism, the reaction processing unit and the measuring unit, and is used to automatically iterate and execute each round of process flow, wherein each round of the process flow includes: transferring wafers between a plurality of functional chambers through the conveying mechanism to complete wafer processing and wafer measurement before and after processing, and obtaining processing result parameters according to changes between physical parameters of the wafer before processing and physical parameters of the wafer after processing, and debugging the process parameters of the reaction processing unit based on the optimization of the processing result parameters.

2. The semiconductor processing machine according to claim 1, It is characterized in that Also includes: Wafer Supply containers and wafer recovery containers are arranged at the plurality of workstations; the wafer supply container conveys wafers to be processed to the transfer chamber; and the wafer recovery container is used to recover wafers.

3. The semiconductor processing machine according to claim 1, It is characterized in that The transfer chamber and the plurality of functional chambers are provided in groups and are stacked in multiple layers; at least one process component is provided in each layer.

4. The semiconductor processing machine according to claim 3, It is characterized in that The wafer supply container and / or wafer recovery container arranged at one of the workstations is provided with a lifting and conveying mechanism for conveying wafers between multiple process components; and / or, the conveying chambers in the multiple layers are independent of each other, or share the same conveying chamber.

5. The semiconductor processing machine according to claim 1, It is characterized in that The control unit is configured with a process parameter prediction model; the process parameter prediction model inputs the processing result parameters and predicts the target process parameters of the reaction processing unit; The step of debugging the process parameters of the reaction processing unit based on the optimization of the processing result parameters includes: In response to the processing result parameter not reaching a preset threshold or the optimization of the processing result parameter tending to saturation, the processing result parameter is input into a process parameter prediction model to predict a target process parameter, and the target process parameter is set for the reaction processing unit.

6. The semiconductor processing machine according to claim 1, It is characterized in that The process parameters include at least one of the following: RF power of the induction coil; power ratio between multiple sub-coils of the induction coil; gas volume; gas type; functional chamber temperature; wafer carrier temperature of the wafer; The voltage when the wafer carrier is an electrostatic chuck; The cavity pressure between the wafer and the electrostatic chuck; And / or, the wafer processing includes etching, and the processing result parameter includes at least one of the following: etching speed at each point on the wafer; Etching uniformity value; The ratio of the mask etching rate to the wafer material etching rate; verticality; aspect ratio.

7. The semiconductor processing machine according to claim 1, It is characterized in that The transmission chamber and the functional chamber are in vacuum environment.

8. The semiconductor processing machine according to claim 1, It is characterized in that The plurality of workstations are arranged around the outer circumference of the functional cavity.

9. The semiconductor processing machine according to claim 1, It is characterized in that The functional chamber equipped with the reaction processing unit is provided with a chamber door for isolating or connecting with the transfer chamber.

10. The semiconductor processing machine according to claim 1, It is characterized in that The plurality of workstations also include spare spare workstations for setting up other functional cavities, and the other functional cavities include at least one of the following: repair; degumming; temperature adjustment.

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