An anti-radiation hardened silicon carbide MOSFET structure and its manufacturing method

Abstract

The present invention relates to a radiation-hardened silicon carbide MOSFET structure and a preparation method thereof. The structure includes a drain metal, an N substrate, N-type silicon carbide, and a source metal stacked sequentially from bottom to top. A polysilicon gate is disposed between the source metal and the N-type silicon carbide. A gate oxide is formed between the polysilicon gate and the N-type silicon carbide. A source region is formed on the surface of the N-type silicon carbide. The surface of the source region contacts the gate oxide and the source metal. A trench is formed on the surface of the N-type silicon carbide. The trench is located below the polysilicon gate. The trench is filled with first N-type polysilicon. A first shielding region is formed on the upper surface of the N-type silicon carbide. The first shielding region covers the outside of the trench. The present invention can improve the single-event gate rupture resistance and single-particle radiation resistance of silicon carbide MOSFET devices.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and specifically relates to a radiation-hardened silicon carbide MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) high-voltage power devices have more excellent electrothermal performance than traditional silicon devices and can work normally in more demanding environments. Therefore, they have broad application prospects in fields such as photovoltaic power generation, electric vehicles, and aerospace.

[0003] In the aerospace field, radiation hardening is a major difficult problem. Current SiC power devices often experience single-event burnout when the blocking voltage is less than 1 / 3 and the LET is not higher than 10 MeV·cm² / mg, far lower than the theoretical expectation. Single-particle radiation usually involves complex electrothermal coupling responses inside the device. When a heavy ion bombards into the power device, a large number of electron-hole pairs are generated along the movement trajectory. These electron-hole pairs drift under the action of an electric field, forming a huge instantaneous current inside the device. Some electrons and holes will also accumulate at both ends of the device, thereby reconstructing the electric field inside the device and causing local strong electric field breakdown of the device, such as single-event gate breakdown. In addition, this large amount of electron-hole movement and strong electric field coupling generate a huge instantaneous heat inside the device, which may cause local single-event burnout of the device. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a radiation-hardened silicon carbide MOSFET structure and a preparation method thereof for the above deficiencies.

[0005] To solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A radiation-hardened silicon carbide MOSFET structure includes a drain metal, an N substrate, an N-type silicon carbide, and a source metal stacked in sequence from bottom to top.

[0007] A polysilicon gate is provided between the source metal and the N-type silicon carbide, and a gate oxide is formed between the polysilicon gate and the N-type silicon carbide.

[0008] A source region is formed on the surface of the N-type silicon carbide, and the surface of the source region is in contact with the gate oxide and the source metal.

[0009] A trench is formed on the surface of the N-type silicon carbide. The trench is located below the polysilicon gate, and the trench is filled with a first N-type polysilicon, and the first N-type polysilicon is in contact with the source metal.

[0010] A first shielding region is formed on the surface of the N-type silicon carbide, and the first shielding region covers the outside of the trench.

[0011] Furthermore, the first shielding region is a P-type doped region.

[0012] Furthermore, the source region includes an N-well trench opened on the surface of the N-type silicon carbide and a second N-type polysilicon filled in the N-well trench.

[0013] A second shielding region is formed on the surface of the N-type silicon carbide, and the second shielding region covers the outside of the source region. One side of the N-well trench is in contact with the N-type silicon carbide, and a heterojunction structure is formed between the second N-type polysilicon and the N-type silicon carbide.

[0014] Furthermore, the second shielding region is a P+ region.

[0015] Furthermore, a P-well region is formed on the N-type silicon carbide, and the P-well region covers the outside of the second shielding region and the source region.

[0016] The surface of the P-well region has a gap with the surface of the N-type silicon carbide, and the gap with a lateral distance forms a channel for the N-type silicon carbide and the second N-type polysilicon to contact; or the surface of the P-well region has no gap with the surface of the N-type silicon carbide, that is, there is no channel.

[0017] Furthermore, the N-type silicon carbide includes an N-buffer layer, an N-type drift layer, and a carrier storage layer sequentially arranged from top to bottom, and the trench, the first shielding region, the source region, the second shielding region, and the P-well region are all located in the carrier storage layer.

[0018] Furthermore, an interlayer dielectric is formed between the polysilicon gate and the source metal.

[0019] Furthermore, a gate dielectric is formed between the gate oxide and the polysilicon gate.

[0020] A method for manufacturing a radiation-hardened silicon carbide MOSFET includes the following steps:

[0021] Step S1: Form N-type silicon carbide on an N substrate.

[0022] Step S2: Inject carrier storage layer ions, P-type doping ions, and P+ ions into the N-type silicon carbide, and perform high-temperature annealing and activation to form a carrier storage layer, a first shielding region, and a second shielding region on the N-type silicon carbide.

[0023] Step S3: Etch the surface of the N-type silicon carbide to form a trench and an N-well trench, and fill the trench and the N-well trench with a first N-type polysilicon and a second N-type polysilicon respectively.

[0024] Step S4: Thermally oxidize above the N-type silicon carbide to form a gate oxide;

[0025] Step S5: Deposit a polysilicon gate and an interlayer dielectric above the gate oxide to form a MOS structure;

[0026] Step S6: Deposit source metal in the region between adjacent polysilicon gates and make the source metal contact the second N-type polysilicon;

[0027] Step S7: Open the gate;

[0028] Step S8: Deposit a layer of thick source metal above the interlayer dielectric to form a source structure;

[0029] Step S9: Form a drain metal below the N-substrate.

[0030] Furthermore, in step S2, before performing high-temperature annealing and activation, it further includes implanting P-well ions into the N-type silicon carbide, and after high-temperature annealing and activation, a P-well region is formed on the N-type silicon carbide.

[0031] After the present invention adopts the above technical solutions, compared with the prior art, it has the following advantages:

[0032] (1) The present invention introduces a trench structure on the device, and the sidewalls and bottom of the trench are provided with P-type doped regions. The trench is filled with N-type polysilicon. The trench structure can transfer the strong electric field at the gate oxide interface to the bottom position of the carrier storage layer, so as to greatly reduce the electric field strength in the gate oxide, thereby improving the single-event gate rupture resistance of the silicon carbide MOSFET device;

[0033] (2) The P-type doped regions at the bottom and sidewalls of the trench strengthen the extraction efficiency of holes near the carrier storage layer during heavy ion bombardment, can quickly and efficiently remove the electron-hole pairs generated by heavy ion bombardment, reduce the current and radiation response time generated by single-event radiation, and can effectively improve the single-event radiation resistance of the SiC MOSFET;

[0034] (3) The introduction of the trench structure can enhance the pinch-off effect of the carrier storage layer at high blocking voltages. Without affecting the voltage blocking ability of the device, the doping concentration of the carrier storage layer can be increased, so as to greatly improve the recombination efficiency of holes and electrons during single-event radiation through the carrier storage layer with a higher doping concentration and the second N-type polysilicon shorted to the source metal, thereby improving the radiation resistance of the silicon carbide MOSFET device;

[0035] (4) By introducing an N buffer layer on the back of the N-type silicon carbide, the transient peak electric field strength on the back of the N-type silicon carbide is reduced, the breakdown of the back N-type high-low junction is inhibited, and the single-event radiation resistance of the silicon carbide MOSFET device is effectively improved;

[0036] (5) The present invention uses N-type polysilicon to form the source electrode. The N-type polysilicon and N-type silicon carbide form a heterojunction, which makes the device in the normally-off state when no gate voltage is applied. This structure realizes the control of the turn-on and turn-off of the silicon carbide MOSFET device by using the method of the gate controlling the heterojunction barrier height, can shorten or omit the channel in the traditional planar gate structure, and realizes the miniaturization of the silicon carbide MOSFET device cell;

[0037] When the channel is retained, an N-type accumulation channel is used to replace the inversion channel, which greatly improves the channel mobility and realizes the reduction of the specific on-resistance of the silicon carbide MOSFET device;

[0038] (6) The present invention can omit the P-well as needed. In the case of no P-well region, the P+ region completely wraps the bottom of the N-well groove to achieve shielding protection. At the same time, the P+ region completely surrounding the N-well can greatly reduce the turn-on of the parasitic NPN transistor and improve the reliability of the device;

[0039] (7) The heterojunction formed by N-type polysilicon and N-type silicon carbide is reverse-biased during the forward blocking of the device. It can combine with the shielding protection of the P-well / P+ to reduce the leakage current of the device. During the reverse conduction of the device, the forward conduction voltage drop of the heterojunction is lower, which can greatly reduce the reverse conduction loss of the silicon carbide MOSFET device and suppress the bipolar degradation caused by the conduction of the body diode. At the same time, the heterojunction stores less excess carriers, and the reverse recovery characteristics of the silicon carbide MOSFET device are better.

[0040] The present invention will be described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0041] Figure 1 It is the device structure diagram of the embodiment of the present invention.

[0042] In the drawings, the list of components represented by each label is as follows:

[0043] 1. Drain metal; 2. N substrate; 3. N-type silicon carbide; 3a. N buffer layer; 3b. N-type drift layer; 3c. Carrier storage layer; 31. Trench; 32. First shielding region; 33. Second shielding region; 34. P-well region; 35. Channel; 4. Source metal; 5. Polysilicon gate; 51. Gate oxide; 52. Interlayer dielectric; 53. Gate dielectric; 6. Source region; 61. N-well groove; 62. Second N-type polysilicon; 7. First N-type polysilicon. Detailed Embodiments

[0044] The principles and features of the present invention will be described below with reference to the drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0045] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "clockwise" and "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0046] Embodiment 1:

[0047] As Figure 1 shown, a radiation-hardened silicon carbide MOSFET structure includes a drain metal 1, an N substrate 2, an N-type silicon carbide 3, and a source metal 4 stacked from bottom to top.

[0048] A polysilicon gate 5 is formed between the N-type silicon carbide 3 and the source metal 4. A gate oxide 51 is formed between the polysilicon gate 5 and the N-type silicon carbide 3 (a gate dielectric 52 can be deposited between the gate oxide 51 and the polysilicon gate 5, or it can be omitted). An interlayer dielectric 53 is formed between the polysilicon gate 5 and the source metal 4.

[0049] The N-type silicon carbide 3 includes an N buffer layer 3a, an N-type drift layer 3b, and a carrier storage layer 3c arranged in sequence from bottom to top.

[0050] A trench 31 is etched on the N-type silicon carbide 3. The trench 31 is filled with a first N-type polysilicon 7, and the trench 31 is located below the polysilicon gate 5. A first shielding region 32 is formed on the surface of the N-type silicon carbide 3. The first shielding region 32 is a P-type doped region, and the first shielding region 32 covers the outside of the trench 31 to form a shielding protection for the first N-type polysilicon 7.

[0051] Specifically, the first N-type polysilicon 7 needs to be grounded. Through layout design, the first N-type polysilicon 7 is short-circuited with the source metal 4, thereby realizing the grounding of the first N-type polysilicon 7 ( Figure 1 is a plan view, and the contact between the first N-type polysilicon 7 and the source metal 4 is not shown).

[0052] The trench structure can transfer the strong electric field at the gate oxide interface to the bottom position of the carrier storage layer, greatly reducing the electric field strength in the thin gate oxide, thereby enhancing the gate breakdown resistance of the silicon carbide MOSFET device against single particles;

[0053] At the same time, the P-type doped regions (i.e., the second shielding regions) at the bottom and side walls of the trench increase the hole extraction path area in the active region, strengthen the hole extraction efficiency in the body during the instant of heavy ion bombardment, can quickly and efficiently remove the electron-hole pairs generated by heavy ion bombardment, reduce the current and radiation response time generated by single particle radiation, and can effectively enhance the single particle radiation resistance of the silicon carbide MOSFET.

[0054] In addition, due to the introduction of the trench structure, the pinch-off effect of the carrier storage layer at high blocking voltages is enhanced. And without affecting the voltage blocking ability of the device, the doping concentration of the carrier storage layer is increased. The carrier storage layer with a higher doping concentration and the second N-type polysilicon shorted to the source in the N-well trench can significantly improve the recombination efficiency of holes and electrons during single-particle radiation, further enhance the extraction speed of excess carriers, and thus further improve the radiation resistance of the silicon carbide MOSFET.

[0055] Moreover, since the N buffer layer 3a is introduced on the back surface of the N-type silicon carbide 3, the transient peak electric field intensity on the back surface of the N-type silicon carbide 3 is reduced, and the breakdown of the back surface N-type high-low junction is suppressed, thereby effectively improving the single-particle radiation resistance.

[0056] A source region 6 is provided on the N-type silicon carbide 3. The source region 6 includes an N-well trench 61 and a second N-type polysilicon 62. The N-well trench 61 is etched on the N-type silicon carbide 3. The N-well trench 61 is located below the left / right side of the polysilicon gate 5. The second N-type polysilicon 62 is filled in the N-well trench 61, and the second N-type polysilicon 62 is in contact with the N-type silicon carbide 3 to form a heterojunction structure. The surface of the second N-type polysilicon 62 is in contact with the source metal 4 and the gate oxide 51.

[0057] A second shielding region 33 and a P-well region 34 are further formed on the N-type silicon carbide 3. The second shielding region 33 and the P-well region 34 are sequentially coated on the outside of the N-well trench 61 to form a shielding protection for the second N-type polysilicon 62.

[0058] To solve the technical problems in the cell scaling of the existing planar gate silicon carbide MOSFET device, in this embodiment, an N-well trench 61 is etched on the N-type silicon carbide 3, and the second N-type polysilicon 62 is filled in the N-well trench 61 as the source. The P+ region and the P-well region surround the second N-type polysilicon 62 to form a shielding protection. There is a certain interval between the upper surface of the P-well region 34 and the upper surface of the N-type silicon carbide 3. The interval with a lateral distance forms the channel 35 of the silicon carbide MOSFET device. The second N-type polysilicon 62 and the N-type silicon carbide 3 form a heterojunction, so that the device is in the normally-off state when no gate voltage is applied.

[0059] The above structure uses the method of controlling the heterojunction barrier height by the gate to realize the turn-on and turn-off of the MOSFET device, which can greatly shorten or remove the channel in the traditional planar gate structure, can use an accumulation-type channel to replace the inversion channel in the traditional structure, improve the mobility of the channel, and reduce the specific on-resistance of the device.

[0060] The heterojunction formed by the second N-type polysilicon 62 and the N-type silicon carbide 3 has a certain barrier height, so that the device is in the normally-off state when no gate voltage is applied;

[0061] When a positive voltage exceeding the threshold voltage is applied to the gate, the barrier height of the heterojunction decreases, and the SiC MOSFET device turns on. The electrons in the second N-type polysilicon 62 pass through the channel 35, the carrier storage layer 3c, the N-type drift layer 3b, the N buffer layer 3a, and the N substrate 2 and then enter the drain metal 1;

[0062] When the gate voltage is lower than the device threshold voltage, the SiC MOSFET device turns off;

[0063] When a high voltage is applied to the drain of the device, the PN junction formed by the P-well region and the P+ region (i.e., the second shielding region) and the N-type drift layer 3b is reverse-biased to withstand the blocking voltage. At the same time, the reverse-biased heterojunction can also reduce the leakage current of the device;

[0064] When the drain-source of the device withstands a reverse voltage, the heterojunction formed by the second N-type polysilicon 62 and the N-type silicon carbide 3 conducts forward, and the device conducts a reverse current. Since the forward conduction voltage drop of the heterojunction is low, the reverse conduction voltage drop of the SiC MOSFET device is low, and the bipolar degradation caused by the conduction of the body diode can be suppressed at the same time; since the heterojunction formed by the second N-type polysilicon 62 and the N-type silicon carbide 3 has unipolarity (only electrons work as carriers), the reverse recovery characteristics of the device are better.

[0065] Specifically, the channel 35, the first N-type polysilicon 7, the source region 6, the first shielding region 32, the second shielding region 33, and the P-well region 34 are all located within the carrier storage layer 3c.

[0066] A method for fabricating a radiation-hardened SiC MOSFET includes the following steps:

[0067] 1. Preparation of a silicon carbide wafer, that is, forming N-type silicon carbide 3 on the surface of the N substrate 2;

[0068] 2. Injecting P-well ions, P+ ions, P-type doping ions, and carrier storage layer ions into the N-type silicon carbide 3, and then performing high-temperature annealing and activation to form a carrier storage layer 3c, a first shielding region 32, a second shielding region 33, and a P-well region 34 on the N-type silicon carbide;

[0069] 3. Etching an N-well groove 61 and a trench 31 in the N-type silicon carbide 3, filling the trench 31 with the first N-type polysilicon 7, and filling the N-well groove 61 with the second N-type polysilicon 62;

[0070] 4. Forming a thin gate oxide 51 on the N-type silicon carbide 3 by thermal oxidation;

[0071] 5. Depositing a high-k dielectric such as Al2O3 above the gate oxide 51 to form a second gate dielectric 53 (this layer and this step can be omitted);

[0072] 6. Depositing a polysilicon gate 5 and an interlayer dielectric 52 on the gate oxide 51 or the gate dielectric 53 to form a MOS structure;

[0073] 7. Deposit source metal 4 between adjacent polysilicon gates 5, and make the source metal contact with the second N-type polysilicon 62;

[0074] 8. Gate opening;

[0075] 9. Deposit a thick source metal 4 on the polysilicon gate 5 to form a source structure;

[0076] 10. Form surface protection structures such as TEOS and PI;

[0077] 11. Thinning the back side of N substrate 2;

[0078] 12. A drain metal 1 is formed on the back side of the N substrate 2 to form a drain structure.

[0079] The production process of the radiation-hardened silicon carbide MOSFET device in this embodiment is largely compatible with the production process of the traditional planar gate silicon carbide MOSFET device, and only the N-well and trench etching steps and the step of filling polysilicon into the N-well and trench need to be adjusted.

[0080] Embodiment 2:

[0081] In this embodiment, the P-well region 34 is omitted based on the first embodiment.

[0082] In this embodiment, the process step of implanting P-well ions on the N-type silicon carbide 3 is omitted, so that the P-well region 34 is omitted.

[0083] In the case where the channel does not need to be retained, the P-well region 34 can be removed at the same time to reduce the mask and an ion implantation process. In this case, the P+ region (second shielding region 33) is directly used to form a shielding protection for the second N-type polysilicon 62 in the N-well groove 61. Since the P+ region forms a full surrounding protection for the bottom of the second N-type polysilicon 62, the ion concentration of the P+ region is very high, and the parasitic NPN transistor inside the silicon carbide MOSFET device will be greatly suppressed, thereby improving the reliability of the device.

[0084] The above is an example of the best implementation of the present invention, and the parts not described in detail are common knowledge of ordinary technicians in the field. The protection scope of the present invention shall be based on the content of the claims, and any equivalent transformation based on the technical enlightenment of the present invention is also within the protection scope of the present invention.

Claims

1. A radiation-hardened silicon carbide MOSFET structure, characterized in that, It includes a drain metal (1), an N substrate (2), an N-type silicon carbide (3), and a source metal (4) stacked in sequence from bottom to top. A polysilicon gate (5) is provided between the source metal (4) and the N-type silicon carbide (3), and a gate oxide (51) is formed between the polysilicon gate (5) and the N-type silicon carbide (3). A source region (6) is formed on the surface of the N-type silicon carbide (3). The surface of the source region (6) is in contact with the gate oxide (51) and the source metal (4). The source region (6) includes an N-well groove (61) formed on the surface of the N-type silicon carbide (3) and a second N-type polysilicon (62) filled in the N-well groove (61). A second shielding region (33) is formed on the surface of the N-type silicon carbide (3). The second shielding region (33) covers the outside of the source region (6). One side of the N-well groove (61) is in contact with the N-type silicon carbide (3). The second N-type polysilicon (62) and the N-type silicon carbide (3) form a heterojunction structure. A groove (31) is formed on the surface of the N-type silicon carbide (3). The groove (31) is located below the polysilicon gate (5). The groove (31) is filled with a first N-type polysilicon (7). The first N-type polysilicon (7) is in contact with the source metal (4). A first shielding region (32) is formed on the upper surface of the N-type silicon carbide (3). The first shielding region (32) covers the outside of the groove (31).

2. The anti-radiation hardened silicon carbide MOSFET structure according to claim 1, wherein The first shielding region (32) is a P-type doped region.

3. The radiation-hardened silicon carbide MOSFET structure according to claim 1, wherein The second shielding region (33) is a P+ region.

4. The radiation-hardened silicon carbide MOSFET structure according to claim 1 or 3, characterized in that, A P-well region (34) is formed on the N-type silicon carbide (3). The P-well region (34) covers the outside of the second shielding region (33) and the source region (6). The surface of the P-well region (34) has a gap with the surface of the N-type silicon carbide (3), and the P-well region (34) wraps the second shielding region (33). The gap with a lateral distance forms a channel (35) where the N-type silicon carbide (3) contacts the second N-type polysilicon (62); or the surface of the P-well region (34) has no gap with the surface of the N-type silicon carbide (3), that is, there is no channel.

5. The radiation-hardened silicon carbide MOSFET structure according to claim 4, characterized in that, The N-type silicon carbide (3) includes an N buffer layer (3a), an N-type drift layer (3b), and a carrier storage layer (3c) provided in sequence from bottom to top. The groove (31), the first shielding region (32), the source region (6), the second shielding region (33), and the P-well region (34) are all located in the carrier storage layer (3c).

6. The radiation-hardened silicon carbide MOSFET structure according to claim 1, characterized in that, An interlayer dielectric (52) is formed between the polysilicon gate (5) and the source metal (4).

7. The radiation-hardened silicon carbide MOSFET structure according to claim 1, characterized in that, A gate dielectric (53) is formed between the gate oxide (51) and the polysilicon gate (5).

8. A preparation method of a radiation-hardened silicon carbide MOSFET, characterized in that, It includes the following steps: Step S1, forming an N-type silicon carbide (3) on the N substrate (2); Step S2: Inject carrier storage layer ions, P-type doping ions, and P+ ions into the N-type silicon carbide (3), and perform high-temperature annealing and activation to form a carrier storage layer (3c), a first shielding region (32), and a second shielding region (33) on the N-type silicon carbide (3). Both the first shielding region (32) and the second shielding region (33) are located within the carrier storage layer (3c). Step S3: Etch trenches (31) and N-well trenches (61) on the surface of the N-type silicon carbide (3). The first shielding region (32) covers the outside of the trench (31), and the second shielding region (33) covers the outside of the N-well trench (61). The trench (31) is located under the polysilicon gate (5), and the N-well trench (61) is located in the source region (6). Then, fill the trench (31) and the N-well trench (61) with the first N-type polysilicon (7) and the second N-type polysilicon (62) respectively. Step S4: Thermally oxidize to form a gate oxide (51) above the N-type silicon carbide (3). Step S5: Deposit a polysilicon gate (5) and an interlayer dielectric (52) above the gate oxide (51) to form a MOS structure. Step S6: Deposit a source metal (4) in the region between adjacent polysilicon gates (5), and make the source metal (4) contact the second N-type polysilicon (62). Step S7: Open the gate. Step S8: Deposit a thick source metal (4) above the interlayer dielectric (52) to form a source structure. Step S9: Form a drain metal (1) under the N-substrate (2).

9. The method for preparing a radiation-hardened silicon carbide MOSFET according to claim 8, characterized in that, In the step S2, before performing the high-temperature annealing and activation, it further includes injecting P-well ions into the N-type silicon carbide (3), so as to form a P-well region (34) on the N-type silicon carbide (3) after the high-temperature annealing and activation.

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