Relay and electronic equipment

Abstract

The invention discloses a relay and electronic equipment. The relay comprises an input end and an output end. Wherein the input end comprises at least one control signal receiving unit which is used for receiving a control signal; the control signal receiving unit at least comprises four P-type substrate high-voltage CMOS (Complementary Metal Oxide Semiconductor Transistor) tubes; the output end comprises at least one analog switch unit which is used for responding to the control signal of the control signal receiving unit and controlling the connection or disconnection of the target switch. According to the relay and the electronic equipment provided by the invention, the problems of input threshold stability and substrate bias effect of an existing electronic relay in high-voltage application can be solved, high stability and high reliability are kept, and the requirement of a modern electronic system for a high-performance relay is met.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a relay and an electronic device. Background Art

[0002] In modern electronic systems, relays are an important electronic switching element and are widely used to control the on and off of circuits. Traditional relays rely on mechanical movement, and drive the mechanical arm through the magnetic field generated by the electromagnetic coil to achieve circuit switching. However, mechanical relays have disadvantages such as slow response speed, easy wear and limited life.

[0003] With the development of integrated circuit technology, electronic relays have gradually replaced traditional mechanical relays. Electronic relays use CMOS technology to control the switch state through electronic signals, and have the advantages of fast response, no mechanical wear, and long life. However, existing electronic relays have some problems in high-voltage applications, especially in input threshold stability and offset effect. Summary of the invention

[0004] The present application provides a relay and an electronic device, which can improve the stability of the relay in terms of input threshold and solve the problem that the input threshold voltage varies with the power supply voltage due to the offset effect.

[0005] In a first aspect, an embodiment of the present application provides a relay, comprising an input end and an output end;

[0006] The input end includes at least one control signal receiving unit for receiving a control signal; the control signal receiving unit includes at least four P-type substrate high-voltage CMOS tubes;

[0007] The output end includes at least one analog switch unit, which is used to control the on or off of the target switch in response to the control signal of the control signal receiving unit.

[0008] Optionally, in some embodiments of the present application, the four P-type substrate high-voltage CMOS tubes in the control signal receiving unit include a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the first NMOS tube and the second NMOS tube are P-type substrate asymmetric high-voltage NMOS tubes, and the first PMOS tube and the second PMOS tube are P-type substrate symmetric high-voltage PMOS tubes.

[0009] Optionally, in some embodiments of the present application, the first PMOS tube and the second PMOS tube are connected to a preset logic voltage signal, and the cross-sectional structure of the first PMOS tube and the second PMOS tube includes:

[0010] P-type substrate;

[0011] An N-type buried layer is provided on the P-type substrate;

[0012] A device layer is arranged on the N-type buried layer, and the device layer includes a first source region, a first gate region, a first drain region, a first isolation region and a second isolation region, the first source region and the first gate region are respectively arranged on both sides of the first gate region, the first isolation region is arranged on a side of the first source region away from the first gate region, and the second isolation region is arranged on a side of the first drain region away from the first gate region.

[0013] Optionally, in some embodiments of the present application, the cross-sectional structures of the first NMOS transistor and the second NMOS transistor include:

[0014] P-type substrate;

[0015] An N-type buried layer is provided on the P-type substrate;

[0016] A device layer is arranged on the N-type buried layer, and the device layer includes a second source region, a second drain region, a third isolation region, a fourth isolation region and a fifth isolation region, the second drain region and the third isolation region are respectively arranged on both sides of the second source region, the fourth isolation region is arranged on a side of the third isolation region away from the second source region, and the fifth isolation region is arranged on a side of the second drain region away from the second source region.

[0017] Optionally, in some embodiments of the present application, the source of the first PMOS tube and the source of the second PMOS tube are respectively connected to their respective substrates and connected to a preset logic voltage signal, and the source of the first NMOS tube and the source of the second NMOS tube are respectively connected to their respective substrates and grounded.

[0018] Optionally, in some embodiments of the present application, the control signal receiving unit also includes a first resistor, a first diode and a second diode, one end of the first resistor is respectively connected to the anode of the first diode and the cathode of the second diode, the other end of the first resistor is respectively connected to the gate of the first PMOS tube and the gate of the first NMOS tube, the cathode of the first diode is connected to the positive power supply voltage, the anode of the second diode is connected to the negative power supply voltage, the source of the first PMOS tube is connected to the source of the second PMOS tube and is connected to a preset logic voltage signal, the source of the first NMOS tube is connected to the source of the second NMOS tube and is grounded, and the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube are connected in common.

[0019] Optionally, in some embodiments of the present application, the analog switch unit includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, the gate of the third PMOS tube is respectively connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the source of the third PMOS tube is connected to the positive power supply voltage, the drain of the third PMOS tube is respectively connected to the gate of the fourth PMOS tube and the drain of the third NMOS tube, the source of the third NMOS tube is connected to the negative power supply voltage, the gate of the fourth PMOS tube is connected to the positive power supply voltage, the source of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and connected to one end of the target switch, and the drain of the fourth PMOS tube is connected to the source of the fourth NMOS tube and connected to the other end of the target switch.

[0020] Optionally, in some embodiments of the present application, the relay also includes a signal processing unit, which is respectively connected to the control signal receiving unit and the analog switch unit, and the signal processing unit is used to perform signal processing on the control signal and convert the control signal into a switching signal for driving the analog switch unit.

[0021] Optionally, in some embodiments of the present application, the first end of the signal processing unit is respectively connected to the source of the first PMOS tube and the source of the second PMOS tube and connected to a preset logic voltage signal, the second end of the signal processing unit is respectively connected to the drain of the second PMOS tube and the drain of the second NMOS tube, the third end of the signal processing unit is respectively connected to the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube, the fourth end of the signal processing unit is respectively connected to the source of the first NMOS tube and the source of the second NMOS tube and grounded, the fifth end of the signal processing unit is connected to the source of the third PMOS tube and connected to the positive power supply voltage, the sixth end of the signal processing unit is connected to the source of the third NMOS tube and connected to the negative power supply voltage, and the seventh end of the signal processing unit is respectively connected to the gate of the third PMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube.

[0022] In a second aspect, an embodiment of the present application further provides an electronic device, comprising the relay as described above.

[0023] In summary, the embodiment of the present application provides a relay and an electronic device, wherein the relay includes an input end and an output end, wherein the input end includes at least one control signal receiving unit for receiving a control signal; the control signal receiving unit includes at least four P-type substrate high-voltage CMOS tubes; the output end includes at least one analog switch unit for responding to the control signal of the control signal receiving unit to control the on or off of the target switch. The relay and electronic device provided by the embodiment of the present application achieve the stability of the input threshold through an innovative circuit design, and can maintain the stability of the circuit performance even when the power supply voltage changes; at the same time, the isolation structure is optimized by utilizing the easy isolation characteristics of the PMOS tube in the P-type substrate process, avoiding the mutual influence between different voltage reference components, and solving the problem of the input threshold voltage changing with the power supply voltage caused by the lining bias effect by improving the design of the PMOS and NMOS tubes. It can be seen that the relay and electronic device provided by the embodiment of the present application can solve the problems of input threshold stability and lining bias effect in existing electronic relays in high-voltage applications, maintain high stability and high reliability, and meet the needs of high-performance relays in modern electronic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a schematic diagram of the structure of a relay provided in an embodiment of the present application;

[0026] Figure 2 Schematic diagram of the circuit principle of the relay provided in the embodiment of the present application;

[0027] Figure 3 It is a schematic cross-sectional structure diagram of a P-type substrate process symmetrical high-voltage PMOS tube provided in an embodiment of the present application;

[0028] Figure 4 It is a schematic cross-sectional structure diagram of an asymmetric isolated high-voltage NMOS tube using a P-type substrate process provided in an embodiment of the present application;

[0029] Figure 5 It is a schematic diagram of the circuit principle of the existing relay provided in the embodiment of the present application;

[0030] Figure 6 It is a schematic cross-sectional structure diagram of a symmetrical high-voltage NMOS tube using an N-type substrate process provided in an embodiment of the present application;

[0031] Figure 7 is a schematic cross-sectional structure diagram of a symmetrical high-voltage PMOS in an N-type substrate process provided in an embodiment of the present application;

[0032] Figure 8 It is a schematic diagram of the change of the threshold voltage Vint of the input terminal of the existing relay according to the embodiment of the present application with Vdd;

[0033] Fig. 9 1 is a schematic diagram comparing the change of the input terminal threshold voltage Vint of the relay provided in this embodiment and the existing relay with Vdd.

[0034] Among them, the diagram illustrates: 10-control signal receiving unit; 20-analog switch unit; 30-signal processing unit; P1-first PMOS tube; P2-second PMOS tube; MP1-third PMOS tube; MP2-fourth PMOS tube; N1-first PNMOS tube; N2-second NMOS tube; MN1-third NMOS tube; MN2-fourth NMOS tube; Rin-first resistor; D1-first diode; D2-second diode. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0038] Relay is a commonly used electronic component. By applying high or low voltage levels to the relay control end, the switch is turned on or off. It is widely used in application scenarios where weak signals are used to control the connection or disconnection of electronic circuits. Traditional relays use the electromagnetic force of an inductor to close / open a mechanical switch. A certain amount of electrical power needs to be input into the inductor to make it work properly. New foreign electronic relays use integrated circuit technology and use CMOS circuits to drive CMOS transmission gates to turn the switch on or off. Integrated circuit chips replace traditional mechanical switches. The characteristic is that the energy requirements of the input control signal are greatly reduced. Only the CMOS input circuit needs to be driven, and the signal current can be as small as nA (10 -9 A) level, and the electronic switch is completely noiseless, spark-free, long service life and high reliability. Foreign electronic relays use N-type substrate high-voltage CMOS integrated circuit process to design and produce electronic relay chips. The body end of all PMOS tubes can only be connected to the highest potential Vdd, which causes the PMOS tube with the input source connected to VL to have a liner bias effect, affecting the stability of the input threshold. At present, the high-voltage CMOS process of domestic integrated circuit production lines generally uses P-type substrates and P-type epitaxy. There are low-voltage input and high-voltage output circuits with different voltage references in electronic relay integrated circuits. The isolation of components with different voltage references and the MOS tube liner bias effect will have a huge impact on the normal operation and circuit performance of the circuit. Changes in substrate materials bring many challenges to line connection methods and component selection.

[0039] See also Figure 1 , Figure 1 The structural schematic diagram of the relay provided in the embodiment of the present application, the relay in the present embodiment may specifically include an input end and an output end, wherein the input end includes at least one control signal receiving unit 10 for receiving a control signal; the control signal receiving unit 10 includes at least four P-type substrate high-voltage CMOS tubes; the output end includes at least one analog switch unit 20 for responding to the control signal of the control signal receiving unit 10 to control the connection or disconnection of the target switch.

[0040] Specifically, the core of the input end of the relay provided in this embodiment is the control signal receiving unit 10, which is responsible for receiving external control signals. The unit is composed of at least one component, but in order to improve stability and reliability, it may specifically include multiple components. The control signal receiving unit 10 is composed of at least four P-type substrate high-voltage CMOS tubes, which are the basis of the control signal receiving unit 10 and are used to process the input control signal. The output end includes at least one analog switch unit 20, and the function of the analog switch unit 20 is to control the state of the target switch according to the control signal received at the input end, that is, to turn on or off. The target switch refers to the device or circuit part that the relay ultimately controls, and the change of its state, whether it is on or off, is determined by the analog switch unit 20 according to the control signal.

[0041] It should be noted that the CMOS tube in this embodiment is particularly suitable for high voltage environments and can work stably at higher voltages, which is crucial to the performance of the relay. The control signal can be a digital signal (such as a high level or a low level) or an analog signal (such as a continuous change in voltage or current). The design of the relay needs to be able to accurately identify and respond to these signals. The analog switch unit can contain various types of electronic components, such as transistors, diodes, resistors, etc., which work together to achieve accurate control of the target switch.

[0042] Since the present embodiment adopts a P-type substrate high-voltage CMOS tube, the relay can work stably within a wider voltage range, improving its adaptability and reliability in different application scenarios; the design of the control signal receiving unit enables the relay to respond quickly to the control signal and achieve fast switching action, which is particularly important for circuits that require fast switching. Compared with traditional mechanical relays, electronic relays consume almost no additional energy during the switching process, which helps to reduce the energy consumption of the entire system. Since electronic relays have no mechanical contact, there is no wear problem and they have a longer service life. Through innovative design, the input threshold of the relay will not change due to changes in the power supply voltage Vdd, ensuring stability under different working conditions.

[0043] Optionally, in some embodiments, the four P-type substrate high-voltage CMOS tubes in the control signal receiving unit include a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the first NMOS tube and the second NMOS tube are P-type substrate asymmetric high-voltage NMOS tubes, and the first PMOS tube and the second PMOS tube are P-type substrate symmetric high-voltage PMOS tubes.

[0044] Specifically, Figure 2 As shown, the control signal receiving unit 10 in this embodiment includes four specific CMOS tubes, namely a first NMOS tube, a second NMOS tube N2, a first PMOS tube P1 and a second PMOS tube P2. The first NMOS tube and the second NMOS tube N2 are designed as asymmetric high-voltage NMOS tubes on a P-type substrate, so that they work on a P-type substrate while maintaining stability and performance under high voltage. The first PMOS tube P1 and the second PMOS tube P2 are designed as symmetric high-voltage PMOS tubes on a P-type substrate. Unlike NMOS tubes, PMOS tubes are more easily designed with symmetrical high voltage on a P-type substrate, which helps to improve the overall performance and stability of the circuit. In addition, the first PMOS tube P1 and the second PMOS tube P2 are also connected to a preset logic voltage signal, which can receive and respond to a specific voltage level, thereby triggering the switching action of the relay.

[0045] It should be noted that the asymmetric high-voltage NMOS tube design in this embodiment allows the NMOS tube to operate in a high-voltage environment while maintaining a low on-resistance and a high switching speed, while the symmetrical design of the symmetrical high-voltage PMOS tube helps to reduce the parasitic capacitance effect of the PMOS tube under high voltage, improve the switching speed and reduce power consumption. The access of the logic voltage signal provides the relay with an interface compatible with digital circuits, enabling it to respond to common digital logic levels such as 5V or 3.3V. The use of a P-type substrate high-voltage CMOS process can better control the threshold voltage of the transistor and reduce performance changes caused by substrate effects.

[0046] The asymmetric and symmetric high-voltage CMOS tube designs in this embodiment improve the stability of the relay in a high-voltage environment and reduce malfunctions caused by voltage fluctuations; by accessing a logic voltage signal, the relay can be seamlessly integrated with an existing digital circuit system, thereby improving application flexibility; the symmetrically designed PMOS tube reduces parasitic effects, improves the switching speed of the relay and reduces power consumption, thereby optimizing overall performance; by using a P-type substrate process, the design of the high-voltage CMOS tube is simplified, and the design complexity caused by the substrate effect is reduced; the problem of the input threshold voltage changing with Vdd due to the substrate bias effect is avoided, thereby ensuring the stable operation of the relay under different power supply voltages.

[0047] In a specific embodiment, in order to be compatible with TTL / CMOS signal reception, a circuit suitable for a 5V logic level is designed at the circuit input end, and the power supply voltage of the input circuit is 5V. Figure 2 The circuit on the left of the core module. The right side of the core module is the high-voltage output circuit. The MP2 and MN2 on the far right of the circuit form an analog switch. D and S are the two ends of the switch. The power supply voltage range Vdd / Vss is ±5~±22V to adapt to different application scenarios. Vdd / Vss is the positive and negative power supply, usually ±15V, GND is the reference potential 0V, and VL is 5V.

[0048] It should be noted that in this embodiment, Vdd represents the positive power supply voltage of the circuit. In CMOS technology, Vdd is the power supply voltage provided to the PMOS transistor and is the main power supply voltage in most digital and analog circuits. Vss represents the negative power supply voltage or ground of the circuit. In CMOS technology, Vss is usually connected to the bulk and substrate of the NMOS transistor as a reference potential point of the circuit. IN usually represents the input terminal or input signal. In an electronic relay or switch circuit, IN may be a control signal input terminal for receiving a signal that triggers a switch action. VL represents a preset logic voltage signal, representing a logic voltage level, especially a voltage level lower than Vdd. In the circuit design in this embodiment, VL can be a voltage level for compatibility with low-voltage logic signals, such as a 5V logic level, to ensure that the circuit can receive and process signals from a low-voltage source.

[0049] Optionally, in some embodiments, the first PMOS transistor and the second PMOS transistor are connected to a preset logic voltage signal, and the cross-sectional structure of the first PMOS transistor and the second PMOS transistor includes:

[0050] P-type substrate;

[0051] An N-type buried layer is provided on a P-type substrate;

[0052] The device layer is arranged on the N-type buried layer, and the device layer includes a first source region, a first gate region, a first drain region, a first isolation region and a second isolation region. The first source region and the first gate region are respectively arranged on both sides of the first gate region, the first isolation region is arranged on the side of the first source region away from the first gate region, and the second isolation region is arranged on the side of the first drain region away from the first gate region.

[0053] Specifically, Figure 3As shown, the cross-sectional structure of the first PMOS transistor P1 and the second PMOS transistor P2 in this embodiment includes a P-type substrate, an N-type buried layer and a device layer, wherein the P-type substrate constitutes the basis of the transistor, and all components are built on this substrate; the N-type buried layer is arranged on the P-type substrate, and provides an N-type semiconductor region for the transistor, which helps to form a PN junction and is a key part of the transistor; the device layer is arranged on the N-type buried layer, and includes multiple functional regions: a first source region, which serves as one of the sources of the transistor; a first gate region, which serves as a gate region for controlling the conduction or cutoff of the transistor; a first drain region, which serves as a drain region of the transistor; a first isolation region and a second isolation region, which are used to isolate different functional regions and ensure the normal operation of the transistor. The first source region and the first drain region are respectively arranged on both sides of the first gate region, and this layout helps to effectively control the transistor. A first isolation region is arranged on the side of the first source region away from the first gate region, and a second isolation region is arranged on the side of the first drain region away from the first gate region, and these isolation regions help to prevent mutual interference between different regions.

[0054] It should be noted that the working principle of the PMOS tube in this embodiment is based on a PN junction, wherein a P-type substrate and an N-type buried layer form a PN junction, and the gate region controls the conductive channel between the source and the drain through an electric field; by setting an isolation region between different regions of the transistor, parasitic capacitance and leakage current can be reduced, and the performance and reliability of the transistor can be improved; the high-voltage CMOS process allows the transistor to operate at a high voltage, which is crucial for high-voltage applications of relays; the first PMOS tube P1 and the second PMOS tube P2 adopt a symmetrical design, which helps to reduce performance differences caused by layout asymmetry and improve the consistency and reliability of the circuit.

[0055] This embodiment improves the stability of transistors in high-voltage environments through precise transistor design and isolation technology; symmetrical transistor design helps to reduce performance differences and improve the overall performance of the circuit; the use of isolation areas reduces mutual interference between different functional areas and improves the anti-interference ability of the circuit; reasonable layout of the gate, source and drain helps to improve the control efficiency and response speed of the transistor; the application of high-voltage CMOS technology enables the relay to adapt to a wider range of high-voltage application scenarios; by optimizing the transistor design, more functions can be integrated in a limited space, thereby improving the integration of integrated circuits; the use of P-type substrate technology simplifies the design of high-voltage PMOS tubes and reduces the design complexity caused by substrate effects. As stated in the technical briefing, this design helps to avoid the problem of input threshold voltage changing with Vdd, thereby ensuring stable operation of the circuit.

[0056] Optionally, in some embodiments, the cross-sectional structure of the first NMOS transistor and the second NMOS transistor includes:

[0057] P-type substrate;

[0058] An N-type buried layer is provided on a P-type substrate;

[0059] The device layer is arranged on the N-type buried layer, and the device layer includes a second source region, a second drain region, a third isolation region, a fourth isolation region and a fifth isolation region. The second drain region and the third isolation region are respectively arranged on both sides of the second source region, the fourth isolation region is arranged on the side of the third isolation region away from the second source region, and the fifth isolation region is arranged on the side of the second drain region away from the second source region.

[0060] Specifically, Figure 4 As shown, the cross-sectional structure of the first NMOS tube and the second NMOS tube N2 in this embodiment includes a P-type substrate, an N-type buried layer, and a device layer; wherein, the P-type substrate, like the PMOS tube, the NMOS tube is also built on the P-type substrate, which is the basic part of the transistor; the N-type buried layer, arranged on the P-type substrate, provides an N-type semiconductor region for the NMOS tube, which helps to form a PN junction; the device layer, arranged on the N-type buried layer, includes multiple functional regions: the second source region serves as the source region of the transistor; the second drain region serves as the drain region of the transistor; the third isolation region, the fourth isolation region, and the fifth isolation region are used to isolate different functional regions to ensure the normal operation of the transistor; the second drain region and the third isolation region are respectively arranged on both sides of the second source region, and this layout helps to effectively control the transistor. The fourth isolation region is arranged on the side of the third isolation region away from the second source region, and the fifth isolation region is arranged on the side of the second drain region away from the second source region, and these isolation regions help to prevent mutual interference between different regions.

[0061] It should be noted that the NMOS tube in this embodiment adopts an asymmetric structure design, and the size or layout of the source and drain regions are not exactly the same. This design can optimize the performance of specific applications; the asymmetric high-voltage NMOS tube design allows the transistor to operate stably in a high-voltage environment while maintaining a low on-resistance and a high switching speed; by setting an isolation area between different areas of the transistor, the parasitic capacitance and leakage current can be reduced, and the performance and reliability of the transistor can be improved; the high-voltage CMOS process allows the transistor design to adapt to higher voltages, which is crucial for high-voltage applications of relays.

[0062] The application of asymmetric structure and isolation technology in this embodiment improves the stability of NMOS tube in high-voltage environment; asymmetric design helps to optimize the performance of transistor, especially in terms of switching speed and on-resistance; the use of isolation area reduces mutual interference between different functional areas and improves the anti-interference ability of the circuit; reasonable source and drain area layout helps to improve the control efficiency and response speed of the transistor; the application of high-voltage CMOS process enables the relay to adapt to a wider range of high-voltage application scenarios; the asymmetric isolation structure of NMOS tube in P-type substrate process helps to avoid the liner bias effect and ensure the stability of the threshold voltage of the circuit input end, which does not change with Vdd.

[0063] Optionally, in some embodiments, the source of the first PMOS tube and the source of the second PMOS tube are respectively connected to their respective substrates and connected to a preset logic voltage signal, and the source of the first NMOS tube and the source of the second NMOS tube are respectively connected to their respective substrates and grounded.

[0064] Specifically, in this embodiment, the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are respectively connected to their respective substrates, which helps to simplify the circuit design and reduce the unstable factors caused by the substrate effect. The source of the PMOS transistor connected to the substrate is simultaneously connected to a preset logic voltage signal, so that the PMOS transistor can respond to the logic voltage signal to achieve control of the circuit. Figure 2 As shown, the source of the first NMOS tube and the source of the second NMOS tube N2 are respectively connected to their respective substrates and grounded, which helps to stabilize the working state of the NMOS tubes and avoid instability caused by power supply voltage fluctuations.

[0065] In this embodiment, the source of the PMOS tube is connected to the substrate to reduce parasitic capacitance and resistance, improve the switching speed and efficiency of the transistor, and the access to the logic voltage signal allows the PMOS tube to respond to the control signal of the digital circuit, thereby improving the compatibility and flexibility of the relay. The source grounding of the NMOS tube helps to provide a stable reference potential and reduce the impact of power supply noise on circuit performance. In the high-voltage CMOS process, the design of the PMOS tube and the NMOS tube needs to take into account the stability and reliability under the high-voltage environment.

[0066] It can be seen that the connection method between the source and substrate of the PMOS tube and the NMOS tube in this embodiment helps to improve the stability of the circuit under high voltage environment; the access of the logic voltage signal improves the compatibility of the relay and the digital circuit system; the grounding of the source of the NMOS tube helps to reduce the influence of power supply noise on the circuit performance and improve the clarity of the signal; the connection method between the source and the substrate helps to improve the switching speed and efficiency of the transistor and optimize the overall performance of the circuit; the source of the PMOS tube is connected to the substrate and accessed with the logic voltage signal, and the source of the NMOS tube is grounded. This design helps to avoid the problem of unstable input threshold voltage caused by substrate effect.

[0067] In order to facilitate understanding of the relay designed based on the P-type substrate high-voltage CMOS integrated circuit process provided in the embodiment of the present application, the differences between the prior art and the present application will be described in detail below.

[0068] like Figure 5 As shown, the existing electronic relay is designed using an N-type substrate high-voltage CMOS integrated circuit process, and the N-type substrate in the chip is connected to the highest potential Vdd; in integrated circuit design, if PN junction isolation is to be achieved, the potential of the adjacent P and N diffusion regions, the N region must be higher than the P region; in the N-type substrate process, the NMOS tube is easy to implement an isolation structure, in which the source (Source) of the NMOS tube and the bulk (Bulk) P-type region under the gate can be disconnected from the lowest potential Vss on the chip, and the NMOS has no substrate bias effect (hereinafter referred to as "substrate bias effect"), and its threshold voltage does not change with the circuit bias voltage, and the performance is stable. Figure 5 N1 and N2 are such NMOS tubes. Figure 6 As shown, Figure 6 This is the cross-sectional structure of the NMOS tube in the existing relay. However, it is not easy to realize the isolation structure of the PMOS tube in the N-type substrate process. Figure 5 As can be seen, the bulk of P1 and P2 are both connected to the highest potential Vdd on the chip.

[0069] like Figure 7 As shown, Figure 7 The cross-sectional structure of P1 and P2 shows that the bulk under the gate region is directly connected to the N-substrate (N-sub), and N-sub is connected to Vdd. The connection between P1 and P2 makes the threshold voltage change with the Vdd potential, thus making Figure 5 The threshold voltage of the circuit input terminal (IN) changes with Vdd. If the input terminal threshold voltage Vint drops below the maximum input low level (usually 0.8V) within the operating voltage range, the normal function of the circuit will be destroyed. Figure 8 As shown, Figure 8 It is a schematic diagram of the change of the input terminal threshold voltage Vint of the existing relay with Vdd.

[0070] The relay provided in the present application is designed using a P-type substrate high-voltage CMOS integrated circuit process. In the P-type substrate high-voltage CMOS integrated circuit process, the P-sub is connected to the lowest potential Vss in the circuit. Unlike the N-type substrate process, the PMOS tube is easy to isolate, while the NMOS is not easy to isolate. In order to solve the problem that the input threshold voltage Vint decreases with the increase of Vdd due to the liner bias effect, based on the characteristic that the PMOS tube with a P-type substrate is easy to isolate, the body (Bulk) of the input PMOS tube is connected to Vdd (see the Vdd of the existing relay) in the design. Figure 2 ) is changed to VL, the new input PMOS tube cross-section is as follows Figure 3 As shown, in Figure 3 In the cross-sectional structure, the P-sub is connected to the lowest potential Vss in the circuit, and the N-well (Bulk) under the gate is connected to the N-buried layer below and the N-wells on both sides. The potential connected to this N-type region is always higher than the lowest potential Vss in the circuit, and a reverse-biased PN junction isolation is formed between it and the P-sub, allowing the Bulk end of the PMOS tube to have a different potential from the P-sub junction; and the N-type region surrounds the P-well in the source (Source) and drain (Drain) regions of the PMOS tube to form an isolation structure. Even if there is no N-buried layer, since the Bulk potential is always higher than the P-sub connected to the lowest potential, the Bulk can also be connected to other potentials without destroying the isolation relationship of the PN junction N high and P low. This is why the PMOS tube is easy to isolate in the P-type substrate process. The source (Source) and body (Bulk) of the PMOS tube can be directly connected to avoid the liner bias effect of the PMOS tube.

[0071] The next question is how to design the NMOS transistor, which is difficult to isolate in the P-type substrate process, so that its bulk potential can be structurally disconnected from the P-sub. Figure 2 The input NMOS tubes N1 and N2 are designed as follows Figure 4 The asymmetric isolated high-voltage NMOS tube structure shown in the figure cleverly utilizes the characteristics that the Bulk in the asymmetric structure surrounds the n-type source (Source), and the drain (Drain) potential of the NMOS tube is higher than the Bulk. By burying N under the Bulk and drain (Drain) regions, the Bulk of the NMOS tube is isolated from the P-sub, so that the Bulk and source (Source) potentials do not need to be connected to the P-sub (connected to Vss). With this NMOS tube, its Bulk can be connected to the source (Source) and connected to GND, avoiding the liner bias effect of the NMOS tube.

[0072] visible, Figure 2The P1, P2, N1, and N2 of the input stage all adopt the design of bulk and source connection, which avoids the bias effect of the input tube, making the threshold voltage Vint of the circuit input end basically in the middle of VL~GND and does not change with Vdd. Fig. 9 As shown, Fig. 9 A is a comparison diagram of the input terminal threshold voltage Vint of the relay provided in this embodiment and the existing relay with Vdd, A is the curve of the input terminal threshold voltage Vint of the existing relay with Vdd, and B is the comparison curve of the input terminal threshold voltage Vint of the relay provided in this embodiment with Vdd. Fig. 9 It can be seen that the present invention adopts a P-type substrate process design and uses PMOS and NMOS tubes with an isolation structure to completely avoid the electronic relay input terminal threshold voltage Vint changing with Vdd, thereby realizing a high-voltage CMOS electronic relay with a stable input threshold.

[0073] Optionally, in some embodiments, the control signal receiving unit also includes a first resistor, a first diode and a second diode, one end of the first resistor is respectively connected to the anode of the first diode and the cathode of the second diode, the other end of the first resistor is respectively connected to the gate of the first PMOS tube and the gate of the first NMOS tube, the cathode of the first diode is connected to the positive power supply voltage, the anode of the second diode is connected to the negative power supply voltage, the source of the first PMOS tube is connected to the source of the second PMOS tube and is connected to a preset logic voltage signal, the source of the first NMOS tube is connected to the source of the second NMOS tube and is grounded, and the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube are connected in common.

[0074] Specifically, Figure 2As shown, the circuit structure of the control signal receiving unit 10 of the relay in this embodiment includes a first resistor Rin, a first diode D1 and a second diode D2. Among them, the first resistor Rin plays a role of voltage division and current limiting in the circuit, one end of which is connected to the positive electrode of the first diode D1 and the negative electrode of the second diode D2, and the other end is connected to the gate of the first PMOS tube P1 and the gate of the first NMOS tube. The negative electrode of the first diode D1 is connected to the positive power supply voltage, which ensures that the diode is in a forward conduction state, allowing current to flow from the positive power supply to the resistor. The positive electrode of the second diode D2 is connected to the negative power supply voltage, which also ensures that the diode is forward-conducted, allowing current to flow from the resistor to the negative power supply. In a specific embodiment, the source of the first PMOS tube P1 is connected to the source of the second PMOS tube P2 and is connected to a preset logic voltage signal to form a common source connection of the PMOS tubes; the source of the first NMOS tube is connected to the source of the second NMOS tube N2 and is grounded to form a common source connection of the NMOS tubes; the drain of the first PMOS tube P1, the gate of the second PMOS tube P2, the drain of the first NMOS tube and the gate of the second NMOS tube N2 are connected in common. This configuration helps to realize the logic control function of the circuit.

[0075] It should be noted that the access of the diode provides a protection mechanism for the circuit to prevent reverse voltage from damaging the transistor; through the cooperation of the resistor and the diode, the control signal can be stably provided to the gate of the PMOS and NMOS tubes to ensure the accuracy of the logic signal; the access method of the diode makes full use of the positive and negative power supply voltages to provide a stable operating point for the circuit; this circuit design allows the parameters of the resistor and diode to be flexibly adjusted to meet different application requirements.

[0076] This embodiment ensures the stability and reliability of the control signal through precise circuit design; the connection of the diode provides reverse voltage protection for the circuit and improves the safety of the circuit; the coordinated use of the resistor and the diode optimizes the signal processing process and reduces signal noise; this circuit design improves the compatibility of the relay with different power supply voltage systems; through reasonable circuit design, the problem of unstable input threshold voltage caused by substrate effect is avoided, ensuring the stable operation of the circuit under different power supply voltages.

[0077] Optionally, in some embodiments, the analog switch unit includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, the gate of the third PMOS tube is respectively connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the source of the third PMOS tube is connected to the positive power supply voltage, the drain of the third PMOS tube is respectively connected to the gate of the fourth PMOS tube and the drain of the third NMOS tube, the source of the third NMOS tube is connected to the negative power supply voltage, the gate of the fourth PMOS tube is connected to the positive power supply voltage, the source of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and connected to one end of the target switch, and the drain of the fourth PMOS tube is connected to the source of the fourth NMOS tube and connected to the other end of the target switch.

[0078] Specifically, Figure 2 As shown, the analog switch unit 20 in this embodiment includes a third PMOS transistor MP1, a fourth PMOS transistor MP2, a third NMOS transistor MN1 and a fourth NMOS transistor MN2, which work together to respond to the signal of the control signal receiving unit 10 to control the target switch. Among them, the gate of the third PMOS tube MP1 is simultaneously connected to the gate of the third NMOS tube MN1 and the gate of the fourth NMOS tube MN2. This configuration allows the PMOS tube to synchronously control the NMOS tube according to the control signal; the source of the third PMOS tube MP1 is connected to the positive power supply voltage to provide power for it; the drain of the third PMOS tube MP1 is connected to the gate of the fourth PMOS tube MP2 and the drain of the third NMOS tube MN1 to form a control loop of the PMOS tube; the source of the third NMOS tube MN1 is connected to the negative power supply voltage to provide power for it and define the conduction state of the NMOS tube; the gate of the fourth PMOS tube MP2 is connected to the positive power supply voltage, and the source of the fourth PMOS tube MP2 is connected to the drain of the fourth NMOS tube MN2 to form a control loop of the PMOS tube; the drain of the fourth PMOS tube MP2 is connected to the source of the fourth NMOS tube MN2 to form a control loop of the NMOS tube. By controlling the gate voltages of the third PMOS tube MP1 and the third NMOS tube MN1, the conduction and cutoff states between them can be controlled, and then the target switch connected between their drains and sources can be controlled.

[0079] In a specific embodiment, the design of the analog switch unit allows precise control of the state of the target switch, which is essential for achieving precise signal routing and load control; the access to positive and negative power supply voltages provides the necessary power for the analog switch, ensuring its normal operation; the synchronous control of PMOS and NMOS tubes helps to reduce noise and interference during the switching process; and the use of high-voltage CMOS technology can design an analog switch unit that can operate stably at higher voltages.

[0080] The design of the analog switch unit in this embodiment allows precise control of the target switch, thereby improving the performance of the relay; the synchronous control of the PMOS tube and the NMOS tube helps to reduce the noise and interference generated during the switching process; the design of the analog switch unit improves the compatibility of the relay with systems with different power supply voltages; the application of high-voltage CMOS technology enables the relay to adapt to a wider range of high-voltage application scenarios; through reasonable design, the problem of unstable input threshold voltage caused by substrate effect is avoided, ensuring the stable operation of the circuit under different power supply voltages.

[0081] Optionally, in some embodiments, the relay further includes a signal processing unit, which is respectively connected to the control signal receiving unit and the analog switch unit, and the signal processing unit is used to perform signal processing on the control signal and convert the control signal into a switch signal for driving the analog switch unit.

[0082] Specifically, the signal processing unit in this embodiment is a key component in the relay, responsible for receiving the signal of the control signal receiving unit and converting it into a switch signal suitable for driving the analog switch unit. Figure 2 As shown, the signal processing unit 30 in this embodiment is Figure 2 The core in the embodiment of the present invention is a core in which the first end of the signal processing unit 30 is connected to the source of the first PMOS tube P1 and the source of the second PMOS tube P2, and is connected to the preset logic voltage signal; the second end is connected to the drain of the second PMOS tube P2 and the drain of the second NMOS tube N2; the third end is connected to the drain of the first PMOS tube P1, the gate of the second PMOS tube P2, the drain of the first NMOS tube and the gate of the second NMOS tube N2; the fourth end is connected to the source of the first NMOS tube and the source of the second NMOS tube N2, and is grounded; the fifth end is connected to the source of the third PMOS tube MP1 and is connected to the positive power supply voltage; the sixth end is connected to the source of the third NMOS tube MN1 and is connected to the negative power supply voltage; the seventh end is connected to the gate of the third PMOS tube MP1, the gate of the third NMOS tube MN1 and the gate of the fourth NMOS tube MN2. The signal processing unit 30 processes and converts the received control signal appropriately through its multiple connection ends to generate a signal capable of driving the analog switch unit 20.

[0083] In a specific embodiment, the signal processing unit can adopt a variety of signal processing technologies, such as amplification, filtering, shaping, etc., to ensure the stability and reliability of the signal; the access to positive and negative power supply voltages provides the signal processing unit with the necessary power supply to ensure its normal operation; through the design of multiple connection terminals, the signal processing unit can process and convert signals more flexibly to adapt to different control requirements; using high-voltage CMOS technology, the signal processing unit can work stably in a higher voltage environment.

[0084] The design of the signal processing unit of this embodiment helps to improve the stability of the control signal and reduce noise and interference; by adopting a variety of signal processing technologies, the signal processing unit can process various control signals more effectively; the multi-terminal connection design improves the compatibility of the relay with different control signal systems; the application of high-voltage CMOS technology enables the relay to adapt to a wider range of high-voltage application scenarios.

[0085] Optionally, in some embodiments, the first end of the signal processing unit is respectively connected to the source of the first PMOS tube and the source of the second PMOS tube and connected to a preset logic voltage signal, the second end of the signal processing unit is respectively connected to the drain of the second PMOS tube and the drain of the second NMOS tube, the third end of the signal processing unit is respectively connected to the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube, the fourth end of the signal processing unit is respectively connected to the source of the first NMOS tube and the source of the second NMOS tube and grounded, the fifth end of the signal processing unit is connected to the source of the third PMOS tube and connected to the positive power supply voltage, the sixth end of the signal processing unit is connected to the source of the third NMOS tube and connected to the negative power supply voltage, and the seventh end of the signal processing unit is respectively connected to the gate of the third PMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube.

[0086] Specifically, Figure 2 As shown, the first end of the signal processing unit 30 in this embodiment is connected to the source of the first PMOS tube P1 and the second PMOS tube P2, and is connected to a preset logic voltage signal, which provides a stable reference voltage for the signal processing unit 30; the second end is connected to the drain of the second PMOS tube P2 and the drain of the second NMOS tube N2, which helps the signal processing unit 30 monitor and process the signals from these transistors; the third end is connected to the drain of the first PMOS tube P1, the gate of the second PMOS tube P2, the drain of the first NMOS tube and the gate of the second NMOS tube N2, which provides the signal processing unit 30 with a control signal. The fourth end is connected to the source of the first NMOS tube and the second NMOS tube N2 and grounded, which provides a ground reference for the signal processing unit 30; the fifth end is connected to the source of the third PMOS tube MP1 and connected to the positive power supply voltage, ensuring the power supply of the signal processing unit 30; the sixth end is connected to the source of the third NMOS tube MN1 and connected to the negative power supply voltage, providing a negative power supply for the signal processing unit 30; the seventh end is connected to the gates of the third PMOS tube MP1, the third NMOS tube MN1 and the fourth NMOS tube MN2, which allows the signal processing unit 30 to control the state of the analog switch unit 20. The signal processing unit 30 not only receives the control signals, but also performs necessary processing on these signals, such as amplification, shaping, filtering, etc., to ensure that the analog switch unit 20 can receive clear and accurate switch signals.

[0087] In a specific embodiment, the signal processing unit helps to maintain the integrity of the signal and reduce attenuation and distortion during transmission; the multi-terminal connection design of the signal processing unit allows more efficient power management and ensures the stability of the unit under different working conditions; the design of the signal processing unit provides a high degree of flexibility and can adapt to different signal characteristics and application requirements; using high-voltage CMOS technology, the signal processing unit can operate stably in a high-voltage environment while maintaining high performance.

[0088] It can be seen that this embodiment improves the stability and reliability of the signal through the multi-terminal connection and processing function of the signal processing unit; the design of the signal processing unit allows the control signal to be effectively amplified, shaped and filtered, thereby improving the performance of signal processing; the multi-terminal connection design helps to manage the power supply more effectively and ensure the stability of the signal processing unit under different working conditions; the design of the signal processing unit improves the compatibility of the relay with different control signal systems, and can adapt to different application requirements.

[0089] In some embodiments, the present application also provides an electronic device, comprising the relay of the above embodiment.

[0090] In summary, the embodiment of the present application provides a relay and an electronic device, wherein the relay includes an input end and an output end, wherein the input end includes at least one control signal receiving unit for receiving a control signal; the control signal receiving unit includes at least four P-type substrate high-voltage CMOS tubes; the output end includes at least one analog switch unit for responding to the control signal of the control signal receiving unit to control the on or off of the target switch. The relay and electronic device provided by the embodiment of the present application achieve the stability of the input threshold through an innovative circuit design, and can maintain the stability of the circuit performance even when the power supply voltage changes; at the same time, the isolation structure is optimized by utilizing the easy isolation characteristics of the PMOS tube in the P-type substrate process, avoiding the mutual influence between different voltage reference components, and solving the problem of the input threshold voltage changing with the power supply voltage caused by the lining bias effect by improving the design of the PMOS and NMOS tubes. It can be seen that the relay and electronic device provided by the embodiment of the present application can solve the problems of input threshold stability and lining bias effect in existing electronic relays in high-voltage applications, maintain high stability and high reliability, and meet the needs of high-performance relays in modern electronic systems.

[0091] It should be understood that "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0092] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0093] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0094] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0095] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0096] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A relay, It is characterized in that including input and output terminals; The input end includes at least one control signal receiving unit for receiving a control signal; the control signal receiving unit includes at least four P-type substrate high-voltage CMOS tubes; The output end includes at least one analog switch unit, which is used to control the on or off of the target switch in response to the control signal of the control signal receiving unit.

2. The relay according to claim 1, It is characterized in that The four P-type substrate high-voltage CMOS tubes in the control signal receiving unit include a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the first NMOS tube and the second NMOS tube are P-type substrate asymmetric high-voltage NMOS tubes, and the first PMOS tube and the second PMOS tube are P-type substrate symmetric high-voltage PMOS tubes.

3. The relay according to claim 2, It is characterized in that The first PMOS tube and the second PMOS tube are connected to a preset logic voltage signal, and the cross-sectional structure of the first PMOS tube and the second PMOS tube includes: P-type substrate; An N-type buried layer is provided on the P-type substrate; A device layer is arranged on the N-type buried layer, and the device layer includes a first source region, a first gate region, a first drain region, a first isolation region and a second isolation region, the first source region and the first gate region are respectively arranged on both sides of the first gate region, the first isolation region is arranged on a side of the first source region away from the first gate region, and the second isolation region is arranged on a side of the first drain region away from the first gate region.

4. The relay according to claim 2, It is characterized in that The cross-sectional structure of the first NMOS tube and the second NMOS tube includes: P-type substrate; An N-type buried layer is provided on the P-type substrate; A device layer is arranged on the N-type buried layer, and the device layer includes a second source region, a second drain region, a third isolation region, a fourth isolation region and a fifth isolation region, the second drain region and the third isolation region are respectively arranged on both sides of the second source region, the fourth isolation region is arranged on a side of the third isolation region away from the second source region, and the fifth isolation region is arranged on a side of the second drain region away from the second source region.

5. The relay according to claim 2, It is characterized in that The source of the first PMOS tube and the source of the second PMOS tube are respectively connected to their respective substrates and connected to a preset logic voltage signal, and the source of the first NMOS tube and the source of the second NMOS tube are respectively connected to their respective substrates and grounded.

6. The relay according to claim 2, It is characterized in that The control signal receiving unit also includes a first resistor, a first diode and a second diode, one end of the first resistor is respectively connected to the anode of the first diode and the cathode of the second diode, the other end of the first resistor is respectively connected to the gate of the first PMOS tube and the gate of the first NMOS tube, the cathode of the first diode is connected to the positive power supply voltage, the anode of the second diode is connected to the negative power supply voltage, the source of the first PMOS tube is connected to the source of the second PMOS tube and is connected to a preset logic voltage signal, the source of the first NMOS tube is connected to the source of the second NMOS tube and is grounded, and the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube are connected in common.

7. The relay according to claim 1, It is characterized in that The analog switch unit includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, the gate of the third PMOS tube is respectively connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the source of the third PMOS tube is connected to a positive power supply voltage, the drain of the third PMOS tube is respectively connected to the gate of the fourth PMOS tube and the drain of the third NMOS tube, the source of the third NMOS tube is connected to a negative power supply voltage, the gate of the fourth PMOS tube is connected to a positive power supply voltage, the source of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and connected to one end of the target switch, and the drain of the fourth PMOS tube is connected to the source of the fourth NMOS tube and connected to the other end of the target switch.

8. The relay according to any one of claims 1 to 7, It is characterized in that The relay further includes a signal processing unit, which is connected to the control signal receiving unit and the analog switch unit respectively, and is used to perform signal processing on the control signal and convert the control signal into a switch signal for driving the analog switch unit.

9. The relay according to claim 8, It is characterized in that The first end of the signal processing unit is respectively connected to the source of the first PMOS tube and the source of the second PMOS tube and connected to a preset logic voltage signal, the second end of the signal processing unit is respectively connected to the drain of the second PMOS tube and the drain of the second NMOS tube, the third end of the signal processing unit is respectively connected to the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube, the fourth end of the signal processing unit is respectively connected to the source of the first NMOS tube and the source of the second NMOS tube and grounded, the fifth end of the signal processing unit is connected to the source of the third PMOS tube and connected to the positive power supply voltage, the sixth end of the signal processing unit is connected to the source of the third NMOS tube and connected to the negative power supply voltage, and the seventh end of the signal processing unit is respectively connected to the gate of the third PMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube.

10. An electronic device, It is characterized in that Comprising a relay as described in any one of claims 1-9.

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