A multi-time programmable device and electronic equipment

Abstract

The present application discloses a multi-time programmable device and an electronic device, wherein the multi-time programmable device comprises a semiconductor layer; a well region and an isolation structure located in the semiconductor layer, wherein the isolation structure surrounds the well region; a selection transistor and a floating gate transistor, which are formed in the well region, wherein the floating gate of the floating gate transistor extends from above the well region to above the isolation structure; and a control gate, which is located above the isolation structure, and the control gate is opposite to the floating gate in a horizontal direction; wherein the floating gate and the control gate are isolated via an inter-gate dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate form a capacitor structure, and the control gate controls the potential of the floating gate. The multi-time programmable device of the present application reduces the device size and improves the coupling ratio between the control gate and the floating gate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a multi-time programmable device and electronic equipment. Background Art

[0002] Multi-Time Programmable Memory (MTP) is a non-volatile memory. The stored data will not disappear after power failure, and it can perform multiple data storage, reading, erasing and other operations. It is widely used in personal computers, electronic devices, mobile storage and other fields.

[0003] In order to be compatible with CMOS process, MTP generally adopts a single-layer floating gate structure, which is mainly composed of MOS floating gate transistors and MOS capacitors. The MOS floating gate transistors and MOS capacitors are respectively located in adjacent wells of different doping types (such as P well and N well).

[0004] In order to ensure the capacitive coupling efficiency of the control gate, the gate area of ​​the MOS capacitor is larger, resulting in an increase in the area of ​​the MTP unit structure. Summary of the invention

[0005] In view of the above problems, the purpose of the present application is to provide a multi-time programmable device and an electronic device, which can reduce the device size and improve the coupling ratio between the control gate and the floating gate.

[0006] According to one aspect of the present invention, there is provided a multi-time programmable device, comprising: a semiconductor layer; a well region and an isolation structure located in the semiconductor layer, the isolation structure surrounding the well region; a selection transistor and a floating gate transistor, formed in the well region, the floating gate of the floating gate transistor extending from above the well region to above the isolation structure; and a control gate, located above the isolation structure, the control gate being opposite to the floating gate in a horizontal direction; wherein the floating gate and the control gate are isolated by an inter-gate dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate constitute a capacitor structure, and the control gate controls the potential of the floating gate.

[0007] Optionally, the floating gate extends in the first axial direction, and includes a first portion located above the well region and a second portion located above the isolation structure; and the control gate surrounds the second portion of the floating gate.

[0008] Optionally, the control gate includes a first control gate, a second control gate, and a third control gate extending in the direction of the first axis, connecting one end of the first control gate and one end of the second control gate; the first control gate is opposite to the first side of the second part, the second control gate is opposite to the second side of the second part, the third control gate is opposite to the end of the second part away from the first part, and the first side and the second side of the second part are opposite.

[0009] Optionally, the capacitive coupling ratio between the control gate and the floating gate decreases as the thickness of the inter-gate dielectric layer increases.

[0010] Optionally, as the width of the overlapping portion of the floating gate and the control gate increases, the capacitive coupling ratio between the control gate and the floating gate first gradually increases and then approaches a saturation value.

[0011] Optionally, a gate dielectric layer is arranged between the select gate and the well region, between the floating gate and the well region, and between the control gate and the isolation structure; the gate dielectric layer between the select gate and the well region, the gate dielectric layer between the floating gate and the well region, and the gate dielectric layer between the control gate and the isolation structure have the same thickness; the select gate, the floating gate, and the control gate are located on the same horizontal plane.

[0012] Optionally, a lead-out structure is further included, wherein the lead-out structure is located in the well region, and the doping type of the well region is the same as the doping type of the lead-out structure.

[0013] Optionally, the selection gate of the selection transistor is connected to the word line, the drain region of the selection transistor is connected to the bit line, the source region of the selection transistor is connected to the source region of the floating gate transistor and connected to the source terminal, the drain region of the floating gate transistor is connected to the drain terminal, and the lead-out structure is connected to the back terminal.

[0014] Optionally, a negative voltage is applied to the control gate, a positive voltage is applied to the source and back ends, a positive voltage is applied to the select gate, and the electrons stored in the floating gate tunnel into the well region below the floating gate to achieve erasure; a positive voltage is applied to the control gate, the source and back ends are grounded, a positive voltage is applied to the select gate, and the electrons in the well region below the floating gate tunnel into the floating gate to achieve programming; a 0V voltage is applied to the control gate, a 0V voltage is applied to the back end, a negative voltage is applied to the source end, a negative voltage is applied to the select gate, the current of the bit line is read, and the current of the bit line is compared with a reference current to determine its storage type.

[0015] According to another aspect of the present invention, an electronic device is provided, comprising the multi-time programmable device mentioned above.

[0016] The unexpected technical effects of this application are:

[0017] In the multi-time programmable device of the present application, when the parameters of the floating gate are the same as those of the floating gate of the traditional MTP device, the capacitive coupling ratio of the present application is improved relative to the capacitive coupling ratio of the traditional MTP device, and the size of the control gate CG of the present application is reduced relative to the size of the control gate CG of the traditional MTP device.

[0018] Furthermore, the control gate CG of the present application is arranged above the isolation structure, which effectively avoids the leakage problem of the first well region and the second well region in the traditional MTP device, increases the operable voltage of the control gate CG, and improves the programming / erasing efficiency.

[0019] In the multi-time programmable device of the present application, the control gate is respectively opposite to the first side, the second side and the end of the second part of the floating gate away from the first part, and the control gate surrounds the second part of the floating gate, thereby increasing the coupling ratio between the control gate and the floating gate.

[0020] In the present application, the thickness of the inter-gate dielectric layer is gradually changed to obtain a corresponding curve between the capacitance coupling ratio and the thickness of the inter-gate dielectric layer, and the width of the overlapping portion of the floating gate FG and the control gate CG is gradually changed to obtain a corresponding curve between the capacitance coupling ratio and the width of the overlapping portion of the floating gate and the control gate. The size of the device can be optimized through the above corresponding curve. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0022] Figure 1a A schematic diagram of the top view of a conventional MTP device is shown;

[0023] Figure 1b Shows Figure 1a Cross-sectional view along AA direction;

[0024] Figure 1c Shows Figure 1a Cross-section along direction BB;

[0025] Figure 1d The circuit schematic diagram of the conventional MTP device is shown;

[0026] Figure 2 A schematic diagram showing a floating gate and a control gate in a conventional MTP device;

[0027] Figure 3a A schematic diagram of the top view of the MTP device of an embodiment of the present application is shown;

[0028] Figure 3b Shows Figure 3a Cross-sectional view along AA direction;

[0029] Figure 3c Shows Figure 3a Cross-section along direction BB;

[0030] Figure 3d A circuit schematic diagram of an MTP device according to an embodiment of the present application is shown;

[0031] Figure 4 A top view of a floating gate and a control gate according to an embodiment of the present application is shown;

[0032] Figure 5 The corresponding curve between the capacitance coupling ratio and the thickness of the inter-gate dielectric layer in the embodiment of the present application is shown;

[0033] Figure 6 The corresponding curve between the capacitance coupling ratio and the width of the overlapping portion between the floating gate and the control gate according to the embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0035] This application may be presented in a variety of forms, some examples of which are described below.

[0036] Figure 1a The top view of the structure of a conventional MTP device is shown. Figure 1b Shows Figure 1a Cross-sectional view along AA direction, Figure 1c Shows Figure 1a Cross-sectional view along BB direction, Figure 1d Figure 2 shows the circuit schematic diagram of a conventional MTP device. Figure 1a to Figure 1d As shown, the MTP device 10 includes a semiconductor layer 110, a first well region 120 of a second doping type located in the semiconductor layer 110, and a second well region 130 of a first doping type, wherein a selection transistor Q11 and a floating gate transistor Q12 are formed in the first well region 120, and a control transistor Q13 is formed in the second well region 130. In one embodiment, the first doping type is, for example, P-type doping, the second doping type is, for example, N-type doping, the first well region 120 is, for example, an N-well, and the second well region 130 is, for example, a P-well.

[0037] like Figure 1a and Figure 1bAs shown, the selection transistor Q11 includes a source region S1 and a drain region D1 located in the first well region 120 and a selection gate SG located on the first well region 120. The first well region 120 located below the selection gate SG and between the source region S1 and the drain region D1 constitutes a channel region HCla of the selection transistor. The floating gate transistor Q12 includes a source region S2 and a drain region D2 located in the first well region 120 and a floating gate FG located on the first well region 120. The first well region 120 located below the floating gate FG and between the source region S2 and the drain region D2 constitutes a channel region HClb of the floating gate transistor. The selection gate SG and the first well region 120, and the floating gate FG and the first well region 120 are isolated via a gate dielectric layer 150.

[0038] like Figure 1a and Figure 1c As shown, the control transistor Q13 includes a doping region 140 of the second doping type located in the second well region 130 and a control gate CG located on the second well region 130, and the doping region 140 surrounds the control gate CG. The control gate CG and the second well region 130 are isolated by a gate dielectric layer 150, and the gate dielectric layer 150 is, for example, a silicon oxide (SiO2) layer.

[0039] like Figure 1a , 1b As shown in 1d, the selection gate SG of the selection transistor Q11 is connected to the word line WL (Word Line), the drain region D1 is connected to the bit line BL (Bit Line), the source region S1 of the selection transistor Q11 is connected to the source region S2 of the floating gate transistor Q12, and the floating gate FG of the floating gate transistor Q12 is connected to the control gate CG of the control transistor Q13.

[0040] The conventional MTP device includes a floating gate transistor Q12 and a control transistor Q13, which are respectively located in two adjacent wells of different types, for example, the floating gate transistor is located in the first well region 120 (NW), and the control transistor is located in the second well region 130 (PW). In order to ensure the capacitive coupling efficiency of the control gate CG, the control gate CG area of ​​the control transistor is usually large, resulting in an increase in the area of ​​the MTP device.

[0041] Figure 2 FIG. 4 shows a schematic diagram of a floating gate FG and a control gate CG in a conventional MTP device. Figure 2 As shown, in the MTP device 10, the length of the channel region of the floating gate transistor Q12 is L HCIb , the width of the channel region of the floating gate transistor Q12 is W HCIb , the total width of the floating gate FG of the floating gate transistor Q12 is W CG , the total width W of the floating gate FG CG is the width W of the channel region of the floating gate transistor Q12 HCIb 11 times, that is, WCG =11W HCIb The length of the control gate CG is L C For example, the width of the control gate CG is W C Among them, the length L of the control gate CG C For example, the length L of the channel region of the floating gate transistor Q12 HCIb twice, that is, L C =2L HCIb , the width W of the control gate CG C For example, the width W of the channel region of the floating gate transistor Q12 HCIb 3 times, that is, W C =3W HCIb The capacitive coupling ratio CR of the MTP device 10 is 0.85.

[0042] Continue reading Figure 1b , the conventional MTP device is programmed by controlling the channel region HClb of the floating gate transistor Q12. Specifically, by controlling the transistor Q13 to apply voltage to the floating gate FG, an electric field is formed between the floating gate FG and the drain region D2 of the floating gate transistor Q12. The electrons in the channel region HClb of the floating gate transistor Q12 are attracted by the electric field between the floating gate FG and the drain region D2 of the floating gate transistor Q12, and are accelerated to collide with the interface (SiO2 / Si interface) between the gate dielectric layer 150 and the first well region 120 near the drain region D2 of the floating gate transistor Q12. Some electrons in the first well region 120 are attracted to the gate dielectric layer 150 (SiO2) or the floating gate FG, and the programming is completed. This programming method is inefficient, and only a very small number of channel hot electrons can be injected into the floating gate FG; the current required for programming is large and the power consumption is high.

[0043] Furthermore, the breakdown voltage (BV ) between the second well region 130 (PW) of the control transistor Q13 and the first well region 120 (NW) of the floating gate transistor Q12 is susceptible to process fluctuations, resulting in increased device leakage. The increase in leakage current reduces the operable voltage of the MTP device, thereby reducing the programming efficiency of the MTP device.

[0044] Figure 3a A schematic diagram of the top view of the MTP device of an embodiment of the present application is shown; Figure 3b Shows Figure 3a Cross-sectional view along AA direction, Figure 3c Shows Figure 3a Cross-sectional view along BB direction, Figure 3d FIG. 2 shows a circuit diagram of an MTP device according to an embodiment of the present application. Figure 3a to Figure 3d As shown, the MTP device 20 includes a semiconductor layer 210 , a well region 220 located in the semiconductor layer 210 , and an isolation structure 230 located in the semiconductor layer 210 and adjacent to the well region 220 .

[0045] The semiconductor layer 210 may be composed of any one or a combination of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. In this embodiment, the semiconductor layer 210 includes a semiconductor substrate 211 of a first doping type and a deep well region 212 of a second doping type. In one embodiment, the first doping type is, for example, P-type doping, the second doping type is, for example, N-type doping, and the deep well region 212 is, for example, a deep N well (DWN).

[0046] The well region 220 and the isolation structure 230 extend from the surface of the semiconductor layer 210 to the inside thereof and stop inside the semiconductor layer 210, specifically, extend from the surface of the deep well region 212 to the inside thereof and stop inside the deep well region 212. In other words, the well region 220 and the isolation structure 230 are located in the semiconductor layer 210 (deep well region 212) and exposed to the surface of the semiconductor layer 210 (deep well region 212). The isolation structure 230 surrounds the well region 220 and is adjacent to the well region 220. The well region 220 is of the second doping type, for example, N-well (NW).

[0047] A selection transistor Q21 and a floating gate transistor Q22 are formed in the well region 220. Figure 3b As shown, the selection transistor Q21 includes a source region S1 and a drain region D1 located in the well region 220 and a gate stack located on the well region 220. The floating gate transistor Q22 includes a source region S2 and a drain region D2 located in the well region 220 and a gate stack located on the well region 220. The source regions S1, S2 and the drain regions D1, D2 are doped regions in the well region 220. For example, for an N-type MOSFET, the source region and the drain region are N-type doped; for a P-type MOSFET, the source region and the drain region are P-type doped. In this embodiment, the selection transistor Q21 and the floating gate transistor Q22 are P-type MOSFETs, and the source regions S1, S2 and the drain regions D1, D2 are P-type doped. The gate stack of the selection transistor Q21 includes a gate dielectric layer 251 and a selection gate SG, and the gate dielectric layer 251 is sandwiched between the well region 220 and the selection gate SG. The gate stack of the floating gate transistor Q22 includes a gate dielectric layer 252 and a floating gate FG, and the gate dielectric layer 252 is sandwiched between the well region 220 and the floating gate FG.

[0048] The MTP device 20 includes a control gate CG, which is located above the isolation structure 230 and opposite to the floating gate FG. The control gate CG is isolated from the isolation structure 230 by a gate dielectric layer 253 , and is isolated from the floating gate structure FG by an inter-gate dielectric layer 254 .

[0049] The gate dielectric layers 251, 252, 253 and the inter-gate dielectric layer 254 are composed of, for example, silicon oxide (SiO2), and the selection gate SG, the floating gate FG and the control gate CG are composed of, for example, doped polysilicon. The gate dielectric layer 251 between the selection gate SG and the well region 220, the gate dielectric layer 252 between the floating gate FG and the well region 220, and the gate dielectric layer 253 between the control gate CG and the isolation structure 230 have the same thickness, and the selection gate SG, the floating gate FG and the control gate CG are located on the same horizontal plane to ensure that the floating gate FG and the control gate CG are opposite in the horizontal direction.

[0050] The MTP device 20 further includes a lead-out structure 260 of the well region 220. The lead-out structure 260 is a doped region of the second doping type located in the well region 220, that is, the doping type of the well region 220 is the same as the doping type of the lead-out structure 260, and the lead-out structure 260 is used to realize the lead-out of the well region 220. The lead-out structure 260 is located at one side of the floating gate transistor Q22 or the selection transistor Q21, and is isolated from the floating gate transistor Q22 or the selection transistor Q21 via the isolation structure 230. In one embodiment, the lead-out structure 260 is located at one side of the floating gate transistor Q22, and is isolated from the drain region D2 of the floating gate transistor Q22 via the isolation structure 230.

[0051] Furthermore, the lead-out structure 260 of the well region 220 is connected to the back end (BulK end), the selection gate SG of the selection transistor is connected to the word line WL (Word Line), the drain region D1 of the selection transistor is connected to the bit line BL (Bit Line), the source region S1 of the selection transistor is connected to the source region S2 of the floating gate transistor, and is connected to the source end (Source end). The floating gate FG of the floating gate transistor extends to above the isolation structure 230 outside the well region 220, the control gate CG is opposite to the floating gate structure FG, the control gate CG, the inter-gate dielectric layer 254 and the floating gate FG constitute a capacitor structure, and the potential of the floating gate FG is controlled by the control gate CG.

[0052] Specifically, a negative voltage (e.g., -10V) is applied to the control gate CG, a positive voltage (e.g., 10V) is applied to the Source / BulK terminal, a positive voltage (e.g., 10V) is applied to the select gate SG (word line WL), and the electrons stored in the floating gate FG tunnel into the well region 220 under the floating gate FG to achieve erasure.

[0053] A programming voltage is applied to the control gate CG, which is a positive voltage (for example, 20V). The Source / BulK terminal is grounded, and a positive voltage (for example, 5V) is applied to the select gate SG (word line WL). The electrons in the well region 220 under the floating gate FG tunnel into the floating gate FG to achieve programming.

[0054] The control gate CG applies a read voltage, which is, for example, 0V, a negative voltage (for example, -5V) is applied to the Source terminal, a negative voltage (for example, -1V) is applied to the select gate SG (word line WL), and a 0V voltage is applied to the BulK terminal, and the current of the bit line BL is read, and the current of the bit line BL is compared with the reference current Iref to determine its storage type. When there are electrons stored in the floating gate FG, corresponding to a low threshold voltage, the current Id generated by the bit line BL is extremely large and read as "1"; when there are no electrons stored in the floating gate, corresponding to a high threshold voltage, the current Id generated by the bit line BL is extremely small and read as "0".

[0055] Figure 4 FIG. 4 shows a top view of the floating gate and the control gate of an embodiment of the present application, as shown in FIG. Figure 4 As shown, the floating gate FG is straight and extends in the first axis direction (e.g., the X-axis direction). The floating gate FG includes a first portion FG1 located above the well region 220 and a second portion FG2 located above the isolation structure 230. The control gate CG includes a first control gate CG1 extending in the first axis direction (e.g., the X-axis direction), a second control gate CG2, and a third control gate CG3 extending in the second axis direction (e.g., the Y-axis direction). The third control gate CG3 connects one end of the first control gate CG1 and one end of the second control gate CG2 to form a "U"-shaped control gate CG. The first control gate CG1 is located on the first side of the second portion FG2 and is opposite to the first side of the second portion FG2. The second control gate CG2 is located on the second side of the second portion FG2 and is opposite to the second side of the second portion FG2. The third control gate CG3 is opposite to the end of the second portion FG2 away from the first portion FG1. The "U"-shaped control gate CG surrounds the second portion FG2 of the floating gate FG.

[0056] The first part FG1 of the floating gate FG is opposite to the well region 220, and the first part FG1 of the floating gate FG, the gate dielectric layer 252 and the well region 220 constitute a first capacitor C1; the second part FG2 of the floating gate FG is opposite to the control gate CG, and the second part FG2, the inter-gate dielectric layer 254 and the control gate CG constitute a second capacitor C2, and the floating gate capacitance Ctotal of the MTP device 20 = C1 + C2; the capacitive coupling ratio CR of the control gate CG and the floating gate FG = C2 / Ctotal = C2 / (C1 + C2).

[0057] According to the capacitance formula C=εA / d, C1=ε1A1 / d1, C2=ε2A2 / d2.

[0058] The gate dielectric layers 251, 252, 253 and the inter-gate dielectric layer 254 are made of the same material, that is, the dielectric constant ε1 of the capacitor C1 and the dielectric constant ε2 of the capacitor C2 are the same, that is, ε1=ε2. The gate dielectric layers 251, 252, 253 have the same thickness, and the thickness of the inter-gate dielectric layer 254 is twice the thickness of the gate dielectric layers 251, 252, 253, that is, the plate spacing d2 of the capacitor C2 is twice the plate spacing d1 of the capacitor C1, that is, d2=2d1. The thickness H1 of the control gate CG and the thickness H2 of the floating gate FG are the same, that is, H1=H2. In one embodiment, H1=H2=100 nm.

[0059] The length of the channel region HC1b of the floating gate transistor Q22 is, for example, L HCIb The width of the channel region HC1b of the floating gate transistor Q22 is, for example, W HCIb , the width of the overlapping portion of the floating gate FG and the control gate CG is substantially equal to the width W2 of the second portion FG2 of the floating gate FG. In one embodiment, the channel length L of the floating gate transistor Q22 is HCIb For example, the width W2 of the second portion FG2 of the floating gate FG is equal to the width W of the channel region HC1b of the floating gate transistor Q22. HCIb The total width W of the floating gate FG is 10 times the width W of the channel region HC1b of the floating gate transistor Q22. HCIb 11 times, that is, W2=10W HCIb , W=11W HCIb .

[0060] The relative area A1 between the first portion FG1 of the floating gate FG and the well region 220 is L HCIb ×W HCIb =100W HCIb .

[0061] The relative area between the first control gate CG1 and the second portion FG2 of the floating gate FG is: A21=W2×H2. Similarly, the relative area between the second control gate CG2 and the second portion FG2 of the floating gate FG is: A22=W2×H2. The relative area between the third control gate CG3 and the second portion FG2 of the floating gate FG is: A23=L HCIb ×H2.

[0062] A2=A21+A22+A23=W2×H2+W2×H2+L HCIb ×H2=(2W2+L HCIb )×H2=100(2W2+L HCIb ) = 100 (20W HCIb +L HCIb )≈2000W HCIb ≈20A1

[0063] C2 / C1 = (A2 / d2) / (A1 / d1) = (20A1 / 2d1) / (A1 / d1) = 10, i.e. C2=10C1

[0064] CR=C2 / Ctotal= C2 / (C1 + C2) ≈0.91

[0065] When the parameters of the floating gate FG of the present application are the same as those of the floating gate of the conventional MTP device, the capacitance coupling ratio of the present application is improved relative to that of the conventional MTP device, and the size of the control gate CG of the present application is reduced relative to that of the control gate CG of the conventional MTP device.

[0066] Furthermore, the control gate CG of the present application is arranged above the isolation structure 230, which effectively avoids the leakage problem of the first well region 120 and the second well region 130 in the traditional MTP device, increases the operable voltage of the control gate CG, and improves the programming / erasing efficiency.

[0067] Figure 5 FIG. 4 shows a corresponding curve between the capacitance coupling ratio CR and the thickness d2 of the inter-gate dielectric layer 254 according to an embodiment of the present application. Figure 5 As shown, the thickness d2 of the inter-gate dielectric layer 254 is gradually changed to obtain a corresponding curve between the capacitive coupling ratio CR and the thickness d2 of the inter-gate dielectric layer 254. As the thickness d2 of the inter-gate dielectric layer 254 increases, the capacitive coupling ratio gradually decreases.

[0068] Figure 6 FIG. 4 shows a corresponding curve between the capacitance coupling ratio CR and the width W2 of the overlapping portion of the floating gate FG and the control gate CG according to an embodiment of the present application. Figure 6 As shown, the width W2 of the overlapping portion of the floating gate FG and the control gate CG is gradually changed to obtain a corresponding curve between the capacitive coupling ratio CR and the width W2 of the overlapping portion of the floating gate FG and the control gate CG. As the width W2 of the overlapping portion of the floating gate FG and the control gate CG increases, the capacitive coupling ratio first gradually increases and then gradually approaches a saturation value.

[0069] Furthermore, an embodiment of the present application also provides an electronic device, which includes the above-mentioned multi-time programmable device.

[0070] The unexpected technical effects of this application are:

[0071] In the multi-time programmable device of the present application, when the parameters of the floating gate are the same as those of the floating gate of the traditional MTP device, the capacitive coupling ratio of the present application is improved relative to the capacitive coupling ratio of the traditional MTP device, and the size of the control gate CG of the present application is reduced relative to the size of the control gate CG of the traditional MTP device.

[0072] Furthermore, the control gate CG of the present application is arranged above the isolation structure, which effectively avoids the leakage problem of the first well region and the second well region in the traditional MTP device, increases the operable voltage of the control gate CG, and improves the programming / erasing efficiency.

[0073] In the multi-time programmable device of the present application, the control gate is respectively opposite to the first side, the second side and the end of the second part of the floating gate away from the first part, and the control gate surrounds the second part of the floating gate, thereby increasing the coupling ratio between the control gate and the floating gate.

[0074] In the present application, the thickness of the inter-gate dielectric layer is gradually changed to obtain a corresponding curve between the capacitance coupling ratio and the thickness of the inter-gate dielectric layer, and the width of the overlapping portion of the floating gate FG and the control gate CG is gradually changed to obtain a corresponding curve between the capacitance coupling ratio and the width of the overlapping portion of the floating gate and the control gate. The size of the device can be optimized through the above corresponding curve.

[0075] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A multi-time programmable device, comprising: Semiconductor layer; A well region and an isolation structure located in the semiconductor layer, wherein the isolation structure surrounds the well region; A selection transistor and a floating gate transistor are formed in the well region, and a floating gate of the floating gate transistor extends from above the well region to above the isolation structure; as well as A control gate, located above the isolation structure, the control gate being opposite to the floating gate in a horizontal direction; The floating gate and the control gate are isolated from each other via an inter-gate dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate form a capacitor structure, and the control gate controls the potential of the floating gate; The floating gate extends in the first axis direction and includes a first portion located above the well region and a second portion located above the isolation structure, and the control gate surrounds the second portion of the floating gate; A gate dielectric layer is arranged between the selection gate and the well region of the selection transistor, between the floating gate and the well region, and between the control gate and the isolation structure. The gate dielectric layer between the selection gate and the well region, the gate dielectric layer between the floating gate and the well region, and the gate dielectric layer between the control gate and the isolation structure have the same thickness, and the selection gate, the floating gate, and the control gate are located on the same horizontal plane.

2. The multi-time programmable device according to claim 1, wherein: The control gate includes a first control gate extending in the first axis direction, a second control gate, and a third control gate connecting one end of the first control gate and one end of the second control gate; The first control gate is opposite to the first side of the second part, the second control gate is opposite to the second side of the second part, the third control gate is opposite to the end of the second part away from the first part, and the first side and the second side of the second part are opposite.

3. The multi-time programmable device according to claim 1, wherein: The capacitive coupling ratio between the control gate and the floating gate decreases as the thickness of the inter-gate dielectric layer increases.

4. The multi-time programmable device according to claim 1, wherein: As the width of the overlapping portion of the floating gate and the control gate increases, the capacitive coupling ratio between the control gate and the floating gate first gradually increases and then approaches a saturation value.

5. The multi-time programmable device according to claim 1, wherein: It also includes a lead-out structure, which is located in the well region, and the doping type of the well region is the same as the doping type of the lead-out structure.

6. The multi-time programmable device according to claim 5, wherein: The selection gate of the selection transistor is connected to the word line, the drain region of the selection transistor is connected to the bit line, the source region of the selection transistor is connected to the source region of the floating gate transistor and is connected to the source terminal, the drain region of the floating gate transistor is connected to the drain terminal, and the lead-out structure is connected to the back terminal.

7. The multi-time programmable device according to claim 6, wherein: A negative voltage is applied to the control gate, a positive voltage is applied to the source terminal and the back terminal, and a positive voltage is applied to the select gate, so that the electrons stored in the floating gate tunnel to the well region under the floating gate to achieve erasure; The control gate is applied with a positive voltage, the source terminal and the back terminal are grounded, the select gate is applied with a positive voltage, and the electrons in the well region under the floating gate are tunneled into the floating gate to realize programming; A 0V voltage is applied to the control gate, a 0V voltage is applied to the back end, a negative voltage is applied to the source end, a negative voltage is applied to the select gate, the current of the bit line is read, and the current of the bit line is compared with the reference current to determine its storage type.

8. An electronic device comprising the multi-time programmable device according to any one of claims 1 to 7.

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