A low static power consumption fast high and low voltage detection circuit and method

Abstract

The present invention relates to the technical field of voltage detection, and specifically discloses a low static power consumption fast high and low voltage detection circuit and method, the circuit comprising: a Zener tube, the output end of which is electrically connected to the voltage to be detected; a high voltage NMOS tube, the drain of which is electrically connected to the input end of the Zener tube, and the gate of which is electrically connected to the power supply; a first and a second positive feedback NMOS tube, the gate of the first positive feedback NMOS tube and the drain of the second positive feedback NMOS tube are electrically connected to the source of the high voltage NMOS tube at the same time; a first resistor, one end of which is electrically connected to the source of the first and second positive feedback NMOS tubes at the same time, and the other end is electrically connected to the ground; a Schmidt inverter, the input of which is electrically connected to the drain of the first positive feedback NMOS tube, and the output is used as the logic signal output end of the detection circuit. The circuit structure of the present invention is simple, and a resistor voltage divider and a comparator are not used. The overall static current is not more than 1.5uA, and the high voltage detection flip delay and the low voltage detection flip delay are small, so that the low static power consumption fast high and low voltage detection function is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage detection, and in particular to a low static power consumption fast high and low voltage detection circuit and method. Background Art

[0002] Figure 1 The figure shows a commonly used high and low voltage detection circuit, V sense is the voltage to be detected, the resistor R f1 , R f2 A set of transformers is formed so that the feedback voltage V fb Proportional to the voltage to be detected, the feedback voltage V fb The calculation formula is: V fb =R f2 / (R f1 +R f2 )* V sense . The feedback voltage V fb and a reference voltage V ref The comparison is performed by comparator COMP1 to generate a logic signal High. fb >V ref When High is high level, it means V sense >V ref *(R f1 +R f2 ) / R f2 , in order to determine when V sense For high voltage. Figure 2 This is the waveform diagram of the commonly used high and low voltage detection circuit. When the voltage to be detected V sense When the voltage divider feedback point V fb The presence of parasitic capacitance on the feedback voltage V fb There is a certain delay in the rate of change, and because of the delay of the comparator, td, V sense There is a certain delay between the jump edge and the logic signal High flip edge, which is generally greater than 10ns. f1 , R f2 And comparator COMP1, generally the static current of this structure will be greater than 10uA.

[0003] Based on this technical background, the present invention studies a low static power consumption fast high and low voltage detection circuit and method. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes a low static power consumption and fast high and low voltage detection circuit and method. The detection circuit has a simple structure, does not use a resistor divider and a comparator, the overall static current is no more than 1.5uA, the high voltage detection flip delay is no more than 2ns, and the low voltage detection flip delay is no more than 10ns, thereby realizing low static power consumption and fast high and low voltage detection functions.

[0005] In order to achieve the above object, the first aspect of the present invention provides a low static power consumption fast high and low voltage detection circuit, comprising:

[0006] A Zener tube, an output end of which is electrically connected to a voltage to be detected;

[0007] A high-voltage NMOS tube, the drain of which is electrically connected to the input end of the Zener tube, and the gate of which is electrically connected to the power supply;

[0008] A positive feedback loop unit, comprising a first positive feedback NMOS tube and a second positive feedback NMOS tube, wherein a gate electrode of the first positive feedback NMOS tube and a drain electrode of the second positive feedback NMOS tube are electrically connected to a source electrode of the high-voltage NMOS tube at the same time;

[0009] A first resistor, one end of which is electrically connected to the source of the first positive feedback NMOS tube and the source of the second positive feedback NMOS tube, and the other end of which is electrically connected to the ground;

[0010] The Schmitt inverter has an input electrically connected to the drain of the first positive feedback NMOS tube, and an output serving as an output end of the detection circuit.

[0011] A second aspect of the present invention provides a low static power consumption fast high and low voltage detection method performed in the above detection circuit, comprising:

[0012] When the voltage to be detected jumps from a low level to a high level, the Zener tube cooperates with the high-voltage NMOS tube to make the high-voltage NMOS tube enter the saturation region from the linear region and pull up its source potential, and then the positive feedback loop unit and the first resistor cooperate to make the first positive feedback NMOS tube enter the linear region and pull down its drain potential, so that the output of the Schmidt inverter jumps to a high level;

[0013] When the voltage to be detected jumps from a high level to a low level, the Zener tube cooperates with the high-voltage NMOS tube to make the high-voltage NMOS tube enter the linear region from the saturation region and pull down its source potential. Then, the positive feedback loop unit and the first resistor cooperate to make the first positive feedback NMOS tube completely turned off, and then the Schmitt inverter output jumps to a low level.

[0014] The beneficial effects of the present invention include:

[0015] (1) The low static power consumption fast high and low voltage detection circuit proposed in the present invention has a simple structure, does not use a resistor divider and a comparator, the overall static current is no more than 1.5uA, the high voltage detection flip delay is no more than 2ns, and the low voltage detection flip delay is no more than 10ns, thus realizing the low static power consumption fast high and low voltage detection function.

[0016] (2) The low static power consumption fast high and low voltage detection circuit proposed in the present invention realizes fast detection of high and low voltages at extremely low power consumption through a Zener tube, a high voltage NMOS tube, a positive feedback loop unit, an NMOS bias unit and a PMOS bias unit.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0019] Figure 1 It is a schematic diagram of the structure of the existing high and low voltage detection circuit.

[0020] Figure 2 It is a detection waveform schematic diagram of the existing high and low voltage detection circuit structure.

[0021] Figure 3 The schematic diagram is a structural diagram of a specific implementation of the low static power consumption fast high and low voltage detection circuit proposed by the present invention.

[0022] Figure 4 This is a schematic diagram of detection waveforms in a specific implementation of the low static power consumption fast high and low voltage detection circuit proposed by the present invention.

[0023] Description of reference numerals:

[0024] V sense - voltage to be detected, D1- Zener tube, M1- high-voltage NMOS tube, INV1- Schmitt inverter, Vcc- power supply, M5- first positive feedback NMOS tube, M3- second positive feedback NMOS tube, M2- first bias NMOS tube, M4- second bias NMOS tube, M6- first bias PMOS tube, M7- second bias PMOS tube, R1- first resistor, R2- second resistor, R3- third resistor, R4- bias resistor, VA- high-voltage NMOS tube source potential, VB- first positive feedback NMOS tube source potential, VC- first positive feedback NMOS tube drain potential, High- logic signal. DETAILED DESCRIPTION

[0025] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0026] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood to indicate or imply relative importance or implicitly indicate the number of the indicated technical features. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0027] The present invention provides a low static power consumption fast high and low voltage detection circuit, such as Figure 3 As shown, including:

[0028] Zener diode D1, output terminal and voltage to be detected V sense Electrical connection;

[0029] A high-voltage NMOS tube M1, a drain of which is electrically connected to the input end of the Zener tube D1, and a gate of which is electrically connected to the power supply Vcc;

[0030] The positive feedback loop unit includes a first positive feedback NMOS tube M5 and a second positive feedback NMOS tube M3, wherein the gate of the first positive feedback NMOS tube M5 and the drain of the second positive feedback NMOS tube M3 are electrically connected to the source of the high-voltage NMOS tube M1 at the same time;

[0031] A first resistor R1, one end of which is electrically connected to the source of the first positive feedback NMOS tube M5 and the source of the second positive feedback NMOS tube M3, and the other end of which is electrically connected to the ground;

[0032] The Schmitt inverter INV1 has an input electrically connected to the drain of the first positive feedback NMOS tube M5, and an output serving as a logic signal High output terminal of the detection circuit.

[0033] The detection circuit in the present invention has a simple structure, does not use a resistor divider and a comparator, has an overall static current of no more than 1.5uA, a high voltage detection flip delay of no more than 2ns, and a low voltage detection flip delay of no more than 10ns, thereby realizing a low static power consumption and fast high and low voltage detection function.

[0034] According to the present invention, it also includes:

[0035] The NMOS bias unit includes a first bias NMOS tube M2 and a second bias NMOS tube M4, wherein the gate of the first bias NMOS tube M2 is electrically connected to its own drain, and is also electrically connected to the gate of the second bias NMOS tube M4 and the gate of the second positive feedback NMOS tube M3;

[0036] A second resistor R2, one end of which is electrically connected to the source of the first bias NMOS transistor M2, and the other end of which is electrically connected to the ground;

[0037] The third resistor R3 has one end electrically connected to the source of the second bias NMOS transistor M4 and the other end electrically connected to the ground.

[0038] According to the present invention, it also includes:

[0039] The PMOS bias unit includes a first bias PMOS tube M6 and a second bias PMOS tube M7. The gate of the first bias PMOS tube M6 is electrically connected to the gate of the second bias PMOS tube M7. Both sources are electrically connected to the power supply Vcc. The drain of the first bias PMOS tube M6 is electrically connected to the drain of the first positive feedback NMOS tube M5. The drain of the second bias PMOS tube M7 is electrically connected to the drain of the second bias NMOS tube M4. The gate of the second bias PMOS tube M7 is also electrically connected to its own drain.

[0040] According to the present invention, it also includes:

[0041] The bias resistor R4 has one end electrically connected to the power source Vcc, and the other end electrically connected to the drain of the first bias NMOS transistor M4.

[0042] According to the present invention, the first bias PMOS tube M6 and the second bias PMOS tube M7 have the same size, and the two form a PMOS current mirror structure;

[0043] The first bias NMOS transistor M2 and the second bias NMOS transistor M4 have the same size, and the two form an NMOS current mirror structure.

[0044] In the present invention, the rapid detection of high and low voltages is achieved at extremely low power consumption through the Zener tube D1, the high-voltage NMOS tube M1, the positive feedback loop unit, the NMOS bias unit and the PMOS bias unit.

[0045] The present invention also provides a low static power consumption fast high and low voltage detection method performed in the above detection circuit, comprising:

[0046] When the voltage to be detected V senseWhen the low level jumps to the high level, the Zener tube D1 cooperates with the high-voltage NMOS tube M1 to make the high-voltage NMOS tube M1 enter the saturation region from the linear region and pull up its source potential. Then, the positive feedback loop unit and the first resistor R1 cooperate to make the first positive feedback NMOS tube M5 enter the linear region and pull down its drain potential, so that the output of the Schmidt inverter INV1 jumps to the high level.

[0047] When the voltage to be detected V sense When the high level jumps to the low level, the Zener tube D1 cooperates with the high-voltage NMOS tube M1 to make the high-voltage NMOS tube M1 enter the linear region from the saturation region and pull down its source potential. Then, the positive feedback loop unit and the first resistor R1 cooperate to make the first positive feedback NMOS tube M5 completely turned off, and then the Schmidt inverter INV1 outputs the logic signal High jumps to a low level.

[0048] According to the present invention, when the voltage to be detected V sense When the low level jumps to the high level, the Zener tube D1 cooperates with the high-voltage NMOS tube M1 to make the high-voltage NMOS tube M1 enter the saturation region from the linear region, and pull up its source potential including:

[0049] When the voltage to be detected V sense When the voltage jumps from low level to high level, the drain voltage of the high-voltage NMOS tube follows the voltage to be detected V sense Increases and is higher than the voltage to be detected V sense Lower than the voltage drop of Zener diode D1;

[0050] When the drain voltage of the high-voltage NMOS tube increases, its working state enters the saturation region from the linear region, so that its source potential is pulled up.

[0051] According to the present invention, the positive feedback loop unit and the first resistor R1 cooperate to make the first positive feedback NMOS tube M5 enter the linear region and pull down its drain potential, and then the Schmidt inverter INV1 outputs a logic signal High that jumps to a high level, including:

[0052] When the source potential VA of the high-voltage NMOS tube is higher than the threshold voltage of the first positive feedback NMOS tube M5, the first positive feedback NMOS tube M5 is turned on, and the current flows from the first positive feedback NMOS tube M5 into the first resistor R1;

[0053] Since the current of the first positive feedback NMOS tube M5 flows into the first resistor R1, the source potential of the second positive feedback NMOS tube M3 is raised, that is, the gate-source voltage of the second positive feedback NMOS tube M3 is reduced, and the current flowing through the second positive feedback NMOS tube M3 is reduced, so that the drain potential of the second positive feedback NMOS tube M3 continues to rise, forming a positive feedback path. When the first positive feedback NMOS tube M5 is fully turned on and enters the linear region, its drain potential is pulled down, so that the output logic signal High of the Schmidt inverter INV1 jumps to a high level, completing the high voltage detection.

[0054] According to the present invention, when the voltage to be detected V sense When the high level jumps to the low level, the Zener tube D1 cooperates with the high-voltage NMOS tube M1 to make the high-voltage NMOS tube M1 enter the linear region from the saturation region, and pull down its source potential including:

[0055] When the voltage to be detected V sense When the high level jumps to the low level, the drain voltage of the high-voltage NMOS tube follows the voltage to be detected V sense Lower than the voltage to be detected V sense Lower than the voltage drop of Zener diode D1;

[0056] When the drain voltage of the high-voltage NMOS tube decreases, its working state enters the linear region from the saturation region, so that its source potential is pulled down.

[0057] According to the present invention, the positive feedback loop unit and the first resistor R1 cooperate to completely turn off the first positive feedback NMOS tube M5, and then the output logic signal High of the Schmidt inverter INV1 jumps to a low level, including:

[0058] When the source potential VA of the high-voltage NMOS tube is lower than the threshold voltage of the first positive feedback NMOS tube M5, the first positive feedback NMOS tube M5 is turned off, and the current flowing into the first resistor R1 is reduced;

[0059] Since the current flowing through the first resistor R1 decreases, the source potential of the second positive feedback NMOS tube M3 decreases, that is, the gate-source voltage of the second positive feedback NMOS tube M3 increases, and the current flowing through the second positive feedback NMOS tube M3 increases, so that the drain potential of the second positive feedback NMOS tube M3 continues to decrease, forming a positive feedback path. When the first positive feedback NMOS tube M5 is completely turned off, at this time, the current flowing through the first bias PMOS tube M6 raises its drain potential, so that it enters the linear region, so that the output logic signal High of the Schmidt inverter INV1 jumps to a low level, completing the low voltage detection.

[0060] The present invention will be described in more detail below through specific embodiments. Example

[0061] like Figure 3 As shown, this embodiment provides a low static power consumption fast high and low voltage detection circuit, including:

[0062] Zener diode D1, output terminal and voltage to be detected Vsense Electrical connection;

[0063] A high-voltage NMOS tube M1, a drain of which is electrically connected to the input end of the Zener tube D1, and a gate of which is electrically connected to the power supply Vcc;

[0064] The positive feedback loop unit includes a first positive feedback NMOS tube M5 and a second positive feedback NMOS tube M3, wherein the gate of the first positive feedback NMOS tube M5 and the drain of the second positive feedback NMOS tube M3 are electrically connected to the source of the high-voltage NMOS tube M1 at the same time;

[0065] A first resistor R1, one end of which is electrically connected to the source of the first positive feedback NMOS tube M5 and the source of the second positive feedback NMOS tube M3, and the other end of which is electrically connected to the ground;

[0066] The Schmitt inverter INV1, whose input is electrically connected to the drain of the first positive feedback NMOS tube M5, and whose output serves as a logic signal High output terminal of the detection circuit;

[0067] The NMOS bias unit includes a first bias NMOS tube M2 and a second bias NMOS tube M4, wherein the gate of the first bias NMOS tube M2 is electrically connected to its own drain, and is also electrically connected to the gate of the second bias NMOS tube M4 and the gate of the second positive feedback NMOS tube M3;

[0068] A second resistor R2, one end of which is electrically connected to the source of the first bias NMOS transistor M2, and the other end of which is electrically connected to the ground;

[0069] A third resistor R3, one end of which is electrically connected to the source of the second bias NMOS transistor M4, and the other end of which is electrically connected to the ground;

[0070] A PMOS bias unit, comprising a first bias PMOS tube M6 and a second bias PMOS tube M7, wherein the gate of the first bias PMOS tube M6 is electrically connected to the gate of the second bias PMOS tube M7, and the sources of both are electrically connected to the power supply Vcc, the drain of the first bias PMOS tube M6 is electrically connected to the drain of the first positive feedback NMOS tube M5, the drain of the second bias PMOS tube M7 is electrically connected to the drain of the second bias NMOS tube M4, and the gate of the second bias PMOS tube M7 is also electrically connected to its own drain;

[0071] A bias resistor R4, one end of which is electrically connected to the power supply Vcc, and the other end of which is electrically connected to the drain of the first bias NMOS tube M4;

[0072] In this embodiment, the first bias PMOS tube M6 and the second bias PMOS tube M7 have the same size, and the two form a PMOS current mirror structure;

[0073] The first bias NMOS transistor M2 and the second bias NMOS transistor M4 have the same size, and the two form an NMOS current mirror structure.

[0074] This embodiment provides a low static power consumption fast high and low voltage detection method, including:

[0075] When the voltage to be detected V sense When the voltage level changes from low to high, the drain voltage of the high-voltage NMOS tube M1 follows the voltage to be detected V sense Increases, through the Zener tube D1, making the drain voltage of the high-voltage NMOS tube M1 higher than V sense The voltage is lower than the voltage drop of a Zener diode;

[0076] The power supply Vcc is the 5V power supply inside the chip. When the drain voltage of the high-voltage NMOS tube M1 increases, its working state enters the saturation region from the linear region, causing the source potential VA of the high-voltage NMOS tube to increase.

[0077] When the potential at the VA point is higher than the threshold voltage of the first positive feedback NMOS tube M5, the first positive feedback NMOS tube M5 is turned on, and the current flows from the first positive feedback NMOS tube M5 into the first resistor R1;

[0078] Since the current of the first positive feedback NMOS tube M5 flows into the first resistor R1, the source voltage of the second positive feedback NMOS tube M3 is raised, that is, the gate-source voltage of the second positive feedback NMOS tube M3 is reduced, and the current flowing through the second positive feedback NMOS tube M3 is reduced, so that the drain voltage VA of the second positive feedback NMOS tube M3 continues to rise, forming a positive feedback path, and the first positive feedback NMOS tube M5 is fully turned on. The first positive feedback NMOS tube M5 enters the linear region to pull down the drain potential VC of the first positive feedback NMOS tube, so that the logic signal High jumps to a high level, completing the high voltage detection function;

[0079] Contrary to the above process, when the voltage to be detected V sense When the high level jumps to the low level, the drain voltage of the high-voltage NMOS tube M1 follows the voltage to be detected V sense Reduce, through Zener diode D1, so that the drain voltage of M1 is lower than the Vsense voltage by a Zener diode voltage drop;

[0080] The power supply Vcc is the 5V power supply inside the chip. When the drain voltage of the high-voltage NMOS tube M1 decreases, its working state enters the linear region from the saturation region, causing the source potential VA of the high-voltage NMOS tube to decrease.

[0081] When the source potential VA of the high-voltage NMOS tube is lower than the threshold voltage of the first positive feedback NMOS tube M5, the first positive feedback NMOS tube M5 is turned off, and the current flowing through the first resistor R1 is reduced;

[0082] Since the current flowing through the first resistor R1 decreases, the source voltage of the second positive feedback NMOS tube M3 decreases, that is, the gate-source voltage of the second positive feedback NMOS tube M3 increases, and the current flowing through the second positive feedback NMOS tube M3 increases, so that the source potential VA of the high-voltage NMOS tube continues to decrease, forming a positive feedback path, and the first positive feedback NMOS tube M5 is completely turned off;

[0083] At this time, the current in the first bias PMOS tube M6 will raise the drain potential VC of the first positive feedback NMOS tube, so that the first bias PMOS tube M6 enters the linear region, and the logic signal High jumps to a low level, indicating that V sense The voltage is already at a low level, and the detection waveforms of the high voltage detection flip and the low voltage detection flip delay are as follows Figure 4 shown.

[0084] The low static power consumption and fast high and low voltage detection circuit proposed in the embodiment of the present invention has a simple structure, does not use a resistor divider and a comparator, the overall static current is no more than 1.5uA, the high voltage detection flip delay is no more than 2ns, and the low voltage detection flip delay is no more than 10ns, thereby realizing the low static power consumption and fast high and low voltage detection function.

[0085] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A low static power consumption fast high and low voltage detection circuit, characterized in that: include: A Zener tube, an output end of which is electrically connected to a voltage to be detected; A high-voltage NMOS tube, the drain of which is electrically connected to the input end of the Zener tube, and the gate of which is electrically connected to the power supply; A positive feedback loop unit, comprising a first positive feedback NMOS tube and a second positive feedback NMOS tube, wherein a gate electrode of the first positive feedback NMOS tube and a drain electrode of the second positive feedback NMOS tube are electrically connected to a source electrode of the high-voltage NMOS tube at the same time; A first resistor, one end of which is electrically connected to the source of the first positive feedback NMOS tube and the source of the second positive feedback NMOS tube, and the other end of which is electrically connected to the ground; A Schmitt inverter, the input of which is electrically connected to the drain of the first positive feedback NMOS tube, and the output of which serves as a logic signal output terminal of the detection circuit; An NMOS bias unit, comprising a first bias NMOS tube and a second bias NMOS tube, wherein the gate of the first bias NMOS tube is electrically connected to its own drain, and is also electrically connected to the gate of the second bias NMOS tube and the gate of the second positive feedback NMOS tube; a second resistor, one end of which is electrically connected to the source of the first bias NMOS tube, and the other end of which is electrically connected to the ground; a third resistor, one end of which is electrically connected to the source of the second bias NMOS tube, and the other end of which is electrically connected to the ground; The PMOS bias unit comprises a first bias PMOS tube and a second bias PMOS tube, wherein the gate of the first bias PMOS tube is electrically connected to the gate of the second bias PMOS tube, and both sources are electrically connected to a power supply, the drain of the first bias PMOS tube is electrically connected to the drain of the first positive feedback NMOS tube, the drain of the second bias PMOS tube is electrically connected to the drain of the second bias NMOS tube, and the gate of the second bias PMOS tube is also electrically connected to its own drain.

2. The detection circuit according to claim 1, characterized in that: Also includes: A bias resistor has one end electrically connected to a power supply, and the other end electrically connected to the drain of the first bias NMOS tube.

3. The detection circuit according to claim 2, characterized in that: The first bias PMOS tube and the second bias PMOS tube have the same size, and the two form a PMOS current mirror structure; The first bias NMOS tube and the second bias NMOS tube have the same size, and the two form an NMOS current mirror structure.

4. A low static power consumption fast high and low voltage detection method performed in the detection circuit as claimed in any one of claims 1 to 3, characterized in that: include: When the voltage to be detected jumps from a low level to a high level, the Zener tube cooperates with the high-voltage NMOS tube to make the high-voltage NMOS tube enter the saturation region from the linear region and pull up its source potential, and then the positive feedback loop unit and the first resistor cooperate to make the first positive feedback NMOS tube enter the linear region and pull down its drain potential, so that the output of the Schmidt inverter jumps to a high level; When the voltage to be detected jumps from a high level to a low level, the Zener tube cooperates with the high-voltage NMOS tube to make the high-voltage NMOS tube enter the linear region from the saturation region and pull down its source potential. Then, the positive feedback loop unit and the first resistor cooperate to make the first positive feedback NMOS tube completely turned off, and then the Schmitt inverter output logic signal jumps to a low level.

5. The method according to claim 4, characterized in that When the voltage to be detected jumps from a low level to a high level, the Zener tube cooperates with the high-voltage NMOS tube to make the high-voltage NMOS tube enter the saturation region from the linear region and pull up its source potential, including: When the voltage to be detected jumps from a low level to a high level, the drain voltage of the high-voltage NMOS tube increases with the voltage to be detected, and is lower than the voltage to be detected by a voltage drop of the Zener tube; When the drain voltage of the high-voltage NMOS tube increases, its working state enters the saturation region from the linear region, so that its source potential is pulled up.

6. The method according to claim 5, characterized in that The positive feedback loop unit and the first resistor cooperate to make the first positive feedback NMOS tube enter the linear region and pull down its drain potential, so that the output logic signal of the Schmitt inverter jumps to a high level, including: When the source potential of the high-voltage NMOS tube is higher than the threshold voltage of the first positive feedback NMOS tube, the first positive feedback NMOS tube is turned on, and current flows from the first positive feedback NMOS tube into the first resistor; Since the current of the first positive feedback NMOS tube flows into the first resistor, the source voltage of the second positive feedback NMOS tube is raised, that is, the gate-source voltage of the second positive feedback NMOS tube is reduced, and the current flowing through the second positive feedback NMOS tube is reduced, so that the drain potential of the second positive feedback NMOS tube continues to rise, forming a positive feedback path. When the first positive feedback NMOS tube is fully turned on and enters the linear region, its drain potential is pulled down, so that the output logic signal of the Schmidt inverter jumps to a high level, completing the high voltage detection.

7. The method according to claim 4, characterized in that When the voltage to be detected jumps from a high level to a low level, the Zener tube cooperates with the high-voltage NMOS tube to make the high-voltage NMOS tube enter the linear region from the saturation region and pull down its source potential, including: When the voltage to be detected changes from a high level to a low level, the drain voltage of the high-voltage NMOS tube decreases along with the voltage to be detected, and is lower than the voltage to be detected by a voltage drop of the Zener tube; When the drain voltage of the high-voltage NMOS tube decreases, its working state enters the linear region from the saturation region, so that its source potential is pulled down.

8. The method according to claim 7, characterized in that The positive feedback loop unit and the first resistor cooperate to completely turn off the first positive feedback NMOS tube, and then the output logic signal of the Schmitt inverter jumps to a low level, including: When the source potential of the high-voltage NMOS tube is lower than the threshold voltage of the first positive feedback NMOS tube, the first positive feedback NMOS tube is turned off, and the current flowing into the first resistor is reduced; Since the current flowing through the first resistor decreases, the source voltage of the second positive feedback NMOS tube decreases, that is, the gate-source voltage of the second positive feedback NMOS tube increases, and the current flowing through the second positive feedback NMOS tube increases, so that the drain potential of the second positive feedback NMOS tube continues to decrease, forming a positive feedback path. When the first positive feedback NMOS tube is completely turned off, the current flowing through the first bias PMOS tube raises its drain potential, causing it to enter the linear region, thereby causing the Schmidt inverter output logic signal to jump to a low level, completing the low voltage detection.

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