Chip detection device and detection method

Abstract

The present application provides a chip detection device and detection method, the detection device includes: a detection circuit, including an electrically connected current source and a plurality of first switch devices, the first switch devices are used to be electrically connected to the chips to be tested in the module to be tested in a one-to-one correspondence, and each first switch device is connected to the connection branch between the current source and the chip to be tested. The detection device can measure the junction temperature distribution of each chip individually by controlling the turn-off of the first switch device, which can solve the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has a large error and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution of each chip inside the module, can effectively avoid the junction temperature measurement error caused by chip bipolar degradation, and accurately measure the chip junction temperature of the module during the power cycle.

Description

Technical Field

[0001] The present application relates to the field of junction temperature measurement of parallel silicon carbide chips, and in particular to a chip detection device and a method for detecting a chip to be detected using the detection device. Background Art

[0002] After a large number of tests and experiments, we know that temperature is the main cause of power device failure, accounting for about 55% of the probability. Power cycle testing can simulate the temperature fluctuation process of the device by controlling the load current interruption, accelerate aging to expose the weak points of the device package in advance, and is the most important test for evaluating the reliability of power semiconductor device packaging.

[0003] In the prior art, most power circulation devices use a method of injecting a small current to measure the body diode voltage drop to measure the junction temperature of SiC MOSFET discrete devices and modules. However, due to process limitations, the chip bipolar degradation problem is serious. At this time, the error in measuring the junction temperature using the body diode method is large, which greatly affects the life estimation of the chip and module. In addition, the power modules in existing products all share a common gate terminal, and the temperature information obtained is the temperature information of all chip couplings, which is manifested as the average junction temperature measured, that is, the average junction temperature of each chip, and it is impossible to measure the junction temperature distribution inside the module. Summary of the invention

[0004] The main purpose of the present application is to provide a chip detection device and a method for detecting a chip to be tested using the detection device, so as to at least solve the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has large errors and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a chip detection device is provided, including: a detection circuit, including an electrically connected current source and a plurality of first switching devices, the first switching devices being used to be electrically connected one-to-one with the chips to be tested in the module to be tested, and each of the first switching devices being connected to a connection branch between the current source and the chip to be tested.

[0006] Optionally, the detection circuit further includes a plurality of second switch devices and a companion test module, the companion test module includes a plurality of companion test chips, the second switch devices correspond to the companion test chips one-to-one, the first end of the second switch device is electrically connected to the control end of the corresponding companion test chip, and the second end of the second switch device is electrically connected to the first end of the corresponding companion test chip.

[0007] Optionally, the detection circuit further includes a third switching device, a first end of the third switching device is electrically connected to the current source, and a second end of the third switching device is electrically connected to each of the first switching devices respectively.

[0008] Optionally, the detection device further includes: an industrial water chiller, electrically connected to the module to be tested, and used to cool the chip to be tested.

[0009] According to another aspect of the present application, a method for detecting a chip to be tested using any one of the detection devices is provided, the method comprising: when the temperature of the chip to be tested is heated to meet a preset temperature condition, controlling the current source to not supply power to all the chips to be tested, and measuring the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment; applying a control signal to the control end of the chip to be tested to put the chip to be tested in a cut-off state, closing the first switch device corresponding to the chip to be tested; when the chip to be tested is lowered to the corresponding minimum preset temperature, measuring the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment, the temperature-sensitive electrical parameter measurement value at least including a measurement threshold voltage; judging whether the chip to be tested has failed based on the relationship between the temperature-sensitive electrical parameter measurement value of the chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold.

[0010] Optionally, when the temperature of the chip to be tested is heated to meet a preset temperature condition, before the current source is controlled to stop supplying power to all the chips to be tested, the method further includes: determining whether there is an initial temperature calibration curve for the chip to be tested, the initial temperature calibration curve being a calibration curve between the temperature-sensitive electrical parameters of the chip to be tested and the temperature; if there is an initial temperature calibration curve for the chip to be tested, controlling the current source to provide a load current to the chip to be tested so as to power the chip to be tested.

[0011] Optionally, before determining whether there is an initial temperature calibration curve of the chip to be tested, the method further comprises: detecting an initial temperature of the chip to be tested, where the initial temperature is a minimum preset temperature of the chip to be tested.

[0012] Optionally, in the presence of an initial temperature calibration curve of the chip to be tested, the current source is controlled to provide a load current to the chip to be tested so as to power the chip to be tested, including: in the presence of an initial temperature calibration curve of the target chip to be tested currently being detected, disconnecting all of the first switching devices; controlling all of the chips to be tested to be turned on, so as to control the current source to provide a load current to all of the chips to be tested so as to heat all of the chips to be tested.

[0013] Optionally, the detection circuit includes N chips to be tested connected in parallel, the maximum cycle period of the load current provided by the current source is M times, the maximum number of measurements of the detection method is equal to the maximum cycle period of the load current, and the cycle period of the load current is the period during which the current source provides the load current. , k is a positive integer, the method further includes: testing each of the chips to be tested in this way, and only testing one of the chips to be tested in one current cycle; and / or, the detection circuit includes a third switching device, a first end of the third switching device is electrically connected to the current source, and a second end of the third switching device is electrically connected to each of the first switching devices respectively, and controlling the current source to not supply power to all the chips to be tested, including: disconnecting the third switching device so that the current source does not supply power to all the chips to be tested.

[0014] Optionally, when the temperature of the chip to be tested is heated to meet a preset temperature condition, the current source is controlled to stop supplying power to all the chips to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured, including: when the temperature of the chip to be tested is heated to a maximum preset temperature, the current source is controlled to stop supplying power to the chip to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured; or, when the temperature of the chip to be tested is heated to a target preset temperature, the current source is controlled to stop supplying power to the chip to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured, and the target preset temperature is the sum of the initial temperature of the chip to be tested and a preset temperature difference.

[0015] Optionally, judging whether the chip to be tested has failed is based on the relationship between the measured values ​​of each temperature-sensitive electrical parameter of the chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, including: when the measured value of the temperature-sensitive electrical parameter of the chip to be tested is greater than the first temperature-sensitive electrical parameter failure threshold of the chip to be tested, characterizing that the chip to be tested has failed, the first temperature-sensitive electrical parameter failure threshold is the sum of a target drift value and an initial threshold voltage of the chip to be tested, the target drift value is the drift value of the threshold voltage of the chip to be tested during the current test; when the measured value of the temperature-sensitive electrical parameter of the chip to be tested is less than or equal to the first temperature-sensitive electrical parameter failure threshold of the chip to be tested, characterizing that the chip to be tested has not failed.

[0016] Optionally, the temperature-sensitive electrical parameter failure threshold of the chip to be tested includes the maximum value of the threshold voltage of the chip to be tested. Before judging whether the chip to be tested has failed based on the size relationship between each temperature-sensitive electrical parameter measurement value of the chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, the method also includes: obtaining a target drift value of the threshold voltage of the chip to be tested during the current test based on the number of tests of the current test and the target mapping relationship, the target mapping relationship characterizing the mapping relationship between the number of cycles of the load current and the drift value of the threshold voltage of the chip to be tested, and the number of cycles of the load current is the same as the number of tests of the test experiment.

[0017] Optionally, judging whether the chip to be tested has failed is based on the relationship between the measured values ​​of each temperature-sensitive electrical parameter of the chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, including: when a target difference is greater than a second temperature-sensitive electrical parameter failure threshold of the chip to be tested, determining that the chip to be tested has failed, the target difference being the difference between the measured value of the temperature-sensitive electrical parameter of the chip to be tested and the target drift value; and when the target difference is less than or equal to the second temperature-sensitive electrical parameter failure threshold of the chip to be tested, determining that the chip to be tested has not failed.

[0018] Optionally, the method also includes: when the temperature of the chip to be tested is heated to meet a preset temperature condition, controlling the current source to not supply power to all the chips to be tested, and measuring the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment, and determining this time as the first time, and determining that the temperature of the chip to be tested at the current moment is the maximum preset temperature; detecting the threshold voltage of the chip to be tested at the second time to obtain a target threshold voltage; and compensating for the maximum preset temperature using the square root t method according to the first time and the second time to obtain a compensation temperature corresponding to the target threshold voltage.

[0019] Optionally, after determining whether the chip to be tested has failed based on the relationship between the measured values ​​of each temperature-sensitive electrical parameter of the chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, the method further includes: obtaining a corrected junction temperature curve of the chip to be tested based on the maximum preset temperature of the chip to be tested and the corresponding threshold voltage and the minimum preset temperature of the chip to be tested and the corresponding measurement threshold voltage; determining the junction temperature distribution curve of each chip to be tested inside the module to be tested within N cycles, the junction temperature distribution curve including a mapping relationship between the highest temperature of the chip to be tested and the temperature-sensitive electrical parameter and a mapping relationship between the lowest temperature of the chip to be tested and the temperature-sensitive electrical parameter.

[0020] Applying the technical solution of the present application, the detection device of the above chip includes: a detection circuit, including an electrically connected current source and a plurality of first switching devices, the first switching devices are used to be electrically connected to the chips to be tested in the module to be tested in a one-to-one correspondence, and each first switching device is connected to the connection branch between the current source and the chip to be tested. The device can effectively avoid the junction temperature measurement error caused by the bipolar degradation of the chip, accurately measure the chip junction temperature of the module during the power cycle, and establish an accurate thermal network model in combination with the electrothermal characteristics of multiple chips under multi-physical field coupling. The extracted thermal resistance parameters are combined with the junction temperature detection method so that the online measurement error of the junction temperature is within ±0.2°C, which solves the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has a large error and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 A schematic structural diagram of a chip detection device provided according to an embodiment of the present application is shown;

[0023] Figure 2 A schematic structural diagram of another chip detection device provided according to an embodiment of the present application is shown;

[0024] Figure 3 A schematic structural diagram of another chip detection device provided according to an embodiment of the present application is shown;

[0025] Figure 4 A schematic structural diagram of another chip detection device provided according to an embodiment of the present application is shown;

[0026] Figure 5 A schematic structural diagram of another chip detection device provided according to an embodiment of the present application is shown;

[0027] Figure 6 A physical diagram of a chip detection device provided according to an embodiment of the present application is shown;

[0028] Figure 7 A schematic flow chart of a method for detecting a chip to be detected by using any of the detection devices described above according to an embodiment of the present application is shown;

[0029] Figure 8 A flow chart of another method for detecting a chip to be detected using any of the detection devices described above is shown according to an embodiment of the present application.

[0030] The above drawings include the following reference numerals:

[0031] 10. Detection circuit; 11. Chip to be tested; 20. Current source; 30. Chip to be tested; 40. Industrial chiller; 50. Drive module; 60. Switch module; 70. Gate voltage scanning module; 80. Current sampling module; 90. Voltage sampling module; 100. Temperature sampling module; 110. Functional protection module; 120. Calculation control module; 130. Auxiliary power supply module; 140. Chip to be tested mounting device; 150. DSP+FPGA control board; 160. PC terminal. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] As introduced in the background technology, in the prior art, most power circulation devices use a method of injecting a small current to measure the body diode voltage drop to measure the junction temperature of SiC MOSFET discrete devices and modules. However, due to process limitations, the chip bipolar degradation problem in the prior art is serious, and the designed SiC MOSFET module usually requires the use of an anti-parallel diode, but at this time the anti-parallel diode will divide the test current and cannot form a reliable test voltage. In addition, the error in measuring the junction temperature using the body diode method is large, which greatly affects the life estimation of the chip and module. In addition, the power modules in the prior art all share a common gate terminal, and the junction temperature measured by the temperature-sensitive electrical parameters is only the average junction temperature of each chip, and the measurement of the junction temperature distribution inside the module cannot be achieved.

[0036] In order to solve the problem that the method of measuring the junction temperature of silicon carbide devices in the prior art has large errors and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module, the embodiments of the present application provide a chip detection device and a method for detecting the chip to be tested using the detection device.

[0037] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0038] In this embodiment, a method for detecting a chip to be tested using any of the above-mentioned detection devices is provided. It should be noted that although the logical order is shown in the flow chart, in some cases, the steps shown or described may be performed in an order different from that here.

[0039] Figure 1 Schematic diagram of the structure of the chip detection device according to the embodiment of the present application. Figure 1 and Figure 2 As shown, the detection device includes: a detection circuit 10, including an electrically connected current source 20 and multiple first switching devices, the above-mentioned first switching devices are used to electrically connect to the chips to be tested in the module to be tested in a one-to-one correspondence, and each of the above-mentioned first switching devices is connected to the connection branch between the above-mentioned current source 20 and the above-mentioned chip to be tested.

[0040] The chip to be tested is a silicon carbide chip. Figure 2 As shown, each first switching device S ij For parallel multi-chip structure, g ij is the gate of the corresponding chip to be tested; i=1,2; j=1,2,…,n.

[0041] The detection device of the above chip of the present application includes: a detection circuit, including an electrically connected current source and a plurality of first switching devices, the first switching devices are used to be electrically connected to the chips to be tested in the module to be tested in a one-to-one correspondence, and each first switching device is connected to the connection branch between the current source and the chip to be tested. The device can effectively avoid the junction temperature measurement error caused by the bipolar degradation of the chip, accurately measure the chip junction temperature of the module during the power cycle, and establish an accurate thermal network model in combination with the electrothermal characteristics of multiple chips under multi-physical field coupling. The extracted thermal resistance parameters are combined with the junction temperature detection method so that the online measurement error of the junction temperature is within ±0.2°C, which solves the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has a large error and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module.

[0042] Compared with traditional power circulation devices, this detection device can monitor the status of each chip in the silicon carbide power module through various circuit modules, locate the cause of failure at the chip level, and complete the reliability testing of modules and chips more accurately and efficiently.

[0043] In some instances, such as Figure 2 As shown, the detection circuit further includes a plurality of second switch devices and a companion test module. The companion test module includes a plurality of companion test chips 30. The second switch devices correspond to the companion test chips 30 one by one. The first end of the second switch device is electrically connected to the control end of the corresponding companion test chip 30, and the second end of the second switch device is electrically connected to the first end of the corresponding companion test chip 30.

[0044] Specifically, the companion test module is flexibly connected when a chip in the module to be tested fails, so that other healthy chips in the module to be tested can continue to perform life test experiments until the ultimate life of all chips in the module to be tested is obtained, which greatly improves test efficiency, reduces test costs, and shortens the optimization cycle of chip design. Moreover, the companion test module is not limited in number and has high flexibility.

[0045] In some instances, such as Figure 2 As shown, the detection circuit further includes a third switch device S0, a first end of the third switch device S0 is electrically connected to the current source 20, and a second end of the third switch device S0 is electrically connected to each of the first switch devices.

[0046] Specifically, the third switch device is used to control the connection or disconnection between the current source and the chip to be tested and the accompanying test module.

[0047] In some instances, such as Figure 3 As shown, the detection device further includes: an industrial chiller 40, which is electrically connected to the module to be tested and is used to cool the chip to be tested 11.

[0048] Specifically, the industrial chiller can cool the chip to be tested and the accompanying chip to prevent the chip to be tested and the accompanying chip from being damaged due to excessive temperature.

[0049] In some instances, such as Figure 4 As shown, the circuit further includes a driving module 50 , a switch module 60 , a gate voltage scanning module 70 , a current sampling module 80 , a voltage sampling module 90 , a temperature sampling module 100 and a functional protection module 110 electrically connected to the chip under test 11 .

[0050] Specifically, the status of each chip in the silicon carbide power module is monitored through various circuit modules, the cause of failure is located at the chip level, and the reliability test of the module and chip is completed more accurately and efficiently.

[0051] In some instances, such as Figure 5 As shown, the above circuit also includes a calculation control module 120 and an auxiliary power supply module 130 .

[0052] Specifically, in this way, the status of each chip in the silicon carbide power module can be monitored through each circuit module, and the reliability test of the module and the chip can be completed more accurately and efficiently.

[0053] In some examples, the actual image of the chip detection device is as follows Figure 6As shown, in the actual operation process, the physical circuit includes a current source 20, an industrial chiller 40, a chip to be tested mounting device 140, a DSP+FPGA control board 150 and a PC terminal 160. Among them, the current source outputs a large current, the industrial chiller is connected to the chip to be tested mounting device through a water inlet pipe and a water outlet pipe to cool the chip to be tested and the accompanying chip to be tested, the DSP+FPGA control board collects the test data of the chip to be tested and the accompanying chip to be tested, and drives the control and protection of the chip to be tested and the accompanying chip to be tested, and finally displays the test data and test results on the PC terminal.

[0054] Another embodiment of the present application further provides a method for detecting a chip to be detected using any of the above-mentioned detection devices, Figure 7 1 is a flow chart of a method for detecting a chip to be detected using any of the above-mentioned detection devices according to an embodiment of the present application. Figure 7 As shown, the above method comprises the following steps:

[0055] Step S101, when the temperature of the chips to be tested is heated to meet a preset temperature condition, the current source is controlled to not supply power to all the chips to be tested, and the temperature-sensitive electrical parameter measurement values ​​of the chips to be tested at the current moment are measured;

[0056] Specifically, the chip under test is a chip within the chip under test, and the chip under test generally refers to an individual in a module form or a TO package form containing the chip under test, that is, a product with complete electrical performance. The method of using any of the above detection devices to detect the chip under test is not only applicable to the junction temperature distribution measurement of silicon carbide modules, but also can be used for the junction temperature distribution measurement of other power modules.

[0057] Wherein, when the temperature of the above-mentioned chips to be tested is heated to meet the preset temperature condition, before the current source is controlled to stop supplying power to all the above-mentioned chips to be tested, the above-mentioned method further includes the following steps:

[0058] Step S201, determining whether there is an initial temperature calibration curve of the chip to be tested, wherein the initial temperature calibration curve is a calibration curve between the temperature-sensitive electrical parameters of the chip to be tested and the temperature;

[0059] Before determining whether there is an initial temperature calibration curve of the chip to be tested, the method further comprises: detecting an initial temperature of the chip to be tested, where the initial temperature is a minimum preset temperature of the chip to be tested.

[0060] Specifically, the initial temperature of the chip to be tested is detected, and the temperature of the chip to be tested in the initial state can be recorded, so that the initial temperature data can be used as a reference to determine whether the device drops to the initial temperature after power-on.

[0061] Among them, health status characterization quantities such as on-state voltage drop and thermal resistance can also be measured.

[0062] In some examples, the measured values ​​of the temperature-sensitive electrical parameters include threshold voltage, on-state voltage drop, and thermal resistance. When at least one of these three parameters exceeds a corresponding threshold, it is determined that the chip under test has failed.

[0063] In some examples, when the threshold voltage exceeds 10% of the original value, and / or the on-state voltage drop exceeds 5% of the original value, and / or the thermal resistance exceeds 20% of the original value, it is determined that the chip under test fails.

[0064] Step S202 , in the case where there is an initial temperature calibration curve of the chip under test, controlling the current source to provide a load current to the chip under test, so as to supply power to the chip under test.

[0065] Specifically, by comparing the on-state voltage drop of the chip under test before no current is passed and the on-state voltage drop of the chip under test after current is passed, it is possible to determine whether the chip under test is failed, and by comparing the thermal resistance of the chip under test before no current is passed and the thermal resistance of the chip under test after current is passed, it is also possible to determine whether the chip under test is failed.

[0066] Wherein, in the case where there is an initial temperature calibration curve of the chip to be tested, controlling the current source to provide a load current for the chip to be tested to power the chip to be tested comprises the following steps:

[0067] Step S2021, when there is an initial temperature calibration curve of the target chip to be tested currently being tested, disconnect all the first switch devices;

[0068] Step S2022: Control all the chips to be tested to be turned on, so as to control the current source to provide load current to all the chips to be tested, so as to heat all the chips to be tested.

[0069] Specifically, by disconnecting the switching device to power on the chip under test, the chip under test can be heated, so that it is possible to determine whether the chip under test has failed by measuring the working parameters of the chip under test after heating, and evaluate the junction temperature curve of the chip under test, so as to effectively control the failure of the chip under test in subsequent practical applications.

[0070] Compared with the traditional module junction temperature measurement, heating all the chips to be tested at the same time can realize the junction temperature distribution measurement of each parallel chip in the silicon carbide power module, and the test topology is simple. It is built through a common PCB board. It only needs to switch the test object through switch control to complete the junction temperature measurement of each chip. There is no need to customize the module packaging structure, and the cost is low. At the same time, this method is not limited by the number of parallel chips, and only needs to replace the PCB board, which is very flexible.

[0071] Step S102, applying a control signal to the control terminal of the chip under test to put the chip under test in a cut-off state, and closing a first switch device corresponding to the chip under test;

[0072] Step S103, when the temperature of the chip under test is lowered to the corresponding lowest preset temperature, measuring and obtaining the temperature-sensitive electrical parameter measurement value of the chip under test at the current moment, wherein the temperature-sensitive electrical parameter measurement value at least includes a measurement threshold voltage;

[0073] In some instances, the chip under test is cooled by a heat dissipation system such as a water cooler.

[0074] Among them, the detection circuit includes multiple switching devices and multiple parallel-connected chips to be tested, and the above-mentioned switching devices correspond one-to-one to the above-mentioned chips to be tested. When the temperature of the above-mentioned chip to be tested is heated to meet the preset temperature conditions, the above-mentioned current source is controlled to stop supplying power to the above-mentioned chip to be tested, and the measurement value of the temperature-sensitive electrical parameters of the above-mentioned chip to be tested at the current moment is obtained, and when the temperature of the above-mentioned chip to be tested is reduced to the lowest preset temperature, the measurement value of the temperature-sensitive electrical parameters of the above-mentioned chip to be tested at the current moment is obtained.

[0075] Specifically, it is necessary to detect the above-mentioned multiple parallel-connected chips to be tested in this way. First, a preset temperature condition is set. When the target chip to be tested is heated to meet the preset temperature condition, the threshold voltage of the target chip to be tested is recorded at this time to obtain the corresponding relationship between the threshold voltage of the target chip to be tested under the preset temperature condition. Then, the above-mentioned current source is controlled to stop supplying power to the chip to be tested to cool down all the chips to be tested, and when the target chip to be tested is reduced to the lowest preset temperature, the threshold voltage of the target chip to be tested is detected. The lowest preset temperature is the initial temperature. In this way, the size of the threshold voltage after the target chip to be tested is determined, thereby determining how many current cycles the target chip to be tested will fail.

[0076] The detection circuit includes N chips to be tested connected in parallel, the maximum cycle period of the load current provided by the current source is M times, the maximum number of measurements of the detection method is equal to the maximum cycle period of the load current, and the cycle period of the load current is the period during which the current source provides the load current. , k is a positive integer, the method further includes: testing each of the above-mentioned chips to be tested in this way, and only testing one of the above-mentioned chips to be tested in one current cycle; and / or, the above-mentioned detection circuit includes a third switching device, the first end of the above-mentioned third switching device is electrically connected to the above-mentioned current source, and the second end of the above-mentioned third switching device is electrically connected to each of the above-mentioned first switching devices respectively, and controlling the above-mentioned current source to not supply power to all of the above-mentioned chips to be tested, including: disconnecting the above-mentioned third switching device so that the above-mentioned current source does not supply power to all of the above-mentioned chips to be tested.

[0077] Specifically, this can achieve the measurement of junction temperature distribution of each parallel chip in the silicon carbide power module. The test topology is simple, built through a common PCB board, and the junction temperature measurement of each chip can be completed by switching the test object through switch control, without the need to customize the module packaging structure, and the cost is low. At the same time, this method is not limited by the number of parallel chips, and only needs to replace the PCB board, which is very flexible.

[0078] The time that the current source passes current once is the current cycle period. For example, if the current is passed once every 1 second or 2 seconds, the current cycle period is 1 second or 2 seconds, and the completion of one cycle (i.e. passing the current once) is considered a test.

[0079] In some instances, the maximum cycle period of the current is 1000 times (i.e., the maximum number of tests is 1000 times), and the detection circuit includes 10 chips to be tested in parallel. The first chip to be tested is tested for the first time, the second chip to be tested is tested for the second time, ..., the first chip to be tested is tested for the eleventh time, the second chip to be tested is tested for the twelfth time, and so on.

[0080] Among them, when the temperature of the above-mentioned chip to be tested is heated to meet the preset temperature condition, the current source is controlled not to supply power to all the above-mentioned chips to be tested, and the temperature-sensitive electrical parameter measurement value of the above-mentioned chip to be tested at the current moment is measured, including: when the temperature of the above-mentioned chip to be tested is heated to the maximum preset temperature, the current source is controlled to stop supplying power to the above-mentioned chip to be tested, and the temperature-sensitive electrical parameter measurement value of the above-mentioned chip to be tested at the current moment is measured; or, when the temperature of the above-mentioned chip to be tested is heated to the target preset temperature, the current source is controlled to stop supplying power to the above-mentioned chip to be tested, and the temperature-sensitive electrical parameter measurement value of the above-mentioned chip to be tested at the current moment is measured, and the target preset temperature is the sum of the initial temperature of the above-mentioned chip to be tested and the preset temperature difference.

[0081] Specifically, the maximum temperature for heating the chip to be tested can be set in this way to prevent damage to the device caused by excessive heating temperature. For example, the maximum preset temperature can be 120°C, 150°C, 200°C, etc. When the initial temperature is 20°C or 50°C, the preset temperature difference can be 100°C, where the initial temperature can also be a negative number to simulate winter or plateau environments.

[0082] Step S104 , judging whether the chip under test is failed according to the magnitude relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding failure threshold values ​​of the temperature-sensitive electrical parameters.

[0083] Specifically, compared with the body diode junction temperature measurement method in the traditional power cycling device, the above embodiment can effectively avoid the junction temperature measurement error caused by chip bipolar degradation and accurately measure the chip junction temperature of the module during the power cycling process.

[0084] Among them, the failure threshold of the temperature-sensitive electrical parameter of the above-mentioned chip to be tested includes the maximum value of the threshold voltage of the above-mentioned chip to be tested. Before judging whether the above-mentioned chip to be tested has failed based on the size relationship between the measured values ​​of each of the above-mentioned temperature-sensitive electrical parameters of the above-mentioned chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, the above-mentioned method also includes: according to the number of tests of the current test and the target mapping relationship, obtaining the target drift value of the threshold voltage of the above-mentioned chip to be tested during the current test, the above-mentioned target mapping relationship represents the mapping relationship between the number of cycles of the load current and the drift value of the threshold voltage of the chip to be tested, and the number of cycles of the above-mentioned load current is the same as the number of tests of the test experiment.

[0085] Specifically, most power cycle devices on the market currently use a small current injection method to measure the body diode voltage drop to measure the junction temperature of SiC MOSFET discrete devices and modules. However, due to process limitations, domestic chips have more serious bipolar degradation problems than internationally advanced chips. At this time, the error of using the body diode method to measure the junction temperature is large, which greatly affects the life estimation of chips and modules.

[0086] The above steps take into account the problem of low accuracy caused by the threshold voltage drift problem when using any of the above detection devices to detect the chip to be tested. The threshold voltage offset of the corresponding silicon carbide device under different current cycle times is pre-tested through test experiments, so that the drift of the threshold voltage is taken into account in the comparison of the threshold value, which can effectively improve the accuracy of measuring the chip junction temperature of the module during the power cycle.

[0087] According to the relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding failure threshold values ​​of the temperature-sensitive electrical parameters, judging whether the chip under test has failed includes the following steps:

[0088] Step S401, determining that the chip under test has failed when the target difference is greater than the second temperature-sensitive electrical parameter failure threshold of the chip under test, the target difference being the difference between the temperature-sensitive electrical parameter measurement value of the chip under test and the target drift value;

[0089] Step S402: When the target difference is less than or equal to the second temperature-sensitive electrical parameter failure threshold of the chip under test, it is determined that the chip under test is not failed.

[0090] Specifically, through preliminary experiments, the magnitude of the threshold voltage shift of the corresponding silicon carbide device under different current cycle numbers can be tested in advance, so that the drift of the threshold voltage is taken into account in the comparison of the threshold, which can effectively improve the accuracy of measuring the chip junction temperature of the module during the power cycle.

[0091] In some examples, preliminary experiments have shown that the threshold voltage of the silicon carbide device drifts by 0.5V after the 1000th current cycle, that is, the target drift value is 0.5V, and the target coefficient can be set to 110%, that is, the test threshold voltage cannot exceed the compensation threshold voltage by 10%, otherwise the device fails.

[0092] According to the relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding failure threshold values ​​of the temperature-sensitive electrical parameters, judging whether the chip under test has failed includes the following steps:

[0093] Step S301, when the measured value of the temperature-sensitive electrical parameter of the chip under test is greater than the first temperature-sensitive electrical parameter failure threshold of the chip under test, it is characterized that the chip under test fails, the first temperature-sensitive electrical parameter failure threshold is the sum of the target drift value and the initial threshold voltage of the chip under test, and the target drift value is the drift value of the threshold voltage of the chip under test during the current test;

[0094] Step S302: When the measured value of the temperature-sensitive electrical parameter of the chip under test is less than or equal to a first temperature-sensitive electrical parameter failure threshold of the chip under test, it indicates that the chip under test is not failed.

[0095] Specifically, the threshold voltage can be used to effectively determine whether the chip under test has failed. The electrothermal characteristics of multiple chips under multi-physical field coupling are combined to establish an accurate thermal network model. The extracted thermal resistance parameters are combined with the junction temperature detection method to ensure that the online measurement error of the junction temperature is within ±0.2°C.

[0096] The above method further comprises the following steps:

[0097] Step S501, when the temperature of the above-mentioned chips to be tested is heated to meet the preset temperature condition, the current source is controlled not to supply power to all the above-mentioned chips to be tested, and the temperature-sensitive electrical parameter measurement value of the above-mentioned chips to be tested at the current moment is measured, and the time at this moment is determined to be the first time, and the temperature of the above-mentioned chips to be tested at the current moment is determined to be the maximum preset temperature;

[0098] Step S502, detecting the threshold voltage of the chip to be tested at a second time to obtain a target threshold voltage;

[0099] Step S503 , compensating the maximum preset temperature by using a square root t method according to the first time and the second time to obtain a compensation temperature corresponding to the target threshold voltage.

[0100] Specifically, since there is a delay time between controlling the above-mentioned current source to stop supplying power to the chip to be tested and starting to detect the threshold voltage of the chip to be tested, and the temperature of the chip to be tested will drop during this period of time, the temperature of the chip to be tested is compensated by using the square root of t. This can effectively determine the actual temperature of the chip to be tested when starting to detect the threshold voltage of the chip to be tested, making the test more accurate.

[0101] After determining whether the chip under test is failed based on the relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding failure thresholds of the temperature-sensitive electrical parameters, the method further includes the following steps:

[0102] Step S601, obtaining a modified junction temperature curve of the chip to be tested according to the maximum preset temperature and the corresponding threshold voltage of the chip to be tested and the minimum preset temperature and the corresponding measurement threshold voltage of the chip to be tested;

[0103] Step S602, determining the junction temperature distribution curve of each of the chips under test in the module under test within N cycles, wherein the junction temperature distribution curve includes a mapping relationship between the maximum temperature of the chip under test and a temperature-sensitive electrical parameter and a mapping relationship between the minimum temperature of the chip under test and a temperature-sensitive electrical parameter.

[0104] Specifically, compared with the body diode junction temperature measurement method in the traditional power cycle device, the measurement topology and method proposed in the above example take into account the drift of the threshold voltage, which can effectively avoid the junction temperature measurement error caused by the chip bipolar degradation and accurately measure the chip junction temperature of the module during the power cycle. In addition, an accurate thermal network model is established by combining the electrothermal characteristics of multiple chips under multi-physical field coupling, and the extracted thermal resistance parameters are combined with the junction temperature detection method to make the junction temperature online measurement error reach within ±0.2°C. And it can realize the junction temperature distribution measurement of each parallel chip in the silicon carbide power module. The test topology is simple and is built through a common PCB board. It only needs to switch the test object through switch control to complete the junction temperature measurement of each chip. There is no need to customize the module packaging structure, and the cost is low. At the same time, this method is not limited by the number of parallel chips. It only needs to replace the PCB board, which is very flexible.

[0105] The method of using any one of the above-mentioned detection devices to detect the chip to be tested in the present application, first, when the temperature of the above-mentioned chip to be tested is heated to meet the preset temperature condition, the current source is controlled to not supply power to all the above-mentioned chips to be tested, and the temperature-sensitive electrical parameter measurement value of the above-mentioned chip to be tested at the current moment is measured; then, a control signal is applied to the control end of the above-mentioned chip to be tested to put the above-mentioned chip to be tested in a cut-off state, and the first switch device corresponding to the above-mentioned chip to be tested is closed; then, when the above-mentioned chip to be tested is lowered to the corresponding minimum preset temperature, the temperature-sensitive electrical parameter measurement value of the above-mentioned chip to be tested at the current moment is measured, and the above-mentioned temperature-sensitive electrical parameter measurement value at least includes a measurement threshold voltage; finally, according to the relationship between the above-mentioned temperature-sensitive electrical parameter measurement value of the above-mentioned chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, it is judged whether the above-mentioned chip to be tested has failed. This method can effectively avoid the junction temperature measurement error caused by chip bipolar degradation, accurately measure the chip junction temperature of the module during the power cycle, and establish an accurate thermal network model based on the electrothermal characteristics of multiple chips under multi-physical field coupling. The extracted thermal resistance parameters are combined with the junction temperature detection method to achieve an online measurement error of the junction temperature within ±0.2°C, which solves the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has a large error and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module.

[0106] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method of using any of the above-mentioned detection devices to detect the chip to be tested in the present application will be described in detail below in combination with specific embodiments.

[0107] This embodiment relates to a specific method for testing a chip to be tested by using any of the above-mentioned detection devices, such as Figure 8 As shown, the following steps are included:

[0108] Step S1: Start the power cycle test to determine whether there is a temperature calibration curve for the chip to be tested. If there is no temperature calibration curve, establish a calibration curve between the temperature-sensitive electrical parameters and temperature of the chip to be tested. If there is a temperature calibration curve, start the chiller and start the current source to enter the current cycle.

[0109] Step S2: Determine whether the maximum current cycle period has been reached. If the maximum current cycle period has not been reached, disconnect S ij (i=1, 2; j=1, 2,..., n), closed g ij (i=1, 2; j=1, 2, ..., n), at this time S ij With g ij The values ​​of i in S are the same. ij With g ijThe value of j is the same, S0 is closed, and the chip under test is heated by current to determine whether the chip under test reaches the set power cycle aging conditions (temperature difference, maximum temperature, etc.). If not, the chip under test continues to be heated by current. If so, S0 is disconnected and g is disconnected. ij (i=1, 2; j=1, 2,..., n), closed S ij (i=1, 2; j=1, 2, ..., n), at this time S ij With g ij The values ​​of i in S are the same. ij With g ij The value of j is the same;

[0110] Step S3: measuring the temperature-sensitive electrical parameters of the chip to be tested, extracting the highest temperature, and performing delay compensation and aging error compensation on the temperature. The chip to be tested is cooled to determine whether the chip to be tested has reached the set minimum temperature. If it has not cooled to the minimum temperature, the chip to be tested continues to be cooled. If it has cooled to the minimum temperature, measuring the temperature-sensitive electrical parameters of the chip to be tested at this time, extracting the minimum temperature, and performing delay measurement and aging error compensation on the temperature.

[0111] Step S4: determining whether the chip under test fails according to the magnitude of the actually measured temperature-sensitive electrical parameter and the preset temperature-sensitive electrical parameter; if the actually measured temperature-sensitive electrical parameter is greater than the preset temperature-sensitive electrical parameter, determining that the chip under test fails; and if the actually measured temperature-sensitive electrical parameter is less than or equal to the preset temperature-sensitive electrical parameter, determining that the chip under test does not fail;

[0112] Step S5: If the device fails, the cycle test is terminated; if the device does not fail, step S2 is repeated.

[0113] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0114] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0115] 1) The detection device of the above-mentioned chip of the present application comprises: a detection circuit, comprising an electrically connected current source and a plurality of first switching devices, the first switching devices being used to be electrically connected to the chips to be tested in the module to be tested in a one-to-one correspondence, and each first switching device being connected to the connection branch between the current source and the chip to be tested. The device can effectively avoid the junction temperature measurement error caused by the bipolar degradation of the chip, accurately measure the chip junction temperature of the module during the power cycle, establish an accurate thermal network model in combination with the electrothermal characteristics of multiple chips under multi-physical field coupling, and combine the extracted thermal resistance parameters with the junction temperature detection method so that the junction temperature online measurement error is within ±0.2°C, which solves the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has a large error and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module.

[0116] 2) The method of using any one of the above detection devices to detect the chip to be tested in the present application, first, when the temperature of the above chip to be tested is heated to meet the preset temperature condition, the current source is controlled to not supply power to all the above chips to be tested, and the temperature-sensitive electrical parameter measurement value of the above chip to be tested at the current moment is measured; then a control signal is applied to the control end of the above chip to be tested to put the above chip to be tested in a cut-off state, and the first switch device corresponding to the above chip to be tested is closed; then, when the above chip to be tested is lowered to the corresponding minimum preset temperature, the temperature-sensitive electrical parameter measurement value of the above chip to be tested at the current moment is measured, and the temperature-sensitive electrical parameter measurement value at least includes a measurement threshold voltage; finally, according to the relationship between the temperature-sensitive electrical parameter measurement value of the above chip to be tested and the corresponding temperature-sensitive electrical parameter failure threshold, it is determined whether the above chip to be tested has failed. This method can effectively avoid the junction temperature measurement error caused by chip bipolar degradation, accurately measure the chip junction temperature of the module during the power cycle, and establish an accurate thermal network model based on the electrothermal characteristics of multiple chips under multi-physical field coupling. The extracted thermal resistance parameters are combined with the junction temperature detection method to achieve an online measurement error of the junction temperature within ±0.2°C, which solves the problem that the method for measuring the junction temperature of silicon carbide devices in the prior art has a large error and can only measure the average junction temperature of each chip but cannot measure the junction temperature distribution inside the module.

[0117] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip detection device, characterized in that: include: A detection circuit, comprising an electrically connected current source and a plurality of first switch devices, wherein the first switch devices are used to be electrically connected to the chips to be tested in the module to be tested in a one-to-one correspondence, each of the first switch devices is connected to a connection branch between the current source and the chip to be tested, the module to be tested is a packaged electrical component, the plurality of chips to be tested include two parts, any one part includes a plurality of chips to be tested connected in parallel, a gate of the chip to be tested is electrically connected to a first end of the corresponding first switch device, and a drain of the chip to be tested is electrically connected to a second end of the corresponding first switch device; The detection circuit further includes a plurality of second switch devices and a companion test module, wherein the companion test module includes a plurality of companion test chips, wherein the second switch devices correspond to the companion test chips one by one, wherein a first end of the second switch device is electrically connected to a control end of the corresponding companion test chip, and a second end of the second switch device is electrically connected to a first end of the corresponding companion test chip; The detection circuit further includes a third switch device, a first end of the third switch device is electrically connected to the current source, and a second end of the third switch device is electrically connected to each of the first switch devices.

2. The detection device according to claim 1, characterized in that: The detection device also includes: An industrial water chiller is electrically connected to the module to be tested and is used to cool the chip to be tested.

3. A method for testing a chip to be tested using the detection device according to any one of claims 1 to 2, characterized in that: The method comprises: When the temperature of the chip to be tested is heated to meet a preset temperature condition, the current source is controlled not to supply power to all the chips to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured; Applying a control signal to the control terminal of the chip under test to put the chip under test in a cut-off state, and closing a first switch device corresponding to the chip under test; When the chip under test is lowered to the corresponding lowest preset temperature, a temperature-sensitive electrical parameter measurement value of the chip under test at the current moment is measured, wherein the temperature-sensitive electrical parameter measurement value at least includes a measurement threshold voltage; Whether the chip under test fails is determined based on the magnitude relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding temperature-sensitive electrical parameter failure thresholds.

4. The method according to claim 3, characterized in that When the temperature of the chip to be tested is heated to meet a preset temperature condition, before controlling the current source to stop supplying power to all the chips to be tested, the method further includes: Determine whether there is an initial temperature calibration curve for the chip to be tested, where the initial temperature calibration curve is a calibration curve between a temperature-sensitive electrical parameter of the chip to be tested and temperature; In the case where there is an initial temperature calibration curve of the chip under test, the current source is controlled to provide a load current to the chip under test, so as to power the chip under test.

5. The method according to claim 4, characterized in that Before determining whether there is an initial temperature calibration curve of the chip to be tested, the method further includes: The initial temperature of the chip to be tested is detected, where the initial temperature is the lowest preset temperature of the chip to be tested.

6. The method according to claim 4, characterized in that In the case where there is an initial temperature calibration curve of the chip to be tested, controlling the current source to provide a load current for the chip to be tested so as to power the chip to be tested comprises: In the case where there is an initial temperature calibration curve of the target chip to be tested currently being detected, disconnecting all the first switch devices; All the chips to be tested are controlled to be turned on, so as to control the current source to provide load current to all the chips to be tested, so as to heat all the chips to be tested.

7. The method according to claim 3, characterized in that The detection circuit includes N chips to be tested connected in parallel, the maximum cycle period of the load current provided by the current source is M times, the maximum number of measurements of the detection method is equal to the maximum cycle period of the load current, and the cycle period of the load current is the period during which the current source provides the load current. , k is a positive integer, and the method further comprises: testing each of the chips to be tested in this manner, and testing only one of the chips to be tested in one current cycle; The detection circuit includes a third switching device, a first end of the third switching device is electrically connected to the current source, and a second end of the third switching device is electrically connected to each of the first switching devices, respectively. The current source is controlled to supply no power to all the chips to be tested, including: disconnecting the third switching device so that the current source does not supply power to all the chips to be tested.

8. The method according to claim 3, characterized in that When the temperature of the chip to be tested is heated to meet a preset temperature condition, the current source is controlled not to supply power to all the chips to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured, including: When the temperature of the chip to be tested is heated to a maximum preset temperature, the current source is controlled to stop supplying power to the chip to be tested, and a temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured; Alternatively, when the temperature of the chip to be tested is heated to a target preset temperature, the current source is controlled to stop supplying power to the chip to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured, and the target preset temperature is the sum of the initial temperature of the chip to be tested and a preset temperature difference.

9. The method according to claim 3, characterized in that: Judging whether the chip under test fails according to the relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding temperature-sensitive electrical parameter failure thresholds includes: In the case where the measured value of the temperature-sensitive electrical parameter of the chip to be tested is greater than a first temperature-sensitive electrical parameter failure threshold of the chip to be tested, it is characterized that the chip to be tested has failed, wherein the first temperature-sensitive electrical parameter failure threshold is the sum of a target drift value and an initial threshold voltage of the chip to be tested, and the target drift value is the drift value of the threshold voltage of the chip to be tested during the current test; When the measured value of the temperature-sensitive electrical parameter of the chip under test is less than or equal to the first temperature-sensitive electrical parameter failure threshold of the chip under test, it indicates that the chip under test has not failed.

10. The method according to claim 3, characterized in that: The temperature-sensitive electrical parameter failure threshold of the chip under test includes the maximum value of the threshold voltage of the chip under test. Before judging whether the chip under test fails according to the magnitude relationship between each temperature-sensitive electrical parameter measurement value of the chip under test and the corresponding temperature-sensitive electrical parameter failure threshold, the method further includes: Based on the test number of the current test and the target mapping relationship, the target drift value of the threshold voltage of the chip to be tested during the current test is obtained. The target mapping relationship represents the mapping relationship between the number of cycles of the load current and the drift value of the threshold voltage of the chip to be tested. The number of cycles of the load current is the same as the number of tests in the test experiment.

11. The method according to claim 10, characterized in that Judging whether the chip under test fails according to the relationship between the measured values ​​of the temperature-sensitive electrical parameters of the chip under test and the corresponding temperature-sensitive electrical parameter failure thresholds includes: In the case where the target difference is greater than a second temperature-sensitive electrical parameter failure threshold of the chip under test, determining that the chip under test has failed, the target difference being the difference between a measured value of the temperature-sensitive electrical parameter of the chip under test and the target drift value; When the target difference is less than or equal to the second temperature-sensitive electrical parameter failure threshold of the chip under test, it is determined that the chip under test has not failed.

12. The method according to claim 3, characterized in that The method further comprises: When the temperature of the chip to be tested is heated to meet the preset temperature condition, the current source is controlled not to supply power to all the chips to be tested, and the temperature-sensitive electrical parameter measurement value of the chip to be tested at the current moment is measured, and the time at this moment is determined to be the first time, and the temperature of the chip to be tested at the current moment is determined to be the maximum preset temperature; Detecting the threshold voltage of the chip to be tested at a second time to obtain a target threshold voltage; The maximum preset temperature is compensated by using a square root t method according to the first time and the second time to obtain a compensation temperature corresponding to the target threshold voltage.

13. The method according to claim 3, characterized in that After determining whether the chip under test has failed based on the magnitude relationship between each temperature-sensitive electrical parameter measurement value of the chip under test and the corresponding temperature-sensitive electrical parameter failure threshold, the method further includes: Obtaining a modified junction temperature curve of the chip to be tested according to the maximum preset temperature and the corresponding threshold voltage of the chip to be tested and the minimum preset temperature and the corresponding measurement threshold voltage of the chip to be tested; Determine the junction temperature distribution curve of each chip under test inside the module under test within N cycles, wherein the junction temperature distribution curve includes a mapping relationship between the maximum temperature of the chip under test and a temperature-sensitive electrical parameter and a mapping relationship between the minimum temperature of the chip under test and a temperature-sensitive electrical parameter.

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