Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes a capacitor including a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, in which at least one of the first electrode and the second electrode includes a nano-laminated electrode including a plurality of first material layers and a plurality of second material layers, a plurality of first material layers and a plurality of second material layers are alternately arranged, the plurality of first material layers including indium oxide (In2O3), the plurality of second material layers including molybdenum oxide (MoOx), each of the plurality of first material layers having a thickness of between about 2 angstroms and about 6 angstroms, and each of the plurality of second material layers including a single layer of molybdenum oxide.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0079934 filed in the Korean Intellectual Property Office on June 21, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor and a method of manufacturing the same. Background Art

[0004] According to the shrinking of semiconductor devices, the size of capacitors used in, for example, dynamic random access memory (DRAM) devices is also decreasing. As the size of the capacitor decreases, leakage current increases.

[0005] Before or during the process of implementing the embodiments of the present application, the information disclosed in this background technology section has been known or derived by the inventor, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the invention

[0006] Provided is a semiconductor device including a capacitor having relatively high capacitance in a high frequency region while having reduced leakage current by adopting an electrode material having a high work function.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to an aspect of example embodiments, a semiconductor device may include: a capacitor including a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a nano-stacked electrode, the nano-stacked electrode includes a plurality of first material layers and a plurality of second material layers, the plurality of first material layers and the plurality of second material layers are alternately arranged, and the plurality of first material layers include indium oxide (In 2 O 3 ), the plurality of second material layers include molybdenum oxide (MoO x ), each of the plurality of first material layers has a thickness between about 2 angstroms and about 6 angstroms, and each of the plurality of second material layers includes a single layer of molybdenum oxide.

[0009] According to an aspect of example embodiments, a semiconductor device may include: a capacitor including a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a nano-stacked electrode, the nano-stacked electrode includes an indium oxide (In 2 O 3 ), and the plurality of second material layers are respectively arranged between two adjacent first material layers in the plurality of first material layers, and each of the plurality of second material layers includes molybdenum oxide (MoO x ) and the nano-stacked electrode has a work function between about 4.95 eV and about 5.05 eV.

[0010] According to an aspect of example embodiments, a semiconductor device may include: a substrate; a contact structure located on the substrate; a lower electrode located on the contact structure, having a cylindrical shape and including a first nano-stacked electrode; a dielectric layer located on the lower electrode; and an upper electrode located on the dielectric layer, wherein the first nano-stacked electrode includes a dielectric layer including indium oxide (In 2 O 3 ) are respectively arranged between two adjacent first material layers in the plurality of first material layers, and each of the plurality of second material layers includes molybdenum oxide (MoO x ) and the first nano-stacked electrode has a work function between about 4.95 eV and about 5.05 eV.

[0011] According to an aspect of an example embodiment, a method of manufacturing a semiconductor device may include: forming a nano-stacked electrode on a substrate by repeating a deposition cycle of a material layer pair k times, the material layer pair including a first material layer and a second material layer, wherein the deposition cycle of the material layer pair includes repeating a first material layer deposition cycle m times on the substrate, the first material layer deposition cycle including depositing indium oxide (In 2 O 3 ) and repeating a second material layer deposition cycle n times on the substrate, the second material layer deposition cycle comprising depositing molybdenum oxide (MoO x ), where m is in the range of 10 to 30, and n is 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments;

[0014] Figure 2According to one or more example embodiments Figure 1 a cross-sectional view of a first electrode;

[0015] Figure 3 According to one or more example embodiments Figure 1 a cross-sectional view of a second electrode;

[0016] Figure 4 is a timing diagram illustrating a method of manufacturing a nano-stacked electrode according to one or more example embodiments;

[0017] Figure 5 is a flow chart illustrating a first material layer deposition cycle according to one or more example embodiments;

[0018] Figure 6 is a flow chart illustrating a second material layer deposition cycle according to one or more example embodiments;

[0019] Figure 7 is an X-ray diffraction analysis graph of a nano-stacked electrode according to one or more example embodiments;

[0020] Figure 8 is a graph showing binding energy of a nano-stacked electrode measured by ultraviolet photoelectron spectroscopy (UPS) according to one or more example embodiments;

[0021] Fig. 9 is a graph showing resistivity, carrier concentration, and mobility of a nano-stacked electrode according to one or more example embodiments;

[0022] Fig.10 shows an image representing the surface morphology of a nano-stacked electrode measured using an atomic force microscope (AFM) according to one or more example embodiments;

[0023] Fig.11 is a scanning electron microscope image of a capacitor according to a comparative example;

[0024] Fig.12 is a scanning electron microscope image of a capacitor according to one or more example embodiments;

[0025] Fig.13 is an energy band diagram of a capacitor according to a comparative example;

[0026] Fig.14 is an energy band diagram of a capacitor according to one or more example embodiments;

[0027] Fig.15 is a graph showing capacitance of a capacitor relative to frequency according to one or more example embodiments;

[0028] Fig.16is a graph showing capacitance in a high frequency region of a capacitor according to one or more example embodiments;

[0029] Fig.17 is a graph showing current intensity and voltage characteristics of a capacitor according to one or more example embodiments;

[0030] Fig.18 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments;

[0031] Fig.19 According to one or more example embodiments Fig.18 an enlarged view of part A;

[0032] Fig. 20 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments;

[0033] Fig.21 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments;

[0034] as well as

[0035] Fig. 22 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments. DETAILED DESCRIPTION

[0036] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto, and can be implemented in various other forms.

[0037] As used herein, expressions such as "at least one of...", when following a list of elements, modify the entire list of elements rather than the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0038] Figure 1 is a cross-sectional view illustrating a semiconductor device 1 according to one or more example embodiments. Figure 2 According to one or more example embodiments Figure 1 FIG. 5 is a cross-sectional view of the first electrode 20 . Figure 3 According to one or more example embodiments Figure 1 4 is a cross-sectional view of the second electrode 40.

[0039] Reference Figure 1, the semiconductor device 1 may include a substrate 10, a first electrode 20, a dielectric layer 30, and a second electrode 40. For example, the first electrode 20, the dielectric layer 30, and the second electrode 40 may constitute a capacitor (eg, a capacitor having a metal-insulator-metal (MIM) structure).

[0040] The first electrode 20 may include Figure 2 The nano-laminated electrode NE described herein may include a plurality of first material layers 22 and a plurality of second material layers 24 that are alternately arranged.

[0041] In some embodiments, the plurality of first material layers 22 may include indium oxide (In 2 O 3 ). For example, the plurality of first material layers 22 may be formed by an atomic layer deposition (ALD) process, and each of the plurality of first material layers 22 may have a first thickness t11 of about 2 angstroms to about 6 angstroms.

[0042] In some embodiments, the plurality of second material layers 24 may include molybdenum oxide (MoO x ). For example, the plurality of second material layers 24 may be formed by an ALD process and may have a second thickness t12 of about 1 angstrom or less.

[0043] For example, each of the plurality of second material layers 24 may include a single layer of molybdenum oxide. In some embodiments, each of the plurality of second material layers 24 may be formed as follows: Figure 2 In some embodiments, each of the plurality of second material layers 24 may be formed as island-shaped particles or aggregates arranged on the top surface of the first material layer 22 .

[0044] For example, a monolayer of molybdenum oxide may refer to all monolayers or island-like particles or aggregates that are continuously extended as molybdenum oxide. For example, a monolayer of molybdenum oxide may be formed by repeating a second material layer deposition cycle of an ALD process n times, where n may be 1. However, in some embodiments, a monolayer of molybdenum oxide may be formed by repeating a second material layer deposition cycle of an ALD process n times, where n may be any number between 1 and 5.

[0045] The first electrode 20 may be formed by repeatedly performing a first material layer deposition cycle for forming each of the plurality of first material layers 22 and a second material layer deposition cycle for forming each of the plurality of second material layers 24 at a predetermined ratio. For example, the first material layer deposition cycle and the second material layer deposition cycle may be repeatedly performed, so that the first material layer deposition cycle is performed until the first material layer 22 is formed to have a first thickness t11 of about 2 angstroms to about 6 angstroms, then the second material layer deposition cycle is performed to form a single layer of molybdenum oxide, then the first material layer deposition cycle is performed until the first material layer 22 is formed to have a first thickness t11 of about 2 angstroms to about 6 angstroms, then the second material layer deposition cycle is subsequently performed to form a single layer of molybdenum oxide. This process may be repeated until the desired structure is constructed. The first electrode 20 may have a thickness t10 of, for example, about 10 nanometers to about 50 nanometers.

[0046] In some embodiments, dielectric layer 30 may include a metal oxide as a high-k dielectric material. In some embodiments, dielectric layer 30 may include titanium oxide. In some embodiments, dielectric layer 30 may include at least one of zirconium oxide, hafnium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanum oxide.

[0047] The second electrode 40 may include Figure 3 The nano-laminated electrode NE described herein may include a plurality of first material layers 42 and a plurality of second material layers 44 that are alternately arranged.

[0048] In some embodiments, the plurality of first material layers 42 may include indium oxide (In 2 O 3 For example, the plurality of first material layers 42 may be formed by an ALD process, and each of the plurality of first material layers 42 may have a first thickness t21 of about 2 angstroms to about 6 angstroms.

[0049] In some embodiments, the plurality of second material layers 44 may include molybdenum oxide (MoO x ). For example, the plurality of second material layers 44 may be formed by an ALD process and may have a second thickness t22 of about 1 angstrom or less. The second electrode 40 may have a thickness t20 of, for example, about 10 nanometers to about 50 nanometers.

[0050] For example, each of the plurality of second material layers 44 may include a single layer of molybdenum oxide. In some embodiments, each of the plurality of second material layers 44 may be formed as follows: Figure 3 In some embodiments, each of the plurality of second material layers 44 may be formed as island-shaped particles or aggregates arranged on the top surface of the first material layer 42 .

[0051] In some embodiments, Figure 2 and Figure 3 The nano-stacked electrode NE shown in FIG. 4 may have a work function of about 4.95 eV to about 5.05 eV. Since the nano-stacked electrode NE is formed in a stacked structure of indium oxide and molybdenum oxide having a relatively high work function, the nano-stacked electrode NE may have a work function higher than that of an electrode according to a comparative example such as titanium nitride (TiN) (e.g., 4.5 eV).

[0052] In some embodiments, in the X-ray diffraction analysis results, Figure 2 and Figure 3 The nano-stacked electrode NE shown in FIG. 1 may present a first peak at 30.48±0.02° originating from the indium oxide (222) plane having a cubic structure and a second peak at 35.43±0.02° originating from the indium oxide (400) plane. In some embodiments, Figure 2 and Figure 3 The nano-laminate electrode NE shown in FIG. 4 may have a surface roughness of 1 nm or less, for example, a surface roughness in the range of about 0.6 nm to about 1.0 nm.

[0053] In some embodiments, Figure 2 and Figure 3 The nano-stacked electrode NE shown in FIG. 1 may have a carrier concentration higher than or equal to that of indium oxide. In addition, Figure 2 and Figure 3 The nano-stacked electrode NE shown in FIG. 2 may have a resistivity lower than or equal to that of indium oxide. For example, when the first material layer 22 of the nano-stacked electrode NE is formed to have a thickness t11 of about 2 angstroms to about 6 angstroms, the resistivity of the nano-stacked electrode NE may be in a range of about 0.1 times to about 1 times the resistivity of indium oxide.

[0054] In some embodiments, the first electrode 20, the dielectric layer 30, and the second electrode 40 may constitute a MIM type capacitor having a relatively high capacitance value over the entire frequency range from the low frequency region to the high frequency region. For example, the capacitor may have a first capacitance at 1 kHz and a second capacitance at 1 MHz, and the second capacitance may be greater than 50% of the first capacitance (e.g., greater than 80% of the first capacitance). In addition, the capacitor may have a significantly lower leakage current than, for example, a capacitor including titanium nitride as an electrode.

[0055] In some embodiments, when the first material layer 22 of the nano-stacked electrode NE is formed to have a thickness t11 of about 2 angstroms to about 6 angstroms and the second material layers 24 each consisting of a single layer of molybdenum oxide are respectively formed between the plurality of first material layers 22, the nano-stacked electrode NE can exhibit a high work function, high carrier mobility, low resistivity, and low surface roughness. In addition, the capacitor including the nano-stacked electrode NE can have a relatively high capacitance value from a low frequency region to a high frequency region, and can have a very low leakage current.

[0056] Figure 4 is a timing diagram illustrating a method DP of manufacturing a nano-stacked electrode according to one or more example embodiments. Figure 5 is a flowchart illustrating a first material layer deposition cycle DPA according to one or more example embodiments. Figure 6 is a flowchart illustrating a second material layer deposition cycle DPB according to one or more example embodiments.

[0057] Reference Figures 4 to 6 , the method DP for manufacturing a nano-stacked electrode may be a method based on an ALD process. For example, a nano-stacked electrode may be formed by sequentially and repeatedly performing a first material layer deposition cycle DPA and a second material layer deposition cycle DPB on a substrate in a reaction chamber. The first material layer deposition cycle DPA and the second material layer deposition cycle DPB may be collectively referred to as a deposition cycle of a material layer pair.

[0058] For example, Figure 4 As shown in, the nano-stacked electrode can be formed by the following steps: first perform the first cycle DP_A1 of the first material layer, then perform the first cycle DP_B1 of the second material layer, then sequentially perform the second cycle DP_A2 of the first material layer and the second cycle DP_B2 of the second material layer, and then perform the kth cycle DP_Ak of ​​the first material layer and the kth cycle DP_Bk of the second material layer, and perform various repeated operations therebetween as needed to form the overall desired structure. That is, the deposition cycle of the material layer pair can be repeated k times. The range of k can be determined in consideration of the total thickness of the nano-stacked electrode, the growth rate of the material layer in each cycle, etc.

[0059] like Figure 5 As shown in , the first material layer deposition cycle DPA may include a unit cycle, which sequentially includes supplying a first metal source (e.g., a metal source including indium) (operation S12), purging (operation S14), supplying a first oxygen source (operation S16), and purging (operation S18). As shown in operation S20, the first material layer deposition cycle DPA may include sequentially repeating operations S12 to S18 m times, where m may be in the range of approximately 10 to 30.

[0060] In one or more example embodiments, in the supplying of the first metal source in operation S12, the first metal source may be supplied into the reaction chamber, and the first metal source may include an organic metal precursor including indium. The first metal source may include trimethylindium (In(CH 3 ) 3 At least one of )(TMIn), [1,1,1-trimethyl-N-(trimethylsilyl)silylamino]indium (InCA-1), [3-(dimethylamino)propyl]dimethylindium (DADI), and cyclopentadienylindium (InCp). In some embodiments, the first metal source may be DADI, but is not limited thereto. For example, the supply of the first metal source of operation S12 may be performed for a period of about 0.5 seconds to about 3 seconds.

[0061] Thereafter, in the purging of operation S14 , an excess of the first metal source that is not adsorbed on the substrate may be purged and / or removed.

[0062] In the supply of the first oxygen source of operation S16, the first oxygen source may be supplied to the reaction chamber, and the first oxygen source may include at least one of hydrogen peroxide, oxygen, ozone, and oxygen plasma. The first oxygen source may also be referred to as a reactant. In the supply of the first oxygen source of operation S16, a reaction between the first metal source adsorbed on the substrate and the first oxygen source may occur to form a first material layer including indium oxide. For example, the supply of the first oxygen source of operation S16 may be performed for a period of about 1 second to about 20 seconds.

[0063] Thereafter, in the purge of operation S18 , an excess of the first oxygen source that is not adsorbed on the substrate may be purged and / or removed.

[0064] For example, indium oxide having a thickness of approximately 0.15 angstroms to 0.20 angstroms may be formed during a unit cycle that sequentially includes supplying a first metal source (operation S12), purging (operation S14), supplying a first oxygen source (operation S16), and purging (operation S18). When m, which is the number of repetitions of a unit cycle in the first material layer deposition cycle DPA, is less than 10, it may be difficult to form the first material layer (indium oxide) to have a thickness thick enough to crystallize, and when m is greater than 30, the first material layer (indium oxide) is formed to have too large a thickness, and thus the nano-stacked electrode may have a relatively large resistivity or a relatively low work function.

[0065] like Figure 6As shown in , the second material layer deposition cycle DPB may include a unit cycle, which sequentially includes supplying a second metal source including molybdenum (operation S32), purging (operation S34), supplying a second oxygen source (operation S36), and purging (operation S38). As shown in operation S40, the second material layer deposition cycle DPB may include sequentially repeating operations S32 to S38 n times, where n may be at least 1.

[0066] In some embodiments, in the supply of the second metal source in operation S32, the second metal source may be supplied to the reaction chamber, and the second metal source may include an organic metal precursor including molybdenum. The first metal source may include bis(tert-butylimino)bis(dimethylamino)molybdenum (TBDMMo), bis(ethylbenzene)molybdenum, MoF 6 、MoCl 6 and Mo(CO) 6 In some embodiments, the second metal source may be TBDMMo, but is not limited thereto. For example, the supply of the second metal source of operation S32 may be performed for a period of about 0.5 seconds to about 5 seconds.

[0067] Thereafter, in the purge of operation S34 , an excess of the second metal source that is not adsorbed on the substrate may be purged and / or removed.

[0068] In the supply of the second oxygen source of operation S36, the second oxygen source may be supplied to the reaction chamber, and the second oxygen source may include at least one of hydrogen peroxide, oxygen, ozone and oxygen plasma. The second oxygen source may also be referred to as a reactant. In the supply of the second oxygen source of operation S36, a reaction between the second metal source adsorbed on the substrate and the second oxygen source may occur to form a second material layer including molybdenum oxide. For example, a monolayer of molybdenum oxide may be formed on the first material layer. For example, the supply of the second oxygen source of operation S36 may be performed for a period of about 1 second to about 20 seconds.

[0069] Thereafter, in the purge of operation S38 , an excess of the second oxygen source that is not adsorbed on the substrate may be purged and / or removed.

[0070] For example, molybdenum oxide having a thickness of approximately 1 angstrom or less or approximately 0.15 angstrom to 0.20 angstrom may be formed during a unit cycle that sequentially includes supplying a second metal source (operation S32), purging (operation S34), supplying a second oxygen source (operation S36), and purging (operation S38). In the second material layer deposition cycle DPB, n (which is the number of repetitions of the unit cycle) may be 1.

[0071] In some embodiments, the second material layer composed of a monolayer of molybdenum oxide can be formed as a monolayer arranged on the first material layer and extending continuously, or can be formed as island particles or aggregates arranged on the top surface of the first material layer. In some embodiments, since molybdenum atoms have a relatively small atomic radius, molybdenum atoms can be arranged to occupy interstitial sites that are not occupied by indium atoms inside the first material layer.

[0072] The ratio of m (which corresponds to the number of repetitions of a unit cycle in the first material layer deposition cycle DPA) to n (which corresponds to the number of repetitions of a unit cycle in the second material layer deposition cycle DPB) may be determined to be approximately 10: 1 to 30: 1. For example, when the first material layer deposition cycle DPA and the second material layer deposition cycle DPB are performed in the range of approximately 10: 1 to 30: 1, the nano-stacked electrode may be formed to have a high work function, high carrier mobility, low resistivity, and low surface roughness.

[0073] In the following, reference will be made to Figures 7 to 17 The physical properties and electrical properties of the nano-stacked electrode according to the ratio of the number of first material layer deposition cycles DPA to the number of second material layer deposition cycles DPB are described.

[0074] Experimental Example 1

[0075] As shown in Table 1, a first material layer deposition cycle DPA and a second material layer deposition cycle DPB are performed on a substrate in an ALD apparatus at ratios of approximately 30:1, 20:1, 10:1, and 5:1, respectively, to form a nano-stacked electrode having a total thickness of approximately 20 nm. As a comparative example, only the first material layer deposition cycle DPA is performed to form indium oxide (In 2 O 3 ) single-layer electrode.

[0076] [Table 1]

[0077]

[0078] Figure 7 is an X-ray diffraction analysis graph of a nano-stacked electrode according to one or more example embodiments.

[0079] Reference Figure 7 , X-ray diffraction analysis curves of Examples 1 to 4 (Table 1) and X-ray diffraction analysis curves of Comparative Example (Table 1) Figure 1. Examples 1 to 3 show a first peak originating from a plane (222) of indium oxide having a cubic crystal structure and a second peak originating from its plane (400). The first peak appears at 30.48±0.02°, and the second peak appears at 35.43±0.02°. It can be seen that the comparative example and Example 4 do not have a peak corresponding to the second peak originating from the plane (400). This is because in the case of Examples 1 to 3, each of which forms a monolayer of molybdenum oxide at a ratio of approximately 30:1, 20:1, and 10:1, the molybdenum oxide monolayer or molybdenum atoms is used as an intermediate layer (insertion layer) or an added element to improve the crystallinity of indium oxide.

[0080] Figure 8 is a graph illustrating binding energy of a nano-stacked electrode measured by ultraviolet photoelectron spectroscopy (UPS) according to one or more example embodiments.

[0081] Reference Figure 8 , the binding energies of Examples 1 to 4 are shown together with the binding energies of Comparative Example 1 (indium oxide) and Comparative Example 2 (titanium nitride). Table 2 shows the work functions of Examples 1 to 4, Comparative Examples 1 and 2 calculated from the binding energies measured by ultraviolet photoelectron spectroscopy (UPS).

[0082] [Table 2]

[0083] serial number <![CDATA[In 2 O 3 :MoO x Composition ratio]]> Binding energy (eV) Work function (eV) Comparative Example 1 <![CDATA[Only In 2 O 3 > 16.31 4.91 Comparative Example 2 TiN only 16.77 4.45 Example 1 30:1 16.27 4.95 Example 2 20:1 16.19 5.03 Example 3 10:1 16.17 5.05 Example 4 5:1 15.88 5.34

[0084] As shown in Table 2, as the content of molybdenum increases, the work function increases, and for example, in the case of Examples 1 to 3, each of which forms a monolayer of molybdenum oxide at a ratio of approximately 30: 1, 20: 1, and 10: 1, it can be seen that the work function is relatively high, approximately 4.95 eV, 5.03 eV, and 5.05 eV, respectively. It can be confirmed that this is a value larger than the work function of each of Comparative Example 1 (indium oxide) and Comparative Example 2 (titanium nitride).

[0085] Fig. 9 is a graph illustrating resistivity, carrier concentration, and mobility of a nano-stacked electrode according to one or more example embodiments.

[0086] Reference Fig. 9 It can be confirmed that the resistivity, carrier concentration, and mobility of each of Examples 1 to 3 of Table 2 are superior to or equal to those of each of the Comparative Examples of Table 2. Specifically, Example 2 in which a monolayer of molybdenum oxide is formed at a ratio of approximately 20:1 exhibits the highest carrier concentration, the highest charge mobility (e.g., 92.6 cm 2 / V·s charge mobility) and the lowest resistivity (e.g., a resistivity of 240 μΩ·cm), thereby presenting the best electrical characteristics. That is, as Examples 1 to 3, it can be seen that the nano-layered electrode in which a single layer of an indium oxide layer and a molybdenum oxide layer having a thickness of about 2 angstroms to about 6 angstroms is repeatedly formed has the highest carrier concentration and the lowest resistivity.

[0087] Example 4 (Table 2) in which a single layer of molybdenum oxide is formed at a ratio of approximately 5:1 exhibits lower carrier concentration and mobility than the comparative example, and the highest resistivity, and it can be considered that this is because the molybdenum content is increased to cause amorphization of indium oxide or because the free carrier mobility is reduced due to the scattering effect of molybdenum.

[0088] Fig.10 An image representing the surface morphology of a nano-stack electrode measured using an atomic force microscope (AFM) according to one or more example embodiments is shown.

[0089] Reference Fig.10 , Examples 1 and 2 have surface roughness values ​​greater than that of the comparative example. That is, in Examples 1 and 2, as the content of molybdenum increases, the crystallinity of the indium oxide layer is improved, thereby increasing the surface roughness value, and on the contrary, Example 4 has the smallest surface roughness value. In the case of Example 4 in which a single layer of molybdenum oxide is formed at a ratio of approximately 5:1 with a relatively large molybdenum content, it can be considered that the surface roughness is reduced to the greatest extent as amorphization is caused.

[0090] All of Examples 1 to 4 have a surface roughness of 1 nm or less, which may be low enough to reduce leakage current by reducing trap sites at the interface between the dielectric layer and the nano-stack electrode.

[0091] Experimental Example 2

[0092] The capacitors according to the embodiment and the comparative example were formed on a substrate in an ALD apparatus as shown in Table 3.

[0093] [Table 3]

[0094] Comparison Examples Example Lower electrode TiN 20nm <![CDATA[In 2 O 3 :MoO x =20:1,20nm]]> Dielectric layer <h2 style=";text-align:left;direction:ltr"><![CDATA[TiO <h2 style=";text-align:left;direction:ltr"> 2 <h2 style=";text-align:left;direction:ltr"> 21nm]]><h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr"><![CDATA[TiO <h2 style=";text-align:left;direction:ltr"> 2 <h2 style=";text-align:left;direction:ltr"> 21nm]]><h2 style=";text-align:left;direction:ltr"> Upper electrode Ag 44nm Ag 44nm

[0095] Fig.11 is a scanning electron microscope image of a capacitor according to a comparative example. Fig.12 is a scanning electron microscope image of a capacitor according to one or more example embodiments.

[0096] Reference Fig.11 and Fig.12 , it can be seen that the comparison example ( Fig.11 ) and Example ( Fig.12) is formed as a continuous material layer covering the entire substrate with a uniform thickness. In addition, it can be seen that the interface between the lower electrode and the dielectric layer also has excellent interface properties without interface defect elements (such as gaps or seams).

[0097] Fig.13 is an energy band diagram EB_CO of a capacitor according to a comparative example. Fig.14 is an energy band diagram EB_EX of a capacitor according to an embodiment.

[0098] Reference Fig.13 The capacitor according to the comparative example has a work function WF1 of the lower electrode TiN of 4.5 eV, and the work function WF1 of the lower electrode TiN is 4.2 eV (which is the dielectric layer TiO 2 The conduction band EC) of the lower electrode has a relatively small difference. Therefore, at the interface between the lower electrode and the dielectric layer, the band offset BO_1 has a relatively small value. When the band offset at the interface between the lower electrode and the dielectric layer is small, leakage current may occur due to thermal electron emission.

[0099] Reference Fig.14 , the capacitor according to the embodiment has a lower electrode (In 2 O 3 :MoO x ) has a work function WF2, which is similar to the 4.2 eV dielectric layer (TiO 2 ) has a relatively large difference in conduction band EC. Therefore, at the interface between the lower electrode and the dielectric layer, the band offset BO_2 has a relatively large value. When the band offset at the interface between the lower electrode and the dielectric layer is large, the occurrence of leakage current can be significantly reduced or lowered.

[0100] Fig.15 is a graph illustrating capacitance of a capacitor with respect to frequency according to one or more example embodiments. Fig.16 is a graph illustrating capacitance in a high frequency region of a capacitor according to one or more example embodiments.

[0101] Reference Fig.15 and Fig.16 , the capacitor according to the comparative example has a large capacitance value of 800 pF or more in the low frequency region, but the capacitance value gradually decreases as the frequency increases, and has a capacitance value of 240 pF or less in the high frequency region of 1 MHz. The capacitor according to the embodiment has a large capacitance value of about 950 pF or more in the low frequency region, maintains an almost constant capacitance value even if the frequency increases, and has a capacitance value of about 800 pF or less in the high frequency region of 1 MHz.

[0102] In other words, although the capacitance value of the embodiment in the low frequency region is greater than that of the comparative example, showing no significant difference, the capacitance value of the embodiment in the high frequency region has a significantly greater value equivalent to three times that of the comparative example.

[0103] In general, it is known that the balanced series resistance component in the low frequency region represents a value corresponding to the dielectric loss due to dielectric relaxation, and as the frequency increases, the influence of the series resistance and inductance becomes dominant, thereby reducing the capacitance and balanced series resistance affected by the loss due to the electrode. The lower electrode according to the embodiment has a dielectric loss coefficient of 0.243 at 1 MHz, while the lower electrode according to the comparative example has a dielectric loss coefficient of 1.31 at 1 MHz. Therefore, since the lower electrode in the high frequency region according to the embodiment has a significantly lower dielectric loss coefficient than the lower electrode according to the comparative example (i.e., because the carrier mobility of the lower electrode according to the embodiment is high and its resistivity is low), the lower electrode according to the embodiment can have a high capacitance value.

[0104] Fig.17 is a graph illustrating current intensity and voltage characteristics of a capacitor according to one or more example embodiments.

[0105] Reference Fig.17 , the capacitor according to the comparative example exhibits 1.75×10 -5 The leakage current intensity of the capacitor according to the embodiment is 6.03×10 -9 , which is about 3000 times the leakage current of the comparative example.

[0106] The narrow band gap of titanium oxide used as the dielectric layer may generate a large leakage current due to Schottky emission at the interface between the dielectric layer and the lower electrode. However, since the lower electrode (referred to as In 2 O 3 :MoO x ) has a high work function, so the potential barrier between the lower electrode and the dielectric layer can be increased to effectively block the leakage path, thereby reducing the leakage current of the capacitor.

[0107] Fig.18 is a cross-sectional view illustrating a semiconductor device 100 according to one or more example embodiments. Fig.19 According to one or more example embodiments Fig.18 An enlarged view of part A of FIG.

[0108] Reference Fig.18 and Fig.19, the semiconductor device 100 may include a dynamic random access memory (DRAM) element, and may include a cell transistor formed on a substrate 110 and a capacitor CAP electrically connected to the cell transistor.

[0109] The lower insulating layer 112 may be disposed on the substrate 110, and the contact structure 114 may be disposed on the substrate 110 to penetrate the lower insulating layer 112. The contact structure 114 may include a conductive material. An etch stop layer 116 having an opening exposing a top surface of each of the contact structures 114 may be disposed on the lower insulating layer 112.

[0110] The capacitor CAP may be disposed on the etch stop layer 116. The capacitor CAP may include a lower electrode 120, a dielectric layer 130, and an upper electrode 140. The lower electrode 120 may have a cylindrical shape, a sidewall of a bottom of the lower electrode 120 may be surrounded by the etch stop layer 116, and a bottom of the lower electrode 120 may be disposed on a top surface of each of the contact structures 114. The lower electrode 120 may be formed with a relatively large height in a vertical direction or may have a large aspect ratio, and a support member 118 may be disposed on a sidewall of the lower electrode 120. The dielectric layer 130 may be conformally disposed on the inner and outer walls of the lower electrode 120. The upper electrode 140 may be disposed on the dielectric layer 130 to cover the lower electrode 120.

[0111] In some embodiments, the lower electrode 120 may include a plurality of first material layers 122 and a plurality of second material layers 124 arranged alternately. The lower electrode 120 may have a Figure 2 The structure of the nano-stacked electrode NE described above is similar to that of the nano-stacked electrode NE. For example, the plurality of first material layers 122 may each include indium oxide having a thickness of about 2 angstroms to about 6 angstroms, and the plurality of second material layers 124 may include a single layer including molybdenum oxide.

[0112] In some embodiments, dielectric layer 130 may include a metal oxide as a high dielectric constant material. In some embodiments, dielectric layer 130 may include titanium oxide. In some embodiments, dielectric layer 130 may include at least one of zirconium oxide, hafnium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanum oxide.

[0113] In some embodiments, the upper electrode 140 may include a plurality of first material layers 142 and a plurality of second material layers 144 arranged alternately. The upper electrode 140 may have a Figure 3 The structure of the nano-stacked electrode NE described above is similar to that of the nano-stacked electrode NE. For example, the plurality of first material layers 142 may each include indium oxide having a thickness of about 2 angstroms to about 6 angstroms, and the plurality of second material layers 144 may include a single layer including molybdenum oxide.

[0114] Fig. 20 is a cross-sectional view illustrating a semiconductor device 100A according to one or more example embodiments.

[0115] Reference Fig. 20 , the lower electrode 120 may include a nano-stacked electrode, and the nano-stacked electrode includes a plurality of first material layers 122 and a plurality of second material layers 124 arranged alternately. The upper electrode 140A may include at least one of the following materials: a metal, such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), etc.; a conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), tungsten nitride (WN), etc.; and a conductive metal oxide, such as iridium oxide (IrO 2 ), ruthenium oxide (RuO 2 ), strontium ruthenium oxide (SrRuO 3 )wait.

[0116] Fig.21 is a cross-sectional view illustrating a semiconductor device 100B according to one or more example embodiments.

[0117] Reference Fig.21 , the lower electrode 120A may have a pillar shape disposed on the top surface of the contact structure 114 and extending in a vertical direction. The dielectric layer 130 may be conformally disposed on the top surface and sidewalls of the lower electrode 120A.

[0118] In some embodiments, the lower electrode 120A may include an integral material layer extending in a vertical direction, and the lower electrode 120A may include a reference Figures 1 to 3 According to the manufacturing method in some embodiments, the lower electrode 120A can be formed by the following steps: forming a mold insulating layer having a columnar opening on a substrate, and Figures 4 to 6 The described manufacturing method forms a reference in the opening Figures 1 to 3 Described nanolaminated electrode NE.

[0119] In some embodiments, the lower electrode 120A may include a base column extending in a vertical direction, and an electrode layer conformally arranged on the sidewall and top surface of the base column. The base column may include at least one of the following materials: a metal such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), etc.; a conductive metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), tungsten nitride (WN), etc.; and a conductive metal oxide such as iridium oxide (IrO 2 ), ruthenium oxide (RuO 2), strontium ruthenium oxide (SrRuO 3 ) etc., and the electrode layer may include a reference Figures 1 to 3 Described nanolaminated electrode NE.

[0120] Fig. 22 is a cross-sectional view illustrating a semiconductor device 200 according to one or more example embodiments.

[0121] Reference Fig. 22 , the semiconductor device 200 may be a global shutter type image sensor, which includes a plurality of photoelectric conversion regions PD formed on a semiconductor substrate 210 and a capacitor CAP arranged on the front side of the semiconductor substrate 210. The transfer gate TG may be arranged to extend into the semiconductor substrate 210, and may be configured to control photoelectrons stored in the photoelectric conversion region PD. A pixel transistor may also be formed on the front surface of the semiconductor substrate 210, and the pixel transistor may be electrically connected to the capacitor CAP, and charges transferred from the photoelectric conversion region PD of each pixel may be stored in the capacitor CAP. The capacitor CAP may include a lower electrode 220, a dielectric layer 230, and an upper electrode 240, and at least one of the lower electrode 220 and the upper electrode 240 may include a reference Figures 1 to 3 The front wiring layer FL may be arranged on the front surface of the semiconductor substrate 210, the front insulating layer FI covering or at least partially covering the front wiring layer FL and the capacitor CAP may be provided on the front wiring layer FL, and the color filter CF and the micro lens ML may be arranged on the rear surface of the semiconductor substrate 210.

[0122] Each of the embodiments provided in the above description is not exclusive of being associated with one or more features of another example or another embodiment that is also provided herein or not provided herein but is consistent with the present disclosure.

[0123] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: A capacitor comprising: a first electrode; a second electrode; and a dielectric layer located between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode comprises a nano-stacked electrode, The nano-layered electrode comprises a plurality of first material layers and a plurality of second material layers, wherein the plurality of first material layers and the plurality of second material layers are arranged alternately. Wherein, the plurality of first material layers include indium oxide, Wherein, the plurality of second material layers include molybdenum oxide, Each of the plurality of first material layers has a thickness between 2 angstroms and 6 angstroms, and Wherein, each of the plurality of second material layers comprises a single layer of molybdenum oxide.

2. The semiconductor device according to claim 1, wherein The nano-stacked electrode has a thickness between 10 nanometers and 50 nanometers.

3. The semiconductor device according to claim 1, wherein The nano-stacked electrode has a work function between 4.95 eV and 5.05 eV.

4. The semiconductor device according to claim 1, wherein In the X-ray diffraction analysis results, the nano-stacked electrode exhibited a first peak at 30.48±0.02° originating from the indium oxide (222) plane having a cubic structure and a second peak at 35.43±0.02° originating from the indium oxide (400) plane.

5. The semiconductor device according to claim 1, wherein The dielectric layer includes a high-k dielectric metal oxide.

6. The semiconductor device according to claim 1, wherein The dielectric layer includes titanium oxide.

7. The semiconductor device according to claim 1, wherein The nano-stacked electrode includes a surface roughness of 1 nm or less.

8. The semiconductor device according to claim 1, wherein The capacitor has a first capacitance at a first frequency of 1 kHz and a second capacitance at a second frequency of 1 MHz, the second capacitance being greater than 50% of the first capacitance.

9. The semiconductor device according to claim 8, wherein: The second capacitance is greater than 80% of the first capacitance.

10. A semiconductor device comprising a capacitor, the capacitor comprising: a first electrode; a second electrode; as well as a dielectric layer located between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode comprises a nano-stacked electrode, Wherein, the nano-stacked electrode comprises: a plurality of first material layers including indium oxide; and a plurality of second material layers, each of which comprises a single layer of molybdenum oxide, and Wherein, the nano-stacked electrode has a work function between 4.95 eV and 5.05 eV.

11. The semiconductor device according to claim 10, wherein Each of the plurality of first material layers has a thickness of 2 angstroms to 6 angstroms, and Wherein, the nano-stacked electrode has a thickness between 10 nanometers and 50 nanometers.

12. The semiconductor device according to claim 10, wherein: In the X-ray diffraction analysis results, the nano-stacked electrode exhibited a first peak at 30.48±0.02° originating from the indium oxide (222) plane having a cubic structure and a second peak at 35.43±0.02° originating from the indium oxide (400) plane.

13. The semiconductor device according to claim 10, wherein: The dielectric layer includes a high-k dielectric metal oxide.

14. The semiconductor device according to claim 10, wherein: The dielectric layer includes titanium oxide.

15. The semiconductor device according to claim 10, wherein The nano-stacked electrode includes a surface roughness of 1 nm or less.

16. The semiconductor device according to claim 10, wherein: The capacitor has a first capacitance at a first frequency of 1 kHz and a second capacitance at a second frequency of 1 MHz, the second capacitance being greater than 50% of the first capacitance.

17. A semiconductor device comprising: substrate; a contact structure located on the substrate; a lower electrode, which is located on the contact structure, has a cylindrical shape, and includes a first nano-stacked electrode; a dielectric layer located on the lower electrode; as well as an upper electrode, which is located on the dielectric layer, Wherein, the first nano-stacked electrode comprises: a plurality of first material layers including indium oxide; and a plurality of second material layers, each of which comprises a single layer of molybdenum oxide, and Wherein, the first nano-stacked electrode has a work function between 4.95 eV and 5.05 eV.

18. The semiconductor device according to claim 17, wherein: The dielectric layer includes titanium oxide.

19. The semiconductor device according to claim 17, wherein: Each of the plurality of first material layers has a thickness between 2 angstroms and 6 angstroms, and Wherein, the first nano-stacked electrode has a thickness between 10 nanometers and 50 nanometers.

20. The semiconductor device according to claim 17, wherein The upper electrode comprises a second nano-layered electrode, Wherein, the second nano-stacked electrode comprises: a plurality of third material layers including indium oxide; and a plurality of fourth material layers, each of which comprises a single layer of molybdenum oxide, and Wherein, the second nano-stacked electrode has a work function between 4.95 eV and 5.05 eV.

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