Gate driver system and method of driving transistors between switching states

Abstract

A gate driver system and a method of driving a transistor between switching states are disclosed. The gate driver system includes an active thermal control (ATC) circuit that monitors a load current change in a load current conducted by the transistor, and enables or disables the ATC of the transistor based on the load current change. The ATC circuit is configured to evaluate a load current change reaching a duration threshold as a qualified load current change. The ATC circuit is configured to detect a direction and magnitude of the qualified load current change, compare the magnitude of the qualified load current change to a threshold, and enable the ATC of the transistor if the qualified load current change has a reduced direction and the magnitude of the qualified load current change reaches the threshold. The ATC circuit is configured to adjust a power dissipation parameter to adjust power dissipation of the transistor when the ATC is enabled.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronics, and in particular to conditional active thermal control that can increase the lifetime and efficiency of power semiconductors. Background Art

[0002] Modern devices rely on power semiconductor devices for many functions in motor vehicles, consumer and industrial applications (e.g., driving motors or electric machines). For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] A transistor typically includes a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures of the transistor. In addition, the load current can be controlled by a control electrode (sometimes referred to as a gate electrode) of the transistor. For example, upon receiving a corresponding control signal from, for example, a gate driver, the control electrode can set its transistor to one of a conducting state or a blocking state. Thus, the semiconductor structure behaves like a switch having an on-state and an off-state (i.e., a conducting state and a blocking state, respectively).

[0004] Typically, the power inverter is composed of two complementary transistors (e.g., a high-side transistor and a low-side transistor) for each motor phase, wherein the two complementary transistors form a half-bridge to drive an output disk connected to a motor winding. A gate driver for driving two complementary transistors can be supplied with a fixed positive voltage by a positive power rail, and a fixed negative voltage by a negative power rail. The positive power rail can be connected to the output disk by the high-side transistor of the two complementary transistors to supply a load current to the motor winding, and the negative power rail can be connected to the output disk by the low-side transistor of the two complementary transistors to sink a load current from the motor winding. Two complementary transistors can be turned on and off complementarily to avoid cross conduction.

[0005] Therefore, the load current (also called the motor phase current) can be controlled by driving two complementary transistors. The amplitude of the control signal received from the gate driver of each transistor can be varied to drive the two complementary transistors between the switching states. This in turn drives the motor. For example, the gate-source voltage Vgs of a MOSFET is usually driven to approximately zero to turn off the MOSFET, and is usually driven to a maximum value to fully turn on the MOSFET. For this reason, the gate-source voltage Vgs can be referred to as a control voltage.

[0006] During run operation, the motor may be driven according to a motor control algorithm to achieve a desired motor speed corresponding to the electrical frequency of the control signal. Summary of the invention

[0007] In some implementations, a gate driver system includes: a gate driver configured to be coupled to a control terminal of a transistor and configured to control a control voltage applied to the control terminal so as to drive the transistor between switching states; and an active thermal control circuit configured to monitor a load current change of a load current conducted by the transistor in a conducting state, and to enable or disable active thermal control of the transistor based on the load current change, wherein the active thermal control circuit is configured to evaluate a load current change that reaches a duration threshold as a qualified load current change, wherein the active thermal control circuit is configured to detect a direction of a qualified load current change among the qualified load current changes, wherein , the direction of the qualified load current change is an increasing direction or a decreasing direction, wherein the active thermal control circuit is configured to detect the amplitude of the qualified load current change among the qualified load current changes and compare the amplitude with a first threshold, wherein the active thermal control circuit is configured to: enable active thermal control of the transistor if the qualified load current change has a decreasing direction and the amplitude of the qualified load current change reaches the first threshold, wherein the active thermal control circuit is configured to adjust the power dissipation parameter to adjust the power dissipation of the transistor when the active thermal control is enabled, and wherein the active thermal control circuit is configured not to adjust the power dissipation parameter when the active thermal control is disabled.

[0008] In some implementations, a gate driver system includes: a gate driver configured to be coupled to a control terminal of a transistor and configured to control a control voltage applied to the control terminal so as to drive the transistor between a switching state; and an active thermal control circuit configured to monitor a load current conducted by the transistor in a conducting state and enable or disable active thermal control of the transistor based on the load current, wherein the active thermal control circuit is configured to determine an average load current of the load current and to evaluate a load current variation of the average load current, wherein evaluating the load current variation of the average load current includes: detecting a load current variation of the average load current; The active thermal control circuit is configured to detect a direction of load current change, wherein the direction of the load current change is an increasing direction or a decreasing direction; detect the magnitude of the load current change of the average load current; and compare the magnitude of the load current change with a first threshold, wherein the active thermal control circuit is configured to: enable active thermal control of the transistor if the load current change has a decreasing direction and the magnitude of the load current change reaches the first threshold, and wherein the active thermal control circuit is configured to adjust the power dissipation parameter to adjust the power dissipation of the transistor when the active thermal control is enabled, and wherein the active thermal control circuit is configured not to adjust the power dissipation parameter when the active thermal control is disabled.

[0009] In some implementations, a method for driving a transistor between switching states includes: monitoring a load current change of a load current conducted by a transistor in a conducting state; enabling or disabling active thermal control of the transistor based on the load current change; evaluating a load current change that reaches a duration threshold as a qualified load current change; detecting a direction of a qualified load current change among the qualified load current changes, wherein the direction of the qualified load current change is an increasing direction or a decreasing direction; detecting an amplitude of a qualified load current change among the qualified load current changes; comparing the amplitude to a first threshold; and enabling active thermal control of the transistor if the qualified load current change has a decreasing direction and the amplitude of the qualified load current change reaches the first threshold, wherein, when the active thermal control is enabled, the active thermal control circuit is enabled to adjust a power dissipation parameter to adjust the power dissipation of the transistor, and wherein, when the active thermal control is disabled, the active thermal control circuit is disabled so that the power dissipation parameter is not adjusted by the active thermal control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Implementations are described herein with reference to the accompanying drawings.

[0011] Figure 1 A schematic block diagram illustrating a motor control system according to one or more implementations is shown.

[0012] Figure 2 A schematic block diagram of a gate driver system according to one or more implementations is shown.

[0013] Figure 3A A schematic block diagram of an active thermal control (ATC) circuit is shown in accordance with one or more implementations.

[0014] Figure 3B A schematic block diagram of an ATC circuit is shown in accordance with one or more implementations.

[0015] Figure 3C A schematic block diagram of an ATC circuit is shown in accordance with one or more implementations.

[0016] Figure 4A Conditional ATC functionality according to one or more implementations is shown.

[0017] Figure 4B Conditional ATC functionality according to one or more implementations is shown.

[0018] Figure 5A A table showing different control modes for ATC and corresponding power dissipation parameters including gate resistance, switching frequency, gate voltage and modulation scheme is shown.

[0019] Figure 5B A table showing power dissipation parameters including gate resistance, switching frequency, gate voltage, and modulation scheme that may be used during a two-step control mode for ATC is shown.

[0020] Fig. 6A Parameter selection circuitry for a two-step control mode of an ATC circuit is shown in accordance with one or more implementations.

[0021] Figure 6B A parameter selection circuit for a multi-step control mode of an ATC circuit is shown in accordance with one or more implementations.

[0022] Figure 6C and Fig.6D Parameter selection circuitry for a continuous control mode of an ATC circuit is shown in accordance with one or more implementations. DETAILED DESCRIPTION

[0023] In the following, the details are set forth to provide a more comprehensive description of example implementations. However, it will be apparent to those skilled in the art that these implementations may be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form or schematic form rather than in detail to avoid obscuring the implementation. In addition, unless otherwise specifically stated, the features of the different implementations described below may be combined with each other.

[0024] In addition, equivalent or similar elements or elements having equivalent or similar functions are indicated by equivalent or similar reference numerals in the following description. Since the same elements or elements having equivalent functions are given the same reference numerals in the drawings, repeated descriptions of elements provided with the same reference numerals may be omitted. Therefore, the descriptions provided for elements having the same or similar reference numerals may be interchangeable.

[0025] Each of the illustrated x-axis, y-axis, and z-axis is substantially perpendicular to the other two axes. In other words, the x-axis is substantially perpendicular to the y-axis and the z-axis, the y-axis is substantially perpendicular to the x-axis and the z-axis, and the z-axis is substantially perpendicular to the x-axis and the y-axis. In some cases, a single reference numeral is shown to refer to a surface, or less than all instances of a component may be labeled with all surfaces of the component. All instances of a component may include associated surfaces of the component, even though not every surface is labeled.

[0026] The orientation of various elements in the drawings is shown as an example, and the examples shown can be rotated relative to the depicted orientation. The description provided herein and the subsequent claims relate to any structure having the relationship between various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to the orientation. Similarly, for ease of description, spatial relative terms such as "top", "bottom", "below", "below", "lower", "above", "upper", "middle", "left side" and "right side" are used herein to describe the relationship between an element and one or more other elements shown in the drawings. Spatial relative terms are intended to cover different orientations of elements, structures and / or components in use or operation except for the orientation depicted in the drawings. Structures and / or components can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article can be interpreted accordingly. In addition, to simplify the drawings, unless otherwise stated, the cross-sectional views in the drawings only show the features in the plane of the cross section, and the material behind the plane of the cross section is not shown.

[0027] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0028] In the implementations described herein or shown in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, and vice versa), as long as the general purpose of the connection or coupling is essentially maintained (e.g., transmitting a certain signal or transmitting certain information). Features from different implementations may be combined to form additional implementations. For example, unless otherwise stated, changes or modifications described with respect to one of the implementations may also be applicable to other implementations.

[0029] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, the terms "substantially" and "approximately" may be used herein to illustrate small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry without departing from aspects of the implementations described herein. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal having an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0030] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. may be used to modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of elements. On the contrary, such expressions are only used for the purpose of distinguishing elements from other elements. For example, a first box and a second box indicate different boxes, although both the first box and the second box are boxes. For another example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0031] A transistor may be referred to as a power switch, a logic switch, or a transistor switch, which may be used to drive a current, such as a load current. In particular, a power transistor is a power semiconductor device that may be used to drive a load current. A power transistor includes a first load terminal (e.g., a source or emitter) and a second load terminal (e.g., a drain or collector). Additionally, the load current path of the power transistor may be controlled by a control electrode (sometimes referred to as a gate) connected to a control terminal of the power transistor. The load current path of the power transistor is a gate-controlled conductive channel, the conductivity of which may be controlled by a control voltage applied to the control electrode of the power transistor. For example, a power transistor may be turned on or off by activating and deactivating its control electrode. For example, applying a positive voltage between the gate and source of a MOSFET will keep the MOSFET in an "on" state, while applying an approximately zero or slightly negative voltage between the gate and source of the MOSFET will turn the MOSFET "off".

[0032] There is a turn-on process for switching the transistor on and a turn-off process for switching the transistor off. During the turn-on process of the n-channel transistor, the gate driver can be used to provide (supply) a gate current (e.g., a turn-on current) to the gate of the n-channel transistor so as to charge the gate voltage to a voltage sufficient to turn on the n-channel transistor. On the contrary, during the turn-off process of the n-channel transistor, the gate driver is used to draw (absorb) a gate current (e.g., a turn-off current) from the gate of the n-channel transistor so as to fully discharge the gate voltage to turn off the n-channel transistor. A voltage pulse can be output from the gate driver as a control signal according to a pulse width modulation (PWM) scheme. Therefore, during the PWM cycle for controlling the n-channel transistor, the control signal can be switched between a turn-on voltage level and a turn-off voltage level. This in turn charges and discharges the gate voltage to turn on and off the n-channel transistor, respectively.

[0033] The situation of p-channel transistors is just the opposite. The gate driver can be used to draw (absorb) a gate current (e.g., a turn-on current) from the gate of the p-channel transistor in order to discharge the gate voltage to a voltage sufficient to turn on the p-channel transistor. Conversely, during the turn-off process of the p-channel transistor, the gate driver is used to provide (supply) a gate current (e.g., a turn-off current) to the gate of the p-channel transistor in order to fully charge the gate voltage of the p-channel transistor to turn off the p-channel transistor. During the PWM cycle for controlling the p-channel transistor, the control signal applied to the gate of the p-channel transistor can be switched between an on voltage level and an off voltage level. This in turn charges and discharges the gate voltage to turn on and off the p-channel transistor, respectively.

[0034] For both n-channel transistors and p-channel transistors, when the gate-source voltage Vgs is approximately zero or lower than the threshold voltage, the n-channel transistor and the p-channel transistor are turned off, and when the gate-source voltage Vgs is equal to or greater than the threshold voltage, the n-channel transistor and the p-channel transistor are turned on.

[0035] In order to drive the load in this manner, two transistors are typically arranged in a half-bridge configuration, including a high-side transistor and a low-side transistor. The high-side transistor can be a p-channel transistor connected to a high-side supply potential, while the low-side transistor can be an n-channel transistor connected to a low-side supply potential. In some implementations, the high-side transistor and the low-side transistor can be the same transistor type (e.g., both are n-channel types or both are p-channel types).

[0036] When the load current flows from the half-bridge to the load, the load current is referred to as a positive load current, and when the load current flows away from the load to the half-bridge, the load current is referred to as a negative load current. The high-side transistor is responsible for conducting the positive load current when it is turned on, so that when its complementary low-side transistor is turned off (for example, the low-side transistor is in a blocking or high-impedance mode), the load current is supplied to the load. In order to absorb the load current from the load, the role of the high-side transistor and the low-side transistor is reversed. Here, the low-side transistor is responsible for conducting the negative load current when it is turned on, so that when its complementary high-side transistor is turned off (for example, the high-side transistor is in a blocking or high-impedance mode), the load current is absorbed from the load. The two complementary transistors are usually switched so that the two are not turned on at the same time.

[0037] The transistor may include an IGBT and a MOSFET (e.g., a Si MOSFET or a SiC MOSFET), etc. It should be understood that one type of transistor may replace another type of transistor. In this case, in any of the examples described herein, when a MOSFET replaces an IGBT, the drain of the MOSFET may replace the collector of the IGBT, the source of the MOSFET may replace the emitter of the IGBT, the drain-source voltage Vds of the MOSFET may replace the collector-emitter voltage Vce of the IGBT, and the gate-source voltage Vgs of the MOSFET may replace the gate-emitter voltage Vge of the IGBT, and vice versa.

[0038] Some implementations described in the present disclosure relate to, but are not limited to, a half-bridge for driving a motor. For example, a multiphase inverter as a power inverter type is configured to provide multiphase power by supplying a multiphase load (e.g., a three-phase motor). For example, three-phase power involves three symmetrical sine waves that are 120 electrical degrees out of phase with each other. In a symmetrical three-phase power supply system, three conductors each carry an alternating current (AC) with the same frequency and voltage amplitude relative to a common reference but with a phase difference of one-third of the drive cycle. Due to the phase difference, the voltage on any one of the three conductors reaches its voltage peak at one-third of the drive cycle, wherein the voltage peaks of the three conductors are distributed with phase delays that are substantially equal to each other within the drive cycle. The phase delay provides constant power transmission for a balanced linear load. This also makes it possible to generate a rotating magnetic field in the motor.

[0039] The three-phase inverter includes three inverter branches, one for each of the three phases, and each inverter branch is connected to a direct current (DC) voltage source in parallel with each other. As described above, each inverter branch includes a pair of transistors arranged in a half-bridge configuration for converting DC into AC to drive a phase load. However, a multiphase inverter is not limited to three phases, and may include two or more phases, wherein an inverter branch is provided for each phase. In some cases, two half-bridges may be connected as an H-bridge circuit, wherein a load (e.g., a motor) is connected as a cross switch between two half-bridges as a single-phase load.

[0040] The power cycle life Nf of the transistor can be determined by factors such as the thermal stress on different packaging layers caused by the periodic variation of the junction temperature Tj of the transistor. For applications with expected large load variations (e.g., traction control, electric vehicles, and wind power generation), controlling and reducing the magnitude of the junction temperature variation ΔTj of the transistor is important for extending the life of the transistor. The junction temperature variation ΔTj may be caused by the power dissipation variation ΔP of the transistor. D Causes the power dissipation to change ΔP DThe load current change ΔIo may be caused by a load current change caused by a load change.

[0041] Although the load current variation ΔIo may not be controllable in all cases, if the system efficiency can be controlled to reduce the power dissipation variation ΔP of the transistor D , the junction temperature variation ΔTj of the transistor can also be reduced, so that the power cycle life Nf of the transistor can be increased. Active thermal control (ATC) technology can be used to regulate the power dissipation variation ΔP of the transistor by controlling the system efficiency when the load current Io changes. D , and thus adjust the junction temperature variation ΔTj of the transistor.

[0042] Some implementations disclosed herein relate to a gate driver system with an ATC circuit that is configured to improve system efficiency by enabling and disabling conditional ATC functionality. In order to balance the tradeoff between system efficiency and the power cycle life Nf of a transistor, an ATC mechanism that regulates transistor power loss (e.g., power dissipation) is enabled only when the expected junction temperature change ΔTj is large under certain conditions, rather than enabling the ATC function unconditionally and continuously. For example, when a substantial reduction in load current is detected, the ATC circuit can use an ATC mechanism (e.g., a power dissipation parameter to be adjusted) to increase the power dissipation of the transistor, and a substantial reduction in load current will result in a substantial reduction in junction temperature Tj. Therefore, the ATC circuit can enable the ATC of the transistor to increase the power dissipation of the transistor in order to reduce the junction temperature change ΔTj that would otherwise occur during a substantial reduction in load current. However, increasing the power dissipation of the transistor reduces system efficiency by introducing higher power losses. Therefore, the ATC circuit aims to balance the trade-off between system efficiency and the power cycle life Nf of the transistor by using conditional enablement of the ATC function only when a substantial reduction in the power cycle life Nf of the transistor is expected based on reaching certain enablement conditions.

[0043] The power dissipation of the transistor can be adjusted by controlling one or more power dissipation parameters, including a gate drive resistance Rg, a gate drive voltage Vg, a switching frequency of the transistor (e.g., corresponding to a switching frequency f of a PWM control signal), and a gate drive resistance Rg. sw ), or a PWM scheme M of a PWM control signal for controlling the switching state of a transistor PWM For example, the gate drive resistance Rg can be increased, the gate drive voltage Vg can be reduced, and the switching frequency f of the PWM control signal can be increased. sw Or change the PWM control signal to PWM scheme M PWMChanging to a less efficient modulation scheme (e.g., space vector PWM) to increase the power dissipation of the transistor. The ATC circuit can enable the ATC of the transistor in response to detecting certain enabling conditions so as to adjust one or more of the power dissipation parameters. Additionally, the ATC circuit can disable the ATC of the transistor in response to detecting certain disabling conditions so that the ATC circuit does not adjust any power dissipation parameters.

[0044] One criterion used to determine whether certain enabling conditions and / or certain disabling conditions have been reached is the duration of the load change. The dynamic thermal performance of the power semiconductor package and heat sink will determine how the junction temperature Tj responds to changes in the load current Io and the power dissipation P of the transistor. D This is mathematically given by Equation 1 and Equation 2:

[0045] ΔT JC = Z thJC * ΔP D (1)

[0046] ΔT CA = Z thCA * ΔP D (2)

[0047] Where, ΔT JC is the change in junction temperature Tj allocated to the dynamic thermal performance of the semiconductor junction to the case, ΔT CA is the change in case temperature Tc allocated to the dynamic thermal performance of the heat sink, Z thJC is the transient thermal impedance from semiconductor junction to case, and Z thCA is the transient thermal impedance of the heat sink. thJC and Z thCA It can be specified by the Cauer model or the Foster model, which is a series of low-pass filters with different time constants to convert the power dissipation of the transistor to a change of ΔP D Converted into a junction temperature change ΔTj. Therefore, the power dissipation change ΔP D The rapid changes in Z thJC and Z thCA is filtered out, and only the power dissipation changes ΔP D A slow change of the junction temperature may appear as a change in junction temperature ΔTj. In order to avoid unnecessary increase in semiconductor power dissipation, only the change in power dissipation ΔP D The transistor’s ATC should be enabled only when the duration of the current is longer than a certain time constant τ, which can be set to be proportional to Z thJC and Z thCA Here, fast changes are filtered out according to the time constant τ of the low-pass filter, while slow changes are passed according to the time constant τ of the low-pass filter.

[0048] Since the junction temperature variation ΔTj and the power cycle life Nf follow an inverse power law, the ATC of the transistor can be conditionally enabled only for large load variations rather than small load variations, so that the additional power loss from the ATC circuit is only used to mitigate large load variations that significantly consume the power cycle life Nf of the transistor. Therefore, the ATC of the transistor should be enabled only when the magnitude of the load variation (e.g., the magnitude of the load current variation ΔIo) exceeds a certain threshold ΔIo,Th.

[0049] In order to simultaneously achieve the conflicting requirements of increasing the power cycle life Nf and increasing the system efficiency, the criteria for turning on and off the ATC of the transistor can be established as follows. If the output load increases significantly from a low level (e.g., if the increased load current change ΔIo is large) and remains at a high level for at least one duration threshold (e.g., a time threshold), the ATC of the transistor should be turned off or maintained in an off state so that the system operates in a low-loss mode to minimize or avoid unnecessary power loss. If the output load decreases significantly from a high level (e.g., if the reduced load current change ΔIo is large) and remains at a low level for at least a duration threshold, the ATC of the transistor should be turned on to reduce the power dissipation change ΔP D , and thus reduce the junction temperature variation ΔTj or keep the junction temperature Tj unchanged.

[0050] In some implementations, the load current change ΔIo can be monitored by measuring the average value of the load current (e.g., the average load current) and monitoring the change in the average load current. For example, the combined conditions of the duration and amplitude of the average load change for turning on (enabling) and off (disabling) the ATC of the transistor may include: (1) when the ATC of the transistor is in the off state, the average load current decreases ΔIo with an amplitude and duration greater than the load current change threshold ΔIo,Th and the time constant τ, respectively, to turn on the ATC of the transistor; and (2) when the ATC of the transistor is in the on state, the average load current increases ΔIo with an amplitude and duration greater than the load current change threshold ΔIo,Th and the time constant τ, respectively, to turn off the ATC of the transistor.

[0051] In some implementations, the conditions can be further refined to reduce the junction temperature variation ΔTj by dynamically setting the load current threshold for turning off the ATC. For example, each time the ATC of the transistor is enabled, the load current threshold for turning off the ATC circuit can be adjusted. The load current threshold for turning off the ATC of the transistor can be set to the average value of the load current sampled at the trigger time, at which the enabling of the ATC is triggered by the ATC circuit. Thus, the ATC circuit can be configured to enable the ATC when the average load current exceeds the dynamic load current threshold for turning off the ATC.

[0052] Figure 1 A schematic block diagram showing a motor control system 100 according to one or more implementations is shown. In particular, the motor control system 100 includes a power inverter 102, a controller 104, and a gate driver 106. The controller 104 and the gate driver 106 work together as a motor control unit. In some implementations, the motor control unit can be a monolithic integrated circuit (IC), wherein the controller 104 and the gate driver 106 are arranged on a single IC. In some implementations, the motor control unit can be divided into two or more ICs, for example, wherein the controller 104 is arranged on a first IC and the gate driver 106 is arranged on one or more second ICs. It should be understood that although the implementations described herein are directed to driving motors, the concepts described herein can be extended to other types of inductive loads and are not limited to motors.

[0053] The motor control system 100 is also coupled to a motor M (e.g., a permanent magnet synchronous motor (PMSM) as an AC motor type) including three phases U, V, and W. The power inverter 102 in this example is a three-phase voltage generator configured to provide three-phase power to drive the motor M by supplying a three-phase voltage.

[0054] Deviations in both amplitude and phase may result in loss of power and torque to the motor M. Therefore, the controller 104 may be configured to monitor and control the amplitude and phase of the voltage supplied to the motor M in real time to ensure that proper current balance is maintained based on a feedback control loop.

[0055] The power inverter 102 for motor M includes a switch array of six transistors 108u, 108v, 108w, 109u, 109v and 109w arranged in complementary pairs. Each complementary pair forms a half-bridge circuit, and constitutes an inverter branch for supplying phase voltage to motor M. Therefore, each inverter branch includes a high-side transistor 108u, 108v or 108w and a low-side transistor 109u, 109v or 109w. In addition, each transistor 108u, 108v, 108w, 109u, 109v and 109w can be connected to corresponding freewheeling diodes D1 to D6 in anti-parallel. Freewheeling diodes D1 to D6 provide an alternative current path for current commutation for load current during the turn-off period of corresponding transistors 108u, 108v, 108w, 109u, 109v and 109w. For example, the freewheeling diode D1 provides an alternative current path with respect to the low-side transistor 109u during the off-time of the low-side transistor 109u.Similarly, the freewheeling diode D2 provides an alternative current path with respect to the high-side transistor 108u during the off-time of the high-side transistor 108u.

[0056] The load current paths U, V and W extend from the output disk Uout, Vout or Wout of each inverter branch (e.g., the output of each half-bridge circuit) between the complementary transistors and are configured to be coupled to a load, such as a motor M. Each load current path U, V and W carries a corresponding phase current Iu, Iv and Iw. Each phase current Iu, Iv and Iw has an AC electrical frequency that directly corresponds to the actual motor speed of the motor M.

[0057] The power inverter 102 is coupled to a DC power source (eg, a battery or a diode bridge rectifier) ​​and a gate driver 106 .

[0058] The controller 104 (which may be a microcontroller or another hardware-based controller) performs the motor control functions of the motor control system 100 in real time (or near real time) and transmits a PWM control signal to the gate driver 106. The controller 104 may use a PWM scheme to control the state of each transistor and ultimately control each phase current provided on the corresponding load current paths U, V, and W. The gate driver 106 generates a drive signal based on the PWM control signal for controlling the switch state (e.g., on state and off state) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. Therefore, the load current paths U, V, and W can be controlled by the controller 104 and the gate driver 106 by controlling the control electrodes (e.g., gate electrodes) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. For example, upon receiving a PWM control signal from the controller 104, the gate driver 106 may set the corresponding transistor 108u, 108v, 108w, 109u, 109v, or 109w to one of a conducting state (eg, an on state) or a blocking state (eg, an off state).

[0059] The gate driver 106 may include one or more gate drivers for driving transistors 108u, 108v, 108w, 109u, 109v and 109w between switch states. For example, the gate driver 106 may include a gate driver for each half-bridge circuit. The gate driver 106 may be configured to receive instructions including PWM control signals from the controller 104, and turn on and off transistors 108u, 108v, 108w, 109u, 109v and 109w respectively according to the received instructions and control signals. For example, during the conduction process of transistors 108u, 108v, 108w, 109u, 109v or 109w, the gate driver 106 may be used to provide (supply) a gate current to the gate of transistors 108u, 108v, 108w, 109u, 109v or 109w to charge the gate. Conversely, during the turn-off process, the gate driver 106 may be used to draw (sink) a gate current from the gate of the transistor 108u, 108v, 108w, 109u, 109v, or 109w to discharge the gate.

[0060] In addition, the transistors 108u, 108v, 108w, 109u, 109v and 109w of power inverter 102 are controlled so that both the high-side transistor and the low-side transistor in the same inverter branch will not be turned on at any time, otherwise the DC power supply will be short-circuited. This requirement can be reached according to the complementary operation of the transistors 108u, 108v, 108w, 109u, 109v and 109w in the inverter branch according to the motor control algorithm. For example, during operation, the motor M can be driven to realize the desired motor speed corresponding to the electrical frequency of the control signal according to the motor control algorithm. Dead time can be applied by controller 104, during which the high-side transistor and the low-side transistor of the same inverter branch are turned off simultaneously.

[0061] As mentioned above, Figure 1 Provided as an example only. Other examples may be found in Figure 1 The examples described are different. For example, in some implementations, the motor phases may be different, or the two half-bridges may be connected as an H-bridge circuit. In some implementations, additional circuit components may be added without departing from the disclosure provided above.

[0062] Figure 2 1 is a schematic block diagram of a gate driver system 200 according to one or more implementations. For example, when the gate driver system 200 is used to drive a motor M, the gate driver system 200 may correspond to Figure 1The motor control system 100 of the present invention. The gate driver system 200 may include a controller 104, a gate driver 106, and a transistor 202 (e.g., a high-side transistor 108 or a low-side transistor 109) connected in anti-parallel to a corresponding freewheeling diode 204. Although the transistor 202 is depicted as a low-side transistor in this example, a similar configuration may be used to drive a high-side transistor. Additionally, although the transistor 202 is an IGBT, in some implementations, the transistor may alternatively be a MOSFET. For example, one type of voltage-controlled transistor may replace another type of voltage-controlled transistor. For example, in any of the examples described herein, when a MOSFET replaces an IGBT, the drain of the MOSFET may replace the collector of the IGBT, the source of the MOSFET may replace the emitter of the IGBT, and the drain-source voltage Vds of the MOSFET may replace the collector-emitter voltage Vce of the IGBT. Therefore, any IGBT may be replaced by a MOSFET, and vice versa. An IGBT is a transistor that combines an input MOSFET and an output bipolar transistor. Therefore, an IGBT is a MOS gate device because an IGBT is the gate of a MOSFET that controls the device state. Specifically, the gate-emitter voltage of an IGBT or similar device is the control voltage. Therefore, depending on the transistor technology, when referring to the control voltage of a voltage-controlled transistor, both the gate-source voltage Vgs and the gate-emitter voltage Vge may be used interchangeably herein. The gate driver 106 may be coupled between the control terminal and the load terminal of the transistor 202 so that the control voltage can be applied.

[0063] The controller 104 may be configured to generate a PWM control signal for driving the transistor 202. The controller 104 may be configured with a plurality of PWM schemes or a simple modulation scheme that may be used to generate the PWM control signal. For example, the controller 104 may select between a state vector PWM scheme (e.g., a high loss modulation scheme) and a discontinuous PWM scheme (e.g., a low loss modulation scheme) to control the switching state of the transistor 202. Thus, the modulation scheme may be used as a power dissipation parameter that may be varied between at least a high loss setting and a low loss setting.

[0064] Additionally or alternatively, the controller 104 may be configured to control the switching frequency f of the PWM control signal sw For example, the controller 104 may be configured to operate at three switching frequencies f corresponding to the switching periods Tsw1, Tsw2, and Tsw3, respectively. sw1 、f sw2 and f sw3 Adjust the switching frequency f of the PWM control signal between sw . Switching frequency f swThe higher the switching frequency f, the greater the power loss (power dissipation) at transistor 202. sw A power dissipation parameter may be used that may be varied between at least a high loss setting and a low loss setting.

[0065] exist Figure 2 In the implementation shown, transistor 202 includes a gate G, a collector C, and an emitter E. The gate G of transistor 202 is a capacitive load that can be charged and discharged to modulate the gate voltage V G , thereby modulating the gate-emitter voltage Vge. A voltage pulse may be output from the gate driver 106 as a gate control signal according to the PWM control signal. Therefore, during a PWM cycle for controlling the transistor 202, the gate control signal may switch between an on voltage level (e.g., a high voltage) and an off voltage level (e.g., a low voltage). This in turn charges and discharges the gate capacitance to modulate the gate voltage V accordingly. G , thereby turning on and off transistor 202 respectively.

[0066] Alternatively, the gate driver 106 may use source current and sink current as gate control signals to turn on and off the transistor 202. For example, during the turn-on process, the gate driver 106 may provide (supply) an on current to the gate G of the transistor 202 so as to charge the gate to a voltage sufficient to turn on the transistor 202. Conversely, during the turn-off process, the gate driver 106 is used to draw (sink) an off current from the gate G of the transistor 202 so as to increase the gate voltage V G The gate current is discharged to a voltage sufficient to turn off the transistor 202. During the turn-off event, after a small period of time (e.g., small compared to the PWM period), the gate current decreases and reaches a zero value when the gate reaches an approximately zero or negative value. During the turn-on event, after a small period of time (e.g., small compared to the PWM period), minus any voltage drop, the gate current decreases and reaches a zero value when the gate reaches a positive supply level.

[0067] The gate driver 106 may include a control logic 206, a source FET 208, and a sink FET 210 connected to the source FET 208 in a half-bridge configuration. The control logic 206 may receive a PWM control signal from the controller 104, and control the on / off state of the source FET 208 and the sink FET 210 based on the PWM control signal. For example, the control logic 206 may implement a PWM scheme for controlling the source FET 208 and the sink FET 210 based on the PWM control signal. The source FET 208 and the sink FET 210 operate in a complementary manner such that both the source FET 208 and the sink FET 210 are not turned on at the same time to avoid cross conduction.

[0068] The gate driver 106 is powered by a first supply potential VCC (e.g., a positive supply voltage) and a second supply potential VEE, which may also be connected to a ground GND of the gate driver 106. When the source FET 208 is turned on, the output pad OUT of the gate driver 106 is electrically coupled to the first supply potential VCC, and the gate driver 106 outputs a voltage Vout at the output pad OUT, which is approximately the first supply potential VCC minus any voltage drop (e.g., driver voltage drop) across the source FET 208. When the absorption FET 210 is turned on, the output pad OUT of the gate driver 106 is electrically coupled to the negative pole of the second supply potential VEE, and the output voltage Vout at the output pad OUT is approximately the negative pole of the second supply potential VEE. The second supply potential VEE may be equal to the ground potential or may be a positive voltage potential. In some implementations, the first supply potential VCC may be adjustable and may be adjusted to control the gate voltage V G For example, the first supply potential VCC may be increased during the on-time to increase the gate voltage V G and control voltage Vge, or can be reduced during the on-time to reduce the gate voltage V G and control voltage Vge. Reducing control voltage Vge during the on-time of the transistor results in higher power loss (e.g., higher power dissipation) at transistor 202. Thus, the voltage level of first supply potential VCC may be used as a power dissipation parameter that may be varied between at least a high loss setting and a low loss setting.

[0069] Therefore, the source FET 208 and the sink FET 210 operate as current sources when turned on. In particular, when turned on, the source FET 208 generates an on-current due to its connection to the first supply potential VCC. The on-current is output from the output pad OUT of the gate driver 106 and used as a gate charging current. Therefore, the source FET 208 provides an on-current to the gate G of the transistor 202 to increase the gate voltage V G , which also causes the control voltage Vge to increase to a level above the conduction threshold (e.g., threshold voltage Vth). On the other hand, when the absorption FET 210 is turned on, the absorption FET 210 generates an off current due to its connection to the second supply potential VEE. The off current is introduced into the output pad OUT of the gate driver 106 and used as a gate discharge current. In other words, the off current is absorbed from the gate G of the transistor 202. Therefore, the gate voltage V G This causes the control voltage Vge to decrease to a level below the conduction threshold (eg, threshold voltage Vth).

[0070] The output pad OUT of the gate driver 106 is coupled to the gate G of the transistor 202 through the gate resistor Rg, which reduces the current between the output pad OUT and the gate G. The resistance value of the gate resistor Rg can be adjusted to control the power dissipation of the transistor 202. For example, a higher resistance value slows down the turn-on and turn-off of the transistor, which results in higher switching power losses. Therefore, the resistance value of the gate resistor Rg can be used as a power dissipation parameter that can be varied between at least a high loss setting and a low loss setting.

[0071] The gate driver system 200 may also include an ATC circuit 212, a current sensor 214, and a temperature sensor 216. The current sensor 214 may be configured to sense the load current Io and generate a current sensor signal Isense representing the load current Io conducted by the transistor 202. The current sensor 214 may include a voltage divider (e.g., a resistor network), a magnetic sensor, and any other sensor circuit capable of sensing current and generating a current sensor signal Isense. The temperature sensor 216 may be configured to sense an ambient temperature and generate a temperature sensor signal T representing the ambient temperature. A .

[0072] The ATC circuit 212 can be configured to perform a conditional ATC function based on one or more inputs. For example, the ATC circuit 212 can be configured to receive a current sensor signal Isense as an input and control the conditional ATC function based on the current sensor signal Isense. In addition, in some implementations, the ATC circuit 212 can be configured to receive a temperature sensor signal T A As another input, and based on the temperature sensor signal TA, the conditional ATC function is controlled. The ATC circuit 212 can be configured to enable active thermal control of the transistor 202 if certain enabling conditions are met. The ATC circuit 212 can be configured to adjust one or more of the dissipation parameters when the active thermal control of the transistor 202 is enabled to adjust the power dissipation of the transistor 202. Conversely, when the active thermal control of the transistor 202 is disabled, the active thermal control circuit 212 is configured not to adjust any power dissipation parameters, thereby leaving the sole control of the power dissipation of the transistor 202 to the controller 104.

[0073] In some implementations, the ATC circuit 212 may be configured to monitor a load current change ΔIo of the load current Io conducted by the transistor in the conduction state, and enable or disable the ATC of the transistor 202 based on the load current change ΔIo. The ATC circuit 212 may be configured to monitor the load current change ΔIo of the load current Io by monitoring the current sensor signal Isense. Therefore, the ATC circuit 212 may be configured to monitor the load current Io directly or indirectly through the current sensor signal Isense, and detect the magnitude of the load current Io.

[0074] The ATC circuit 212 may be configured to evaluate a load current change ΔIo that reaches a duration threshold as a qualified load current change. For example, to avoid unnecessary increases in the power dissipation of the transistor 202, the ATC circuit 212 may evaluate a load current change only when the power dissipation change ΔP D The ATC of transistor 202 is enabled or disabled when the duration of the load current change ΔIo is longer than a certain time constant τ (e.g., longer than a duration threshold). Therefore, those load current changes ΔIo that are longer than the duration threshold can be further evaluated as qualified load current changes, while those load current changes ΔIo that are not longer than the duration threshold can be filtered out without further evaluation. For example, if a load current decrease that is determined to be long and large is detected by the ATC circuit 212, the ATC circuit 212 can enable the ATC of transistor 202. On the other hand, if a load current increase that is determined to be long and large is detected, the ATC circuit 212 can disable the ATC of transistor 202.

[0075] In some implementations, the ATC circuit 212 can measure an average value of the load current Io (e.g., an average value of the current sensor signal Isense) as a way to filter out load current variations ΔIo that are not longer than a duration threshold, and allow for further evaluation of load current variations ΔIo that are longer than the duration threshold to determine whether the ATC of the transistor 202 should be enabled or disabled. Thus, if a decrease in the average load current that is identified as large is detected by the ATC circuit 212, the ATC circuit 212 can enable the ATC of the transistor 202. On the other hand, if an increase in the average load current that is identified as large is detected, the ATC circuit 212 can disable the ATC of the transistor 202.

[0076] The ATC circuit 212 may be configured to detect the direction of the qualified load current change. For example, the direction of the qualified load current change may be an increasing direction or a decreasing direction. The ATC circuit 212 may be configured to detect the amplitude of the qualified load current change ΔIo, and compare the amplitude with the first threshold Vth1. The ATC circuit 212 may be configured to enable the ATC of the transistor 202 if the qualified load current change ΔIo has a decreasing direction and the amplitude of the qualified load current change ΔIo reaches the first threshold Vth1. In some implementations, the first threshold Vth1 may be a negative threshold, and when the amplitude of the qualified load current change ΔIo is more negative than (e.g., less than) the first threshold Vth1, the amplitude of the qualified load current change ΔIo reaches the first threshold Vth1. The ATC circuit 212 may be configured to adjust the power dissipation parameter to adjust the power dissipation of the transistor when the ATC is enabled. The ATC circuit 212 may be configured to adjust the power dissipation parameter by setting the power dissipation parameter in a high loss mode or a low loss mode.

[0077] In contrast, when the ATC is disabled, the ATC circuit 212 can be configured not to adjust the power dissipation parameter. In some implementations, the ATC circuit 212 can be configured to compare the magnitude of the qualified load current change ΔIo with the second threshold Vth2. For example, the ATC circuit 212 can be configured to disable the ATC of the transistor 202 if the qualified load current change ΔIo has an increasing direction and the magnitude of the qualified load current change ΔIo reaches the second threshold. In some implementations, the second threshold Vth2 can be a positive threshold, and when the magnitude of the qualified load current change ΔIo is more positive than (e.g., greater than) the second threshold Vth2, the magnitude of the qualified load current change ΔIo reaches the second threshold Vth2. In some implementations, both the first threshold and the second threshold are fixed thresholds.

[0078] In some implementations, the magnitude of the qualified load current change ΔIo is based on a difference between average values ​​of the load current Io, the average values ​​comprising a first average value of the load current Io determined at a most recent sampling time and a second average value of the load current determined at a previous sampling time. In other words, the average value of the load current Io (or the average value of the current sensor signal Isense) may be sampled at a sampling interval, and the difference between the samples may be calculated to determine the magnitude of the qualified load current change ΔIo.

[0079] In some implementations, the ATC circuit 212 may be configured to compare the magnitude of the load current Io with a second threshold value Vth2, rather than comparing the magnitude of the qualified load current change ΔIo with the second threshold value Vth2. In this case, the ATC circuit 212 may be configured to disable the ATC of the transistor 202 if the qualified load current change ΔIo has an increasing direction and the magnitude of the load current Io reaches the second threshold value Vth2 (e.g., the load current Io is greater than the second threshold value Vth2). In this case, the magnitude of the qualified load current change ΔIo may be based on the difference between the average values ​​of the load current Io, the average value including a first average value of the load current determined at the most recent sampling time and a second average value of the load current determined at the previous sampling time. Additionally, the first average value of the load current Io may be used as the magnitude of the load current Io for comparison with the second threshold value Vth2. Additionally, the first threshold may be a fixed threshold, and the second threshold may be a dynamic threshold. For example, the ATC circuit 212 may be configured to dynamically set the second threshold value Vth2 equal to the average value of the load current Io sampled at the trigger time at which the enabling of the ATC is triggered by the ATC circuit 212. For example, the second threshold value Vth2 may be set to the value of the load current Io detected when the ATC is enabled by the ATC circuit 212. Thus, the second threshold value Vth2 may be set each time the ATC is enabled to serve as a threshold used by the ATC circuit 212 to determine when to disable the ATC.

[0080] In some implementations, the ATC circuit 212 may be configured to determine an average load current Io,avg of the load current Io, and evaluate a load current change ΔIo,avg of the average load current Io,avg to determine when to enable or disable the ATC of the transistor 202. For example, the ATC circuit 212 may be configured to detect a direction of the load current change ΔIo,avg of the average load current Io,avg, detect a magnitude of the load current change ΔIo,avg of the average load current Io,avg, and compare the magnitude of the load current change ΔIo,avg with a first threshold value Vth1. The ATC circuit 212 may be configured to enable the ATC of the transistor 202 if the load current change ΔIo,avg has a decreasing direction and the magnitude of the load current change ΔIo,avg reaches a first threshold value. The ATC circuit 212 may be configured to adjust a power dissipation parameter to adjust the power dissipation of the transistor 202 when the ATC is enabled. In addition, when the ATC is disabled, the ATC circuit 212 may be configured not to adjust the power dissipation parameter. The ATC circuit 212 may be configured to compare the magnitude of the load current variation ΔIo,avg with a second threshold value Vth2 (e.g., a fixed threshold value), and if the load current variation ΔIo,avg has an increasing direction and the magnitude of the load current variation ΔIo,avg reaches the second threshold value Vth2, then disable the ATC of the transistor 202. Alternatively, the ATC circuit 212 may be configured to compare the magnitude of the average load current Io,avg with a second threshold value Vth2 (e.g., a dynamic threshold value), and if the qualified load current variation ΔIo,avg has an increasing direction and the magnitude of the average load current Io,avg reaches the second threshold value Vth2, then disable the ATC of the transistor 202. When used as a dynamic threshold value, the second threshold value Vth2 may be set to the value of the load current Io detected when the ATC is enabled by the ATC circuit 212.

[0081] As mentioned above, Figure 2 Other examples can be found in the Figure 2 The examples described are different. Figure 2 The number and arrangement of the devices and components shown are for example only. Figure 2 There may be additional devices or components, fewer devices or components, different devices or components, or differently arranged devices or components than those shown.

[0082] Figure 3A A schematic block diagram of an ATC circuit 300A according to one or more implementations is shown. The ATC circuit 300A may correspond to a combination of Figure 2ATC circuit 212 is depicted. ATC circuit 300A may be an analog circuit that may include current sensor 214, low pass filter 302 with time constant τ, high pass filter 304, comparator network 306, and enable / disable circuit 308, such as a set-reset flip-flop.

[0083] The low-pass filter 302 is configured to filter out fast transients of the load current and only allow qualified load current changes ΔIo to pass through for further evaluation. That is, load current changes ΔIo that are longer than a duration threshold corresponding to the time constant τ of the low-pass filter 302 can be further evaluated as qualified load current changes, while those load current changes ΔIo that are not longer than the duration threshold can be filtered out without further evaluation. Therefore, the low-pass filter 302 can be configured to receive the current sensor signal Isense, filter out the load current change components that do not reach the duration threshold in the current sensor signal Isense, and output the load current change components that reach the duration threshold in the current sensor signal Isense as qualified load current changes. The low-pass filtering of the transient load current Io or the transient current sensor signal Isense performed by the low-pass filter 302 can cause the low-pass filter 302 to generate an average value of the load current (e.g., an average load current Io,avg).

[0084] The high pass filter 304 can be coupled to the output of the low pass filter 302 and can be configured to output the polarity and magnitude of the qualified load current change. The polarity can indicate the direction of the qualified load current change. Therefore, the high pass filter 304 can be used to detect the direction of change of the load current Io or the direction of change of the average load current Io,avg. The current change edge can determine the polarity of the output of the high pass filter 304 and can indicate whether the current change is increasing or decreasing.

[0085] The comparator network 306 can be coupled to the output of the high pass filter 304 and can be configured to enable the ATC of the transistor 202 if the qualified load current change has a decreasing direction and the magnitude of the qualified load current change reaches a first threshold value Vth1, and disable the ATC of the transistor 202 if the qualified load current change has an increasing direction and the magnitude of the qualified load current change reaches a second threshold value Vth2. For example, the comparator network 306 can include a first comparator 310 that monitors a qualified load current change with a decreasing direction; and a second comparator 311 that monitors a qualified load current change with an increasing direction. If the first comparator 310 detects that the qualified load current change is large enough (e.g., less than or more negative than the first threshold value Vth1), the first comparator 310 can place the enable / disable circuit 308 in a set state (e.g., an enabled state), which enables the ATC of the transistor 202. Alternatively, if the second comparator 311 detects that the qualified load current changes sufficiently (eg, greater than the second threshold Vth2 ), the second comparator 311 may place the enable / disable circuit 308 in a reset state (eg, a disabled state), which disables the ATC of the transistor 202 .

[0086] Therefore, the output of the high pass filter 304 is compared with the first threshold value Vth1 and the second threshold value Vth2 for both positive and negative polarities, respectively. If the current change edge is positive and the current change amplitude of the average load current Io,avg is greater than the second threshold value Vth2, the average current change ΔIo,avg is detected as an increase, and the ATC will be turned off. If the current change edge is negative and the current change amplitude of the average load current Io,avg is less than the first threshold value Vth1, the average current change ΔIo,avg is detected as a decrease, and the ATC will be turned on.

[0087] As mentioned above, Figure 3A Provided as an example only. Other examples may be found in Figure 3A The examples described are different.

[0088] Figure 3B A schematic block diagram of an ATC circuit 300B according to one or more implementations is shown. The ATC circuit 300B may correspond to a combination of Figure 2The ATC circuit 212 described above. The ATC circuit 300B may include a current sensor 214 and a digital circuit, which may include an analog-to-digital converter (ADC) 312 and an evaluation circuit 313. The ADC 312 may be configured to convert the current sensor signal Isense into a digital signal. The evaluation circuit 313 may be configured to receive the digital signal, determine the average current value of the digital signal, and determine the difference between the most recent average current value and the previous average current value obtained before the most recent average current value. The difference may be the magnitude of the qualified load current change, and the polarity of the difference may indicate the direction of the qualified load current change.

[0089] In some implementations, the evaluation circuit 313 may include a moving average filter 314 and a threshold comparison circuit 316. The moving average filter 314 may be configured to determine the average load current Io,avg by receiving a digital signal, sampling the digital signal at a corresponding sampling time, and generating an average current value according to N consecutive samples (e.g., n-1 consecutive samples) of the digital signal. The N consecutive samples may include the most recent sample Io(t) of the digital signal, where N is an integer greater than one. The threshold comparison circuit 316 may be configured to sample the average load current Io,avg at the corresponding sampling time, and determine the difference between the most recent average current value Io(t) and the previous average current value Io(t-k+1) obtained before the most recent average current value, where k represents the kth sample before the most recent average current value Io(t). The threshold comparison circuit 316 may be configured to compare the difference with a first threshold value -Ith and a second threshold value Ith. Both the first threshold value -Ith and the second threshold value Ith may be fixed thresholds. If the difference is less than the first threshold value -Ith, the average current change ΔIo,avg is detected as decreasing by a sufficient magnitude to enable ATC, and the threshold comparison circuit 316 can enable ATC. On the other hand, if the difference is greater than the second threshold value Ith, the average current change ΔIo,avg is detected as increasing by a sufficient magnitude to disable ATC, and the threshold comparison circuit 316 can disable ATC.

[0090] As mentioned above, Figure 3B Provided as an example only. Other examples may be found in Figure 3B The examples described are different.

[0091] Figure 3C A schematic block diagram of an ATC circuit 300C according to one or more implementations is shown. The ATC circuit 300C may correspond to a combination of Figure 2The ATC circuit 212 described. The ATC circuit 300C may include a current sensor 214 and a digital circuit, which may include an ADC 312 and an evaluation circuit 313. The ADC 312 may be configured to convert the current sensor signal Isense into a digital signal. The evaluation circuit 313 may be configured to receive the digital signal, determine the average current value of the digital signal, and determine the difference between the most recent average current value and the previous average current value obtained before the most recent average current value. The difference may be the amplitude of the qualified load current change, and the polarity of the difference may indicate the direction of the qualified load current change. In some implementations, the evaluation circuit 313 may include a moving average filter 314 and a threshold comparison circuit 318.

[0092] The threshold comparison circuit 318 can be configured to sample the average load current Io,avg at the corresponding sampling time and determine the difference between the most recent average current value Io(t) and the previous average current value Io(t-k+1) acquired before the most recent average current value, where k represents the kth sample before the most recent average current value Io(t). The threshold comparison circuit 318 can be configured to be combined with the above Figure 3B The difference is compared to the first threshold -Ith in a similar manner as described. Thus, if the difference is less than the first threshold -Ith, the average current change ΔIo,avg is detected as decreasing by a sufficient magnitude to enable ATC, and the threshold comparison circuit 318 can enable ATC. The first threshold -Ith can be a fixed threshold.

[0093] Additionally, the second threshold may be a dynamic threshold Io,index adjusted by the threshold comparison circuit 318. For example, the threshold comparison circuit 318 may be configured to dynamically set the second threshold Io,index equal to the average value of the load current Io sampled at the trigger time at which the enabling of the ATC is triggered by the threshold comparison circuit 318. For example, the second threshold Io,index may be set to the value of the load current Io (or the average load current Io,avg) detected when the ATC is enabled by the threshold comparison circuit 318. Thus, the second threshold Io,index may be set each time the ATC is enabled to serve as a threshold used by the threshold comparison circuit 318 to determine when to disable the ATC.

[0094] The threshold comparison circuit 318 can be configured to monitor the load current Io (or the average load current Io,avg) and detect the magnitude of the load current Io (or the average load current Io,avg) to compare with the second threshold Io,index. For example, the threshold comparison circuit 318 can be configured to compare the magnitude of the load current Io (or the average load current Io,avg) with the second threshold Io,index, and if the qualified load current change has an increasing direction and the magnitude of the load current Io (or the magnitude of the average load current Io,avg) reaches the second threshold Io,index (for example, if the magnitude of the average load current Io,avg is greater than the second threshold Io,index), then disable the ATC of the transistor 202.

[0095] As mentioned above, Figure 3C Provided as an example only. Other examples may be found in Figure 3C The examples described are different.

[0096] Figure 4A Conditional ATC functionality according to one or more implementations is shown. Figure 4A A first view 400A showing a set of enabling conditions for enabling ATC and a second view 401A showing a set of disabling conditions for disabling ATC are shown. Figure 4A The conditional ATC function shown can be combined with Figure 3A and Figure 3B For example, the thresholds in both the first view 400A and the second view 401A can be fixed, and the magnitude of the qualified load current change (e.g., the magnitude of the average current change ΔIo,avg) can be compared with the two thresholds to turn on or off the ATC.

[0097] As mentioned above, Figure 4A Provided as an example only. Other examples may be found in Figure 4A The examples described are different.

[0098] Figure 4B Conditional ATC functionality according to one or more implementations is shown. Figure 4B A first view 400B showing a set of enabling conditions for enabling ATC and a second view 401B showing a set of disabling conditions for disabling ATC are shown. Figure 4B The conditional ATC function shown can be combined with Figure 3C The ATC circuit 300C described above is implemented.

[0099] For example, the threshold in the first view 400B can be fixed, and the threshold (e.g., Io,index) in the second view 401B can be adjustable. The magnitude of the qualified load current change (e.g., the magnitude of the average current change ΔIo,avg) can be compared with the threshold in the first view 400B to determine whether the ATC should be turned on. The magnitude of the average current Io,avg can be compared with the threshold in the second view 401B to determine whether the ATC should be turned off.

[0100] As mentioned above, Figure 4B Provided as an example only. Other examples may be found in Figure 4B The examples described are different.

[0101] Figure 5A The following figure shows different control modes for ATC and the corresponding power dissipation parameters (including gate resistance Rg, switching frequency f sw , gate voltage V G and modulation scheme M PWM ) of Table 500A. The different control modes include a two-step control mode, a multi-step control mode, and a continuous control mode. "Y" indicates that the control mode can be used to adjust the corresponding power dissipation parameter, and "N" indicates that the control mode cannot be used to adjust the corresponding power dissipation parameter. During the two-step control mode, the power dissipation parameter can be switched between a low loss mode (e.g., a low loss setting) and a high loss mode (e.g., a high loss setting) to adjust the power dissipation of the transistor 202. The ATC circuit 212 can be configured to adjust the power dissipation parameter by setting the power dissipation parameter in the high loss mode or in the low loss mode. During the multi-step control mode, the power dissipation parameter can be switched between two or more discrete modes or settings (including a low loss mode and a high loss mode) to adjust the power dissipation of the transistor 202. In some implementations, during the multi-step control mode, the power dissipation parameter can be switched between three or more discrete modes or settings (including a low loss mode, at least one intermediate loss mode, and a high loss mode) to adjust the power dissipation of the transistor 202. During the continuous control mode, the power dissipation parameter may be adjusted along the characteristic curve in order to regulate the power dissipation of transistor 202 .

[0102] As mentioned above, Figure 5A Provided as an example only. Other examples may be found in Figure 5A The examples described are different.

[0103] Figure 5B The power dissipation parameters (including gate resistance Rg, switching frequency f) that can be used during the two-step control mode for ATC are shown. sw , gate voltage V G and modulation scheme MPWM ). During the two-step control mode, the power dissipation parameter can be switched between a low loss mode (e.g., a low loss setting) and a high loss mode (e.g., a high loss setting) to adjust the power dissipation of transistor 202. For example, ATC circuit 212 can be configured to adjust the power dissipation of transistor 202 according to the duty cycle D of the power dissipation parameter. ATC The power dissipation parameter is switched between a low loss mode and a high loss mode to adjust the power dissipation of the transistor 202. The duty cycle D of the power dissipation parameter ATC can be defined as the amount of time T that the power dissipation parameter is set in the high loss mode Hi The total amount of time (e.g., T Hi +T Lo ), the total amount of time including the amount of time T that the power dissipation parameter is set in the high loss mode Hi The amount of time T that the power dissipation parameter sets in low-loss mode Lo In other words, the duty cycle D of the power dissipation parameter is ATC Can be equal to T Hi / (T Hi +T Lo In order to adjust the power dissipation of transistor 202, ATC circuit 212 can be used at different duty cycles D ATC For example, to increase the power dissipation of transistor 202, ATC circuit 212 may increase the duty cycle D of the power dissipation parameter. ATC , and in order to reduce the power dissipation of transistor 202, ATC circuit 212 can reduce the duty cycle D of the power dissipation parameter ATC For example, by increasing the duty cycle D as the load current Io decreases ATC , a constant power dissipation can be achieved. In some implementations, when ATC is disabled, the duty cycle D of the power dissipation parameter ATC is set to zero to always operate in low-loss mode.

[0104] As mentioned above, Figure 5B Provided as an example only. Other examples may be found in Figure 5B The examples described are different.

[0105] Fig. 6A 6A is a parameter selection circuit for a two-step control mode of an ATC circuit according to one or more implementations. For the two-step control mode, the ATC circuit 212 may be configured to switch power dissipation parameters (e.g., gate resistance Rg, switching frequency f ) between a low-loss mode and a high-loss mode over a PWM switch controlled by the controller 104. sw , gate voltage V G Or modulation scheme MPWM ). The duty cycle D of the power dissipation parameter can be modulated ATC To control the average power loss.

[0106] The power dissipation P of transistor 202 can be measured over the entire range of load current Io. D , where the duty cycle D ATC As a parameter ranging from 0 (e.g., corresponding to always operating in low-loss mode) to 1 (e.g., corresponding to always operating in high-loss mode). ATC Different values ​​of P D -Io curve. According to P D -Io curve, a set of D ATC and Io characteristic curve, where the power dissipation P D As the range from P D,Min To P D,Max Alternatively, the group D ATC The Io characteristic curve may be stored in a lookup table 602 stored in a memory associated with the ATC circuit 212, and the group D ATC The characteristic curve with Io can be indexed by the load current index value Io,index as a characteristic curve selection parameter. The ATC circuit 212 can be configured to select from a plurality of D ATC Select D from the Io characteristic curve ATC The ATC circuit 212 can then use the selected D ATC The Io characteristic curve is used for ATC of transistor 202. For example, ATC circuit 212 can be configured to receive average load current Io,avg as an input to lookup table 602 and, when ATC is enabled, select D based on average load current Io,avg. ATC The duty cycle D of the power dissipation parameter is adjusted by the Io characteristic curve ATC Therefore, when the average load current Io,avg is selected according to D ATC The duty cycle D can be adjusted by changing the Io characteristic curve ATC .

[0107] The load current index value Io,index may be determined in a manner similar to the dynamic threshold used above to set the second threshold Vth2. For example, the load current index value Io,index may be the value of the most recent sample of the average load current that caused the activation of the ATC triggered by the ATC circuit 212.

[0108] In some implementations, the ATC circuit 212 can be configured to receive the ambient temperature T AAs an additional input, for use according to the selected D ATC Adjust the duty cycle D with Io characteristic curve ATC Therefore, the ATC circuit 212 can be configured to receive the ambient temperature T A and the average load current Io,avg as inputs to the lookup table 602, and when ATC is enabled, the load current Io,avg is calculated based on the ambient temperature T A and the average load current Io,avg of the selected D ATC The duty cycle D of the power dissipation parameter is adjusted by the Io characteristic curve ATC Therefore, D ATC The Io characteristic curve can be implemented in the lookup table 602, where the load current Io (or the average load current Io,avg) and the ambient temperature T A As a parameter to select the input, the duty cycle D ATC as output, and Io,index as the characteristic curve selection parameter.

[0109] When ATC is turned on (enabled), the duty cycle D ATC Can be composed of Io and T A To determine the duty cycle D ATC can increase as Io decreases, making the power dissipation P D and the junction temperature Tj will be at the selected D ATC The current value of Io when ATC is enabled can be used to select the applicable D ATC When the ATC is turned off (disabled), the ATC circuit 212 can set the duty cycle D ATC = is set to zero so that the power dissipation parameter operates in a low-loss mode. Lookup table 602 may be configured to compensate for the ambient temperature T by adjusting the power dissipation of transistor 202. A The change of ambient temperature T A The lookup table 602 may be enabled or disabled by an ATC on control signal and an ATC off control signal provided by the ATC circuit 300A, 300B, or 300C.

[0110] Lookup table 602 can be configured to provide PWM ATC Generator 604 provides a duty cycle D ATC , PWM ATC Generator 604 may be configured to generate a duty cycle D according to the duty cycle D received from lookup table 602. ATC To adjust the power dissipation parameters. For example, PWM ATC Generator 604 may be configured to output a control signal that controls the mode of the power dissipation parameter. In other words, the PWMATC The control signal of the generator 604 may be a PWM signal, which is based on the duty cycle D ATC Switches a power dissipation parameter between its low loss mode and its high loss mode.

[0111] As mentioned above, Fig. 6A Provided as an example only. Other examples may be found in Fig. 6A The examples described are different.

[0112] Figure 6B 6B is a parameter selection circuit for a multi-step control mode of an ATC circuit according to one or more implementations. For the multi-step control mode, the ATC circuit 212 can be configured to adjust a power dissipation parameter (e.g., gate resistance Rg, switching frequency f ) between two or more power dissipation parameter values. sw Or gate voltage V G ). The parameter selection circuit 600B may include a step selector circuit 606, which may be configured with a plurality of ranges of power dissipation parameter values. The step selector circuit 606 may be configured to adjust the power dissipation parameter by setting the power dissipation parameter to a power dissipation parameter value in the plurality of ranges of power dissipation parameter values. For example, the step selector circuit 606 may receive an ambient temperature T A and the average load current Io,avg as inputs for selecting a power dissipation parameter value from a plurality of power dissipation parameter values. The step selector circuit 606 may be configured to select a power dissipation parameter value based on the ambient temperature T when ATC is enabled. A The step selector circuit 606 can be configured to compensate for the ambient temperature T by adjusting the power dissipation of the transistor 202. A The change of ambient temperature T A The step selector circuit 606 may be enabled or disabled by an ATC on control signal and an ATC off control signal provided by the ATC circuit 300A, 300B, or 300C.

[0113] As mentioned above, Figure 6B Provided as an example only. Other examples may be found in Figure 6B The examples described are different.

[0114] Figure 6C and Fig.6D 6 and 600D are shown for parameter selection circuits 600C and 600D for a continuous control mode of an ATC circuit according to one or more implementations. D Or Io,index as a parameter to derive a set of power dissipation parameters and Io characteristic curves.D With Rg and f SW increases with the increase of P D With V G The decrease of Rg and Io and f SW The characteristic curve with Io will have a negative slope, such as Figure 6C As shown, V G The characteristic curve with Io will have a positive slope, such as Fig.6D The parameter selection circuits 600C and 600D may be implemented as a lookup table, where the load current Io (or the average load current Io,avg) and the ambient temperature T A As parameter selection input, power dissipation parameters Rg, f SW or V G As output, and Io,index as a characteristic curve selection parameter. Therefore, the load current index value Io,index can be used to select a characteristic curve from the set of power dissipation parameters and Io characteristic curves, such as a similar combination Fig. 6A described.

[0115] The parameter selection circuits 600C and 600D may each be configured to adjust the power dissipation parameter by setting the power dissipation parameter to a power dissipation parameter value in a range of multiple power dissipation parameter values. The selected power dissipation parameter versus Io characteristic curve may define a range of multiple power dissipation parameter values ​​and a slope of multiple power dissipation parameter values. The parameter selection circuits 600C and 600D may each be configured to receive an ambient temperature T A and average load current Io,avg as input for the selected power dissipation parameter vs. Io characteristic curve, and when ATC is enabled, the load current is set to the value based on the ambient temperature T A The power dissipation parameter value is selected based on the selected power dissipation parameter and Io characteristic curve of the average load current Io,avg to adjust the junction temperature Tj of the transistor 202. The parameter selection circuits 600C and 600D can be configured to offset the ambient temperature Tj by adjusting the power dissipation of the transistor 202. A The change of ambient temperature T A The parameter selection circuits 600C and 600D may be enabled or disabled by an ATC on control signal and an ATC off control signal provided by the ATC circuit 300A, 300B, or 300C.

[0116] As mentioned above, Figure 6C and Fig.6D Provided as an example only. Other examples may be found in Figure 6C and Fig.6D The examples described are different.

[0117] The following provides an overview of some aspects of the disclosure:

[0118] Aspect 1: A gate driver system, comprising: a gate driver configured to be coupled to a control terminal of a transistor and configured to control a control voltage applied to the control terminal so as to drive the transistor between switch states; and an active thermal control circuit configured to monitor a load current change of a load current conducted by the transistor in a conduction state, and enable or disable active thermal control of the transistor based on the load current change, wherein the active thermal control circuit is configured to evaluate a load current change that reaches a duration threshold as a qualified load current change, wherein the active thermal control circuit is configured to detect a direction of a qualified load current change among the qualified load current changes, wherein the qualified load current change The direction of the current change is an increasing direction or a decreasing direction, wherein the active thermal control circuit is configured to detect the amplitude of the qualified load current change among the qualified load current changes and compare the amplitude with a first threshold, wherein the active thermal control circuit is configured to: if the qualified load current change has the decreasing direction and the amplitude of the qualified load current change reaches the first threshold, enable active thermal control of the transistor, wherein the active thermal control circuit is configured to adjust a power dissipation parameter to adjust the power dissipation of the transistor when the active thermal control is enabled, and wherein the active thermal control circuit is configured not to adjust the power dissipation parameter when the active thermal control is disabled.

[0119] Aspect 2: A gate driver system according to Aspect 1, wherein the active thermal control circuit is configured to compare the magnitude of the qualified load current change with a second threshold, and wherein the active thermal control circuit is configured to: disable active thermal control of the transistor if the qualified load current change has the increasing direction and the magnitude of the qualified load current change reaches the second threshold.

[0120] Aspect 3: The gate driver system according to Aspect 2, wherein the first threshold and the second threshold are fixed thresholds.

[0121] Aspect 4: A gate driver system according to Aspect 2, wherein the magnitude of the qualified load current change is based on the difference between average values ​​of the load current, the average values ​​comprising a first average value of the load current determined at a most recent sampling time and a second average value of the load current determined at a previous sampling time.

[0122] Aspect 5: A gate driver system according to Aspect 2, wherein the first threshold is a negative threshold, and when the amplitude of the qualified load current change is less than the first threshold, the amplitude of the qualified load current change reaches the first threshold, and wherein the second threshold is a positive threshold, and when the amplitude of the qualified load current change is greater than the second threshold, the amplitude of the qualified load current change reaches the second threshold.

[0123] Aspect 6: A gate driver system according to any one of Aspects 1 to 5, wherein the active thermal control circuit is configured to monitor the load current and detect the amplitude of the load current, wherein the active thermal control circuit is configured to compare the amplitude of the load current with the second threshold, and wherein the active thermal control circuit is configured to: disable active thermal control of the transistor if the qualified load current change has the increasing direction and the amplitude of the load current reaches the second threshold.

[0124] Aspect 7: A gate driver system according to Aspect 6, wherein the first threshold is a negative threshold, and when the amplitude of the qualified load current change is less than the first threshold, the amplitude of the qualified load current change reaches the first threshold, and wherein the second threshold is a positive threshold, and when the amplitude of the load current is greater than the second threshold, the amplitude of the load current reaches the second threshold.

[0125] Aspect 8: A gate driver system according to Aspect 6, wherein the magnitude of the qualified load current change is based on the difference between average values ​​of the load current, the average values ​​including a first average value of the load current determined at a most recent sampling time and a second average value of the load current determined at a previous sampling time, and wherein the magnitude of the load current is the first average value of the load current.

[0126] Aspect 9: A gate driver system according to Aspect 7, wherein the first threshold is a fixed threshold and the second threshold is a dynamic threshold, and wherein the active thermal control circuit is configured to dynamically set the second threshold to be equal to the average value of the load current sampled at a trigger time, at which the enabling of the active thermal control is triggered by the active thermal control circuit.

[0127] Aspect 10: A gate driver system according to Aspect 2, wherein the active thermal control circuit includes: a current sensor configured to sense the load current and generate a sensor signal representing the load current; a low-pass filter configured to receive the sensor signal and filter out load current change components in the sensor signal that do not reach the duration threshold, and output load current change components in the sensor signal that reach the duration threshold as the qualified load current change; a high-pass filter coupled to the output of the low-pass filter and configured to output the polarity and amplitude of the qualified load current change, wherein the polarity indicates the direction of the qualified load current change; and a comparator network coupled to the output of the high-pass filter and configured to: enable active thermal control of the transistor if the qualified load current change has the decreasing direction and the amplitude of the qualified load current change reaches the first threshold, and disable active thermal control of the transistor if the qualified load current change has the increasing direction and the amplitude of the qualified load current change reaches the second threshold.

[0128] Aspect 11: A gate driver system according to Aspect 2, wherein the active thermal control circuit includes: a current sensor configured to sense the load current and generate a sensor signal representing the load current; an analog-to-digital converter (ADC) configured to convert the sensor signal into a digital signal; a moving average filter configured to receive the digital signal and generate an average current value based on N consecutive samples of the digital signal, wherein the N consecutive samples include a most recent sample of the digital signal, and wherein N is an integer greater than one; and an evaluation circuit configured to determine a difference between a most recent average current value and a previous average current value acquired before the most recent average current value, wherein the difference is the magnitude of the change in the qualified load current, and the polarity of the difference indicates the direction of the change in the qualified load current.

[0129] Aspect 12: The gate driver system according to Aspect 11, wherein the evaluation circuit is configured to compare the difference with the first threshold and the second threshold, and enable or disable active thermal control of the transistor based on the difference reaching the first threshold or the second threshold.

[0130] Aspect 13: The gate driver system according to any one of Aspects 1 to 12, wherein the load current variation is a load current transient of the load current caused by a change in load.

[0131] Aspect 14: A gate driver system according to any one of Aspects 1 to 13, wherein the power dissipation parameter is a gate drive resistance coupled to the control terminal, a gate drive voltage applied to the control terminal during the conduction state, a switching frequency of the transistor, or a pulse width modulation (PWM) scheme of the gate drive voltage applied to the control terminal to drive the switching state.

[0132] Aspect 15: A gate driver system comprising: a gate driver configured to be coupled to a control terminal of a transistor and configured to control a control voltage applied to the control terminal so as to drive the transistor between a switching state; and an active thermal control circuit configured to monitor a load current conducted by the transistor in a conducting state and enable or disable active thermal control of the transistor based on the load current, wherein the active thermal control circuit is configured to determine an average load current of the load current and to evaluate a load current variation of the average load current, wherein evaluating the load current variation of the average load current comprises: detecting a direction of the load current variation of the average load current, wherein the direction of the load current change is an increasing direction or a decreasing direction; the magnitude of the load current change of the average load current is detected; and the magnitude of the load current change is compared with a first threshold, wherein the active thermal control circuit is configured to: enable active thermal control of the transistor if the load current change has the decreasing direction and the magnitude of the load current change reaches the first threshold, and wherein the active thermal control circuit is configured to adjust a power dissipation parameter to adjust the power dissipation of the transistor when the active thermal control is enabled, and wherein the active thermal control circuit is configured not to adjust the power dissipation parameter when the active thermal control is disabled.

[0133] Aspect 16: The gate driver system of Aspect 15, wherein the active thermal control circuit is configured to compare the magnitude of the load current change with a second threshold, and wherein the active thermal control circuit is configured to disable active thermal control of the transistor if the load current change has the increasing direction and the magnitude of the load current change reaches the second threshold.

[0134] Aspect 17: A gate driver system according to any one of Aspects 15 to 16, wherein the active thermal control circuit is configured to compare the magnitude of the average load current with the second threshold, and wherein the active thermal control circuit is configured to disable active thermal control of the transistor if the load current change has the increasing direction and the magnitude of the average load current reaches the second threshold.

[0135] Aspect 18: The gate driver system according to any one of Aspects 15 to 17, wherein the active thermal control circuit is configured to adjust the power dissipation parameter by setting the power dissipation parameter in a high loss mode or a low loss mode.

[0136] Aspect 19: A gate driver system according to Aspect 18, wherein the active thermal control circuit is configured to adjust the power dissipation parameter according to the duty cycle of the power dissipation parameter when the active thermal control is enabled, and wherein the active thermal control circuit switches the power dissipation parameter between the high loss mode and the low loss mode according to the duty cycle to adjust the power dissipation of the transistor.

[0137] Aspect 20: A gate driver system according to Aspect 19, wherein the duty cycle of the power dissipation parameter is a ratio of the amount of time that the power dissipation parameter is set in the high-loss mode to a total amount of time, and the total amount of time includes the sum of the amount of time that the power dissipation parameter is set in the high-loss mode and the amount of time that the power dissipation parameter is set in the low-loss mode.

[0138] Aspect 21: The gate driver system of Aspect 19, wherein the active thermal control circuit is configured to receive the ambient temperature and the average load current as inputs, and wherein the active thermal control circuit is configured to adjust the duty cycle of the power dissipation parameter according to a characteristic curve based on the ambient temperature and the average load current when the active thermal control is enabled.

[0139] Aspect 22: The gate driver system according to Aspect 21, wherein the characteristic curve is implemented as a lookup table stored in a memory.

[0140] Aspect 23: A gate driver system according to Aspect 21, wherein the active thermal control circuit is configured to select the characteristic curve from a plurality of characteristic curves stored in a memory associated with the active thermal control circuit based on a load current index value, wherein the load current index value is the value of the most recent sample of the average load current that causes the enablement of the active thermal control triggered by the active thermal control circuit.

[0141] Aspect 24: A gate driver system according to Aspect 19, wherein the power dissipation parameter is a gate drive resistance coupled to the control terminal, a gate drive voltage applied to the control terminal during the conduction state, a switching frequency of the transistor, or a pulse width modulation (PWM) scheme of the gate drive voltage applied to the control terminal to drive the switching state.

[0142] Aspect 25: A gate driver system according to any one of Aspects 15 to 24, wherein the active thermal control circuit is configured to adjust the power dissipation parameter by setting the power dissipation parameter to a power dissipation parameter value within a range of multiple power dissipation parameter values, wherein a characteristic curve defines the range of the multiple power dissipation parameter values ​​and the slope of the multiple power dissipation parameter values, wherein the active thermal control circuit is configured to receive ambient temperature and the average load current as inputs for the characteristic curve, wherein the active thermal control circuit is configured to select the power dissipation parameter value according to the characteristic curve based on the ambient temperature and the average load current to adjust the junction temperature of the transistor when the active thermal control is enabled, and wherein the active thermal control circuit is configured to offset the change in ambient temperature by adjusting the power dissipation of the transistor to produce a temperature change in the junction temperature that is opposite to the change in ambient temperature.

[0143] Aspect 26: A gate driver system according to any one of Aspects 15 to 25, wherein the active thermal control circuit is configured to adjust the power dissipation parameter by setting the power dissipation parameter to a power dissipation parameter value within a range of multiple power dissipation parameter values, wherein the active thermal control circuit is configured to receive the ambient temperature and the average load current as inputs for selecting the power dissipation parameter value from the multiple power dissipation parameter values, wherein the active thermal control circuit is configured to select the power dissipation parameter value from the multiple power dissipation parameter values ​​based on the ambient temperature and the average load current when the active thermal control is enabled.

[0144] Aspect 27: The gate driver system according to Aspect 26, wherein the power dissipation parameter is a gate drive resistance coupled to the control terminal, a gate drive voltage applied to the control terminal during the conduction state, or a switching frequency of the transistor.

[0145] Aspect 28: A method for driving a transistor between switching states, comprising: monitoring a load current change of a load current conducted by the transistor in a conducting state; enabling or disabling active thermal control of the transistor based on the load current change; evaluating a load current change that reaches a duration threshold as a qualified load current change; detecting a direction of a qualified load current change among the qualified load current changes, wherein the direction of the qualified load current change is an increasing direction or a decreasing direction; detecting an amplitude of a qualified load current change among the qualified load current changes; comparing the amplitude with a first threshold; and if the qualified load current change has the decreasing direction and the amplitude of the qualified load current change reaches the first threshold, enabling active thermal control of the transistor, wherein, when the active thermal control is enabled, an active thermal control circuit is enabled to adjust a power dissipation parameter, thereby adjusting the power dissipation of the transistor, and wherein, when the active thermal control is disabled, the active thermal control circuit is disabled so that the power dissipation parameter is not adjusted by the active thermal control circuit.

[0146] Aspect 29: A system configured to perform one or more operations described in one or more of Aspects 1 to 28.

[0147] Aspect 30: An apparatus comprising means for performing one or more operations as recited in one or more of Aspects 1 to 28.

[0148] Aspect 31: A non-transitory computer-readable medium storing an instruction set, wherein the instruction set includes one or more instructions, and when the one or more instructions are executed by a device, the device causes the device to perform one or more operations described in one or more of aspects 1 to 28.

[0149] Aspect 32: A computer program product comprising instructions or codes for performing one or more operations described in one or more of Aspects 1 to 28.

[0150] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementation.

[0151] Some implementations may be described herein in conjunction with thresholds. As used herein, "reaching" a threshold may refer to a value being greater than a threshold, exceeding a threshold, being above a threshold, being greater than or equal to a threshold, being less than a threshold, being less than a threshold, being below a threshold, being less than or equal to a threshold, being equal to a threshold, etc.

[0152] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, when the operation and behavior of the systems and / or methods are described herein without reference to specific software codes, it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0153] Any processing component can be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transient computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, the instruction can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuit systems. Therefore, the term "processor" used in this article refers to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. The software can be stored on a non-transient computer-readable medium, so that the non-transient computer-readable medium includes a program code or a program algorithm stored thereon, which causes the processor to perform the steps of the method through a computer program when executed.

[0154] A controller including hardware may also perform one or more of the techniques of the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its reception, analysis, and control functions, which may also include correction functions. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure.

[0155] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive additional information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal so that the signal meets the requirements of the next stage for further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0156] Even if a particular feature combination is listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementation described herein. Many of these features can be combined in a manner not specifically listed in the claims and / or not disclosed in the specification. For example, the disclosure includes each dependent claim in the claim set combined with each other independent claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase "at least one" in the list of items refers to any combination of these items, including a single member. For example, "at least one of a, b or c" is intended to cover a, b, c, a and b, a and c, b and c and a, b and c, and any combination with multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c, or any other order of a, b and c).

[0157] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order unless these actions or functions are not interchangeable due to technical reasons. In addition, in some implementations, a single action may include multiple sub-actions or may be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action.

[0158] Unless explicitly stated, any element, action or instruction used in this article should not be interpreted as key or necessary. In addition, as used in this article, the article "a" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used in this article, the article "the" is intended to include one or more projects quoted in combination with the article "the", and can be used interchangeably with "one or more". In the case of being intended to only one project, phrases "only one", "single" or similar language are used. In addition, as used in this article, the term "has", "have", "having" etc. are intended to be open terms (for example, "having" A elements can also have B) that do not limit the elements modified. In addition, unless otherwise clearly stated, the phrase "based on" is intended to mean "based on at least in part". As used in this article, the term "multiple" can be replaced with "a plurality of", and vice versa. Furthermore, as used herein, the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or" unless expressly stated otherwise (eg, if used in conjunction with "either" or "only one").

Claims

1. A gate driver system, comprising: a gate driver configured to be coupled to a control terminal of the transistor and configured to control a control voltage applied to the control terminal to drive the transistor between switching states; as well as an active thermal control circuit configured to monitor a load current variation of a load current conducted by the transistor in a conducting state and to enable or disable active thermal control of the transistor based on the load current variation, wherein the active thermal control circuit is configured to evaluate a load current change that reaches a duration threshold as a qualified load current change, wherein the active thermal control circuit is configured to detect a direction of a qualified load current change among the qualified load current changes, wherein the direction of the qualified load current change is an increasing direction or a decreasing direction, wherein the active thermal control circuit is configured to detect a magnitude of a qualified load current variation among the qualified load current variations and compare the magnitude with a first threshold, wherein the active thermal control circuit is configured to enable active thermal control of the transistor if the qualified load current change has the decreasing direction and the magnitude of the qualified load current change reaches the first threshold, wherein the active thermal control circuit is configured to adjust a power dissipation parameter to adjust power dissipation of the transistor when the active thermal control is enabled, and Wherein the active thermal control circuit is configured to not adjust the power dissipation parameter if the active thermal control is disabled.

2. The gate driver system according to claim 1, wherein: The active thermal control circuit is configured to compare the magnitude of the qualified load current change to a second threshold, and The active thermal control circuit is configured to disable active thermal control of the transistor if the qualified load current change has the increasing direction and the magnitude of the qualified load current change reaches the second threshold.

3. The gate driver system according to claim 2, wherein: The magnitude of the qualified load current change is based on a difference between average values ​​of the load current, the average values ​​comprising a first average value of the load current determined at a most recent sampling time and a second average value of the load current determined at a previous sampling time.

4. The gate driver system according to claim 2, wherein: The first threshold is a negative threshold, and when the magnitude of the qualified load current change is less than the first threshold, the magnitude of the qualified load current change reaches the first threshold, and The second threshold is a positive threshold, and when the amplitude of the change of the qualified load current is greater than the second threshold, the amplitude of the change of the qualified load current reaches the second threshold.

5. The gate driver system according to claim 1, wherein: The active thermal control circuit is configured to monitor the load current and detect a magnitude of the load current, wherein the active thermal control circuit is configured to compare the magnitude of the load current with a second threshold, and The active thermal control circuit is configured to disable active thermal control of the transistor if the qualified load current change has the increasing direction and the magnitude of the load current reaches the second threshold.

6. The gate driver system according to claim 5, wherein: The first threshold is a negative threshold, and when the magnitude of the qualified load current change is less than the first threshold, the magnitude of the qualified load current change reaches the first threshold, and The second threshold is a positive threshold, and when the amplitude of the load current is greater than the second threshold, the amplitude of the load current reaches the second threshold.

7. The gate driver system according to claim 5, wherein: The magnitude of the qualified load current change is based on a difference between average values ​​of the load current, the average values ​​comprising a first average value of the load current determined at a most recent sampling time and a second average value of the load current determined at a previous sampling time, and The amplitude of the load current is a first average value of the load current.

8. The gate driver system according to claim 6, wherein: The first threshold is a fixed threshold, and the second threshold is a dynamic threshold, and The active thermal control circuit is configured to dynamically set the second threshold value to be equal to an average value of the load current sampled at a trigger time, at which enabling of the active thermal control is triggered by the active thermal control circuit.

9. The gate driver system according to claim 2, wherein: The active thermal control circuit comprises: a current sensor configured to sense the load current and generate a sensor signal representative of the load current; a low-pass filter configured to receive the sensor signal, filter out the load current variation component in the sensor signal that does not reach the duration threshold, and output the load current variation component in the sensor signal that reaches the duration threshold as the qualified load current variation; a high pass filter coupled to an output of the low pass filter and configured to output a polarity and a magnitude of the qualified load current change, wherein the polarity indicates a direction of the qualified load current change; and a comparator network coupled to the output of the high pass filter and configured to enable active thermal control of the transistor if the qualified load current change has the decreasing direction and the magnitude of the qualified load current change reaches the first threshold, and to disable active thermal control of the transistor if the qualified load current change has the increasing direction and the magnitude of the qualified load current change reaches the second threshold.

10. The gate driver system according to claim 2, wherein: The active thermal control circuit comprises: a current sensor configured to sense the load current and generate a sensor signal representative of the load current; an analog-to-digital converter configured to convert the sensor signal into a digital signal; and an evaluation circuit configured to receive the digital signal, determine an average current value of the digital signal, and determine a difference between a most recent average current value and a previous average current value acquired prior to the most recent average current value, wherein the difference is the magnitude of the change in the qualified load current and the polarity of the difference indicates a direction of the change in the qualified load current.

11. The gate driver system according to claim 10, wherein: The evaluation circuit is configured to compare the difference to the first threshold and the second threshold and to enable or disable active thermal control of the transistor based on the difference reaching the first threshold or the second threshold.

12. The gate driver system according to claim 1, wherein: The power dissipation parameter is a gate drive resistance coupled to the control terminal, a gate drive voltage applied to the control terminal during the conduction state, a switching frequency of the transistor, or a pulse width modulation scheme of the gate drive voltage applied to the control terminal to drive the switching state.

13. A gate driver system comprising: a gate driver configured to be coupled to a control terminal of the transistor and configured to control a control voltage applied to the control terminal so as to drive the transistor between switching states; as well as an active thermal control circuit configured to monitor a load current conducted by the transistor in a conducting state and to enable or disable active thermal control of the transistor based on the load current, The active thermal control circuit is configured to determine an average load current of the load current and evaluate a load current variation of the average load current, wherein evaluating the load current variation of the average load current comprises: Detecting a direction of a load current change of the average load current, wherein the direction of the load current change is an increasing direction or a decreasing direction; detecting a magnitude of a load current change of the average load current; and comparing the magnitude of the load current change with a first threshold, wherein the active thermal control circuit is configured to enable active thermal control of the transistor if the load current variation has the decreasing direction and the magnitude of the load current variation reaches the first threshold, wherein the active thermal control circuit is configured to adjust a power dissipation parameter to adjust power dissipation of the transistor when the active thermal control is enabled, and Wherein the active thermal control circuit is configured to not adjust the power dissipation parameter if the active thermal control is disabled.

14. The gate driver system according to claim 13, wherein: The active thermal control circuit is configured to compare the magnitude of the load current change with a second threshold, and The active thermal control circuit is configured to disable active thermal control of the transistor if the load current variation has the increasing direction and the magnitude of the load current variation reaches the second threshold.

15. The gate driver system according to claim 13, wherein: The active thermal control circuit is configured to compare the magnitude of the average load current to a second threshold, and The active thermal control circuit is configured to disable active thermal control of the transistor if the load current variation has the increasing direction and the magnitude of the average load current reaches the second threshold.

16. The gate driver system according to claim 13, wherein: The active thermal control circuit is configured to adjust the power dissipation parameter by setting the power dissipation parameter in a high-loss mode or in a low-loss mode.

17. The gate driver system according to claim 16, wherein: The active thermal control circuit is configured to adjust the power dissipation parameter according to a duty cycle of the power dissipation parameter when the active thermal control is enabled, and wherein the active thermal control circuit switches the power dissipation parameter between the high loss mode and the low loss mode according to the duty cycle to adjust the power dissipation of the transistor.

18. The gate driver system according to claim 17, wherein: The active thermal control circuit is configured to receive as input the ambient temperature and the average load current, and The active thermal control circuit is configured to adjust a duty cycle of the power dissipation parameter according to a characteristic curve based on the ambient temperature and the average load current when the active thermal control is enabled.

19. The gate driver system according to claim 18, wherein: The active thermal control circuit is configured to select the characteristic curve from a plurality of characteristic curves stored in a memory associated with the active thermal control circuit based on a load current index value, Wherein the load current index value is the value of the most recent sample of the average load current that caused the enabling of the active thermal control to be triggered by the active thermal control circuit.

20. The gate driver system of claim 17, wherein: The power dissipation parameter is a gate drive resistance coupled to the control terminal, a gate drive voltage applied to the control terminal during the conduction state, a switching frequency of the transistor, or a pulse width modulation scheme of the gate drive voltage applied to the control terminal to drive the switching state.

21. A method of driving a transistor between switching states, comprising: monitoring a load current change of a load current conducted by the transistor in a conducting state; enabling or disabling active thermal control of the transistor based on the load current variation; evaluating a load current change that reaches a duration threshold as a qualified load current change; Detecting a direction of a qualified load current change among the qualified load current changes, wherein the direction of the qualified load current change is an increasing direction or a decreasing direction; Detecting an amplitude of a qualified load current change among the qualified load current changes; comparing the amplitude to a first threshold; and enabling active thermal control of the transistor if the qualified load current change has the decreasing direction and the magnitude of the qualified load current change reaches the first threshold, Wherein, in the case where the active thermal control is enabled, the method further comprises enabling an active thermal control circuit to adjust a power dissipation parameter to adjust the power dissipation of the transistor, and Wherein, in the case where the active thermal control is disabled, the method further comprises disabling the active thermal control circuit so that the power dissipation parameter is not adjusted by the active thermal control circuit.

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