Converter circuit

Abstract

One example discloses a converter circuit comprising: an input configured to receive a voltage or current; an output configured to transmit a voltage or a current; a voltage reference; a half bridge (HB) node; a high side (HS) switch coupled between the input and the HB node; a low side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; wherein the controller is configured to send a first command signal after a first regulation time to turn on the HS switch after an HB voltage on the HB node begins to rise in response to the LS switch having been turned off.

Description

Technical Field

[0001] The present specification relates to systems, methods, devices, apparatus, articles of manufacture, and instructions for voltage and current converter circuits. Background Art

[0002] Power supplies for converting AC mains voltage to a lower DC voltage suitable for a specific application are ubiquitous. They are used as adapters or embedded power supplies for mobile devices, edge devices, computers, smartphones, electric vehicles, smart TVs, game consoles, etc. Summary of the invention

[0003] According to an example embodiment, a converter circuit includes: an input configured to receive a voltage or a current; an output configured to transmit a voltage or a current; a voltage reference; a half-bridge (HB) node; a high-side (HS) switch coupled between the input and the HB node; a low-side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; wherein the controller is configured to send a first command signal after a first regulation time to turn on the HS switch after the HB voltage on the HB node begins to rise in response to the LS switch having been turned off.

[0004] In another example embodiment, the controller is configured to send the first command signal after the first adjustment time to turn on the HS switch before the HB voltage on the HB node stops rising in response to the LS switch having been turned off.

[0005] In another example embodiment, the first adjustment time is less than the total time for the HB voltage to rise.

[0006] In another example embodiment, the first adjustment time is equal to the total time of the HB voltage rising minus the first measurement time.

[0007] In another example embodiment, if the first measured time is less than a first target time, the controller is configured to decrease the first adjustment time.

[0008] In another example embodiment, if the first measured time is greater than the first target time, the controller is configured to increase the first adjustment time.

[0009] In another example embodiment, the controller is configured to send a second command signal after a second regulation time to turn on the LS switch after the HB voltage on the HB node starts to decrease in response to the HS switch having been turned off.

[0010] In another example embodiment, the second adjustment time is less than the total time for the HB voltage to drop.

[0011] In another example embodiment, the second adjustment time is equal to the total time of the HB voltage falling minus the second measurement time.

[0012] In another example embodiment, if the second measured time is less than a second target time, the controller is configured to decrease the second adjustment time.

[0013] In another example embodiment, if the second measured time is greater than the second target time, the controller is configured to increase the second adjustment time.

[0014] In another example embodiment, the converter circuit is embedded in a switch mode power supply (SMPS).

[0015] In another example embodiment, the converter circuit is embedded in an AC to DC converter.

[0016] In another example embodiment, the voltage reference is a ground reference.

[0017] In another example embodiment, further comprising an inductor coupled between the half-bridge node and the transformer.

[0018] In another example embodiment, further comprising a transformer coupled between the half-bridge node and the resonant capacitor.

[0019] In another example embodiment, the converter circuit is a resonant converter circuit or an asymmetric half-bridge (AHB) converter circuit.

[0020] According to an example embodiment, a converter circuit includes: an input; an output; a voltage reference; a half-bridge (HB) node; a high-side (HS) switch coupled between the input and the HB node; a low-side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; wherein the controller is configured to send a command signal after a regulation time to turn on the LS switch after the HB voltage on the HB node begins to drop in response to the HS switch having been turned off.

[0021] The above discussion is not intended to present every example embodiment or every implementation that is within the scope of the current or future claim sets.The figures and detailed description also illustrate various example embodiments.

[0022] Various example embodiments may be more fully understood by considering the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A first example of a resonant converter is shown.

[0024] Figure 2 A first example operation timing diagram of a resonant converter is shown.

[0025] Figure 3 A second example operation timing diagram of a resonant converter is shown.

[0026] Figure 4 A third example operation timing diagram of the resonant converter is shown.

[0027] Although the present disclosure allows for various modifications and alternative forms, details thereof have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments other than the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed. DETAILED DESCRIPTION

[0028] AC to DC power converters are a common type of power supply, some of which are configured as resonant power converters. Some resonant power converters contain switch mode power supply (SMPS) circuits. In order to reduce the size of such resonant power converters, the operating frequency of the resonant power converter can be increased. However, one of the limitations of operating at higher frequencies is the precise control of the non-overlap time between the switching elements so that hard switching is avoided. The power converter mainly consists of a first AC to DC stage and a second DC to DC stage. Therefore, the entire power converter is AC to DC. A resonant converter (as described below in Figure 1 ) is almost the second level, which is DC to DC.

[0029] Figure 1 1 shows a first example of a resonant converter 100. The resonant converter 100 includes an input (e.g., for receiving Vin(DC)), an output (e.g., for presenting Vout(DC)), a voltage reference (GND / Vss), a high-side (HS) mosfet 102 switch, a low-side (LS) mosfet 104 switch, a controller 106, and a half-bridge (HB) node 110. In various example embodiments, the converter 100 is configured to receive a voltage or current at the input and to deliver a voltage or current at the output.

[0030] During operation of the resonant converter 100: the resonant current 108 flows through the high-side (HS) mosfet 102 and the resonant tank (Ls, Lm, CR) or the low-side (LS) mosfet 104 and the resonant tank (Ls, Lm, CR); the HB voltage rises and falls at the half-bridge (HB) node 110 and is monitored by the controller 106; and the controller 106 sends a command signal (HS) 112 (gatehs_d) and a command signal (LS) 114 (gatels_d) to the high-side (HS) mosfet 102 switch and the low-side (LS) mosfet 104 switch, respectively.

[0031] In normal resonant converter 100 operation, the resonant current 108 flows in both positive and negative directions. When the high side (HS) mosfet 102 is turned off, the resonant current 108 flows in one (e.g., positive) direction. Initially, the resonant current keeps flowing in this positive direction, discharging the HB node. Once the HB node is discharged to a minimum level (usually equal to ground), the low side (LS) mosfet 104 is turned on. Due to resonance, the current changes direction to the opposite (e.g., negative) direction. When the low side (LS) mosfet 104 is turned off, the current still flows in this negative direction, charging the HB node. When the HB node is charged to a maximum level (usually equal to the input voltage), the high side (HS) mosfet 102 is turned on again. Due to resonance, the current changes direction to the opposite (e.g., positive) direction, and all this repeats from the beginning.

[0032] Various other circuit elements are also shown (e.g., inductor LS, transformer w / Lm, resonant capacitor CR, rectifier diodes D1 and D2, and output capacitor at Vout). These elements may or may not be present in various example embodiments, and / or may be supplemented or replaced with additional circuitry depending on the specific application.

[0033] Figure 2 A first example operation timing diagram 200 of the resonant converter 100 is shown. During operation of the resonant converter 100, when the LS mosfet 104 is turned off at time (t1) by the command signal (LS) 114, the resonant current 108 initially charges the half-bridge (HB) node voltage during time (t2) before finally flowing through the back gate diode of the high-side (HS) mosfet 102 at time (t3).

[0034] If the controller 106 waits until the half-bridge (HB) node voltage 110 is equal to Vin(DC) before turning on the high-side (HS) mosfet 102 via the command signal (HS) 112 at time (t4), the voltage across the high-side (HS) mosfet 102 will already be substantially zero, which minimizes switching losses. This is called "zero voltage switching".

[0035] The time between actually turning off the low-side (LS) MOSFET 104 (ie, GATELS state) and actually turning on the high-side (HS) MOSFET 102 (ie, GATEHS state) is referred to as the LSHS non-overlap time (t no_LSHS ).

[0036] Similarly, after the high-side (HS) MOSFET 102 is turned off by the command signal (HS) 112 and the low-side (LS) MOSFET 104 is turned on by the command signal (LS) 114, a period of time called the HSLS non-overlap time (t no_HSLS ), except that the resonant current 108 flows in the opposite direction. In this case, before the controller 106 turns on the low-side (LS) mosfet 104, the half-bridge (HB) node voltage 110 is discharged.

[0037] These two non-overlapping times (t no )(i.e., t no_LSHS or no_HSLS ) should be neither too small nor too large in order to ensure zero voltage switching (ie, prevent hard switching).

[0038] Although controller 106 includes circuitry and / or instructions for automatically varying these non-overlap times, the optimal non-overlap time (t no ) varies depending on the application values ​​of the specific resonant converter 100 (ie, the specific components, voltage and current static and operating parameters).

[0039] Furthermore, as the operating frequency of the resonant converter 100 increases, the non-overlap time becomes smaller. For example, at low frequencies, the non-overlap time can be as high as 1 us, while at higher frequencies, the non-overlap time can drop to 100 ns.

[0040] Figure 3 A second example operation timing diagram 300 of the resonant converter 100 is shown. no_LSHS Thereafter, the controller 106 detects that the rising edge ( t2 + t3 ) of the voltage at the half-bridge (HB) node 110 has ended.

[0041] However, assuming that the high-side (HS) MOSFET 102 (and similarly, the low-side (LS) MOSFET 104) does not turn on immediately after its respective command signal (LS / HS) 112, 114 is sent by the controller 106, there is still a t before the high-side (HS) MOSFET 102 is effectively turned on (GATEHS). delay_gatehs time (which is typically about 150ns).

[0042] Since the resonant current 108 has reversed direction, the voltage at the half-bridge (HB) node 110 has dropped before the high-side (HS) mosfet 102 is turned on. This results in hard switching, which reduces the efficiency and life of the high-side (HS) mosfet 102. This hard switching also occurs when the controller 106 turns on (GATELS) the low-side (LS) mosfet 104 later in the switching cycle using the command signal (LS) 114, and this hard switching will similarly reduce the efficiency and life of the low-side (LS) mosfet 104.

[0043] Although the high side (HS) MOSFET 102 turns on with a delay (i.e., t delay_gatehs ) (e.g., the difference between the command signal (HS) 112 and the GATEHS change) may be negligible at low resonant converter 100 operating frequencies, but this turn-on delay becomes unacceptable at high operating frequencies and may make automatic non-overlap time control problematic.

[0044] For the low side (LS) MOSFET 104 turn-on delay (i.e., t delay_gatels ) (eg, the difference between the command signal (LS) 114 and the GATELS change) is similar.

[0045] Even if the automatic non-overlap time of the controller 106 is replaced by a fixed non-overlap time, it will need to be fine-tuned circuit by circuit according to the application value of the resonant converter 100 , and the specific fixed non-overlap time is limited to the operating frequency of the specific resonant converter 100 .

[0046] Discussed now is a configuration of the controller 106 that implements automatic non-overlapping time adjustments for both low resonant converter 100 operating frequency and high resonant converter 100 operating frequency and that is independent of the application values ​​of the resonant converter 100 (e.g., specific circuit components, operating voltage and frequency, aging of any circuit components, temperature effects, and load and / or input voltage variations).

[0047] Figure 4 A third example operation timing diagram 400 of the resonant converter 100 is shown. In this example 400, when the low side (LS) mosfet 104 is turned off, the voltage on the half bridge (HB) node 110 rises. This HB_rising voltage on the half bridge (HB) node 110 is detected by the controller 106. When the voltage on the half bridge (HB) node 110 stops rising, the controller 106 sets the HB_rising state to low.

[0048] If the controller 106 waits until HB_rising is set low before sending the command signal (HS) 112 (GATEHS_D) to turn on the high-side (HS) mosfet 102, there will likely be hard switching at high frequencies due to internal and external delays in both the controller 106 and the high-side (HS) mosfet 102. Therefore, it will take some extra time before the high-side (HS) mosfet 102 will effectively turn on (i.e., the GATEHS state goes high).

[0049] Since the resonant current 108 may have changed direction during this delay, in order to avoid hard switching, the high-side (HS) mosfet 102 should be effectively turned on (ie, GATEHS state goes high) at the moment the HB_rising signal goes low.

[0050] The controller 106 achieves this zero voltage switching scenario by turning on the high side (HS) mosfet 102 even before the rising edge of the HB node voltage is over, because waiting to send the command signal (HS) 112 (gatehs_d) to make HB_rising low would result in hard switching.

[0051] This is accomplished by configuring the controller 106 to adjust the regulated_HS ) after the high side (HS) mosfet 102 is turned on after the HB voltage on the HB node 110 starts to rise in response to the low side (LS) mosfet 104 being turned off, but the first regulation time is less than the total time for the HB node 110 voltage to rise (i.e., before the total time).

[0052] First, the controller 106 sets the first adjustment time (Δt regulated_HS ) is defined as the total time for the HB voltage to rise (i.e., HB_rising duration) minus the first measurement time (t meas_HS Next, the controller 106 sets the first measurement time (t meas_HS ) and the first target time (t delay_gatehs ) for comparison.

[0053] If the first measurement time (t meas_HS ) is less than the first target time (t delay_gatehs ), the controller 106 reduces the first adjustment time (Δt regulated_HS ). However, if the first measurement time (t meas_HS ) is greater than the first target time (t delay_gatehs ), the controller 106 increases the first adjustment time (Δt regulated_HS ).

[0054] The low side (LS) MOSFET 104 is similar. The controller 106 is configured to adjust the current during the second regulation time (Δt regulated_LS ) after which a command signal (LS) 114 (gatels_d) is sent to turn on the low side (LS) mosfet 104 after the HB voltage on the half bridge (HB) node 110 begins to drop in response to the high side (HS) mosfet 102 having been turned off.

[0055] The second adjustment time (Δt regulated_LS ) is equal to the total time of HB voltage drop minus the second measurement time (t meas_LS ). If the second measurement time (t meas_LS ) is less than the second target time (t delay_gatels ), the controller 106 is configured to reduce the second adjustment time (Δ tregulated_LS ). However, if the second measurement time (t meas_LS ) is greater than the second target time (t delay_gatels ), the controller 106 is configured to increase the second adjustment time (Δt regulated_LS );

[0056] Applying the above discussion to the HB_rising portion of the voltage curve of the half-bridge (HB) node 110, the first adjustment time (Δt regulated_HS ) may initially be set equal to the previously measured width of the HB_rising signal. Next, the controller 106 starts by aligning gatehs_d (starting to turn on the high-side (HS) MOSFET 102) with the end of the rising edge of HB (t delay_gatehs ) (i.e., the first target time (t delay_gatehs )) as the goal.

[0057] If the measurement time (t meas_HS ) is higher or lower than the first target time (t delay_gatehs ), then Δt is reduced or increased respectively. regulated_HS The value of is such that at the voltage curve of the half bridge (HB) node 110 in the next cycle, the delay t is measured. meas_HS Closer to the first target time (tdelay_gatehs ).

[0058] In this way, the controller 106 can ensure that the high side (HS) mosfet 102 switch is turned on at exactly the right moment to prevent hard switching.

[0059] The above discussion of the high side (HS) mosfet 102 switch may also be applied to the low side (LS) mosfet 104 switch.

[0060] Therefore, the first adjustment time (Δt regulated_HS ) and the second adjustment time (Δt regulated_LS ) not only takes into account all MOSFET turn-on delays, but also any other delays in the resonant converter 100 that affect the non-overlap time (e.g., comparator delays, internal digital switch delays of the controller 106, etc.).

[0061] The controller 106 increases or decreases Δt regulated_HS The rate of Δt can also be varied, possibly using filtering circuits and / or routines in controller 106 so that controller 106 adjusts Δt as quickly or slowly as desired for a particular application. regulated_HS Adjust to the desired value.

[0062] These controller 106 configurations are independent of application values ​​(eg, circuit components, circuit design, operating voltage and frequency, output load, and the steepness of rising and falling voltage changes on the half-bridge (HB) node 110).

[0063] Unless a specific order is explicitly stated, the various instructions and / or operational steps discussed in the above figures may be performed in any order. In addition, those skilled in the art will recognize that although some example instruction sets / steps have been discussed, the material in this specification may be combined in various ways to also produce other examples, and should be understood within the context provided by this detailed description.

[0064] In some example embodiments, these instructions / steps are implemented as functional and software instructions. In other embodiments, the instructions can be implemented using logic gates, application specific chips, firmware, and other hardware forms.

[0065] When instructions are implemented as executable instruction sets in non-transitory computer-readable or computer-usable media, these instructions are implemented on a computer or machine programmed with the executable instructions and controlled by the executable instructions. The instructions are loaded for execution on a processor (e.g., one or more CPUs). The processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. The processor may refer to a single component or multiple components. The computer-readable or computer-usable storage medium is considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. A non-transitory machine or computer-usable medium as defined herein does not include signals, but such a medium is capable of receiving and processing information from signals and / or other temporary media.

[0066] It is readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the detailed description of the various embodiments as represented in the figures is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the drawings, unless otherwise specifically stated, the drawings may not be drawn to scale.

[0067] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. The described embodiments are considered in all respects to be merely illustrative and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than by this detailed description. All changes belonging to the equivalent meaning and scope of the claims should be included within the scope of the claims.

[0068] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that may be realized with the present invention should be or are in any single embodiment of the present invention. Rather, language referring to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussion of features, advantages, and similar language throughout this specification may (but need not necessarily) refer to the same embodiment.

[0069] In addition, the described features, advantages and characteristics of the present invention may be combined in one or more embodiments in any suitable manner. Those skilled in the relevant art will recognize that, in view of the description herein, the present invention may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present invention may be recognized in certain embodiments.

[0070] References throughout this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may (but do not necessarily) all refer to the same embodiment.

Claims

1. A converter circuit, characterized in that: include: an input configured to receive a voltage or a current; an output configured to transmit a voltage or a current; Voltage reference; Half-bridge (HB) node; a high-side (HS) switch coupled between the input and the HB node; a low-side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; The controller is configured to send a first command signal after a first regulation time to turn on the HS switch after a HB voltage on the HB node starts to rise in response to the LS switch having been turned off.

2. The circuit according to claim 1, characterized in that: The controller is configured to send the first command signal after the first regulation time to turn on the HS switch before the HB voltage on the HB node stops rising in response to the LS switch having been turned off.

3. The circuit according to claim 1, characterized in that: The first adjustment time is less than the total time for the HB voltage to rise.

4. The circuit according to claim 1, characterized in that: The first adjustment time is equal to the total time of the HB voltage rising minus the first measurement time.

5. The circuit according to claim 4, characterized in that: If the first measured time is less than a first target time, the controller is configured to decrease the first adjustment time.

6. The circuit according to claim 5, characterized in that: If the first measured time is greater than the first target time, the controller is configured to increase the first adjustment time.

7. The circuit according to claim 1, characterized in that: The controller is configured to send a second command signal after a second regulation time to turn on the LS switch after the HB voltage on the HB node begins to decrease in response to the HS switch having been turned off.

8. The circuit according to claim 7, characterized in that: The second adjustment time is less than the total time of the HB voltage falling.

9. The circuit according to claim 7, characterized in that: The second adjustment time is equal to the total time of the HB voltage drop minus the second measurement time.

10. A converter circuit, characterized in that: include: enter; Output; Voltage reference; Half-bridge (HB) node; a high-side (HS) switch coupled between the input and the HB node; a low-side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; The controller is configured to send a command signal after a regulation time to turn on the LS switch after a HB voltage on the HB node starts to decrease in response to the HS switch having been turned off.

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