Output driving circuit, clock chip and electronic equipment

Abstract

The invention provides an output driving circuit, a clock chip and electronic equipment. The output driving circuit comprises a low-voltage push-pull module and an output isolation module, the low-voltage push-pull module is connected with a low-voltage bias voltage and is used for receiving a high-speed input signal, processing the high-speed input signal and outputting an intermediate signal with a target level, and the output isolation module is connected with the low-voltage bias voltage; the low-voltage push-pull module comprises a push-pull unit formed by a low-voltage transistor pair; and the output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit, and the output isolation module is used for being conducted when the output driving circuit works normally and outputting the intermediate signal as a target output signal of the output driving circuit. The output driving circuit has relatively low power consumption.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits and relates to a driving circuit, and in particular to an output driving circuit, a clock chip and an electronic device. Background Art

[0002] High-Speed ​​Current-Mode Logic (HCSL) is a high-speed differential signaling standard. HCSL is primarily used in high-speed data transmission and communications, such as in high-speed buses, network switches, and routers. Compared to traditional voltage transmission standards such as Low Voltage Differential Signaling (LVDS) and Current-Mode Logic (CML), HCSL offers lower power consumption and reduced noise, while also offering higher transmission rates and longer transmission distances.

[0003] HCSL output driver circuits are a key component of HCSL, providing high-speed electrical signal driving capabilities and converting input signals into current output signals, thereby enabling high-speed data transmission. HCSL output driver circuits are commonly used in drivers and transceivers for high-speed digital circuits such as data transmission, memory, and processors. However, existing HCSL output driver circuits generally suffer from excessive power consumption. Summary of the Invention

[0004] Embodiments of the present application provide an output drive circuit, a clock chip, and an electronic device for solving the problem of excessive power consumption of an HCSL output drive circuit.

[0005] In a first aspect, an embodiment of the present application provides an output drive circuit, which includes a low-voltage push-pull module and an output isolation module, wherein: the low-voltage push-pull module is connected to a low-voltage bias voltage, is used to receive a high-speed input signal and process the high-speed input signal, and output an intermediate signal with a target level, the low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair; the output isolation module is connected between the output end of the push-pull unit and the output end of the output drive circuit, and the output isolation module is used to be turned on when the output drive circuit is operating normally, and output the intermediate signal as the target output signal of the output drive circuit.

[0006] In an implementation of the first aspect, the low-voltage push-pull module includes two push-pull units, and the two push-pull units receive a pair of differential signals.

[0007] In an implementation of the first aspect, the push-pull unit includes a first low-voltage transistor and a second low-voltage transistor with opposite polarities, and the first low-voltage transistor and the second low-voltage transistor are connected in series between the low-voltage bias voltage and ground.

[0008] In an implementation of the first aspect, the first low-voltage transistor is a low-voltage PMOS transistor, and the second low-voltage transistor is a low-voltage NMOS transistor.

[0009] In an implementation of the first aspect, the source of the first low-voltage transistor is connected to the low-voltage bias voltage, the drain of the first low-voltage transistor is connected to the drain of the second low-voltage transistor, the source of the second low-voltage transistor is grounded, the gate of the first low-voltage transistor is connected to the gate of the second low-voltage transistor, the connection point between the gate of the first low-voltage transistor and the gate of the second low-voltage transistor serves as the input end of the push-pull unit, and the connection point between the drain of the first low-voltage transistor and the drain of the second low-voltage transistor serves as the output end of the push-pull unit.

[0010] In an implementation of the first aspect, the output isolation module includes an output isolation unit corresponding one-to-one to the push-pull unit, and the output isolation unit includes a first high-voltage transistor, wherein: the drain of the first high-voltage transistor is connected to the output end of the push-pull unit for receiving the intermediate signal; the gate of the first high-voltage transistor receives a control voltage, wherein the conduction and disconnection of the first high-voltage transistor are controlled by the control voltage; the source of the first high-voltage transistor is connected to the output end of the output drive circuit, so as to output the intermediate signal as the target output signal via the output end of the output drive circuit when the first high-voltage transistor is turned on.

[0011] In an implementation of the first aspect, the first high-voltage transistor is a native NMOS transistor.

[0012] In an implementation of the first aspect, the output driving circuit further includes an impedance calibration module, which is configured to calibrate the output impedance of the output driving circuit so that the output driving circuit has a constant output impedance.

[0013] In an implementation of the first aspect, the impedance calibration module includes: a reference voltage generation circuit for generating a reference voltage; a calibration voltage generation circuit for generating a calibration voltage, wherein the calibration voltage is negatively correlated with the output impedance of the output drive circuit; and an impedance calibration circuit for adjusting the control voltage according to the reference voltage and the calibration voltage.

[0014] In an implementation of the first aspect, the reference voltage generating circuit includes a first resistor and a second resistor, the first resistor and the second resistor are connected in series between the low-voltage bias voltage and ground, and the connection point between the first resistor and the second resistor serves as an output end of the reference voltage generating circuit to output the reference voltage.

[0015] In an implementation of the first aspect, the resistance values ​​of the first resistor and the second resistor are equal.

[0016] In an implementation of the first aspect, the calibration voltage generating circuit includes a third low-voltage transistor, a second high-voltage transistor and a third resistor; the third low-voltage transistor, the second high-voltage transistor and the third resistor are connected in series between the low-voltage bias voltage and the ground, and the connection point between the second high-voltage transistor and the third resistor serves as the output end of the calibration voltage generating circuit to output the calibration voltage, and the second high-voltage transistor receives the control voltage output by the impedance calibration circuit; wherein the third low-voltage transistor is of the same type as the first low-voltage transistor, the second high-voltage transistor is of the same type as the first high-voltage transistor, the overall size of the third low-voltage transistor and the second high-voltage transistor is 1 / N of the overall size of the first low-voltage transistor and the first high-voltage transistor, and the ratio of the resistance value of the third resistor to N is the target output impedance of the output drive circuit.

[0017] In an implementation of the first aspect, the third low-voltage transistor is a low-voltage PMOS transistor, and the second high-voltage transistor is a high-voltage native NMOS transistor.

[0018] In an implementation of the first aspect, the source of the third low-voltage transistor is connected to the low-voltage bias voltage, the drain of the third low-voltage transistor is connected to the drain of the second high-voltage transistor, the gate of the third low-voltage transistor is grounded, the source of the second high-voltage transistor is connected to one end of the third resistor, the other end of the third resistor is grounded, the gate of the second high-voltage transistor receives the control voltage output by the impedance calibration circuit, and the connection point between the source of the second high-voltage transistor and one end of the third resistor serves as the output end of the calibration voltage generating circuit to output the calibration voltage.

[0019] In an implementation of the first aspect, the impedance calibration circuit includes an operational amplifier, a positive input terminal of the operational amplifier is used to receive the reference voltage, a negative input terminal of the operational amplifier is used to receive the calibration voltage, and the operational amplifier outputs the control voltage based on the reference voltage and the calibration voltage.

[0020] In an implementation of the first aspect, the output drive circuit further includes a voltage stabilizer, which is configured to step down the power supply voltage to output the low-voltage bias voltage.

[0021] In an implementation of the first aspect, the output drive circuit further includes a pre-drive module, which is connected to the input end of the push-pull unit and is used to pre-drive the high-speed input signal, wherein the operating voltage of the pre-drive module is the low-voltage bias voltage.

[0022] In an implementation of the first aspect, the low-voltage bias voltage is 0.75V.

[0023] In a second aspect, an embodiment of the present application provides a clock chip, which includes: a clock signal generating circuit for generating a high-speed clock signal; an output driving circuit, including a low-voltage push-pull module and an output isolation module, for inputting the high-speed clock signal and outputting a target high-speed clock signal; the low-voltage push-pull module is connected to a low-voltage bias voltage, for receiving the high-speed clock signal and processing the high-speed clock signal, and outputting an intermediate signal with a target level, the low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair; the output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit, the output isolation module is used to be turned on when the output driving circuit is working normally, and output the intermediate signal as the target high-speed clock signal.

[0024] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a signal generating circuit for generating a high-speed signal; an output driving circuit, comprising a low-voltage push-pull module and an output isolation module, for inputting the high-speed signal and outputting a target high-speed signal; the low-voltage push-pull module is connected to a low-voltage bias voltage, for receiving the high-speed signal and processing the high-speed signal, and outputting an intermediate signal with a target level, the low-voltage push-pull module comprising a push-pull unit composed of a low-voltage transistor pair; the output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit, the output isolation module is used to be turned on when the output driving circuit is operating normally, and output the intermediate signal as the target high-speed signal.

[0025] The output drive circuit provided in the embodiment of the present application adopts a push-pull voltage mode output structure, which can provide a large swing level for the receiving circuit without the need for a termination resistor, thereby reducing the output dynamic power consumption. In addition, the output drive circuit uses low-voltage transistors to form a push-pull voltage mode output, which has a faster output signal slew rate and is suitable for higher-speed application scenarios. Furthermore, the size and parasitic capacitance of the low-voltage transistor are smaller. Compared with the technical solution of using high-voltage transistors as switching tubes, the output drive circuit provided in the embodiment of the present application has lower switching capacitance power consumption and parasitic power consumption.

[0026] In some embodiments of the present application, the pre-driver circuit of the low-voltage transistor can be implemented using a control circuit operating at a low voltage, which is beneficial for further reducing the overall dynamic power consumption of the output driver circuit.

[0027] In some embodiments of the present application, the output driver circuit further includes an adaptive impedance calibration module. This module utilizes a high-voltage native NMOS (N-type Metal Oxide Semiconductor) transistor as an output isolation device, effectively protecting the low-voltage transistor from reliability issues while also ensuring a constant output impedance for the output driver circuit, ensuring better signal integrity in high-speed applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is the circuit diagram of the HCSL output driver circuit.

[0029] Figure 2 Shown is a structural schematic diagram of the output drive circuit provided in an embodiment of the present application.

[0030] Figure 3 Shown is a circuit diagram of an output drive circuit provided in an embodiment of the present application.

[0031] Figure 4 Shown is a circuit diagram of an output drive circuit provided in an embodiment of the present application.

[0032] Figure 5 Shown is a structural schematic diagram of the impedance calibration module in an embodiment of the present application.

[0033] Figure 6 Shown is a circuit diagram of the impedance calibration module in an embodiment of the present application.

[0034] Figure 7 Shown is a schematic diagram of the structure of the clock chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0037] HCSL output driver circuits are a key component of HCSL, providing high-speed electrical signal driving capabilities. They convert input signals into current output signals, enabling high-speed data transmission. HCSL output driver circuits are commonly used in drivers and transceivers for high-speed digital circuits such as data transmission, memory, and processors.

[0038] Figure 1 The circuit diagram of the HCSL output driver circuit in some technical solutions is shown. Figure 1 As shown in the figure, the HCSL output driver circuit in these technical solutions includes a current source Is output from the power supply VDD and a pair of differential high-voltage PMOS (P-type Metal Oxide Semiconductor) switch tubes. The pre-driver circuit of the high-voltage PMOS switch tube is implemented by a high-voltage logic circuit working under VDD, and the output pin (Pad) is externally connected to the termination resistor R T Ground (GND) to provide the desired swing level for the receiving circuit.

[0039] However, if Figure 1 In the HCSL output driver circuit shown, since the two differential high-voltage PMOS switches are always on when outputting differential signals, for this current mode output driver circuit, the current provided by the current source Is is constantly consumed by the termination resistor R T The voltage provided by the power supply VDD is 3.3V, the current output by the current source Is is 15mA, and the termination resistor R T Taking 50 ohms as an example, Figure 1 The power consumption of the HCSL output driver circuit shown is about 50mW. Figure 1The slew rate of the rising and falling edges of the HCSL output driver circuit shown is determined by the termination resistor R T The output clock signal integrity is poor when transmitting high-speed clock signals and driving long printed circuit board (PCB) traces.

[0040] At least to address the above-mentioned problem, an embodiment of the present application provides an output driving circuit. Figure 2 The structure diagram of the output drive circuit 2 provided in the embodiment of the present application is shown. Figure 2 As shown, the output driving circuit 2 provided in the embodiment of the present application includes a low-voltage push-pull module 21 and an output isolation module 22 .

[0041] The low-voltage push-pull module 21 is connected to a low-voltage bias voltage, the voltage value of which is, for example, 0.75 V. In some embodiments, the low-voltage bias voltage can be a voltage (e.g., 0.75 V) regulated by a low-dropout (LDO) linear regulator (e.g., 3.3 V) from a power supply voltage. In other embodiments, the low-voltage bias voltage can also be provided by an external power supply (e.g., a 0.75 V power supply).

[0042] The low-voltage push-pull module 21 includes a push-pull unit composed of a pair of low-voltage transistors. The push-pull unit is configured to receive a high-speed input signal and output an intermediate signal having a target voltage level. In some embodiments, the high-speed input signal may be, for example, a high-speed clock signal, but the present application is not limited thereto.

[0043] A low-voltage transistor refers to a type of transistor that requires a lower voltage when operating in a logic circuit. For example, in some embodiments, a low-voltage transistor may be a transistor having an operating voltage lower than 1V, but this application is not limited thereto. The low-voltage characteristics of a low-voltage transistor can be achieved through a process. For example, the transistor can be able to operate normally at a low voltage by reducing the threshold voltage of the transistor, reducing the thickness of the gate oxide layer, etc. In addition, this application does not impose any restrictions on the type of low-voltage transistor. For example, the low-voltage transistor may be an NMOS transistor, a PMOS transistor, etc.

[0044] In the embodiment of the present application, the low-voltage push-pull module 21 may include one push-pull unit or multiple push-pull units. Each push-pull unit includes two low-voltage transistors with opposite polarities, which are connected in series to form a push-pull voltage-mode output stage.

[0045] The output isolation module 22 includes one or more output isolation units for isolating high voltage, and an output isolation unit is connected between the output terminal of each push-pull unit and the output terminal (Pad) of the output driver circuit. The output isolation unit is turned on when the output driver circuit is working normally, and outputs the above-mentioned intermediate signal as the target output signal of the output driver circuit. Specifically, when the output driver circuit 2 is working normally, the output isolation unit is controlled to be turned on, and now the output driver circuit 2 is connected to the external circuit, and the intermediate signal output by the push-pull unit is provided to the external circuit to drive the external circuit. When the output driver circuit 2 is not working, the output isolation unit is controlled to be disconnected, and now the output driver circuit 2 is disconnected from the external circuit.

[0046] According to the above description, the output drive circuit provided by the embodiment of the present application adopts a push-pull unit composed of a low-voltage transistor pair as the output structure, which can provide the desired swing level for the receiving circuit without the need for a termination resistor. This method is conducive to reducing the output dynamic power consumption. In addition, the low-voltage transistor can operate at a lower power supply voltage, which is conducive to further reducing the power consumption of the output drive circuit. Furthermore, compared with the technical solution of using a high-voltage transistor device as a switch tube, the low-voltage transistor has a smaller size and parasitic capacitance, so the output drive circuit provided by the embodiment of the present application has lower switching capacitance power consumption and parasitic power consumption.

[0047] Moreover, the push-pull voltage-mode output composed of a low-voltage transistor pair can provide a faster output signal slew rate and a faster switching speed, making it suitable for higher-speed application scenarios.

[0048] In addition, when the output drive circuit is not working, the output isolation module is in a disconnected state. At this time, even if the output pin is in a high-voltage working mode, it will not cause damage to the low-voltage transistor. Therefore, the output drive circuit provided in the embodiment of the present application has high reliability.

[0049] Figure 3 Shown is a structural diagram of the output drive circuit 2 in one embodiment of the present application. Figure 3 The low voltage push-pull module includes two push-pull units as an example for illustration, but the present application is not limited to this. Figure 3 As shown, in the embodiment of the present application, the low-voltage push-pull module 21 includes two push-pull units, namely a first push-pull unit 211 and a second push-pull unit 212. Each push-pull unit includes two low-voltage transistors with opposite polarities, namely a first low-voltage transistor and a second low-voltage transistor, which serve as a pull-up transistor and a pull-down transistor respectively. The first low-voltage transistor is a low-voltage PMOS tube ( Figure 3 PMOS1, PMOS2 in), the second low-voltage transistor is a low-voltage NMOS tube ( Figure 3Taking NMOS1 and NMOS2 in the figure as an example, the source of the first low-voltage transistor is connected to the low-voltage bias voltage, the drain of the first low-voltage transistor is connected to the drain of the second low-voltage transistor, the source of the second low-voltage transistor is grounded (GND), the gate of the first low-voltage transistor is connected to the gate of the second low-voltage transistor, the connection point between the gate of the first low-voltage transistor and the gate of the second low-voltage transistor serves as the input end of the push-pull unit, and the connection point between the drain of the first low-voltage transistor and the drain of the second low-voltage transistor serves as the output end of the push-pull unit.

[0050] It should be noted that Figure 3 The type and connection method of the transistors in the push-pull unit shown is only one possible method of the present application, but the present application is not limited thereto. For example, in some embodiments, the first push-pull unit and / or the second push-pull unit may also use a low-voltage NMOS transistor as a pull-up transistor and a low-voltage PMOS transistor as a pull-down transistor.

[0051] In some embodiments, the high-speed input signals input to the two push-pull units may be a pair of differential signals, such as differential high-speed clock signals. Figure 3 In the output driving circuit 2 shown, the high-speed input signals are differential clock signals CLK+ and CLK−, wherein CLK+ is input to the first push-pull unit 211 and CLK− is input to the second push-pull unit 212 .

[0052] In other embodiments, the input high-speed input signal may be a single-ended high-speed signal. In this case, the single-ended high-speed signal may be selectively input into any one of the push-pull units, such as the first push-pull unit 211, which processes the single-ended high-speed signal and then outputs it.

[0053] In some embodiments, the output isolation module 22 may include output isolation units 221 and 222. The output isolation unit 221 is connected between the output terminal of the first push-pull unit 211 and one output terminal of the output driver circuit 2, and the output isolation unit 222 is connected between the output terminal of the second push-pull unit 212 and the other output terminal of the output driver circuit 2. The output isolation units 221 and 222 each have an open state and an open state. By controlling the open and closed states of the output isolation units 221 and 222, the connection between the first push-pull unit 211 and the second push-pull unit 212 and the external circuit can be controlled.

[0054] In some embodiments, the output isolation units 221 and 222 can be implemented by high-voltage transistors, such as high-voltage native MOS transistors. The voltage required for high-voltage native MOS transistors to operate in logic circuits is relatively high, and the specific operating voltage value varies depending on different applications and manufacturing processes. For example, in some embodiments, the operating voltage of the high-voltage native MOS transistor can be greater than or equal to 3.3V, but this application is not limited to this. The high-voltage native MOS transistor can be a high-voltage native NMOS transistor or a PMOS transistor. In order to distinguish it from the following text, the high-voltage transistors constituting the output isolation units 221 and 222 are referred to as first high-voltage transistors. Figure 4 The first high-voltage transistor is a high-voltage native NMOS transistor. Figure 4 As shown, the high-voltage native NMOS tube ( Figure 4 The drain of the native NMOS1 and native NMOS2 in the push-pull unit is connected to the output end of the push-pull unit for receiving the intermediate signal. The source is connected to the output end of the output drive circuit so that when the high-voltage native NMOS tube is turned on, the intermediate signal is output as the target output signal via the output end of the output drive circuit. The gate receives a control voltage Na_vctrl, which can be used to control the conduction and disconnection of the high-voltage native NMOS tube. For example, when the output drive circuit is operating normally, its gate can be connected to the high-voltage signal to turn on the high-voltage native NMOS1 and high-voltage native NMOS2; when the output drive circuit is not operating, its gate can be grounded to disconnect the high-voltage native NMOS1 and high-voltage native NMOS2, thereby preventing the high voltage of the external circuit from damaging the low-voltage transistor in the push-pull unit and avoiding reliability issues.

[0055] When using the aforementioned high-voltage native NMOS transistor to isolate high voltage, the output impedance of the high-voltage native NMOS transistor itself varies significantly with process, voltage, and temperature. To address this issue, embodiments of the present application employ an impedance calibration module to calibrate the output impedance of the output driver circuit, maintaining a constant output impedance and ensuring better signal integrity in high-speed applications.

[0056] Figure 5 The structure diagram of the impedance calibration module 24 in one embodiment of the present application is shown. Figure 5As shown, the impedance calibration module 24 includes a reference voltage generating circuit 241, a calibration voltage generating circuit 242, and an impedance calibration circuit 243. The reference voltage generating circuit 241 is used to generate a reference voltage, and the voltage value of the reference voltage can be set to 1 / 2 of the above-mentioned low-voltage bias voltage, but the present application is not limited to this. The calibration voltage generating circuit 242 is used to generate a calibration voltage, and the calibration voltage is negatively correlated with the output impedance of the output drive circuit, that is, the smaller the output impedance of the output drive circuit, the higher the calibration voltage, and the larger the output impedance of the output drive circuit, the lower the calibration voltage. When the calibration voltage and the reference voltage are equal, the output impedance of the output drive circuit is the target impedance value. The impedance calibration circuit 243 is used to adjust the control voltage Na_vctrl output to the gate of the first high-voltage native NMOS according to the calibration voltage and the reference voltage, thereby adjusting the output impedance of the first high-voltage native NMOS (including native NMOS1 and native NMOS2). Specifically, when the calibration voltage is higher than the reference voltage, since the calibration voltage is negatively correlated with the output impedance of the output drive circuit, it can be determined that the output impedance of the output drive circuit is less than the target impedance value. In this case, the impedance calibration circuit 243 is used to reduce the control voltage Na_vctrl, thereby increasing the output impedance of the first high-voltage native NMOS transistor. Similarly, when the calibration voltage is lower than the reference voltage, it can be determined that the output impedance of the output driver circuit is greater than the target impedance value. In this case, the impedance calibration circuit 243 is used to increase the control voltage Na_vctrl, thereby reducing the output impedance of the first high-voltage native NMOS transistor. In this manner, the impedance calibration module 24 can ensure that the output impedance of the output driver circuit is constant.

[0057] Figure 6 Shown is a structural diagram of the impedance calibration module 24 provided in an embodiment of the present application. Figure 6 As shown, the reference voltage generating circuit 241 may include a first resistor R1 and a second resistor R2. The first resistor R1 and the second resistor R2 are connected in series between a low voltage bias voltage and ground. The connection point between the first resistor R1 and the second resistor R2 serves as the output terminal of the reference voltage generating circuit 241, which outputs the reference voltage to the impedance calibration circuit 243.

[0058] In some embodiments, the resistance values ​​of the first resistor R1 and the second resistor R2 are equal, and the reference voltage is 1 / 2 of the low voltage bias voltage, but the present application is not limited thereto.

[0059] The calibration voltage generation circuit 242 includes a third low-voltage transistor, a second high-voltage transistor, and a third resistor. The third low-voltage transistor, the second high-voltage transistor, and the third resistor are connected in series between the low-voltage bias voltage and ground. The connection point between the second high-voltage transistor and the third resistor serves as the output terminal of the calibration voltage generation circuit 242 to output the calibration voltage. The second high-voltage transistor receives the control voltage output by the impedance calibration circuit 243. It can be understood that the connection structure between the third low-voltage transistor and the second high-voltage transistor simulates the pull-up circuit portion of the output drive circuit body, that is, the connection structure between the first low-voltage transistor and the first high-voltage transistor. This simulated portion and the third resistor divide the low-voltage bias voltage to generate the calibration voltage. The third low-voltage transistor is of the same type as the first low-voltage transistor, and the second high-voltage transistor is of the same type as the first transistor. The overall size of the third low-voltage transistor and the second high-voltage transistor is 1 / N of the overall size of the first low-voltage transistor and the first high-voltage transistor, that is, the overall output impedance of the third low-voltage transistor and the second high-voltage transistor is N times the overall output impedance of the first low-voltage transistor and the first high-voltage transistor, where N is the ratio of the resistance value of the third resistor to the target output impedance of the output drive circuit. For example, if the third resistor R3 is 1k ohms and the target output impedance is 50 ohms, then N is 20.

[0060] Figure 6 Take the example where the third low-voltage transistor is a low-voltage PMOS transistor (ie, PMOS3) and the second high-voltage transistor is a high-voltage native NMOS transistor (native NMOS3). Figure 6 As shown, the source of PMOS3 is connected to the low-voltage bias voltage Vreg, its gate is grounded, and its drain is connected to the drain of native NMOS3. The source of native NMOS3 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded. The gate of native NMOS3 receives the control voltage Na_vctrl output by the impedance calibration circuit 243. The connection point between the source of native NMOS3 and the third resistor R3 serves as the output end of the calibration voltage generating circuit 242 to output the calibration voltage.

[0061] The impedance calibration circuit 243 includes an operational amplifier. The positive input of the operational amplifier is used to receive a reference voltage, and the negative input of the operational amplifier is used to receive a calibration voltage. The operational amplifier outputs a control voltage based on the reference voltage and the calibration voltage. In some embodiments, the output of the operational amplifier is connected to the gate of the second high-voltage transistor (i.e., native NMOS 3). The output impedance of the native NMOS 3 can be adjusted by adjusting the control voltage Na_vctrl output to the gate (e.g., adjustable between 0 and 3.3 V).

[0062] As can be seen from the above description, the operational amplifier and the native NMOS3 form a negative feedback loop. By adjusting the control voltage Na_vctrl, the output impedance of the native NMOS3 can be adjusted in real time, thereby adjusting the overall output impedance of the PMOS3 and the native NMOS3. When the overall output impedance of the PMOS3 and the native NMOS3 is adjusted to the same as the third resistor R3, for example, 1k ohm, the overall output impedance of the first low-voltage transistor (PMOS1, PMOS2) and the first high-voltage transistor (native NMOS1, nativeNMOS2) is synchronously adjusted to 1 / 20 of its impedance (taking N equal to 20 as an example), that is, 50 ohms. In this way, the output impedance of the output driver circuit can be kept constant, thereby ensuring that the output signal of the output driver circuit has better signal integrity in high-speed applications.

[0063] In one embodiment of the present application, the output driver circuit may further include a pre-driver module. The pre-driver module's output is connected to the input of the push-pull unit, configured to receive a high-speed input signal and output a regulated high-speed input signal to the push-pull unit to pre-drive the push-pull unit, thereby improving the output driver circuit's drive capability and output speed. In this embodiment of the present application, the pre-driver module operates at a low-voltage bias voltage.

[0064] Please continue reading Figure 3 In the embodiment of the present application, the pre-driver module 23 includes pre-driver units 231 and 232. The pre-driver unit 231 is used to pre-drive CLK+, and the pre-driver unit 232 is used to pre-drive CLK-. It should be noted that, Figure 3 The pre-driving units 231 and 232 shown are merely examples, and the present application is not limited thereto.

[0065] In some embodiments, the pre-driving units 231 and 232 are both implemented by a low-voltage control circuit operating at a low-voltage bias voltage, such as an operational amplifier.

[0066] As can be seen from the above description, in the output drive circuit provided by the embodiment of the present application, both the push-pull unit and the pre-drive unit can operate at a low voltage (e.g., 0.75V). This approach helps further reduce the overall power consumption of the output drive circuit. For example, when outputting a 100MHz differential high-speed clock signal, the dynamic current consumption of the output drive circuit provided by the embodiment of the present application is approximately 2.2mA.

[0067] An embodiment of the present application also provides a clock chip, which includes a clock signal generating circuit and an output driving circuit.

[0068] The clock signal generating circuit is used to generate a high-speed clock signal, and the frequency of the high-speed clock signal is, for example, 100 MHz. In some embodiments, the clock signal generating circuit can use a crystal oscillator and a frequency multiplier to generate the high-speed clock signal. In other embodiments, the clock signal generating circuit can also use a phase-locked loop (PLL) or a delay-locked loop (DLL) to generate the high-speed clock signal. It should be understood that the above two methods of generating a high-speed clock signal are only two feasible methods of the embodiments of the present application, but the present application is not limited thereto.

[0069] The output drive circuit includes a low-voltage push-pull module and an output isolation module, which are used to input a high-speed clock signal and output a target high-speed clock signal. The low-voltage push-pull module is connected to a low-voltage bias voltage, is used to receive and process the high-speed clock signal, and output an intermediate signal with a target level. The low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair. The output isolation module is connected between the output end of the push-pull unit and the output end of the output drive circuit. The output isolation module is used to be turned on when the output drive circuit is operating normally and output the intermediate signal as the target high-speed clock signal. The output drive circuit is used to provide sufficient current and voltage to drive the high-speed clock signal to the target device to ensure the stability and reliability of the clock signal.

[0070] The clock chip provided in the embodiment of the present application can be represented as a saleable active device that packages a clock signal generating circuit and an output driving circuit manufactured on a wafer using semiconductor technology, or can be represented as a saleable active device that packages a clock signal generating circuit and an output driving circuit using PCB packaging technology.

[0071] Figure 7 Shown is a packaging schematic diagram of a clock chip provided in an embodiment of the present application. Figure 7 As shown, the clock chip at least includes a first pin for receiving a high-speed clock signal, a second pin for outputting a target high-speed clock signal, a third pin for connecting a voltage, and a fourth pin for grounding.

[0072] An embodiment of the present application also provides an electronic device, which includes a signal generating circuit and an output driving circuit. The signal generating circuit is used to generate a high-speed signal. The output driving circuit includes a low-voltage push-pull module and an output isolation module, which are used to input a high-speed signal and output a target high-speed signal. The low-voltage push-pull module is connected to a low-voltage bias voltage, is used to receive and process the high-speed signal, and output an intermediate signal with a target level. The low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair. The output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit. The output isolation module is used to be turned on when the output driving circuit is operating normally, and output the intermediate signal as the target high-speed signal.

[0073] In summary, the low-power, high-speed output driver circuit structure provided by the embodiment of the present application, compared to the traditional HCSL output driver circuit structure, operates at a lower power supply voltage (0.75V) and adopts a voltage-mode output structure. It can provide the desired swing level to the receiving circuit without a termination resistor, thereby greatly reducing the output dynamic power consumption; and because it is a push-pull voltage-mode output composed of low-voltage transistor devices, it has a faster output signal slew rate and is suitable for higher-speed application scenarios. Compared with the existing low-power output driver circuit structure, the low-power, high-speed output driver circuit structure provided by the embodiment of the present application adopts low-voltage transistor devices as the output stage body, so the switching speed is faster and can be applied to higher-speed application scenarios. The low-voltage transistor devices are smaller in size and have smaller parasitic capacitance. Therefore, compared with using high-voltage transistor devices as switching tubes, the switching capacitance power consumption and parasitic power consumption are lower. At the same time, the pre-driver circuit of the low-voltage transistor device is also implemented using a control circuit operating at low voltage, further reducing the overall dynamic power consumption of the output driver circuit. On the other hand, the use of high-voltage native NMOS transistors as isolation devices not only protects low-voltage devices and avoids reliability issues, but also uses an adaptive impedance calibration circuit to ensure that the drive circuit has a constant output impedance, giving the output signal better signal integrity in high-speed applications.

[0074] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0075] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. An output drive circuit, characterized in that: It includes low voltage push-pull module and output isolation module, including: The low-voltage push-pull module is connected to a low-voltage bias voltage, and is used to receive a high-speed input signal and process the high-speed input signal, and output an intermediate signal with a target level. The low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair; The output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit. The output isolation module is used to be turned on when the output driving circuit works normally, and output the intermediate signal as the target output signal of the output driving circuit.

2. The output drive circuit according to claim 1, characterized in that: The low voltage push-pull module includes two push-pull units, and the two push-pull units receive a pair of differential signals.

3. The output drive circuit according to claim 1, characterized in that: The push-pull unit includes a first low-voltage transistor and a second low-voltage transistor with opposite polarities, and the first low-voltage transistor and the second low-voltage transistor are connected in series between the low-voltage bias voltage and ground.

4. The output drive circuit according to claim 3, characterized in that: The first low-voltage transistor is a low-voltage PMOS transistor, and the second low-voltage transistor is a low-voltage NMOS transistor.

5. The output drive circuit according to claim 4, characterized in that: The source of the first low-voltage transistor is connected to the low-voltage bias voltage, the drain of the first low-voltage transistor is connected to the drain of the second low-voltage transistor, the source of the second low-voltage transistor is grounded, the gate of the first low-voltage transistor is connected to the gate of the second low-voltage transistor, the connection point between the gate of the first low-voltage transistor and the gate of the second low-voltage transistor serves as the input end of the push-pull unit, and the connection point between the drain of the first low-voltage transistor and the drain of the second low-voltage transistor serves as the output end of the push-pull unit.

6. The output drive circuit according to claim 3, characterized in that: The output isolation module includes an output isolation unit corresponding to the push-pull unit one by one, and the output isolation unit includes a first high-voltage transistor, wherein: The drain of the first high-voltage transistor is connected to the output end of the push-pull unit and is used to receive the intermediate signal; The gate of the first high-voltage transistor receives a control voltage, wherein the on and off of the first high-voltage transistor is controlled by the control voltage; The source of the first high-voltage transistor is connected to the output terminal of the output driving circuit, so that the intermediate signal is output as the target output signal via the output terminal of the output driving circuit when the first high-voltage transistor is turned on.

7. The output drive circuit according to claim 6, characterized in that: The first high-voltage transistor is a native NMOS transistor.

8. The output drive circuit according to claim 6, characterized in that: The output driving circuit further includes an impedance calibration module, and the impedance calibration module is used to calibrate the output impedance of the output driving circuit so that the output driving circuit has a constant output impedance.

9. The output drive circuit according to claim 8, characterized in that: The impedance calibration module comprises: A reference voltage generating circuit, used for generating a reference voltage; A calibration voltage generating circuit, used for generating a calibration voltage, wherein the calibration voltage is negatively correlated with the output impedance of the output driving circuit; The impedance calibration circuit is used to adjust the control voltage according to the reference voltage and the calibration voltage.

10. The output drive circuit according to claim 9, characterized in that: The reference voltage generating circuit includes a first resistor and a second resistor, the first resistor and the second resistor are connected in series between the low voltage bias voltage and ground, and the connection point between the first resistor and the second resistor serves as the output end of the reference voltage generating circuit to output the reference voltage.

11. The output drive circuit according to claim 10, characterized in that: The resistance values ​​of the first resistor and the second resistor are equal.

12. The output driving circuit according to claim 9, characterized in that: The calibration voltage generating circuit comprises a third low voltage transistor, a second high voltage transistor and a third resistor; the third low voltage transistor, the second high voltage transistor and the third resistor are connected in series between the low voltage bias voltage and ground, a connection point between the second high voltage transistor and the third resistor serves as an output end of the calibration voltage generating circuit to output the calibration voltage, and the second high voltage transistor receives the control voltage output by the impedance calibration circuit; Among them, the third low-voltage transistor is of the same type as the first low-voltage transistor, the second high-voltage transistor is of the same type as the first high-voltage transistor, the overall size of the third low-voltage transistor and the second high-voltage transistor is 1 / N of the overall size of the first low-voltage transistor and the first high-voltage transistor, and the ratio of the resistance value of the third resistor to N is the target output impedance of the output drive circuit.

13. The output driving circuit according to claim 12, characterized in that: The third low-voltage transistor is a low-voltage PMOS transistor, and the second high-voltage transistor is a high-voltage native NMOS transistor.

14. The output driving circuit according to claim 13, characterized in that: The source of the third low-voltage transistor is connected to the low-voltage bias voltage, the drain of the third low-voltage transistor is connected to the drain of the second high-voltage transistor, the gate of the third low-voltage transistor is grounded, the source of the second high-voltage transistor is connected to one end of the third resistor, the other end of the third resistor is grounded, the gate of the second high-voltage transistor receives the control voltage output by the impedance calibration circuit, and the connection point between the source of the second high-voltage transistor and one end of the third resistor serves as the output end of the calibration voltage generating circuit to output the calibration voltage.

15. The output driving circuit according to claim 9, characterized in that: The impedance calibration circuit includes an operational amplifier, a positive input terminal of the operational amplifier is used to receive the reference voltage, a negative input terminal of the operational amplifier is used to receive the calibration voltage, and the operational amplifier outputs the control voltage based on the reference voltage and the calibration voltage.

16. The output driving circuit according to claim 1, characterized in that: The output drive circuit further includes a voltage stabilizer, which is used to step down the power supply voltage to output the low voltage bias voltage.

17. The output driving circuit according to claim 1, characterized in that: The output driving circuit further includes a pre-driving module, which is connected to the input end of the push-pull unit and is used to pre-drive the high-speed input signal, wherein the operating voltage of the pre-driving module is the low-voltage bias voltage.

18. The output driving circuit according to claim 1, characterized in that: The low voltage bias voltage is 0.75V.

19. A clock chip, characterized in that: The clock chip comprises: A clock signal generating circuit, used for generating a high-speed clock signal; An output drive circuit, comprising a low voltage push-pull module and an output isolation module, for inputting the high-speed clock signal and outputting a target high-speed clock signal; The low-voltage push-pull module is connected to a low-voltage bias voltage, and is used to receive the high-speed clock signal and process the high-speed clock signal, and output an intermediate signal with a target level. The low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair; The output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit. The output isolation module is used to be turned on when the output driving circuit works normally and output the intermediate signal as the target high-speed clock signal.

20. An electronic device, characterized in that: The electronic device comprises: A signal generating circuit for generating a high-speed signal; An output drive circuit, including a low voltage push-pull module and an output isolation module, is used to input the high-speed signal and output a target high-speed signal; The low-voltage push-pull module is connected to a low-voltage bias voltage, and is used to receive and process the high-speed signal, and output an intermediate signal with a target level. The low-voltage push-pull module includes a push-pull unit composed of a low-voltage transistor pair; The output isolation module is connected between the output end of the push-pull unit and the output end of the output driving circuit. The output isolation module is used to be turned on when the output driving circuit works normally and output the intermediate signal as the target high-speed signal.

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