Conversion start-up of analog-to-digital converter in integrated circuit

Abstract

The invention relates to conversion start-up of an analog-to-digital converter in an integrated circuit. The analog-to-digital converter is clocked by a converter clock signal. The first clock signal has a frequency that is a multiple of a frequency of the converter clock signal. A timer clocked with the rhythm of the first clock signal has a timing period that is a multiple of the period of the converter clock signal. The processor is configured to control the converter based on a timing signal transmitted by the timer, and has a first mode of operation in which the processor is further configured to time the timer in synchronization with the converter clock signal, and transmit a first periodic conversion control signal of the converter based on the timing signal, the first cycle conversion control signal has a cycle that is a multiple of a cycle of the converter clock signal and has a first constant phase difference from the converter clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 2306551 filed on June 23, 2023, which is hereby incorporated herein by reference. Technical Field

[0003] Embodiments relate to integrated circuits, particularly microcontrollers, eg, embedding one or more analog-to-digital converters and timers, and associated methods, and more particularly to managing the initiation of a conversion cycle of a converter. Background Art

[0004] Some current microcontrollers provide a so-called "fixed trigger latency" feature, ie, a fixed duration or latency between the time an analog-to-digital conversion is commanded or triggered and the time when the conversion actually begins.

[0005] This feature is particularly useful in motor control or audio processing applications.

[0006] The timer then drives the application based on a pulse width modulated signal ("PWM: Pulse Width Modulation").

[0007] The analog-to-digital conversion is regularly controlled in each period of the PWM signal, and for some applications it is essential that the above mentioned waiting time does not change for different periods, ie there is no jitter.

[0008] This is ensured by construction when the converter and timer are each clocked by a synchronized clock.

[0009] When the converter and the timer are each clocked by a pseudo-synchronous clock with a low frequency ratio (2 or 4), a fixed latency can be obtained, but at the expense of a change in the performance of the converter.

[0010] However, the maximum clock frequency of analog-to-digital converters is currently in the range of 75 MHz, while the maximum clock frequency of timers can range up to several hundred MHz.

[0011] Therefore, the trigger signal for the conversion emitted by the timer may occur at any time within the cycle of the clock signal clocking the converter.

[0012] Therefore, the waiting time between the trigger time point and the actual conversion start time point may vary.

[0013] Therefore, there is a need to provide a fixed waiting time between the triggering point in time and the actual start point in time of the conversion for a high frequency ratio between the clock frequency of the timer and the clock frequency of the converter, and without changing the performance of the converter. Summary of the invention

[0014] According to one aspect, there is provided an integrated circuit, such as a microcontroller, comprising:

[0015] at least one first analog-to-digital converter, the at least one first analog-to-digital converter being clockable by a converter clock signal,

[0016] a clock input terminal for receiving a first clock signal having a frequency that is a multiple of the frequency of the converter clock signal,

[0017] a timer that can be clocked at the rhythm of the first clock signal and has a timing period that is a multiple of the period of the converter clock signal, and

[0018] A processor is configured to control the at least one first converter based on a timing signal transmitted by the timer.

[0019] The processor has a first operating mode, in which the processor is also configured to clock the timer synchronously with the converter clock signal and transmit a first periodic conversion control signal of the converter based on the timing signal transmitted by the timer, wherein the first periodic conversion control signal has a period that is a multiple of the period of the converter clock signal and has a first constant phase difference with the converter clock signal.

[0020] Thus, even for high frequency ratios between the clock frequency of the timer and the clock frequency of the converter, a fixed (constant) and predictable waiting time is obtained between the triggering point in time and the actual conversion start point in time.

[0021] According to one embodiment, the integrated circuit further comprises a control input terminal for receiving a conversion control external signal (eg, one bit).

[0022] In the first operation mode, in response to the conversion control external signal, the processor is configured to:

[0023] Each time the timer reaches a selected timing value (eg, but not necessarily, a value corresponding to the value of the timing period), an edge, eg, a rising edge, of the first period switching control signal is generated.

[0024] The first converter is configured to periodically start switching after a fixed and constant first duration after an edge of the first periodic switching control signal.

[0025] The fixed duration may be equal to an integer number of periods of the converter clock signal. It may also be equal to a fraction of a period of the converter clock signal, or equal to x cycles or periods of the first clock signal plus y cycles or periods of the converter clock signal.

[0026] Advantageously, the processor is also configured to transmit the converter clock signal and a synchronization signal indicating a first time point (for example but not necessarily the start) of each cycle of the converter clock signal, the first time point being the same for each cycle, and in the presence of a conversion control external signal, the processor is also configured to delay the triggering of the timer until the next first time point (for example, the start of the next cycle of the converter clock signal).

[0027] According to one embodiment, the processor is configured to select the timing value from among several predefined timing values.

[0028] In the first operating mode, the timer may advantageously be reset synchronously with the converter clock signal.

[0029] According to one embodiment, the integrated circuit may include at least one second analog-to-digital converter, and may include more than two converters, which may be clocked by a converter clock signal, and the processor is configured in the first configuration to transmit a second periodic conversion control signal, the second periodic conversion control signal having a period that is a multiple of the period of the converter clock signal and having a second constant phase difference with the converter clock signal.

[0030] Therefore, the same clock signal clocks all converters.

[0031] This is particularly advantageous because aligning the clocks of all converters enables reduced disturbances to a common reference (eg a common reference voltage) of the converters.

[0032] In fact, the inventors have observed that when several converters present on the same integrated circuit operate asynchronously with respect to each other, they interfere with each other by injecting noise in the reference.

[0033] Furthermore, transmitting the same clock signal to all converters makes it possible to predict the point in time at which each converter injects noise, and thus control this interference in order to reduce it, which is not possible in prior art solutions.

[0034] Furthermore, for at least some of them, the constant phase differences (constant latencies) associated with the different converters may be the same or different.

[0035] Advantageously, the processor may have a second mode of operation in which it is arranged to clock the timer asynchronously to the converter clock signal.

[0036] Indeed, in some applications it may be useful not to have a constant wait time.

[0037] It is then particularly advantageous if the integrated circuit comprises a selection input for receiving a selection signal (eg one bit), so that the two operating modes of the processor are selectable via the selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other advantages and features of the invention will appear upon examination of the detailed description of non-limiting implementations and embodiments, and from the accompanying drawings, in which:

[0039] Figure 1 An embodiment integrated circuit is illustrated;

[0040] Figure 2 An embodiment processor is illustrated;

[0041] Figure 3 illustrates a timing diagram of a divider counter and a synchronization signal marking the start of a cycle of a converter clock signal herein;

[0042] Figure 4 A timing diagram illustrating a first time point of each cycle of a converter clock signal;

[0043] Figure 5 Pictured Figure 2 A timing diagram of the operating modes of the device;

[0044] Figure 6 illustrates a timing diagram of a second operating mode of the processor;

[0045] Figure 7 illustrates a timing diagram of a first operating mode of a processor;

[0046] Figure 8 A microcontroller including several analog-to-digital converters is illustrated; and

[0047] Fig. 9 The diagram shows Figure 5 The timing diagram of a signal similar to that of Figure 5 In comparison, the synchronization signal is advanced by one cycle of the first clock signal. DETAILED DESCRIPTION

[0048] exist Figure 1 In the present invention, the MC referred to refers to an integrated circuit forming, for example, a microcontroller in this document.

[0049] Very schematically, in this simplified embodiment, the microcontroller MC comprises a processor MTR, an exemplary structure and operation of which in cooperation with the timer CNT will be examined in more detail below.

[0050] The microcontroller MC herein also comprises an analog-to-digital converter ADC1 which may be clocked by a converter clock signal CLKADC.

[0051] The microcontroller MC comprises a clock input E1 to receive a first clock signal CLKT having a frequency comprised, for example, between 250 MHz and 400 MHz.

[0052] The frequency of the first clock signal is a multiple of the frequency of the converter clock signal CLKADC which may comprise, for example, between 10 MHz and 70 MHz.

[0053] The timer CNT may be clocked at the rhythm of the first clock signal CLKT and, as will be seen in more detail below, have a timing period that is a multiple of the period of the converter clock signal CLKADC.

[0054] The processor MTR in cooperation with the timer CNT is configured to control the converter ADC based on the timing signal delivered by the timer CNT.

[0055] As will be seen in more detail below, the processor has a first operating mode in which the processor is further configured to:

[0056] The timer CNT is clocked synchronously with the converter clock signal CLKADC, and

[0057] Based on a timing signal delivered by a timer, a first conversion control signal TRGS is delivered at a first output terminal BS1 , which signal TRGS is intended for the converter ADC1 .

[0058] As will be seen in more detail below, the processor MTR has a second operating mode in which it is configured to clock the timer CNT asynchronously to the converter clock signal CLKADC.

[0059] In this second operating mode, the processor MTR delivers a conversion control signal TRGA intended for the converter ADC1 on the second output terminal BS2 .

[0060] The processor MTR also delivers on a third output terminal BS3 a logic signal SYNC (for example one bit) intended for the converter ADC1 , so that the converter ADC1 can process the signal TRGS or the signal TRGA depending on the logic value of the bit SYNC.

[0061] The two operating modes are selectable by a select signal ADS received at the select input E3.

[0062] The microcontroller also comprises a control input E2 intended to receive an external signal SWCEN which, as will be seen in more detail below, will in fact be able to control the starting of the timer CNT with a certain delay.

[0063] However, as will be seen in more detail below, the activation of the timer will enable the activation of the conversion control of the converter ADC1 .

[0064] Therefore, the signal SWCEN may be referred to as a switching control external signal.

[0065] Finally, another input E4 is intended to receive a reset external signal of the counter CNT, this external signal being called SWCRST.

[0066] Now, more specifically referring to Figure 2 Detailed description of the drawings is given to illustrate an embodiment of a processor MTR, which is provided herein only as a non-limiting example.

[0067] The processor MTR comprises a first stage ET1 comprising a divider timer CLKDC clocked by a first clock signal CLKT and receiving a division factor DVF.

[0068] The frequency divider counter has an overflow bit ("overflow") which controls the two inputs 0 and 1 of the duplexer DPX1 via its logic value.

[0069] The output terminal of the duplexer DPX1 is connected to a first input terminal of an AND logic gate (referred to as PL1 ), a second input terminal of which is an inverting input terminal.

[0070] The output end of the duplexer DPX1 is also connected to the input end D of the D-type flip-flop BSC1 clocked by the first clock signal CLKT, and the output end Q of the D-type flip-flop BSC1 is connected to the inverting input end of the logic gate PL1, connected to the input end 0 of the duplexer DPX1, and connected to the input end 1 of the duplexer DPX1 after inversion.

[0071] The output terminal Q of the flip-flop BSC1 is also connected to the input terminal 0 of the duplexer DPX2 , and the input terminal 1 of the duplexer DPX2 receives the first clock signal CLKT.

[0072] The output end of the duplexer DPX2 forms an output terminal BS4 transmitting the converter clock signal CLKADC.

[0073] The output of the logic gate PL1 is connected to a first input of an OR logic gate PL2, a second input of which receives the frequency division factor DVF when the frequency division factor DVF is equal to 1 due to the bypass BYP.

[0074] A control input of the duplexer DPX2 is connected to a second input of the gate PL2.

[0075] The output of logic gate PL2 transmits the synchronization signal CADCS. Now, the reference Figure 3 and Figure 4 The role of the synchronization signal CADCS will be described in more detail.

[0076] exist Figure 3 In the example, it can be seen that the divider counter increases until it reaches the value of the division factor DVC, then decreases, and so on, each time accompanied by the emission of the overflow bit OVF.

[0077] When the overflow bit OVF is issued, there is a pulse of the synchronization signal CADCS, which pulse marks the beginning of a period of the converter clock signal CLKADC in this context.

[0078] exist Figure 4 , where the frequency division factor DVF is considered to be equal to 4, for example, it can be seen that the synchronization signal CADCS is synchronized with the first clock signal CLKT.

[0079] Furthermore, the synchronization signal CADCS indicates, for example, with its falling edge, a first time point INST of each period of the converter clock signal CLKADC.

[0080] In this example, the first time point INST is the beginning of each period of the converter clock signal CLKADC.

[0081] Furthermore, the rising edge of the synchronization signal CADCS before the falling edge indicating the time point INST provides an indication IND that the rising edge of the converter clock signal CLKADC will occur at the next rising edge of the first clock signal CLKT.

[0082] Now, refer again Figure 2 The description of the processor MTR continues.

[0083] It comprises a second stage ET2 comprising a duplexer DPX3 having its input 0 connected to a control input E2 receiving an external control signal SWCEN and its input 1 connected to an output Q of a flip-flop D (called BSC2).

[0084] An input terminal D of the flip-flop is connected to an output terminal of the duplexer DPX3.

[0085] The flip-flop BSC2 is clocked by the first clock signal CLKT.

[0086] An output Q of the flip-flop BSC2 is connected to an enable input EN (“enable”) of the timer CNT.

[0087] The duplexer DPX3 is controlled by the logic value at the output of an AND logic gate (referred to as PL3).

[0088] A first input terminal of the logic gate PL3 is connected to a selection input terminal E3 receiving a selection signal ADS.

[0089] The synchronization signal CADCS is transmitted to the other input terminal of the logic gate PL3 after being inverted.

[0090] The second stage ET2 also comprises an AND logic gate (referred to as PL4) having three input terminals.

[0091] A first input terminal of the gate PL4 receives the synchronization signal CADCS after being inverted.

[0092] A second input terminal of the gate PL4 receives the selection signal ADS, and a third input terminal of the gate PL4 is fed back to the output terminal Q of a flip-flop D (referred to as BSC3), which is also clocked by the first clock signal CLKT.

[0093] The output of the logic gate PL4 is connected to a first input of an OR logic gate (referred to as PL5).

[0094] A second input terminal of the logic gate PL5 is connected to the input terminal E4 to receive the signal SWCRST.

[0095] The output terminal of the logic gate PL5 is connected to the input terminal D of the flip-flop BSC3.

[0096] The output terminal Q of the flip-flop BSC3 is also connected to the reset input terminal RST of the timer CNT.

[0097] So far it has been noted that the logic value of the selection signal (bit) ADS defines the operating mode of the processor MTR.

[0098] Thus, for example, if the signal ADS has the logic value 1, the processor MTR is in its first operating mode, wherein the timer CNT is in particular synchronized with the converter clock signal CLKADC.

[0099] However, if the synchronization signal ADS has a logic 0, the processor MTR is in its second operating mode, in which it is configured to clock the timer CNT asynchronously to the converter clock signal CLKADC.

[0100] If the logic value of the selection signal ADS is equal to 1, the value of the bit SYNC transmitted by the output terminal BS3 is equal to 1, and if the logic value of the signal ADS is equal to 0, the value of the bit SYNC is equal to 0.

[0101] The processor MTR also comprises a third stage ET3 connected to the output of the timer CNT.

[0102] More specifically, in this embodiment, the stage ET3 includes a first register RG1 , a second register RG2 and a third register RG3 .

[0103] For example, the first register RG1 comprises the value of the timing period of the timer, for example the value 7 if the timer counts from 0 to 7.

[0104] The second register RG2 may contain another timing value of the timer CNT, for example, a value of 2, and the register RG3 may also contain another timing value of the timer, for example, a value of 5.

[0105] Then, the third stage ET3 comprises three comparators CMP1 , CMP2 and CMP3 .

[0106] The first comparator CMP1 is configured to compare the timing value of the timer CNT with the value of the first register RG1 and transmit an event pulse when the timing value of the timer CNT reaches the value 7.

[0107] The second comparator CMP2 is configured to compare the timing value of the timer CNT with the timing value contained in the register RG2 (herein value 2 ) and to transmit an event pulse whenever the timer CNT transmits the timing value 2 .

[0108] The third comparator CMP3 is configured to compare the timing value of the timer CNT with the timing value stored in the third register RG3 and output an event pulse whenever the timing value reaches the value stored in the register RG3 (the value 5 in this case).

[0109] The controller MCM (eg software or hardware) is intended to control a multiplexer MX whose three inputs are connected to the three outputs of the comparators CMP1 , CMP2 and CMP3 to select one among the three inputs to connect it to the output of the multiplexer MX.

[0110] The processor MTR also comprises a fourth stage ET4.

[0111] This stage ET4 comprises an AND logic gate (called PL6) having three inputs.

[0112] A first input terminal of the logic gate PL6 receives the selection signal ADS, which is also transmitted to the output terminal BS3 to become the bit SYNC.

[0113] A second input terminal of the logic gate PL6 receives the inverted synchronization signal CADCS.

[0114] The third input terminal of the logic gate PL6 is fed back to the output terminal Q of the D-type flip-flop BSC4.

[0115] The output of the logic gate PL6 is connected to a first input of an OR logic gate, called PL7, the second input of which is connected to the output of the multiplexer MX of the stage ET3.

[0116] The output of the logic gate PL7 is connected to the input D of a flip-flop BSC4 which is clocked by the first clock signal CLKT.

[0117] The fourth stage ET4 also comprises an AND logic gate called PL8 , a first input of which is connected to the output Q of the flip-flop BSC4 and a second input of which receives the selection signal ADS.

[0118] The output end of the logic gate PL8 forms the output terminal BS1 and transmits the switching control signal TRGS.

[0119] The fourth stage ET4 also comprises an AND logic gate called PL9, a first input of which is connected to the output Q of the flip-flop BSC4 and a second input of which receives the inverted selection signal ADS.

[0120] The output terminal of the logic gate PL9 provides a switching control signal TRGA.

[0121] Depending on the logic value of the bit SYNC, the analog-to-digital converter ADC1 will select the signal TRGS or the signal TRGA.

[0122] Now more specifically refer to Figure 5 , Figure 5 The diagram shows the timer and the converter clock signal CLKADC when the selection signal ADS has a logic value of 1 (the timer is synchronized with the converter clock signal CLKADC). Figure 2 Timing diagrams associated with the operating modes of the device.

[0123] Figure 5 The upper part of the timing diagram illustrates the first clock signal CLKT.

[0124] The synchronization signal CADCS indicates a first point in time INST, for example, when a falling edge occurs, which in this case is herein the start of each period of the converter clock signal CLKADC.

[0125] In this illustration, the period of the clock signal CLKADC is four times longer than the period of the first clock signal CLKT.

[0126] In addition, the activation signal EN of the timer CNT is delayed relative to the external control signal SWCEN to coincide with the first time point INST.

[0127] In other words, activation of EN of the timer starts at the beginning of a period of the converter clock signal CLKADC.

[0128] In this example, the period PER of the timer is equal to 8 and the timer counts from 0 to 7.

[0129] The timing period is a multiple of the period of the converter clock signal CLKADC.

[0130] In this exemplary implementation, it is assumed that the multiplexer MX has selected the output of the first comparator CMP1 connected to the first register RG1, which contains the value of the time period minus 1, which is the value 7 in this case.

[0131] Therefore, each time the counter reaches the value 7, the third stage ET3 issues an event pulse PERVT, and when the event pulse PERVT falls to 0, it generates a rising edge FM2 of the periodic switching control signal TRGS.

[0132] In this embodiment, when a period of the converter clock signal CLKADC is completed, a falling edge FM1 of the signal TRGS occurs, which triggers a conversion phase CONV1 of the converter ADC1.

[0133] This is repeated regularly at each event pulse PERVT to produce conversion cycles CONV2, CONV3, ...

[0134] It can be noted that the duration DD between the rising edge FM2 and the falling edge of the signal TRGS is constant and fixed.

[0135] Therefore, the switching control signal TRGS of the converter is a periodic signal having a period which is a multiple of the period of the converter clock signal (herein a period which is equal to the period of the converter clock signal) and having a constant phase difference with the converter clock signal.

[0136] This phase difference corresponds to the duration DD and it also represents the waiting time.

[0137] In the example that has just been described, the transition is triggered directly upon expiration of the duration DD.

[0138] Alternatively, instead of directly triggering the conversion, one or more trigger stages crossing the signal TRGS and clocked by the signal CLKADC may be set before triggering the conversion.

[0139] Therefore, by adding 2 flip-flop stages, two periods of the signal CLKADC are added to the duration DD before triggering the conversion, making the fixed and constant waiting time three periods of the signal CLKADC.

[0140] However, the phase difference between the signal TRGS and the signal CLKADC remains constant and equal to the duration DD, ie in this case the period of the signal CLKADC. Fig. 9 As can be seen in more detail, alternatively, the phase difference DD between the signal TRGS and the signal CLKADC can be made constant and equal to the period of the clock signal CLK (and therefore equal to a fraction of the period of the signal CLKADC), and the fixed waiting time can be made equal to DD but can be increased by, for example, a few periods of the signal CLKADC.

[0141] Now more specifically refer to Figure 6 and Figure 7 , to illustrate timing diagrams respectively associated with the second operating mode (ADS=0) and the first operating mode (ADS=1) of the processor MTR.

[0142] like Figure 7 As illustrated in and reviewed above, in a first operating mode of the processor (ADS=1), the timer CNT is clocked synchronously with the converter clock signal CLKADC.

[0143] Therefore, the activation signal EN is delayed in relation to the external control signal SWCEN to coincide with each cycle of the converter clock signal CLKADC.

[0144] Similarly, the active reset RST of the timer is also delayed relative to the reset request external signal SWCRST so as to also coincide with the start of a cycle of the converter clock signal CLKADC.

[0145] Furthermore, this is not the case in the second operating mode (ADS=0), in which the timer is clocked asynchronously with respect to the converter clock signal CLKADC.

[0146] In fact, it can be seen that the activation enable signal EN of the timer follows the signal SWCEN (after a period of the signal CLKT) and is not synchronized with the converter clock signal CLKADC.

[0147] The same applies to the reset active signal RST which follows the external signal SWCRST and is also not synchronized with the converter clock signal CLKADC.

[0148] Now more specifically refer to Figure 8 , Figure 8 The illustrated microcontroller MC comprises several analog-to-digital converters (for simplicity only two converters ADC1 and ADC2 are presented herein).

[0149] The converter clock signal CLKADC clocks the two converters ADC1 and ADC2 , so that the two converters ADC1 and ADC2 receive the same clock signal.

[0150] Furthermore, the multiplexer MX and the fourth stage ET4 are duplicated.

[0151] More specifically, the first multiplexer MX is connected to the comparators CMP1 - CMP3 , followed by a stage ET4 which transmits the signals TRGS1 , TRGA1 , SYNC1 to the first converter DC1 .

[0152] Furthermore, a second multiplexer MX is also connected at the outputs of the comparators CMP1 - CMP3 , followed by a further stage ET4 which transmits the signals TRGS2 , TRGA2 and SYNC2 to the second converter ADC2 .

[0153] Typically, because both converters will operate in either the first mode of operation or the second mode of operation, the signals SYNC1 and SYNC2 are identical.

[0154] Furthermore, the controller MCM will control the multiplexer MX in a first manner to transmit the signals TRGA1 and TRGS1 , while the controller will control the second multiplexer MX in a second manner to transmit the signals TRGS2 and TRGA2 .

[0155] Thus, for example, the first multiplexer MX may be controlled to select a first input terminal connected to the first register RG1, while the second multiplexer may be controlled to select another input terminal connected to any one of the registers RG2 and RG3, for example.

[0156] It will also be possible to copy timer CNT and stages ET3 and ET4.

[0157] The invention is not limited to the embodiments and implementations that have just been described, but encompasses all variants thereof.

[0158] Therefore, if Fig. 9 As shown in the timing diagram of Figure 5 Similar signals carry the same reference numerals, and Figure 5 Compared with the timing diagram of FIG. 1 , the synchronization signal CADCS is advanced by one cycle of the first clock signal CLKT.

[0159] The synchronization signal CADCS indicates the first time point INST when a falling edge occurs. The first time point INST is now located within each cycle of the converter clock signal CLKADC, and is no longer Figure 5 The same is located at the beginning of each cycle of the converter clock signal CLKADC.

[0160] exist Fig. 9 In this illustration, the period of the clock signal CLKADC is four times longer than the period of the first clock signal CLKT.

[0161] Furthermore, the activation signal EN of the timer CNT is also delayed here relative to the external control signal SWCEN to coincide with the first time point INST.

[0162] Also, in this example, the period PER of the timer is equal to 8, and the timer counts from 0 to 7.

[0163] In this exemplary implementation it is also assumed that the multiplexer MX has selected the output of the first comparator CMP1 which is connected to the first register RG1 which contains the value of the time period minus 1, in this case the value 7.

[0164] Therefore, each time the counter reaches the value 7, the third stage ET3 issues an event pulse PERVT, and when the event pulse PERVT falls to 0, it generates a rising edge FM2 of the periodic switching control signal TRGS.

[0165] In this embodiment, the signal TRGS is captured in a “flip-flop” type latch, thereby generating a periodic signal TRGSR having a rising edge FM2R at the end of a period of the first clock signal CLKT.

[0166] This results in the generation of a pulse signal TRGSP, whose falling edge FM2P in this context will directly trigger the conversion phase CONV1.

[0167] This is repeated regularly at each event pulse PERVT to produce conversion cycles CONV2, CONV3, ...

[0168] Hence, the fixed and constant phase difference DD between the signal TRGS and the signal CLKADC is here equal to the period of the clock signal CLKT and thus to a fraction of the converter clock signal CLKADC.

[0169] Here, too, the waiting time is equal to DD.

[0170] Here too, alternatively, instead of directly triggering the conversion, one or more trigger stages crossing the signal TRGS and clocked by the signal CLKADC may be provided before triggering the conversion.

[0171] Therefore, by adding 2 flip-flop stages, two periods of the signal CLKADC are added to the duration DD before triggering the conversion, making the fixed and constant waiting time the period of the clock signal CLKT plus two periods of the signal CLKADC.

[0172] However, the phase difference between the signal TRGS and the signal CLKADC remains constant and equal to the duration DD, ie in this context the period of the signal CLKT.

Claims

1. An integrated circuit, comprising: at least one first analog-to-digital converter of the integrated circuit, the at least one first analog-to-digital converter configured to be clocked by a converter clock signal having a first frequency and a first period; a clock input of the integrated circuit, the clock input configured to receive a first clock signal having a second frequency that is a multiple of the first frequency of the converter clock signal; a timer of the integrated circuit, the timer being configured to time at a cadence of the first clock signal and having a second period that is a multiple of the first period of the converter clock signal; and A processor of the integrated circuit, the processor being configured to control the at least one first analog-to-digital converter based on a timing signal transmitted by the timer, wherein the processor has a first operating mode, in which the processor is further configured to clock the timer synchronously with the converter clock signal, and based on the timing signal, transmit a first period conversion control signal to the at least one first analog-to-digital converter, the first period conversion control signal having a third period that is a multiple of the first period of the converter clock signal and having a first constant phase difference with the converter clock signal.

2. The integrated circuit of claim 1 , wherein: The integrated circuit further comprises a control input terminal, wherein the control input terminal is configured to receive a conversion control external signal; The processor is configured to generate an edge of the first periodic switching control signal each time the timer reaches a selected timing value in response to the switching control external signal in the first operating mode; and The at least one first analog-to-digital converter is configured to start converting periodically after a fixed and constant first period after an edge of the first period conversion control signal.

3. The integrated circuit according to claim 2, wherein: The processor is also configured to transmit the converter clock signal and a synchronization signal indicating a first time point of each cycle of the converter clock signal, wherein the first time point is the same for each cycle, and in the presence of the conversion control external signal, the processor is also configured to delay the triggering of the timer until the next first time point.

4. The integrated circuit according to claim 2, wherein: The processor is configured to select the selected timing value from among several predefined timing values.

5. The integrated circuit according to claim 2, wherein: The timer is reset in synchronization with the converter clock signal.

6. The integrated circuit of claim 1 , further comprising at least one second analog-to-digital converter clocked by the converter clock signal, and the processor is further configured to transmit a second periodic conversion control signal in the first operating mode, the second periodic conversion control signal having a fourth period that is a multiple of the first period of the converter clock signal and having a second constant phase difference with the converter clock signal.

7. The integrated circuit according to claim 1, wherein: The processor has a second mode of operation in which the processor is configured to clock the timer asynchronously with the converter clock signal.

8. The integrated circuit of claim 7, further comprising a selection input terminal configured to receive a selection signal, wherein The first operation mode and the second operation mode of the processor are selectable by the selection signal.

9. A microcontroller comprising: at least one first analog-to-digital converter configured to be clocked by a converter clock signal having a first frequency and a first period; a clock input configured to receive a first clock signal having a second frequency that is a multiple of the first frequency of the converter clock signal; a timer configured to time at a cadence of the first clock signal and having a second period that is a multiple of the first period of the converter clock signal; as well as A processor, the processor being configured to control the at least one first analog-to-digital converter based on a timing signal transmitted by the timer, wherein the processor has a first operating mode, in which the processor is further configured to clock the timer synchronously with the converter clock signal, and based on the timing signal, transmit a first period conversion control signal to the at least one first analog-to-digital converter, the first period conversion control signal having a third period that is a multiple of the first period of the converter clock signal and having a first constant phase difference with the converter clock signal.

10. The microcontroller according to claim 9, wherein: The microcontroller further comprises a control input terminal, wherein the control input terminal is configured to receive a conversion control external signal; The processor is configured to generate an edge of the first periodic switching control signal each time the timer reaches a selected timing value in response to the switching control external signal in the first operating mode; and The at least one first analog-to-digital converter is configured to periodically start converting after a fixed and constant first period after an edge of the first periodic conversion control signal.

11. The microcontroller of claim 9 , further comprising at least one second analog-to-digital converter clocked by the converter clock signal, and the processor is further configured to transmit a second periodic conversion control signal in the first operating mode, the second periodic conversion control signal having a fourth period that is a multiple of the first period of the converter clock signal and having a second constant phase difference with the converter clock signal.

12. The microcontroller according to claim 9, wherein: The processor has a second mode of operation in which the processor is configured to clock the timer asynchronously with the converter clock signal.

13. A method of operating an integrated circuit, the method comprising: clocking at least one first analog-to-digital converter via a converter clock signal having a first frequency and a first period; receiving, at a clock input, a first clock signal having a second frequency that is a multiple of the first frequency of the converter clock signal; clocking a timer at a cadence of the first clock signal and at a second period that is a multiple of the first period of the converter clock signal; controlling, by a processor, the at least one first analog-to-digital converter based on a timing signal transmitted by the timer; Operating, by the processor in a first operating mode, comprises: clocking the timer by the processor in synchronization with the converter clock signal; and A first period conversion control signal is transmitted by the processor to the at least one first analog-to-digital converter based on the timing signal, wherein the first period conversion control signal has a third period that is a multiple of the first period of the converter clock signal and has a first constant phase difference with the converter clock signal.

14. The method according to claim 13, wherein: Receiving a conversion control external signal through a control input terminal of the integrated circuit; generating, by the processor in the first operating mode in response to the switching control external signal, an edge of the first periodic switching control signal each time the timer reaches a selected timing value; and Conversion by the at least one first analog-to-digital converter is periodically started after a fixed and constant first period after an edge of the first periodic conversion control signal.

15. The method according to claim 14, further comprising, by the processor: transmitting the converter clock signal and a synchronization signal indicating a first time point of each cycle of the converter clock signal, the first time point being the same for each cycle; and When the conversion control external signal is present, triggering of the timer is delayed until a next first time point.

16. The method of claim 14, further comprising selecting, by the processor, the selected timing value from among several predefined timing values.

17. The method of claim 14, further comprising resetting the timer in synchronization with the converter clock signal.

18. The method according to claim 13, further comprising: clocking at least one second analog-to-digital converter by the converter clock signal; and A second periodic switching control signal is transmitted by the processor in the first operating mode, the second periodic switching control signal having a fourth period that is a multiple of the first period of the converter clock signal and having a second constant phase difference with the converter clock signal.

19. The method of claim 13, further comprising clocking, by the processor in a second mode of operation, the timer asynchronously with the converter clock signal.

20. The method of claim 19, further comprising receiving a selection signal at a selection input, the first operation mode and the second operation mode of the processor being selectable by the selection signal.

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