CMOS image data training method

Abstract

The invention relates to the technical field of CMOS image training, in particular to a CMOS image data training method, which comprises low-frequency CMOS image data training and high-frequency CMOS image data training. According to low-frequency CMOS image data training, a local clock in an imaging controller is used for carrying out double-edge sampling of a double-edge sampler, the sampling range of a sampling clock on serial image data is widened, and the optimal sampling position is obtained; different sampling point positions are set for the situation that the sampling area is discontinuous due to incomplete coverage of the sampling area in a low-frequency sampling state, so that the influence of temperature drift can be avoided; for high-frequency CMOS image data training, an accompanying clock with the same delay characteristic as serial image data in an imaging detector is used for sampling, and different sampling point positions are set for different sampling states, so that the stability and reliability of system work are ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of CMOS image training, and in particular relates to a training method for CMOS image data. Background Art

[0002] CMOS detectors usually output serial image data. In order to perform bit correction of serial image data and find the best sampling position, an input / output delay (IODELAY) is usually used. For FPGAs before the Xilinx 7 series, there are many reference clocks for IODELAY, and the lowest frequency is usually 200MHz. When the data rate of serial image data is higher than 400Mbps, the position detection of the transition edge of the serial image data must detect two transition edge positions; when the data rate of the serial image is lower than 200Mbps, the transition edge of the serial image data may not be detected.

[0003] For Xilinx7 series and higher-level FPGAs, the number of taps available for the internal IODELAY is reduced by half compared to FPGAs before the 7 series, that is, under the same frequency reference clock, the adjustable delay range using IODELAY is reduced by half. The area that can be continuously covered by the IDDR method will also have sampling blind areas. The signal that can detect two transition edges may only detect one transition edge, and the signal that can detect one transition edge may not detect the transition edge. In addition, in high-frequency applications, as the number of adjustable taps decreases, the area available for sampling decreases, so the sampling strategy needs to be readjusted according to the sampling situation.

[0004] The invention patent with publication number CN107659807A uses alternating training pulses in the word correction stage to obtain the correct training word only under the correct word data combination sequence, thus avoiding channel training failure caused by incorrect word combination.

[0005] The invention patent with publication number CN108810431A can achieve fine sampling within the entire data clock cycle by combining the counting position of high-frequency sampling with the fine phase adjustment of IODELAY, thereby obtaining a stable and reliable data sampling position.

[0006] The invention patent with publication number CN111586324A achieves a controllable delay of 1 / 2 pixel clock cycle by adding an optional shift register in front of the parallel p / 2-bit parallel data, which can overcome the training errors caused by the different relative positions of the serial data intercepted each time during the serial-to-parallel conversion process due to changes in ambient temperature.

[0007] The invention patent with publication number CN112118441A, by limiting the length of the position correction cycle, ensures that the setting delay of IODELAY has taken effect and the state has been stable each time the data stability test is performed; by limiting the number of IODELAY delays, it is ensured that even if only one jump edge position is detected, another virtual jump edge position can be formed; by setting the data stability and instability standards, the stability and reliability of the detection of the jump edge position are guaranteed; by limiting the training telemetry information, when a problem occurs in the training, the problematic link can be quickly located and the cause of the error can be obtained.

[0008] The invention patent with publication number CN113141476A uses dual-edge sampling of dual-edge sampler (IDDR) for low-frequency applications to broaden the sampling range of the sampling clock for serial image data and obtain the best sampling position, which is conducive to avoiding the influence of temperature drift. For high-frequency applications, ISERDES is used for serial-to-parallel conversion. The high-frequency clock only drives io resources and can be applied at a higher frequency. In the low-frequency parallel clock domain, a combination of parallel field data with different delay phases is used to overcome the half-word deviation of the parallel number caused by temperature drift, ensuring stable and reliable training.

[0009] The invention patent with publication number CN113179359A detects whether the channel training is successful based on the synchronization word during the channel training stage, the position of the last synchronization word and the number of relative delayed pixel clocks of the synchronization control signal; after the channel training is completed, a data valid signal is generated each time the last synchronization word is detected.

[0010] The invention patent with publication number CN115190258A combines four synchronization words before the detector outputs valid data, and performs word correction and channel correction at the same time to ensure that the image data received after the timing of each line is reset is the trained image data.

[0011] The invention patent with publication number CN117395490A is designed in three working modes according to the internal resources of the controller and the inter-frame redundancy time of the array detector.

[0012] The invention patent with publication number CN117171088A performs classification processing according to the number of stable areas and unstable areas sampled, and expands the sampling area by delaying the serial image data and the sampling clock respectively, obtains complete sampling information, and thus sets the best sampling position.

[0013] The invention patent with publication number CN115936147A avoids serial image data sampling errors caused by temperature changes by using a companion clock with low temperature drift between the serial data; monitors the ambient temperature changes through a temperature sensor, and then adjusts the phase of the timing reset signal according to the temperature changes, thereby ensuring that the sampling of the timing reset signal inside the detector will not be metastable.

[0014] The invention patent with publication number CN115242932A uses a single counter to generate write pulses of valid data and control the write operation address during the word correction stage. Each word correction pulse only acts before the counting signal of the valid write pulse is output, avoiding repeated writing of two sets of data and reducing resource utilization.

[0015] The above patents are designed for FPGAs before the Xilinx 7 series, and cannot cope with the situation where the number of IODELAY taps in Xilinx 7 series and higher-level FPGAs is halved. Summary of the invention

[0016] In view of this, the present invention aims to provide a CMOS image data training method to solve the problem of poor system stability and reliability when the number of taps used by IODELAY inside FPGAs of Xilinx7 series and higher levels is halved.

[0017] To achieve the above object, the technical solution created by the present invention is implemented as follows:

[0018] A CMOS image data training method includes low-frequency CMOS image data training and high-frequency CMOS image data training; wherein:

[0019] When training low-frequency CMOS image data, the sampling in the bit correction stage includes the following four states:

[0020] (1) When one unstable position is detected in the rising edge detectable area and one unstable position is detected in the falling edge detectable area, the sampling position is set at the midpoint between the maximum value of the unstable area in the rising edge detectable area and the minimum value of the unstable area in the falling edge detectable area;

[0021] (2) when an unstable position is detected in the rising edge detectable area, the sampling position is set at the midpoint between the maximum value of the unstable area in the rising edge detectable area and the maximum value of the unstable area in the falling edge detectable area;

[0022] (3) When an unstable position is detected in the falling edge detectable area, the sampling position is set at half of the minimum value of the unstable area in the falling edge detectable area;

[0023] (4) When no unstable position is detected in either the rising edge detectable area or the falling edge detectable area, the sampling position is set at the midpoint of the rising edge detectable area;

[0024] When training high-frequency CMOS image data, the sampling in the bit correction stage includes the following four states:

[0025] (1) When two unstable positions are detected, the sampling position is set at the midpoint between the maximum value of the first unstable region detected and the minimum value of the second unstable region detected;

[0026] (2) when only one unstable position is detected and the minimum value of the first unstable region detected is greater than or equal to half of the maximum delay value of the input-output delay device, the sampling position is set at half of the minimum value of the first unstable region detected;

[0027] (3) when only one unstable position is detected and the maximum value of the first unstable region detected is less than or equal to half of the maximum delay value of the input-output delayer, the sampling position is set at a position where half of the maximum delay value of the input-output delayer minus half of the maximum value of the first unstable region detected;

[0028] (4) When the unstable position is not detected, the sampling position is set to half of the maximum delay value of the input-output delay device.

[0029] Furthermore, low-frequency CMOS image data training is implemented based on a low-frequency CMOS image data training system. The low-frequency CMOS image data training system includes a differential-to-single-ended converter, an input-output delay device, a dual-edge sampler, a dual-channel multiplexer, a p-bit shift register, a data buffer and a controllable parallel shift register. The differential serial image data output by the imaging detector is converted into single-ended data by the differential-to-single-ended converter and then input into the input-output delay device for delay. The delayed single-ended data is transmitted to the dual-edge sampler. The dual-edge sampler outputs two channels of sampling data to the dual-channel multiplexer. The dual-channel multiplexer selects one channel of sampling data according to an external rising or falling edge control signal. The multiplexed selected sampling data is transmitted to the p-bit shift register. The p-bit shift register outputs p-bit parallel data and sends it to the data buffer. The data buffer outputs parallel data after crossing the clock domain and sends it to the controllable parallel shift register. The controllable parallel shift register outputs parallel data after channel training.

[0030] Furthermore, the sampling clock of the dual-edge sampler is a local clock inside the imaging controller, the frequency of which is the same as the frequency of the serial image data and is equal to or less than the minimum reference clock frequency of the input-output delayer.

[0031] Further, when the rising or falling edge control signal is 0, the corresponding detectable area is the rising edge detectable area, and when the rising or falling edge control signal is 1, the corresponding detectable area is the falling edge detectable area.

[0032] Furthermore, the number of taps of the input and output delays is 2 n , n is a positive integer greater than 1; then the number of taps available for the low-frequency CMOS image data training system is 2 n+1 , the level value of the rising or falling edge control signal is the highest bit of the tap number available in the low-frequency CMOS image data training system.

[0033] Furthermore, high-frequency CMOS image data training is implemented based on a high-frequency CMOS image data training system. The high-frequency CMOS image data training system includes a differential-to-single-ended converter, an input-output delay device, a dual-edge sampler, an m-bit shift register, a random access memory, five D flip-flops, two inverters and an m / 2-bit shift register. The differential serial image data output by the imaging detector is converted into single-ended data by the differential-to-single-ended converter and then delayed by the input-output delay device. The delayed single-ended data is sent to the dual-edge sampler and the accompanying clock inside the imaging detector for dual-edge sampling. After the dual-edge sampling, one signal passes through the first D flip-flop and outputs a rising edge sampling signal which is sent to the m-bit shift register. After the dual-edge sampling, the other signal passes through the second D flip-flop and outputs a falling edge sampling signal which is sent to the m-bit shift register. At the same time, the falling edge sampling signal passes through the third D flip-flop and outputs a falling edge sampling delay signal which is sent to the m-bit shift register. The shift data output by the m-bit shift register is sent to the random access memory across the clock domain after being latched by the fourth D flip-flop.

[0034] Furthermore, the frequency of the accompanying clock inside the imaging detector is half of the frequency of the serial image data, the even-numbered word correction level control signal enables the inversion operation at the rising edge of each pulse signal and is connected to the EN terminal of the first inverter, and the word correction level control signal is used to control the m-bit shift register to realize different parallel data combinations in the high level and low level stages respectively; the m / 2-bit shift register generates a parallel data loading enable signal, the data input terminal of the m / 2-bit shift register is connected to a low level, the parallel set terminal of the m / 2-bit shift register is connected to a high level, the parallel set control terminal of the m / 2-bit shift register is connected to the control signal of the second inverter, and the m / 2-bit shift register increases 1 bit of 0 each time it moves;

[0035] When the values ​​in the m / 2-bit shift register are all 0, the parallel data loading enable signal is set to a high level and is set to all 1s in the next clock; the word correction level control signal is connected to the first enable terminal of the fifth D flip-flop; the second enable terminal of the fifth D flip-flop is connected to the lower 3 bits of the m / 2-bit shift register, and the lower 3 bits are the second bit and the 0th bit inverted and ANDed with the first bit; the third enable terminal of the fifth D flip-flop is the inversion of the control signal passed through the second inverter, that is, when the word correction level control signal input by the fifth D flip-flop is a high level and the values ​​of the lower 3 bits of the m / 2-bit shift register are 010 and the control signal of the second inverter is a low level, the control signal of the second inverter outputs a high level pulse; the m / 2 shift register outputs a parallel data loading enable signal to control the fourth D flip-flop, and when the parallel data loading enable signal is a high level, the fourth D flip-flop is enabled to output.

[0036] Compared with the prior art, the invention can achieve the following beneficial effects:

[0037] 1. For low-frequency CMOS image data training, the local clock inside the imaging controller is used to perform dual-edge sampling of the dual-edge sampler, broaden the sampling range of the sampling clock for serial image data, obtain the best sampling position, and set different sampling point positions for the situation where the sampling area may be discontinuous due to incomplete coverage of the sampling area in the low-frequency sampling state, which is beneficial to avoid the influence of temperature drift.

[0038] 2. For high-frequency CMOS image data training, a companion clock with the same delay characteristics as the serial image data is used inside the imaging detector for sampling, and different sampling point positions are set for different sampling states to ensure stable and reliable operation of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0040] Figure 1 is a schematic diagram of the structure of a CMOS imaging system according to an embodiment of the present invention;

[0041] Figure 2 It is a structural schematic diagram of a low-frequency CMOS image data training system according to an embodiment of the invention;

[0042] Figure 3a-3d It is a schematic diagram of four detection states of a dual-edge sampler used in low-frequency CMOS image data training according to an embodiment of the invention;

[0043] Figure 4It is a structural schematic diagram of a high-frequency CMOS image data training system according to an embodiment of the invention;

[0044] Figure 5a-5d It is a schematic diagram of four detection states using a companion clock during low-frequency CMOS image data training according to an embodiment of the invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0046] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0047] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0048] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0049] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0050] The training method of CMOS image data provided by the embodiment of the present invention is applicable to CMOS imaging systems, such as Figure 1As shown, the structure of the CMOS imaging system includes a power conversion circuit, an imaging detector, a drive and control circuit, an imaging controller, a data transmission interface circuit, a memory and a control interface circuit; the power conversion circuit is used to provide power supply for the imaging detector, the drive and control circuit, the imaging controller, the data transmission interface circuit, the memory and the control interface circuit; the external input control communication signal is sent to the imaging controller through the control interface circuit, and the drive and control signals generated by the imaging controller are sent to the imaging detector after passing through the drive and control circuit; the memory is used to store the non-uniformity correction coefficient; the serial image data output by the imaging detector is processed by the imaging controller and output by the data transmission interface circuit.

[0051] In a specific embodiment, the power conversion circuit adopts the DCDC module of 510; the imaging detector uses the TDICMOS detector of Everbright Chenxin; the driving and control circuits are mainly based on the level conversion chip 164245; the imaging controller mainly adopts the FPGA and refresh chip of Shanghai Fudan Microelectronics; the data transmission interface circuit adopts the TLK2711 chip, and the control interface circuit mainly adopts 54AC14, DS26LV31 and DS26LV32; the memory adopts the MRAM of 3DPLUS.

[0052] The training method of CMOS image data includes low-frequency CMOS image data training and high-frequency CMOS image data training. The low-frequency CMOS image data training is implemented by using a low-frequency CMOS image data training system, and the low-frequency CMOS image data training system is based on a local clock inside an imaging controller. The high-frequency CMOS image data training is implemented by using a high-frequency CMOS image data training system, and the high-frequency CMOS image data training system is based on a companion clock inside an image detector having the same delay characteristics as serial image data.

[0053] like Figure 2As shown, the structure of the low-frequency CMOS image data training system includes a differential-to-single-ended converter IBUFDS, an input-output delay device IODELAY, a dual-edge sampler IDDR, a dual-channel multiplexer MUX, a p-bit shift register p bit shifter, a data buffer data_buffer and a controllable parallel shift register data_chan_shifter. The differential serial image data lvds_data_p and lvds_data_n output by the imaging detector are converted into single-ended data datain_buf by the differential-to-single-ended converter IBUFDS and then input to the input-output delay device IODELAY for delay. The delayed single-ended data datain_buf is transmitted to the dual-edge sampler IDDR. The dual-edge sampler IDDR outputs two sampling data dataout_iddr_ql and dataout_iddr_q2 to the dual-channel multiplexer MUX. The dual-channel multiplexer MUX selects one sampling data for output according to an external rising or falling edge control signal IDDR_sel. The multiplexed selected sampling data dataout_delay_q is transmitted to the p-bit shift register p bit shifter, p bit shift register p bit shifter outputs p bit parallel data data_t2 and sends it to data buffer data_buffer, data buffer data_buffer outputs parallel data data_out_bbuf after crossing the clock domain and sends it to controllable parallel shift register data_chan_shifter, controllable parallel shift register data_chan_shifter outputs parallel data after channel training.

[0054] The sampling clock serial_clk of the dual-edge sampler IDDR is a local clock inside the imaging controller, and its frequency is the same as that of the serial image data, and is equal to or less than the minimum reference clock frequency of the input-output delay IODELAY. The two sampling data output by the dual-edge sampler IDDR are not used at the same time, but according to the external rising or falling edge control signal IDDR_sel. When IDDR_sel is 0, the corresponding detection area is the rising edge detectable area, and when IDDR_sel is 1, the corresponding detection area is the falling edge detectable area.

[0055] The number of taps of the input and output delay IODELAY is 2 n , n is a positive integer greater than 1; then the number of taps available for the low-frequency CMOS image data training system is 2 n+1 , but there may be 2 n+1The tap regions are not continuous, but there may be discontinuous regions in the middle. The level value of the rising or falling edge control signal IDDR_sel is the highest bit of the tap number available for the low-frequency CMOS image data training system.

[0056] When training low-frequency CMOS image data, the sampling in the bit correction stage includes the following four states:

[0057] (1) When an unstable position is detected in the rising edge detectable area and the falling edge detectable area respectively (such as Figure 3a As shown), the sampling position is set to the midpoint between the "maximum value of the unstable area within the detectable area on the rising edge" and the "minimum value of the unstable area within the detectable area on the falling edge".

[0058] (2) When an unstable position is detected in the rising edge detectable area (such as Figure 3b As shown), the sampling position is set at the midpoint between "the maximum value of the unstable area within the detectable area on the rising edge" and "the maximum value of the unstable area within the detectable area on the falling edge".

[0059] (3) When an unstable position is detected in the falling edge detectable area (such as Figure 3c As shown), the sampling position is set at half of the minimum value of the unstable area within the falling edge detectable area.

[0060] (4) When no unstable position is detected in the rising edge detectable area and the falling edge detectable area (such as Figure 3d As shown), the sampling position is set at the midpoint of the rising edge detectable area, that is, when the rising or falling edge control signal IDDR_sel is set to a low level state (that is, IDDR_sel is 0), the position of the input-output delay device IODELAY is set to half of the available tap value.

[0061] like Figure 4As shown in the figure, the structure of the high-frequency CMOS image data training system includes a differential to single-ended converter IBUFDS, an input and output delay device IODELAY, a dual-edge sampler IDDR, and a m bit shift register, random access memory RAM, five D flip-flops D1-D5, the first inverter INV1, the second inverter INV2 and the m / 2bit shift register. The differential serial image data data_serailin_p and data_serailin_n output by the imaging detector are converted into single-ended data data_ser by the differential to single-ended converter IBUFDS, and then delayed by the input-output delay device IODELAY. The delayed signal data_ser_del is sent to the dual-edge sampler IDDR for dual-edge sampling with the accompanying clock clk_ser inside the imaging detector. The two signals after dual-edge sampling are respectively the signal iddr_q1 and the signal iddr_q2. The signal iddr_q1 passes through the first D flip-flop D1 and outputs the rising edge sampling signal data_1 which is sent to the mbit shift register. The signal iddr_q2 passes through the second D flip-flop D2 and outputs the falling edge sampling signal data_2 which is sent to the m bit shift register, and at the same time, the falling edge sampling signal data_2 outputs the falling edge sampling delay signal data_2_q after passing through the third D flip-flop D3 and is sent to the m bit shift register, and the m bit shift register outputs the shift data shift_data, which is latched by the fourth D flip-flop D4 and then output to the random access memory RAM across the clock domain.

[0062] The frequency of the accompanying clock clk_ser inside the imaging detector is half the frequency of the serial image data. The word correction level control signal bitsip_even corresponding to the even number enables the inversion operation at the rising edge of each pulse bitsip and is connected to the EN terminal of the first inverter INV1; bitsip_even controls the m bit shift register to realize different parallel data combinations in the high level and low level stages respectively. The m / 2bit shift register generates a parallel data loading enable signal load_parallel. The data input terminal D of the m / 2bit shift register is connected to the low level 0, the parallel set terminal s of the m / 2bit shift register is connected to the high level 1, and the parallel set control terminal l of the m / 2bit shift register is connected to the control signal bitslip_req. The m / 2bit shift register increases 1 bit of 0 each time it moves.

[0063] When the values ​​in the m / 2-bit shift register are all 0, the parallel data loading enable signal load_parallel is set to a high level, otherwise it is set to a low level, and is set to all 1s in the next clock; bitsip_even is connected to the enable terminal EN of the fifth D flip-flop D5; the second enable input terminal of the fifth D flip-flop D5 is connected to the lower 3 bits of the m / 2-bit shift register, and the lower 3 bits are the values ​​obtained by inverting the 2nd bit and the 0th bit and the 1st bit; the third enable input terminal of the fifth D flip-flop D5 is the inversion of the control signal bitslip_req through the second inverter INV2. That is, when bitsip_even of the input of the fifth D flip-flop D5 is a high level, and the value of the lower 3 bits of the m / 2-bit shift register is 010, and bitslip_req is a low level, bitslip_req outputs a high level pulse; that is, when bitsip_even is a high level, the m / 2-bit shift register directly skips the state where the lower 3 bits are 001. The “parallel data loading enable signal load_parallel” output by the m / 2 shift register is used to control the fourth D flip-flop D4. When load_parallel is at a high level, the output of the fourth D flip-flop D4 is enabled.

[0064] When training high-frequency CMOS image data, the sampling strategy is: the taps that need to be sampled are only the maximum number of taps that can be adjusted by IODELAY, and there is no need to increase the number of sampled taps, that is, the delay value of IODELAY can be traversed from 0 to the maximum value.

[0065] For the sampling of the bit correction stage, there are four states:

[0066] (1) When two unstable positions are detected (such as Figure 5a ), setting the sampling position at the midpoint between the "maximum value of the first unstable region detected" and the "minimum value of the second unstable region detected".

[0067] (2) When only one unstable position is detected and the "minimum value of the first unstable area detected" is greater than or equal to half of the maximum delay value of the input-output delay device IODELAY (e.g. Figure 5b , the unstable position is at the front), and the sampling position is set at half of the "minimum value of the first unstable area detected".

[0068] (3) When only one unstable position is detected and the "maximum value of the first unstable region detected" is less than or equal to half of the maximum delay value of the input-output delay device IODELAY (e.g. Figure 5c, the unstable position is at the back), and the sampling position is set at half of "half of the maximum delay value of the input-output delay device IODELAY" minus half of "the maximum value of the first unstable area detected".

[0069] (4) When no unstable position is detected (e.g. Figure 5d ), the sampling position is set at half of the maximum delay value of the input-output delay device IODELAY.

[0070] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the disclosure of the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0071] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A training method for CMOS image data, characterized in that: Including low-frequency CMOS image data training and high-frequency CMOS image data training; among them, When training low-frequency CMOS image data, the sampling in the bit correction stage includes the following four states: (1) When one unstable position is detected in the rising edge detectable area and one unstable position is detected in the falling edge detectable area, the sampling position is set at the midpoint between the maximum value of the unstable area in the rising edge detectable area and the minimum value of the unstable area in the falling edge detectable area; (2) when an unstable position is detected in the rising edge detectable area, the sampling position is set at the midpoint between the maximum value of the unstable area in the rising edge detectable area and the maximum value of the unstable area in the falling edge detectable area; (3) When an unstable position is detected in the falling edge detectable area, the sampling position is set at half of the minimum value of the unstable area in the falling edge detectable area; (4) When no unstable position is detected in either the rising edge detectable area or the falling edge detectable area, the sampling position is set at the midpoint of the rising edge detectable area; When training high-frequency CMOS image data, the sampling in the bit correction stage includes the following four states: (1) When two unstable positions are detected, the sampling position is set at the midpoint between the maximum value of the first unstable region detected and the minimum value of the second unstable region detected; (2) when only one unstable position is detected and the minimum value of the first unstable region detected is greater than or equal to half of the maximum delay value of the input-output delay device, the sampling position is set at half of the minimum value of the first unstable region detected; (3) when only one unstable position is detected and the maximum value of the first unstable region detected is less than or equal to half of the maximum delay value of the input-output delayer, the sampling position is set at a position where half of the maximum delay value of the input-output delayer minus half of the maximum value of the first unstable region detected; (4) When the unstable position is not detected, the sampling position is set to half of the maximum delay value of the input-output delay device.

2. The training method of CMOS image data according to claim 1, characterized in that: The low-frequency CMOS image data training is implemented based on the low-frequency CMOS image data training system. The low-frequency CMOS image data training system includes a differential-to-single-ended converter, an input-output delay device, a dual-edge sampler, a dual-channel multiplexer, a p-bit shift register, a data buffer and a controllable parallel shift register. The differential serial image data output by the imaging detector is converted into single-ended data by the differential-to-single-ended converter and then input into the input-output delay device for delay. The delayed single-ended data is transmitted to the dual-edge sampler. The dual-edge sampler outputs two channels of sampling data to the dual-channel multiplexer. The dual-channel multiplexer selects one channel of sampling data according to an external rising or falling edge control signal. The multiplexed selected sampling data is transmitted to the p-bit shift register. The p-bit shift register outputs p-bit parallel data and sends it to the data buffer. The data buffer outputs parallel data after crossing the clock domain and sends it to the controllable parallel shift register. The controllable parallel shift register outputs parallel data after channel training.

3. The training method of CMOS image data according to claim 2, characterized in that: The sampling clock of the dual-edge sampler is a local clock inside the imaging controller, the frequency of which is the same as the frequency of the serial image data and is equal to or less than the minimum reference clock frequency of the input and output delayer.

4. The training method of CMOS image data according to claim 3, characterized in that: When the rising or falling edge control signal is 0, the corresponding detectable area is the rising edge detectable area, and when the rising or falling edge control signal is 1, the corresponding detectable area is the falling edge detectable area.

5. The training method of CMOS image data according to claim 4, characterized in that: The number of taps of the input and output delays is 2 n , n is a positive integer greater than 1; then the number of taps available for the low-frequency CMOS image data training system is 2 n+1 , the level value of the rising or falling edge control signal is the highest bit of the tap number available in the low-frequency CMOS image data training system.

6. The training method of CMOS image data according to claim 1, characterized in that: The high-frequency CMOS image data training is implemented based on the high-frequency CMOS image data training system. The high-frequency CMOS image data training system includes a differential-to-single-ended converter, an input-output delay device, a dual-edge sampler, an m-bit shift register, a random access memory, five D flip-flops, two inverters and an m / 2-bit shift register. The differential serial image data output by the imaging detector is converted into single-ended data by the differential-to-single-ended converter and then delayed by the input-output delay device. The delayed single-ended data is sent to the dual-edge sampler and the accompanying clock inside the imaging detector for dual-edge sampling. After the dual-edge sampling, one signal passes through the first D flip-flop and outputs a rising edge sampling signal and is sent to the m-bit shift register. After the dual-edge sampling, the other signal passes through the second D flip-flop and outputs a falling edge sampling signal and is sent to the m-bit shift register. At the same time, the falling edge sampling signal passes through the third D flip-flop and outputs a falling edge sampling delay signal and is sent to the m-bit shift register. The shift data output by the m-bit shift register is sent to the random access memory across the clock domain after being latched by the fourth D flip-flop.

7. The training method of CMOS image data according to claim 6, characterized in that: The frequency of the accompanying clock inside the imaging detector is half of the frequency of the serial image data. The even-numbered word correction level control signal enables the inversion operation at the rising edge of each pulse signal and is connected to the EN terminal of the first inverter. The word correction level control signal is used to control the m-bit shift register to realize different parallel data combinations in the high level and low level stages respectively; the m / 2-bit shift register generates a parallel data loading enable signal, the data input terminal of the m / 2-bit shift register is connected to a low level, the parallel setting terminal of the m / 2-bit shift register is connected to a high level, the parallel setting control terminal of the m / 2-bit shift register is connected to the control signal of the second inverter, and the m / 2-bit shift register increases 1 bit of 0 each time it moves; When the values ​​in the m / 2-bit shift register are all 0, the parallel data loading enable signal is set to a high level and is set to all 1s in the next clock; the word correction level control signal is connected to the first enable terminal of the fifth D flip-flop; the second enable terminal of the fifth D flip-flop is connected to the lower 3 bits of the m / 2-bit shift register, and the lower 3 bits are the second bit and the 0th bit inverted and ANDed with the first bit; the third enable terminal of the fifth D flip-flop is the inversion of the control signal passed through the second inverter, that is, when the word correction level control signal input by the fifth D flip-flop is a high level and the values ​​of the lower 3 bits of the m / 2-bit shift register are 010 and the control signal of the second inverter is a low level, the control signal of the second inverter outputs a high level pulse; the m / 2 shift register outputs a parallel data loading enable signal to control the fourth D flip-flop, and when the parallel data loading enable signal is a high level, the fourth D flip-flop is enabled to output.

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