Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board comprises a first insulating layer; a first wiring layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and having a cavity; and a first barrier layer, at least a portion of which is disposed between the first insulating layer and the second insulating layer and is in contact with a side surface of at least a portion of the first wiring layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0080770 filed on June 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] As packages have been designed to have larger areas, a technology for embedding bridges in packages is being developed. In order to embed the bridge, a cavity may need to be formed in the substrate, and a laser may be used, and a metal barrier layer may be applied to control the depth of the cavity. However, in this case, due to the process of forming and removing the metal barrier layer, the cost may increase and the design freedom may be reduced. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board which can form a cavity in a board without applying a metal barrier layer.

[0005] An aspect of the present disclosure is to form a barrier layer instead of a metal barrier layer using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method, and to form a cavity in a plate using the barrier layer.

[0006] For example, according to one aspect of the present disclosure, a printed circuit board includes: a first insulating layer; a first wiring layer, which is arranged on the upper surface of the first insulating layer; a second insulating layer, which is arranged on the upper surface of the first insulating layer and has a cavity; and a first barrier layer, at least a portion of the first barrier layer is arranged between the first insulating layer and the second insulating layer and contacts with the side surface of at least a portion of the first wiring layer.

[0007] For example, according to another aspect of the present disclosure, a printed circuit board includes: a first insulating layer; a wiring layer, which is arranged on the upper surface of the first insulating layer; a second insulating layer, which is arranged on the upper surface of the first insulating layer and has a cavity; and a barrier layer, at least a portion of which is arranged between the first insulating layer and the second insulating layer, wherein the upper surface of the barrier layer and the upper surface of the wiring layer are substantially coplanar with each other, or the lower surface of the barrier layer and the lower surface of the wiring layer are substantially coplanar with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating an example embodiment of an electronic device system;

[0010] Figure 2 is a perspective view showing an example embodiment of an electronic device;

[0011] Figure 3 is a cross-sectional view illustrating an example embodiment of a printed circuit board;

[0012] Figure 4 is a cross-sectional view showing another example embodiment of a printed circuit board;

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E It shows the manufacturing Figure 3 The printed circuit board and Figure 4 A cross-sectional view of an example of a process for producing a printed circuit board in FIG.

[0014] Figure 6 is a cross-sectional view showing another example of a printed circuit board;

[0015] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F and Figure 7G It shows the manufacturing Figure 6 A cross-sectional view of an example of a process for producing a printed circuit board in FIG.

[0016] Figure 8 is a cross-sectional view showing another example of a printed circuit board;

[0017] Fig. 9 is a cross-sectional view showing another example of a printed circuit board;

[0018] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D It shows the manufacturing Figure 8 The printed circuit board and Fig. 9 A cross-sectional view of an example of a process for producing a printed circuit board in FIG.

[0019] Fig.11 is a cross-sectional view showing another example of a printed circuit board;

[0020] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D It shows the manufacturing Fig.11A cross-sectional view of an example of a process for producing a printed circuit board in FIG. 1 ; and

[0021] Fig.13 is a cross-sectional view showing another example of a printed circuit board. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0023] Electronic Devices

[0024] Figure 1 is a block diagram illustrating an example embodiment of an electronic device system.

[0025] Reference Figure 1 , a main board 1010 may be accommodated in the electronic device 1000. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the main board 1010. These components may be connected to other electronic components to be described below via various signal lines 1090.

[0026] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0027] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Environment (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), third generation mobile communication technology (3G) protocol, fourth generation mobile communication technology (4G) protocol and fifth generation mobile communication technology (5G) protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include a component compatible with or operating according to at least one of a plurality of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0028] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0029] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, the other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk) drive, a compact disk (CD) drive, and a digital versatile disk (DVD) drive, etc. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0030] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0031] Figure 2 is a perspective view illustrating an example embodiment of an electronic device.

[0032] Reference Figure 2 , the electronic device may be a smart phone 1100. The mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the components 1120 may be a chip-related component, for example, a component package 1121, but the example embodiments thereof are not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface mounted. Alternatively, the component package 1121 may be constructed in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is buried. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0033] Printed Circuit Board

[0034] Figure 3 is a cross-sectional view illustrating an example embodiment of a printed circuit board.

[0035] Referring to the drawings, according to an example, a printed circuit board 100A may include: a first insulating layer 111; a first wiring layer 121 disposed on an upper surface of the first insulating layer 111; a second insulating layer 112 disposed on an upper surface of the first insulating layer 111, covering at least a portion P1 of the first wiring layer 121 (also referred to as a "first portion P1") and having a cavity C; a first barrier layer 141, at least a portion of which is disposed between the first insulating layer 111 and the second insulating layer 112; a second wiring layer 122 disposed on a lower surface of the first insulating layer 111; a first via layer 131 penetrating at least a portion of the first insulating layer 111 and connecting at least a portion of the first wiring layer 121 to at least a portion of the second wiring layer 122; a third wiring layer 123 embedded in an upper side of the second insulating layer 112; and a second via layer 132 penetrating at least a portion of the second insulating layer 112 and connecting at least a portion of the first wiring layer 121 and at least a portion of the third wiring layer 123 to each other. Here, the first wiring layer 121 is arranged on the upper surface of the first insulating layer 111, including the case where the first wiring layer 121 protrudes from the upper surface of the first insulating layer 111 and including the case where the first wiring layer 121 is embedded in the upper surface (or upper side) of the first insulating layer 111, and similar expressions in the following text can be interpreted similarly.

[0036] The first barrier layer 141 may be formed using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method. For example, the first barrier layer 141 may include a thin insulating film having a thickness of less than 0.1 μm, preferably about 0.001 μm to 0.01 μm, and the insulating film may be an aluminum oxide film, but the embodiment is not limited thereto. In this case, after the first wiring layer 121 is formed on the second insulating layer 112, the first barrier layer 141 may be formed to cover the first wiring layer 121 located between the first insulating layer 111 and the second insulating layer 112. Therefore, the first barrier layer 141 may contact the side surface of at least a portion P1 of the first wiring layer 121, and may preferably cover at least a portion of each of the side surface and the lower surface of at least a portion P1 of the first wiring layer 121. In addition, at least a portion of the first barrier layer 141 may contact the side surface of the first via layer 131. In addition, the upper surface of the first barrier layer 141 and the upper surface of the first wiring layer 121 may be substantially coplanar with each other. In addition, the upper surface of the first insulating layer 111 and the upper surface of at least a portion P1 of the first wiring layer 121 may have a step difference. When the cavity C is formed in the second insulating layer 112, the first barrier layer 141 may be used as a stopper for spraying (e.g., sandblasting) processing, and may also be used as a stopper for laser (e.g., CO2 laser) processing. Therefore, it is possible to prevent footing from being formed on the bottom surface of the cavity C. In addition, the first barrier layer 141 may be used as an adhesive protection layer and may improve reliability.

[0037] The cavity C may penetrate the second insulating layer 112. At least a portion of the first barrier layer 141 may be disposed on the bottom surface of the cavity C. For example, the bottom surface of the cavity C may be formed by the first barrier layer 141. In addition, at least a portion of the upper surface of the first barrier layer 141 may be exposed from the first insulating layer 111 and the second insulating layer 112 through the cavity C. Various types of components may be disposed in the cavity C, and the components may be attached to the upper surface of the exposed first barrier layer 141. In this case, the components may be easily embedded and reliability may be improved. The cavity C may have a tapered shape in which the width of the upper side is greater than the width of the lower side, but embodiments thereof are not limited thereto.

[0038] The first insulating layer 111 and the second insulating layer 112 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber and a thermosetting resin or a thermoplastic resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto deposited film (ABF) or a prepreg (PPG), but its embodiments are not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material such as a photoimageable dielectric (PID). The boundaries between the first insulating layer 111 and the second insulating layer 112 may be distinguished from each other, but the first insulating layer 111 and the second insulating layer 112 may be integrated with each other to the extent that the boundaries are difficult to distinguish after curing. When the boundary between the first insulating layer 111 and the second insulating layer 112 cannot be distinguished, the boundary may be distinguished by drawing a conceptual line relative to the upper surface of at least a portion P1 of the first wiring layer 121 in consideration of the manufacturing process.

[0039] Each of the first wiring layer 121, the second wiring layer 122 and the third wiring layer 123 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal material may include copper (Cu), but its embodiment is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122 and the third wiring layer 123 may perform various functions according to the design. For example, each of the first wiring layer 121, the second wiring layer 122 and the third wiring layer 123 may include a signal pattern, a power pattern and a ground pattern. Each of these patterns may have various forms such as lines, planes and pads. Each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), or may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., a chemical copper plating layer), and if necessary, both the sputtering layer and the electroless plating layer may be included.

[0040] Each of the first via layer 131 and the second via layer 132 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and preferably, the metal material may include copper (Cu), but the embodiment is not limited thereto. Each of the first via layer 131 and the second via layer 132 may include a micropore. The micropore may be a filled via that fills the via hole, or may be a conformal via arranged along the wall surface of the via hole. The micropore may be arranged in a stacked type and / or staggered type. Depending on the design of the corresponding layer, the micropore may perform various functions. For example, the micropore may include a ground via, a power via, and a signal via. Each of the first via layer 131 and the second via layer 132 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the embodiment is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included. The first via layer 131 and the second via layer 132 may have a tapered shape tapering in the same direction. For example, each of the first via layer 131 and the second via layer 132 may have a tapered shape in which the width of the upper side is smaller than the width of the lower side in a cross section, but the embodiment is not limited thereto.

[0041] Figure 4 is a cross-sectional view illustrating another example embodiment of a printed circuit board.

[0042] Referring to the drawings, in a printed circuit board 100B according to another example, unlike the printed circuit board 100A according to the above-described example, a portion of the first barrier layer 141 exposed through the cavity C may be removed by plasma etching after the cavity C is formed. In this case, the cavity C may expose at least a portion of the upper surface of the first insulating layer 111, and at least a portion of the upper surface of the first insulating layer 111 exposed through the cavity C may have a step difference with an upper surface of at least a portion P1 of the first wiring layer 121. In addition, at least a portion of a side surface of the first barrier layer 141 may be exposed through the cavity C, and the side surface of the first barrier layer 141 exposed through the cavity C may have no step difference with a wall surface of the second insulating layer 112 exposed through the cavity C. For example, formation of a groove on the edge of the cavity C may be prevented.

[0043] The other descriptions are substantially the same as those described with respect to the printed circuit board 100A according to the above-described example, and therefore, a repeated description will not be provided.

[0044] FIG. 5A to FIG. 5E It shows the manufacturing Figure 3 The printed circuit board and Figure 4 A cross-sectional view of an example of a process for a printed circuit board.

[0045] Reference Figure 5A , first, a board may be formed in the form of an embedded trace substrate (ETS) using a carrier 210. For example, a third wiring layer 123 may be formed on the carrier 210 by a plating process, a second insulating layer 112 may be formed on the carrier 210 by a lamination process, a via hole may be processed in the second insulating layer 112 by laser processing, and a second via layer 132 may be formed in the via hole of the second insulating layer 112 by a plating process and a first wiring layer 121 may be formed on the second insulating layer 112. The carrier 210 may include a core layer and a copper (Cu) layer and a nickel (Ni) layer sequentially formed on both surfaces of the core layer, but embodiments thereof are not limited thereto. Thereafter, a first barrier layer 141 may be formed on the lower surface of the second insulating layer 112 to cover the first wiring layer 121 using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method.

[0046] Reference Figure 5B , the first insulating layer 111 may be formed on the lower surface of the second insulating layer 112 to cover the first barrier layer 141. The first insulating layer 111 may be formed by a lamination process. Thereafter, a via hole may be processed in the first insulating layer 111 by laser processing, and a first via layer 131 may be formed in the via hole of the first insulating layer 111 by a plating process and a second wiring layer 122 may be formed on the first insulating layer 111. When processing the via hole, at least a portion of the first barrier layer 141 may be removed to ensure interlayer connection.

[0047] Reference Figure 5C , the carrier 210 may be removed. For example, the carrier 210 and the laminate manufactured using the carrier 210 may be separated, for example, the core layer and the copper (Cu) layer of the carrier 210 may be separated from each other, and then the copper (Cu) layer and the nickel (Ni) layer of the carrier 210 remaining in the laminate may be sequentially removed by etching.

[0048] Reference Figure 5D , the cavity C penetrating the second insulating layer 112 may be formed by CO2 laser processing using the first barrier layer 141 as a barrier. Through a series of processes, the printed circuit board 100A according to the above example may be manufactured.

[0049] Reference Figure 5E At least a portion of the first barrier layer 141 exposed through the cavity C may be removed by plasma etching. Through a series of processes, the printed circuit board 100B according to the above-described another example may be manufactured.

[0050] The other descriptions may be substantially the same as those described with respect to the above-mentioned printed circuit boards 100A and 100B, and thus, a repeated description will not be provided.

[0051] Figure 6 is a cross-sectional view showing another example of a printed circuit board.

[0052] Referring to the drawings, in a printed circuit board 100C according to another example, unlike the printed circuit board 100B according to the above-mentioned other example, at least another portion P2 (also referred to as "second portion P2") of the first wiring layer 121 may be exposed through the cavity C. In this case, the component disposed in the cavity C may be connected to at least another portion P2 of the first wiring layer 121, and may be electrically connected to the circuit in the board. Therefore, various electrical connection paths may be ensured. To this end, after forming the first barrier layer 141 only in a partial region between the first insulating layer 111 and the second insulating layer 112, only the region of the first barrier layer 141 exposed through the cavity C may be selectively removed by plasma etching. Therefore, the upper surface of at least a portion P1 of the first wiring layer 121 and the upper surface of at least another portion P2 of the first wiring layer 121 may have a step difference from each other.

[0053] The other descriptions may be substantially the same as those described with respect to the above-mentioned printed circuit boards 100A and 100B, and thus, a repeated description will not be provided.

[0054] FIG. 7A to FIG. 7G It shows the manufacturing Figure 6 A cross-sectional view of an example of a process for a printed circuit board.

[0055] Reference Fig. 7A, a third wiring layer 123 may be formed on the carrier 210 by a plating process, a second insulating layer 112 may be formed on the carrier 210 by a lamination process, and a via hole V may be processed in the second insulating layer 112 by laser processing. The carrier 210 may include a core layer and a copper (Cu) layer and a nickel (Ni) layer sequentially formed on both surfaces of the core layer, but the embodiment is not limited thereto.

[0056] Reference Figure 7B and Figure 7C First, a pattern region for forming the first barrier layer 141 may be formed by a mask 220, and the first barrier layer 141 may be formed in the mask pattern region on the lower surface of the second insulating layer 112 using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method. Thereafter, the mask 220 may be removed. The mask 220 may be a metal mask and may be removed by separation, but the embodiment is not limited thereto.

[0057] Reference Fig.7D , a second via layer 132 may be formed in the via hole V of the second insulating layer 112 by a plating process, and a first wiring layer 121 may be formed on the second insulating layer 112 and the first barrier layer 141. In this case, an upper surface of at least a portion P1 of the first wiring layer 121 and an upper surface of at least another portion P2 of the first wiring layer 121 may have a step difference. Thereafter, a first insulating layer 111 may be formed on the lower surface of the second insulating layer 112 to cover the first barrier layer 141. The first insulating layer 111 may be formed by a lamination process. Thereafter, a via hole may be processed in the first insulating layer 111 by laser processing, and a first via layer 131 may be formed in the via hole of the first insulating layer 111 by a plating process, and a second wiring layer 122 may be formed on the first insulating layer 111.

[0058] Reference Fig. 7E , the carrier 210 may be removed. For example, the carrier 210 and the laminate manufactured using the carrier 210 may be separated, for example, the core layer and the copper (Cu) layer of the carrier 210 may be separated from each other, and then the copper (Cu) layer and the nickel (Ni) layer of the carrier 210 remaining in the laminate may be sequentially removed by etching.

[0059] Reference Figure 7F and Figure 7G , a cavity C penetrating the second insulating layer 112 may be formed by CO2 laser processing using the first barrier layer 141 as a barrier. Thereafter, a portion of the first barrier layer 141 exposed by the cavity C may be removed by plasma etching. Through a series of processes, the printed circuit board 100C according to the above another example may be manufactured.

[0060] The other descriptions may be substantially the same as those described with respect to the above-mentioned printed circuit boards 100A, 100B, and 100C, and thus, a repeated description will not be provided.

[0061] Figure 8 is a cross-sectional view showing another example of a printed circuit board.

[0062] Referring to the drawings, a printed circuit board 100D according to another example may include: a first insulating layer 111; a first wiring layer 121 disposed on an upper surface of the first insulating layer 111; a second wiring layer 122 disposed on a lower surface of the first insulating layer 111; a first via layer 131 penetrating the first insulating layer 111 and connecting at least a portion of the first wiring layer 121 to at least a portion of the second wiring layer 122; one or more second insulating layers 112-1 and 112-2 disposed on an upper surface of the first insulating layer 111 and having a cavity C; a first barrier layer 141, at least a portion of which is disposed between the first insulating layer 111 and the second insulating layers 112-1 and 112-2; and one or more third insulating layers 113-1 and 113-2 disposed on the first insulating layer 111. 11; a second barrier layer 142, at least a portion of which is disposed between the first insulating layer 111 and the third insulating layers 113-1 and 113-2; one or more third wiring layers 123-1 and 123-2, respectively disposed on the upper surfaces of the one or more second insulating layers 112-1 and 112-2; one or more second via layers 132-1, 132-2, respectively penetrating the one or more second insulating layers 112-1 and 112-2; one or more fourth wiring layers 124-1 and 124-2, respectively disposed on the lower surfaces of the one or more third insulating layers 113-1 and 113-2; and one or more third via layers 133-1 and 133-2, respectively penetrating the one or more third insulating layers 113-1 and 113-2. The one or more second via layers 132-1 and 132-2 can connect the first wiring layer 121 to the one or more third wiring layers 123-1 and 123-2. One or more third via layers 133-1 and 133-2 can connect the second wiring layer 122 to one or more fourth wiring layers 124-1 and 124-2. In addition, the second via layer can also be used for connection between adjacent third wiring layers, and the third via layer can also be used for connection between adjacent fourth wiring layers.

[0063] The first barrier layer 141 and the second barrier layer 142 may be formed using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method. For example, each of the first barrier layer 141 and the second barrier layer 142 may include a thin insulating film having a thickness of less than 0.1 μm, preferably about 0.001 μm to 0.01 μm, and the insulating film may be an aluminum oxide film, but the embodiment is not limited thereto. In this case, after forming the first wiring layer 121 and the second wiring layer 122, the first barrier layer 141 and the second barrier layer 142 may be formed to cover the first wiring layer 121 and the second wiring layer 122, respectively. Therefore, the first barrier layer 141 may be in contact with the side surface of at least a portion P1 of the first wiring layer 121, and may preferably cover at least a portion of each of the side surface and the upper surface of at least a portion P1 of the first wiring layer 121. In addition, the second barrier layer 142 may be in contact with the side surface of at least a portion of the second wiring layer 122, and may preferably cover at least a portion of each of the side surface and the lower surface of at least a portion of the second wiring layer 122. In addition, at least a portion of the first barrier layer 141 may be in contact with the side surface of the second via layer 132-1, and at least a portion of the second barrier layer 142 may be in contact with the side surface of the third via layer 133-1. In addition, the lower surface of the first barrier layer 141 and the lower surface of the first wiring layer 121 may be substantially coplanar with each other. In addition, the upper surface of the second barrier layer 142 and the upper surface of the second wiring layer 122 may be substantially coplanar with each other. When the cavity C is formed in one or more second insulating layers 112-1 and 112-2, the first barrier layer 141 may be used as a stopper for spraying (e.g., sandblasting) processing, and may also be used as a stopper for laser (e.g., CO2 laser) processing. Therefore, the formation of a footing on the bottom surface of the cavity C can be prevented. In addition, the first barrier layer 141 and the second barrier layer 142 may be adhesion protection layers, and reliability may be improved.

[0064] The cavity C may penetrate one or more second insulating layers 112-1 and 112-2. At least a portion of the first barrier layer 141 may be disposed on the bottom surface of the cavity C. For example, the bottom surface of the cavity C may be formed by the first barrier layer 141. In addition, at least a portion of the upper surface of the first barrier layer 141 may be exposed from the first insulating layer 111 and the second insulating layers 112-1 and 112-2 through the cavity C. Various types of components may be disposed in the cavity C, and the components may be attached to the upper surface of the exposed first barrier layer 141. In this case, the components may be easily embedded and reliability may be improved. The cavity C may have a tapered shape in which the width of the upper side is greater than the width of the lower side, but embodiments thereof are not limited thereto.

[0065] Each of the first insulating layer 111, the second insulating layers 112-1 and 112-2, and the third insulating layers 113-1 and 113-2 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber and a thermosetting resin or a thermoplastic resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto deposited film (ABF) or a prepreg (PPG), but embodiments thereof are not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material such as a photoimageable dielectric (PID). Preferably, the first insulating layer 111 may be a core layer, and one or more second insulating layers 112-1 and 112-2 and one or more third insulating layers 113-1 and 113-2 may be a deposited layer. Therefore, the first insulating layer 111 may have a thickness greater than that of one or more insulating layers of the second insulating layers 112-1 and 112-2 and the third insulating layers 113-1 and 113-2, and may have a modulus greater than that of one or more insulating layers of the second insulating layers 112-1 and 112-2 and the third insulating layers 113-1 and 113-2. The plurality of second insulating layers 112-1 and 112-2 may have distinguishable boundaries, or may be integrated with each other without boundaries after curing. The plurality of third insulating layers 113-1 and 113-2 may have distinguishable boundaries, or may be integrated with each other without boundaries after curing. When the boundaries between the plurality of second insulating layers 112-1 and 112-2 cannot be distinguished, in consideration of the manufacturing process, a conceptual line may be drawn relative to the lower surface of each of the third wiring layers 123-1 and 123-2 so that the boundaries can be distinguished. When the boundary between the plurality of third insulating layers 113 - 1 and 113 - 2 cannot be distinguished, a conceptual line may be drawn with respect to the upper surface of each of the fourth wiring layers 124 - 1 and 124 - 2 in consideration of a manufacturing process so that the boundary can be distinguished.

[0066] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123-1 and 123-2, and the fourth wiring layer 124-1 and 124-2 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal material may include copper (Cu), but its embodiment is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123-1 and 123-2, and the fourth wiring layer 124-1 and 124-2 may perform various functions according to the design. For example, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123-1 and 123-2, and the fourth wiring layer 124-1 and 124-2 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various shapes, such as a linear, a planar, or a pad shape. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layers 123-1 and 123-2, and the fourth wiring layers 124-1 and 124-2 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), or may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), or may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., a chemical copper plating layer), and if necessary, both the sputtering layer and the electroless plating layer may be included.

[0067] Each of the first via layer 131, the second via layer 132-1 and 132-2, and the third via layer 133-1 and 133-2 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Preferably, the metal material may include copper (Cu), but its embodiment is not limited thereto. The first via layer 131 may include a through-hole. The through-hole may be a filled via that fills the via hole, or may be a conformal via arranged along the wall surface of the via hole. Optionally, the through-hole may be a conformal type, and a plug may be included therein. Each of the one or more second via layers 132-1 and 132-2 and the one or more third via layers 133-1 and 133-2 may include a microhole. The microhole may be a filled via that fills the via hole, or may be a conformal via arranged along the wall surface of the via hole. The microhole may be arranged in a stacked type and / or staggered type. Through-holes and micro-holes may perform various functions according to the design of the corresponding layers. For example, through-holes and micro-holes may include ground vias, power vias, and signal vias. Each of the first via layer 131, the second via layers 132-1 and 132-2, and the third via layers 133-1 and 133-2 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but its embodiments are not limited thereto. A sputtering layer may be formed instead of an electroless plating layer, and if necessary, both a sputtering layer and an electroless plating layer may be included. The first via layer 131 may have an hourglass shape or a cylindrical shape, and one or more second via layers 132-1 and 132-2 and one or more third via layers 133-1 and 133-2 may have a shape that tapers in opposite directions.

[0068] Fig. 9 is a cross-sectional view showing another example of a printed circuit board.

[0069] Referring to the drawings, in a printed circuit board 100E according to another example, unlike the printed circuit board 100D according to the above-described another example, a portion of the first barrier layer 141 exposed through the cavity C may be removed by plasma etching after the cavity C is formed. In this case, the cavity C may expose at least a portion of the upper surface of the first insulating layer 111. In addition, at least a portion of the side surface of the first barrier layer 141 may be exposed through the cavity C, and the side surface of the first barrier layer 141 exposed through the cavity C may have no step difference from the wall surfaces of the second insulating layers 112-1 and 112-2 exposed through the cavity C. For example, a groove may be prevented from being formed on the edge of the cavity C.

[0070] The other descriptions may be substantially the same as those described with respect to the printed circuit board 100D according to the above-described other example, and thus, a repeated description will not be provided.

[0071] FIG. 10A to FIG. 10D It shows the manufacturing Figure 8 The printed circuit board and Fig. 9 A cross-sectional view of an example of a process for a printed circuit board.

[0072] Reference Fig. 10A First, a through hole may be formed in the first insulating layer 111 by laser processing, and the first wiring layer 121 and the second wiring layer 122 and the first via layer 131 may be formed by a plating process. Thereafter, a first barrier layer 141 and a second barrier layer 142 may be formed on the upper surface and the lower surface of the first insulating layer 111 by a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method to cover the first wiring layer 121 and the second wiring layer 122, respectively.

[0073] Reference Fig. 10B Using a deposition process, one or more second insulating layers 112-1 and 112-2, one or more third insulating layers 113-1 and 113-2, one or more third wiring layers 123-1 and 123-2, one or more fourth wiring layers 124-1 and 124-2, one or more second via layers 132-1 and 132-2, and one or more third via layers 133-1 and 133-2 can be formed on the first insulating layer 111.

[0074] Reference Fig. 10C , a cavity C penetrating the one or more second insulating layers 112 - 1 and 112 - 2 may be formed by CO 2 laser processing using the first barrier layer 141 as a barrier. Through a series of processes, the printed circuit board 100D according to the above another example may be manufactured.

[0075] Reference Fig. 10D , the portion of the first barrier layer 141 exposed through the cavity C may be removed by plasma etching. Through a series of processes, the printed circuit board 100E according to the above-mentioned another example may be manufactured.

[0076] The other descriptions may be substantially the same as those described above with respect to the printed circuit boards 100D and 100E, and thus, a repeated description will not be provided.

[0077] Fig.11 is a cross-sectional view showing another example of a printed circuit board.

[0078] Referring to the drawings, in a printed circuit board 100F according to another example, unlike the printed circuit board 100E according to the above-described another example, at least another portion P2 of the first wiring layer 121 may be exposed through the cavity C. In this case, a component disposed in the cavity C may be connected to at least another portion P2 of the first wiring layer 121 and may be electrically connected to a circuit in the board. Therefore, various electrical connection paths may be ensured.

[0079] The other descriptions may be substantially the same as those described above with respect to the printed circuit boards 100D and 100E, and thus, a repeated description will not be provided.

[0080] FIG. 12A to FIG. 12D It shows the manufacturing Fig.11 A cross-sectional view of an example of a process for a printed circuit board.

[0081] Reference Fig. 12A First, a through hole may be formed in the first insulating layer 111 by laser processing, and the first wiring layer 121 and the second wiring layer 122 and the first via layer 131 may be formed by a plating process. Thereafter, a first barrier layer 141 and a second barrier layer 142 may be formed on the upper surface and the lower surface of the first insulating layer 111 by a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method to cover the first wiring layer 121 and the second wiring layer 122, respectively.

[0082] Reference Fig. 12B Using a deposition process, one or more second insulating layers 112-1 and 112-2, one or more third insulating layers 113-1 and 113-2, one or more third wiring layers 123-1 and 123-2, one or more fourth wiring layers 124-1 and 124-2, one or more second via layers 132-1 and 132-2, and one or more third via layers 133-1 and 133-2 can be formed on the first insulating layer 111.

[0083] Reference Fig. 12C and Fig.12D First, a cavity C penetrating the one or more second insulating layers 112-1 and 112-2 may be formed by CO2 laser processing using the first barrier layer 141 as a barrier. Thereafter, a portion of the first barrier layer 141 exposed through the cavity C may be removed by plasma etching. Through a series of processes, the printed circuit board 100F according to the above another example may be manufactured.

[0084] The other descriptions may be substantially the same as those described with respect to the above-mentioned printed circuit boards 100D, 100E, and 100F, and thus, a repeated description will not be provided.

[0085] Fig.13 is a cross-sectional view showing another example of a printed circuit board.

[0086] With reference to the accompanying drawings, a printed circuit board 100G according to another example may have a package form. For example, a first component 191 may be embedded in a package board 150, and a second component 192 and a third component 193 may be mounted on the package board 150, respectively. The package board 150 may include one of the above-mentioned printed circuit boards 100A, 100B, 100C, 100D, 100E, and 100F. For example, the structure of a printed circuit board 100D according to another example may be partially modified and may be applied as a package board 150 of a printed circuit board 100G according to another example. In the package board 150, for other components, components of a typical package board commonly used in the relevant technical field may be applied. The first component 191 may be a bridge for interconnecting the second component 192 and the third component 193, and the bridge may be an organic bridge and / or a silicon bridge. The second component 192 and the third component 193 may be semiconductor chips of the same type or semiconductor chips of different types. If necessary, a barrier layer may be formed on a layer at a height other than the position of the barrier to form a cavity. For example, the barrier layer may be formed on the entire layer on which the wiring layer is formed, but the embodiment is not limited thereto. In the package board 150, the insulating layers may have a distinguishable boundary or an indistinguishable boundary. When the boundary is indistinguishable, the boundary may be distinguished by drawing a conceptual line relative to the upper surface or the lower surface of the wiring layer at each height in consideration of the manufacturing process.

[0087] The other descriptions may be substantially the same as those described in the above-mentioned printed circuit boards 100A, 100B, 100C, 100D, 100E, and 100F, and thus, a repeated description will not be provided.

[0088] According to the aforementioned example embodiments, by omitting a process for removing the metal barrier layer, the process may be simplified, and thus, a printed circuit board with reduced cost may be provided.

[0089] Furthermore, it is possible to provide a printed circuit board capable of reducing the possibility of grooves being formed at the edge of a cavity when the metal barrier layer is removed.

[0090] Furthermore, a printed circuit board can be provided which can increase the degree of freedom in designing a cavity.

[0091] In example embodiments, the cross-sectional shape may refer to the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. In addition, the plane shape may refer to the plane shape when the object is cut horizontally, or the plane shape when the object is viewed from the top or bottom.

[0092] In the present disclosure, example embodiments may include process errors, positional deviations, and measurement errors that occur in the process. For example, a configuration in which components are substantially the same may include examples in which the components are exactly the same, and examples in which there may be slight differences due to process errors. In addition, a configuration in which elements are substantially unchanged may include examples in which elements are completely unchanged, and examples in which there may be slight differences due to process errors.

[0093] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection", for example, connection through an adhesive layer or the like. In addition, the term "electrical connection" may include both a case where an element is "physically connected" and a case where an element is "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of rights of example embodiments.

[0094] In the example embodiments, the term "example embodiment" may not refer to the same example embodiment, and may be provided to describe and emphasize different unique features of each example embodiment. The example embodiments suggested above may be implemented, and the possibility of combining with features of other example embodiments is not excluded. For example, even if a feature described in one example embodiment is not described in another example embodiment, the description may be understood to be related to another example embodiment unless otherwise stated.

[0095] An expression used in the singular includes an expression in the plural unless it has an apparently different meaning in the context.

[0096] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; A first wiring layer is arranged on the upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and having a cavity; as well as A first barrier layer, at least a portion of which is disposed between the first insulating layer and the second insulating layer and in contact with a side surface of at least a portion of the first wiring layer.

2. The printed circuit board according to claim 1, wherein: The first barrier layer includes an aluminum oxide film with a thickness less than 0.1 μm.

3. The printed circuit board according to claim 1, wherein: The first barrier layer covers at least a portion of a side surface of the at least a portion of the first wiring layer and at least a portion of an upper surface or a lower surface of the at least a portion of the first wiring layer.

4. The printed circuit board according to claim 1, wherein: At least a portion of the first barrier layer is disposed on a bottom surface of the cavity.

5. The printed circuit board according to claim 4, further comprising: a first component disposed in the cavity and attached to at least a portion of the first barrier layer disposed on the bottom surface of the cavity; as well as A second component and a third component are disposed on an upper surface of the second insulating layer and connected to the first component.

6. The printed circuit board according to claim 1, wherein The cavity exposes at least a portion of the upper surface of the first insulating layer.

7. The printed circuit board according to claim 6, wherein: At least a portion of a side surface of the first barrier layer is exposed through the cavity.

8. The printed circuit board according to claim 7, wherein: A side surface of the first barrier layer exposed through the cavity and a wall surface of the second insulating layer exposed through the cavity have no step difference.

9. The printed circuit board according to claim 6, wherein: At least another portion of the first wiring layer is exposed through the cavity.

10. The printed circuit board according to claim 1, further comprising: a second wiring layer, disposed on a lower surface of the first insulating layer; a first via layer that penetrates at least a portion of the first insulating layer and connects at least a portion of the first wiring layer to at least a portion of the second wiring layer; a third wiring layer embedded in the upper side of the second insulating layer; as well as a second via layer penetrating at least a portion of the second insulating layer and connecting at least a portion of the first wiring layer to at least a portion of the third wiring layer, Wherein, the first wiring layer is embedded in the upper surface of the first insulating layer.

11. The printed circuit board according to claim 10, wherein: The first barrier layer covers at least a portion of each of a side surface and a lower surface of the at least a portion of the first wiring layer, and at least a portion of the first barrier layer is in contact with a side surface of the first via layer.

12. The printed circuit board according to claim 10, in, The cavity exposes at least a portion of the upper surface of the first insulating layer, and The at least a portion of the first barrier layer contacts a side surface of a first portion of the first wiring layer, and an upper surface of the first insulating layer exposed through the cavity has a step difference with an upper surface of the first portion of the first wiring layer.

13. The printed circuit board according to claim 12, in, A second portion of the first wiring layer is exposed through the cavity, and The upper surface of the first portion of the first wiring layer and the upper surface of the second portion of the first wiring layer have a step difference.

14. The printed circuit board according to claim 10, in, The first wiring layer is embedded from the upper surface of the first insulating layer, and the second wiring layer protrudes from the lower surface of the first insulating layer.

15. The printed circuit board according to claim 1, further comprising: a second wiring layer, disposed on a lower surface of the first insulating layer; a first via layer that penetrates at least a portion of the first insulating layer and connects at least a portion of the first wiring layer to at least a portion of the second wiring layer; a third wiring layer, disposed on an upper surface of the second insulating layer; a second via layer penetrating at least a portion of the second insulating layer and connecting at least a portion of the first wiring layer to at least a portion of the third wiring layer; a third insulating layer, disposed on a lower surface of the first insulating layer; A fourth wiring layer, disposed on the lower surface of the third insulating layer; a third via layer penetrating at least a portion of the third insulating layer and connecting at least a portion of the second wiring layer to at least a portion of the fourth wiring layer; as well as A second barrier layer, at least a portion of which is provided between the first insulating layer and the third insulating layer and is in contact with a side surface of at least a portion of the second wiring layer.

16. The printed circuit board according to claim 15, in, The first barrier layer covers at least a portion of each of the side surface and the upper surface of the at least a portion of the first wiring layer, and at least a portion of the first barrier layer is in contact with a side surface of the second via layer, and The second barrier layer covers at least a portion of each of a side surface and a lower surface of at least a portion of the second wiring layer, and at least a portion of the second barrier layer contacts a side surface of the third via layer.

17. The printed circuit board according to claim 15, in, The first wiring layer and the second wiring layer protrude from the upper surface and the lower surface of the first insulating layer, respectively.

18. A printed circuit board, comprising: a first insulating layer; A wiring layer, disposed on an upper surface of the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer and having a cavity; as well as a barrier layer, at least a portion of which is disposed between the first insulating layer and the second insulating layer, The upper surface of the barrier layer and the upper surface of the wiring layer are substantially coplanar with each other, or the lower surface of the barrier layer and the lower surface of the wiring layer are substantially coplanar with each other.

19. The printed circuit board according to claim 18, wherein The barrier layer includes an aluminum oxide film with a thickness less than 0.1 μm.

20. The printed circuit board according to claim 18, wherein At least a portion of the barrier layer is disposed on a bottom surface of the cavity.

Images