Inductance detection for power converter

Abstract

In an example, a circuit (100) includes an emulation current generator (114) configured to provide an emulation current signal in response to a charging current and a discharging current. The emulated current signal may represent an emulated current through the output inductor (E1). A comparator (116) is configured to provide a comparator signal in response to the emulated current signal and a sensed current signal representative of a measure of current through the output inductor (E1). An inductor code counter (134) is configured to adjust an inductor code count value in response to the comparator signal. A slope of the emulated current signal may be adjusted in response to the inductor code count value.

Description

Technical Field

[0001] This specification relates to inductance sensing for power converters. Background Art

[0002] Power converter circuits, such as switching power supplies, can use external inductors with a wide inductance range. For some power converters, a priori knowledge of the output inductance is used to configure the power converter for operation. However, in some cases, such a priori knowledge is not readily available. Summary of the invention

[0003] In the described example, a circuit includes an emulated current generator having a current output. A current sensor has a sensor output. A comparator has a first comparator input and a second comparator input and a comparator output. The first comparator input is coupled to the current output, and the second comparator input is coupled to the sensor output. An inductor code counter has a counter input and a counter output, wherein the counter input is coupled to the comparator output. A charging circuit has an input coupled to the comparator output, and the charging circuit includes a variable slope resistor, and the variable slope resistor has a trimming input coupled to the counter output. A discharge circuit has an input coupled to the comparator output, and the discharge circuit includes a variable valley resistor, and the variable valley resistor has a trimming input coupled to the counter output.

[0004] In another described example, a circuit includes an emulated current generator configured to provide an emulated current signal in response to a charging current and a discharging current for charging or discharging a timing capacitor, respectively. The emulated current signal may represent an emulated current through an output inductor. A comparator is configured to provide a comparator signal in response to the emulated current signal and a sensed current signal, wherein the comparator signal represents a measure of the current through the output inductor. An inductor code counter is configured to adjust an inductor code count value in response to the comparator signal. The slope of the emulated current signal may be adjusted in response to the inductor code count value.

[0005] In a further described example, a system includes an inductor and a power stage. The power stage includes a high-side switch and a low-side switch. The high-side switch is coupled between a voltage supply terminal and a switch output terminal. The low-side switch is coupled between the switch output terminal and a ground terminal, and the inductor is coupled to the switch output terminal. A driver is configured to control the high-side switch and the low-side switch in response to a pulse width modulation control signal. The power stage also includes an inductance detection circuit system, the inductance detection circuit system includes an emulated current generator, and the emulated current generator has a current output. A comparator has a first comparator input and a second comparator input and a comparator output. The first comparator input is coupled to the current output, and the second comparator input is configured to receive a measure of the current through the inductor. An inductor code counter has a counter input and a counter output, wherein the counter input is coupled to the comparator output. A charging circuit has an input coupled to the comparator output, and the charging circuit includes a variable slope resistor, and the variable slope resistor has a trimming input coupled to the counter output. A discharge circuit has an input coupled to the comparator output and includes a variable valley resistor having a trim input coupled to the counter output. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of an example power converter including inductance detection circuitry.

[0007] Figure 2 is a schematic diagram of an example inductance sensing circuit.

[0008] Figure 3 is a schematic diagram of another example inductance detection circuit.

[0009] Figure 4 It is shown Figure 3 Timing diagram of the inductance detection circuit.

[0010] Figure 5 is a block diagram of an example power converter system.

[0011] Figure 6 is a flow chart illustrating an example method for detecting inductance.

[0012] Figure 7 is a graph of current versus time showing how the simulated current and the sensed current change during inductance detection.

[0013] Figure 8 is a graph of simulation results showing emulated current and sensed current in an example power stage during inductance detection.

[0014] Fig. 9is another graph showing simulation results of the inductor code adjusted with the emulated current and the sensed current during inductance detection. DETAILED DESCRIPTION

[0015] Examples relate to systems and methods for detecting the output inductance of a power converter. For example, the inductance detection circuit system includes a counter configured to provide an inductor code that is adjusted (e.g., incremented or decremented) in response to a comparison between an emulated current and a sensed inductor current. An emulated current can be generated in response to a charging current and a discharging current to simulate an inductor current. The circuit system is configured to provide a charging current and a discharging current in response to the inductor code, whereby the charging current and the discharging current provide a measure of the output inductance. Therefore, by changing the inductor code in response to the comparison over multiple cycles, the inductor code can converge to a value representing an estimated value of the output inductance, and the resulting inductor code value can be stored (e.g., in a memory).

[0016] In an example, the inductance detection circuitry may include additional detection circuitry that uses the stored inductor code value. The additional detection circuitry is configured to fine-tune the charging current and the discharging current in response to a comparison between the simulated inductor current and the sensed inductor current during another set of cycles. The inductance detection circuitry may be added to the power stage circuitry to configure the power stage circuitry to implement self-regulating (e.g., adaptive) output inductance detection. Thus, the methods described herein may provide a practical production solution that enables the power stage circuitry to detect output inductance without adding dedicated pins on an integrated circuit die containing the corresponding power stage.

[0017] Figure 1A block diagram of a power converter circuit 100 is depicted, the power converter circuit being configured to provide a regulated output voltage at an output 102. For example, depending on the application needs, the power converter circuit 100 can be implemented as a buck regulator, a boost regulator, a buck-boost regulator, or other regulator. The power converter circuit 100 also includes an output stage 104 having an output 106 (e.g., a switching output terminal). For example, the output stage 104 is configured to provide a switching voltage VSW at the output 106 in response to a drive signal provided by a driver circuit system 108. The control circuit 110 can be configured to implement one or more control loops to generate a control signal (e.g., a pulse width modulation signal) to command an increase or decrease in the output power (e.g., voltage and / or current) at the output 102. The power converter circuit 100 also includes an inductance detection circuit system 112, which is configured to detect the inductance of an output inductor L1 coupled between the outputs 102 and 106. For example, inductor L1 is external to an integrated circuit (IC) that includes power converter circuit 100. An output capacitor COUT may also be coupled between output 102 and a ground terminal.

[0018] As used herein, the term "circuit" may include a collection of active and / or passive elements that perform a circuit function, such as an analog circuit or a control circuit. Additionally or alternatively, for example, the term "circuit" may include an IC in which all and / or some circuit elements are fabricated on a common substrate (e.g., a semiconductor substrate, such as a die or chip). Thus, the power converter circuit 100 or its components may be implemented on a semiconductor substrate to provide an IC. In one example, a power stage circuit including an output stage 104, a driver 108, a control circuit 110, and an inductance detection circuit system 112 is implemented in a discrete IC, and the inductor L1 is coupled to the output 106 of the IC. In another example, the control circuit 110 is implemented as an IC separate from the IC that implements the power stage circuit.

[0019] The inductance detection circuit system 112 includes an emulated current generator 114. The emulated current generator 114 has current inputs 117 and 118 and a current output 120. The current output 120 is coupled to the input of the comparator 116. The current input 117 is coupled to a charge current generator circuit (also referred to as a charging circuit) 122, and the current input 118 is coupled to a discharge current generator circuit (also referred to as a discharge circuit) 124. The emulated current generator 114 is configured to provide an emulated current signal I_EM at the current output 120 in response to the charge current I_CHARGE and the discharge current I_DISCHARGE generated by the respective charge circuit 122 and discharge circuit 124. The emulated current signal I_EM represents the simulated current through the output inductor. As described herein, the inductance detection circuit system 112 is configured to implement a self-regulated closed-loop control to adjust the slope of the emulated current I_EM to approximate or match the actual current through the inductor L1.

[0020] For example, the current sensor 126 has a sensor input 128 and a sensor output 130. The sensor input 128 is coupled to the output stage 104, and the sensor output is coupled to another input of the comparator 116. The current sensor 126 is configured to provide a sensed current signal I_SNS representing a measure of the current through the inductor L1 at the sensor output 130. In an example where the output stage includes a high-side switch and a low-side switch, the current sensor 126 can be coupled across the low-side output switch and configured to provide the signal I_SNS as a measure of the inductor current when the low-side switch is turned on and the high-side switch is turned off.

[0021] The comparator 116 has a comparator output 132 and is configured to provide a comparator output signal in response to the emulation current signal I_EM and the sense current signal I_SNS. In an example, the comparator is implemented as a transconductance amplifier configured to generate a current error signal at 132 in response to the emulation current signal I_EM and the sense current signal I_SNS (e.g., where I_EM and I_SNS are currents). In another example, for example, when I_EM and I_SNS are provided as voltage signals, the comparator 116 can be implemented as a voltage comparator.

[0022] The inductance detection circuit system 112 further includes an inductor code counter 134 having a counter input 136 and a counter output 138. The counter input 136 is coupled to the comparator output 132, and the counter output 138 is coupled to corresponding inputs of the charging circuit 122 and the discharging circuit 124. The inductor code counter 134 is configured to adjust a count value representing an inductor code and provide the count value at the counter output 138 in response to a comparator signal received at 136. Thus, the counter 134 can increment or decrement the counter value each cycle depending on the relative values of I_EM and I_SNS. For example, if I_EM > I_SNS, the counter 134 can increment the count value (e.g., count up), and if I_EM < I_SNS, the counter can decrement the count value (e.g., count down).

[0023] As described herein, the charging circuit 122 and the discharging circuit 124 are configured to adjust the slopes of the corresponding charging current I_CHARGE and discharging current I_DISCHARGE in response to the count value at 138 (e.g., the inductor code count value). For example, the charging current generator circuit 122 includes a variable resistor 140, shown as a slope resistor RSLP, which is coupled in the path of the charging current I_CHARGE being generated. The discharging current generator circuit 124 also includes a variable resistor 142, shown as a valley resistor RVAL, which is coupled in the path of the discharging current I_DISCHARGE being generated. The variable resistors 140 and 142 have corresponding inputs coupled to the counter output 138 to receive the inductor code count value and trim the corresponding resistances accordingly. In one instance, in response to the inductor code count value at 138, each of the variable resistors 140 and 142 is trimmed to the same resistance. In another instance, in response to the inductor code count value at 138, the variable resistors 140 and 142 are trimmed to different resistances. Thus, the charging circuit 122 and the discharging circuit 124 are configured to adjust the corresponding charging current I_CHARGE and discharging current I_DISCHARGE over a plurality of clock cycles (e.g., PWM cycles) in response to the inductor code count value that sets the resistances of the variable resistors 140 and 142 at 138. Since the corresponding charging and discharging currents are adjusted, the slope of the simulated current I_EM (e.g., the rising slope and falling slope of I_EM) is adjusted to converge and match the slope of the sensed inductor current I_SNS.

[0024] In some examples, the controller 144 is configured to control the inductance detection circuit system 112 during a power-on phase of the power converter 100 for a plurality of cycles. For example, the controller 144 has a power input 146 and a control output 148. The power input 146 is coupled to a power supply terminal to receive a supply voltage, shown as VDD. The control output 148 can be coupled to an enable input of the inductor code counter 134. For example, in response to power-on, the voltage VDD is supplied at 146, and the controller 144 is configured to provide an enable signal at 148 to enable (e.g., activate) the inductor code counter 134. The controller 144 can be configured to enable the inductor code counter 134 for a plurality of cycles of the PWM or clock signal. Alternatively, the controller 144 can be configured to enable the inductor code counter 134 for a plurality of cycles (e.g., a variable number) in response to detecting jitter between the I_EM and I_SNS signals. For example, the controller 144 may detect jitter in response to the difference between I_EM and I_SNS still being less than the jitter threshold. Other methods may be used to detect sufficient convergence between the I_EM and I_SNS signals. The controller 144 may also be configured to store (e.g., latch) the inductor code count value provided by the inductor code counter 134 in a memory (e.g., a register). Thus, the values ​​of the variable resistors 140 and 142 may be fixed in response to the stored inductor code count value.

[0025] In response to the controller 144 detecting the convergence of the I_EM and I_SNS signals, the controller 144 can be configured to disable the inductor code counter 134 and enable the charge counter 150 and the discharge counter 152 of the corresponding charging circuit 122 and the discharge circuit 124, for example, as described herein. For example, the controller 144 also has a control output 153, which is coupled to enable the inputs of the corresponding charge counter 150 and the discharge counter 152. The charge counter 150 has an input 154 coupled to the comparator output 132. The discharge counter 152 also has an input 156 coupled to the comparator output 132. When activated in response to the enable signal provided by the controller 144 at 153, the charge counter 150 and the discharge counter 152 are configured to adjust the corresponding count value in response to the comparator output at 132. For example, the charging circuit 122 includes a trimming circuit that is configured to set a corresponding offset voltage for tuning the charging current I_CHARGE in response to the charge counter output. The discharge circuit 124 may also include a trimming circuit configured to set a corresponding offset voltage for tuning the discharge current I_DISCHARGE in response to the discharge counter output. While the variable resistors 140 and 142 are fixed in response to the stored inductor code value, the controller 144 is configured to fine-tune the charge current and discharge current over a plurality of cycles, which may be fixed or variable. As a result of such fine-tuning, the inductance detection circuit system 112 may be used to provide an emulated current I_EM to match the actual inductor current I_SNS to a desired accuracy.

[0026] Figure 2 Another example of a power converter 200 implementing an inductance detection circuit is shown. The inductance detection circuit 202 may be used to implement Figure 1 The inductance detection circuit 112. Therefore, Figure 2 The description also refers to Figure 1 For example, circuit 200 includes an output stage 104 having a switching output (eg, a switching node or terminal) 106 to which inductor L1 may be coupled. Figure 2 In the example of , the output stage 104 includes field effect transistors (FETs) Q1 and Q2 coupled in series between a supply voltage VIN and ground, where Q1 is a high-side FET and Q2 is a low-side FET. The source of Q1 is coupled to the drain of Q2, which is also coupled to the switch output 106. The driver circuit ( Figure 2 Not shown, but see Figure 1 The driver 108 is configured to supply gate drive signals to control Q1 and Q2 and provide a switching voltage VSW at 106.

[0027] The current sensor 126 has an input coupled across Q2 and is configured to provide a sensor current signal at 130 representing a measure of the current through the inductor L1. For example, the current sensor 126 is configured to measure the low-side output waveform of the low-side FET Q2, such as the voltage across the low-side FET when Q2 is turned on (e.g., the drain-to-source voltage). The current sensor 126 can be configured to provide a sensor signal I_SNS as a current signal proportional to the inductor output current through L1. Alternatively, the sensor signal I_SNS can be a voltage representing the inductor output current.

[0028] In addition, as referenced Figure 1 As depicted, circuit 200 also includes an inductor code counter 134 having a counter input 136 and a counter output 138. Counter input 136 is coupled to comparator output 132, and counter output 138 is coupled to respective inputs of charging circuit 122 and discharging circuit 124. Inductor code counter 134 is configured to adjust a count value representing an inductor code and to provide a count value at counter output 138 in response to a comparator signal at 136.

[0029] Figure 2 Also shown is a controller 144 having a control output 148 coupled to an enable input of the inductor code counter 134. The controller 144 is configured to provide a control signal at 148 to enable / disable the inductor code counter 134 during the inductance detection phase of the circuit 200, and to provide another control signal at 153 to enable / disable the charge counter 150 and the discharge counter 152. For example, the controller 144 is configured to enable the inductor code counter to perform coarse inductance detection during a first number of cycles of the inductance detection phase, while disabling the charge counter 150 and the discharge counter 152. The controller is further configured to enable the charge counter 150 and the discharge counter 152 to perform finer inductance detection during a subsequent second number of cycles in the inductance detection phase, while disabling the inductor code counter 134.

[0030] exist Figure 2In the example of , the emulation current generator 114 includes a charging current source 204 and a discharging current source 206. The charging current source 204 is coupled between a voltage supply terminal (shown as a supply voltage VDD) and a switch (shown as FET Q3). The charging current source 204 is configured to provide a charging current I_CHARGE (or a current proportional to I_CHARGE) in response to the current generated by the charging current generator circuit 122. The discharging current source 206 is coupled between Q3 and a ground terminal. The discharging current source 206 is configured to provide a discharging current I_DISCHARGE (or a current proportional to I_DISCHARGE) in response to the current generated by the discharging current generator circuit 124.

[0031] The switch voltage (VSW) detector 208 has an output coupled to the control input (e.g., gate) of Q3. In an example, the VSW detector 208 has an input coupled to the switch output 106 and is configured to control Q3 in response to the switch voltage VSW at 106. The VSW detector can be implemented as a driver circuit, for example, configured to supply a drive signal to turn on Q3 to conduct when the switch voltage VSW is greater than a threshold voltage, and to turn off Q3 when VSW is less than a threshold voltage. The timing capacitor C1 is coupled in parallel with the discharge current source 206 between the source and ground of Q3. Therefore, the emulation current generator 114 is configured to provide an emulation current I_EM in response to the charging current I_CHARGE and the discharge current I_DISCHARGE and based on the operation of Q3 (in response to VSW). For example, I_CHARGE and I_DISCHARGE are configured to charge and discharge the timing capacitor C1 to generate the emulation current I_EM, respectively.

[0032] Figure 2 Also shown are example charge current generator circuits 122 and discharge current generator circuits 124. For example, the charge current generator circuit 122 includes a resistor divider circuit of resistors R1 and R2 coupled between an input voltage (VIN) terminal and ground. The output of the voltage divider (e.g., a node between R1 and R2) is coupled to a non-inverting input 210 of an amplifier 212. The voltage divider circuit can be configured to provide a fractional portion of VIN to the amplifier input 210 based on a ratio of resistors R1 and R2. The amplifier 212 has an output coupled to the gate of a transistor, shown as FET Q4. A compensation capacitor C2 is coupled between the amplifier output and ground.

[0033] A charging current source 214 is coupled between the voltage supply terminal VDD and Q4. A variable resistor 140 having a resistance shown as RSLP is coupled between the source of Q4 and ground. As described herein, resistor 140 has a trim input coupled to the output 138 of the inductor code counter 134. A variable input offset voltage source 216 is coupled between the source of Q4 and the inverting input 218 of amplifier 212. Figure 2 As shown, offset voltage source 216 has an input coupled to output 219 of charge counter 150 and is configured to provide an input offset voltage VIO1 to input 218 in response to the charge count value at 219 .

[0034] In an example, amplifier 212 is implemented as an operational transconductance amplifier, which is configured to provide an output current in response to the difference between the voltages at the corresponding inputs 210 and 218. Therefore, amplifier 212 can provide an output current at 210 and 218 as a linear function of the differential input voltage. Charging current source 214 is configured to provide current I_CHARGE, and the I_CHARGE value changes in response to the resistance RSLP of variable resistor 140. Therefore, by adjusting the resistance RSLP of variable resistor 140 over multiple cycles, charging current I_CHARGE changes accordingly. Charging current generator circuit 122 can be configured to provide charging current I_CHARGE to emulation current generator 114, for example, through one or more current mirrors (not shown). In another example, charging current generator circuit 122 can be used to implement charging current source 204 in emulation current generator 114.

[0035] The discharge current generator circuit 124 can be configured to generate a discharge current I_DISCHARGE in a manner similar to the charge current generator circuit 122. The discharge circuit 124 includes a resistor divider circuit of resistors R3 and R4 coupled between an output (VOUT) terminal and ground. The output of the voltage divider (e.g., a node between R3 and R4) is coupled to a non-inverting input 220 of an amplifier 222. The voltage divider circuit can be configured to provide a fractional portion of the output voltage VOUT to the amplifier input 220 according to the ratio of resistors R3 and R4. The amplifier 222 has an output coupled to the gate of a transistor, shown as FET Q5. A compensation capacitor C3 is coupled between the amplifier output and ground.

[0036] A charging current source 224 is coupled between the voltage supply terminal VDD and Q5. A variable resistor 142 having a resistance (shown as RVAL) is coupled between the source of Q5 and ground. As described herein, the resistor 142 has a trim input coupled to the output 138 of the inductor code counter 134, so that RVAL varies in response to the count value at 138. A variable input offset voltage source 226 is coupled between the source of Q5 and the inverting input 228 of the amplifier 222. The offset voltage source 226 has an input coupled to the output 230 of the discharge counter 152. The offset voltage source 226 is configured to provide an input offset voltage VIO2 to the input 228 in response to the discharge count value at 230. The amplifier 222 can be implemented as an operational transconductance amplifier that is configured to provide an output current in response to the difference between the voltages at the respective inputs 220 and 228. The charging current source 224 can be configured to provide a current I_DISCHARGE that varies in response to the resistance RVAL. Therefore, by adjusting the resistance RVAL of the variable resistor 140 during a plurality of cycles, the value of the charging current I_DISCHARGE is changed accordingly.

[0037] As described herein, within the first number of cycles of power-on, the inductor code counter 134 is configured to adjust the count value (e.g., representing the inductor code) from the starting value in response to the comparator output signal at 138. The starting value can be set to an initial value, such as at or near an intermediate count value between a minimum count value and a maximum count value. The count value at 138 is used to set the resistance RSLP of the resistor 140 and the resistance RVAL of the resistor 142 (e.g., by pin strapping). In response to the count value at 138, the resistance values ​​of RSLP and RVAL can be set to the same or different resistances. As described herein, the values ​​of the charging current I_CHARGE and the discharging current I_DISCHARGE change in response to the corresponding changes of RSLP and RVAL. When the inductor code counter 134 is enabled in the first number of cycles (e.g., by a controller), the charging counter 150 and the discharging counter 152 can be disabled, so VIO1 and VIO2 remain constant at this stage. Thus, the inductance detection circuit system 112 can implement coarse adjustments of the charging current I_CHARGE and the discharging current I_DISCHARGE, and the emulated current I_EM signal is ramped within the first phase of the inductance detection process. The first inductance detection phase can be set to a programmable number of cycles (e.g., a number of PWM cycles or a time period). Additionally or alternatively, the controller 144 can implement the first inductance detection phase until convergence between I_EM and I_SNS is detected, such as described herein. The count value at 138 at the end of the first inductance detection phase can be stored in memory, and the controller can disable the inductor code counter 134.

[0038] After the first phase of the inductance detection process is completed, the inductance detection circuit system 112 can implement the second phase of the inductance detection process. For example, the inductance detection circuit system 112 can make more subtle adjustments to the charging current I_CHARGE and the discharging current I_DISCHARGE over a second number of cycles defining the second inductance detection phase. For example, the controller can provide a control signal at 153 to enable the charge counter 150 and the discharge counter 152, while the inductor code counter remains disabled. The charge counter 150 is configured to trim the offset voltage source 216 and adjust VIO1 in response to the comparator output at 138 and the slope clock signal (SLP_CLK). For example, the slope clock signal controls the sampling of I_EM and I_SNS. The discharge counter 152 can also be configured to trim the offset voltage source 226 and adjust VIO2 in response to the comparator output at 138 and the valley clock signal (VAL_CLK). For example, the valley clock signal VAL_CLK controls the sampling of I_EM and I_SNS at a different time than that used by the charge counter 150 .

[0039] Figure 3 FIG. 3 is another example of an inductance detection circuit 300. The inductance detection circuit 300 may be used to implement Figure 1 or 2 of the inductance detection circuit 112. Therefore, Figure 3 The description also refers to Figure 1 and Figure 2 For example, the circuit 300 includes the emulation current generator circuit 114 , the charge current generator circuit 122 , and the discharge current generator circuit 124 .

[0040] exist Figure 3 In the example of , the charging current generator circuit 122 includes an amplifier 212 having a non-inverting input 210, which is configured to receive an input voltage VIN (or a voltage derived from VIN). The output of the amplifier 212 has an output coupled to the gate of a transistor Q4. A diode-connected transistor Q6 is coupled between a voltage supply terminal VDD and the drain of Q4. A variable resistor 140 is coupled between the source of Q4 and ground. As described herein, the resistor 140 has a trim input configured to receive an inductor code value from the inductor code counter 134. A variable offset voltage source 216 is coupled between the source of Q4 and an inverting input 218 of the amplifier 212. The output of the charge counter 150 is coupled to the variable offset voltage source 216 and is configured to set the voltage VIO1.

[0041] The charging current generator circuit 122 is configured to generate a charging current through Q4 and resistor 140 in response to the amplifier output signal. A current mirror 302 including Q6 and another FET Q7 is configured to mirror the generated charging current I_CHARGE from the charging current generator circuit 122 to the emulation current generator 114. For example, the output of the current mirror 302 (e.g., the drain of Q7) is coupled to a switch 304 (e.g., Figure 2 A first terminal of the switch 304 is shown as FET Q3 in FIG. 1 . The switch 304 has a control input configured to receive a switch voltage signal VSW (e.g., at the switch output 106). A timing capacitor C1 is coupled between a second terminal of the switch 304 and ground. A second terminal of the switch 304 is coupled to another current mirror 306, which is configured to mirror the discharge current generated by the discharge current generator circuit 124 to another branch of the emulation current generator 114.

[0042] The discharge current generator circuit 124 includes an amplifier 222 having a non-inverting input 220, the non-inverting input being configured to receive the output voltage VOUT or a voltage derived from VOUT. The amplifier 222 has an output coupled to the gate of Q5. A diode-connected transistor Q8 is coupled between the voltage supply terminal VDD and the drain of Q5. A variable resistor 142 is coupled between the source of Q5 and ground. The resistor 142 has a trim input configured to receive an inductor code value. A variable offset voltage source 226 is coupled between the source of Q5 and the inverting input 228 of the amplifier 222. The output of the discharge counter 152 is coupled to the variable offset voltage source 226 and is configured to set the voltage VIO2. The discharge current generator circuit 124 is configured to generate a discharge current through Q5 and the resistor 142 in response to an output signal at the output of the amplifier 222. The current mirror 308 including Q8 and another FET Q9 is configured to mirror the generated discharge current I_DISCHARGE to the current mirror 306 and ultimately to the emulated current generator 114 .

[0043] exist Figure 3In the example of , the inductor code counter 134 has a multi-bit output 312, which is coupled to a corresponding multi-bit input of a register 314. During the first inductance detection phase, the inductor code value can be shifted (e.g., latched) from the counter 134 into the register 314. The output 316 of the register 314 (e.g., representing the output 138) provides a multi-bit code to set the resistance of the corresponding variable resistors 140 and 142. When the first inductance detection phase is completed, as described herein, the controller 144 can disable the inductor code counter 134, and the last final inductor code can remain stored in the register 304. Therefore, the resistance values ​​RSLP and RVAL remain constant during further operation including the second phase of the inductance detection process. In some examples, the second inductance detection phase is omitted.

[0044] To provide greater accuracy, circuit 300 may provide finer tuning of I_CHARGE and I_DISCHARGE. Figure 3 In the example of , circuit 300 includes charging side sample-and-hold (S / H) circuits 320 and 322. Sample-and-hold circuit 320 has a sampling input coupled to current sensor output 130 and a clock input configured to receive a slope sampling clock signal (SLPS_CLK). A clock circuit (not shown) can be configured to provide SLPS_CLK to control the sampling of I_SNS and I_EM, for example, during a charging cycle. Sample-and-hold circuit 322 has a sampling input coupled to output 120 of emulated current generator circuit 114 and a clock input configured to receive SLPS_CLK. Circuits 320 and 322 have respective outputs coupled to a non-inverting input and an inverting input of a comparator 324 (e.g., an error amplifier). The output of comparator 324 is coupled to an input of charge counter 150 and an input of inductor code counter 134 (e.g., input 136). Counters 134 and 150 may each have a respective clock input configured to receive an update clock signal (UP_CLK), which may be generated, for example, by an update clock circuit once per PWM cycle. However, as described herein, during the second inductance detection phase, the charge counter 150 may be enabled while the inductor code counter 134 may be disabled.

[0045] The circuit 300 also includes discharge side sample-and-hold (S / H) circuits 330 and 332. The sample-and-hold circuit 330 has a sampling input coupled to the current sensor output 130 and a clock input configured to receive a valley sampling clock signal (VALS_CLK). The sample-and-hold circuit 332 has a sampling input coupled to the output 120 of the emulated current generator circuit 114 and a clock input configured to receive VALS_CLK, which may be derived, for example, from the clock signal CLK1 for sampling the current signals I_SNS and I_EM. The circuits 330 and 332 have respective outputs coupled to the non-inverting input and the inverting input of a comparator 334 (e.g., another error amplifier). The output of the comparator 334 is coupled to the input of the discharge counter 152.

[0046] The circuit 300 also includes a DC reset circuit system 340 having one input coupled to the output 120 of the emulated current generator 114 and another input coupled to the current sensor output 130. For example, the DC reset circuit system 340 includes a switch 342 (e.g., a FET) coupled in series with corresponding buffers 344 and 346 between the outputs 120 and 130. The switch 342 has a control input configured to receive a clock signal (CLK2). The switch 342 is configured to close (e.g., turn on) in response to CLK2 to couple (e.g., short) the outputs 130 and 120 together. The shorting of the switch 342 forces the signals I_SNS and I_EM to be equal, which resets (e.g., to zero) the accumulated AC errors in the signals I_SNS and I_EM. The cycle-by-cycle reset by activating the switch 342 in each cycle also helps track the DC value in the inductor current. In an example, the low-side switch Q4 (see Figure 2 ) is turned on, the clock signal CLK2 is asserted to close the switch with a certain delay in each cycle.

[0047] As another example, Figure 4 Shown for control Figure 3 FIG. 4 is a timing diagram 400 of signals of the inductance detection circuit 300 . The timing diagram shows a PWM signal 402 supplied by the control circuit 110 , for example. Figure 4 Also shown are the low side turn-on signal 404 and the clock signals CLK1 and CLK2. The low side turn-on signal 404 indicates the activation of the low side FET Q2 in the output stage of the power stage. CLK1 includes the slope sampling clock signal SLPS_CLK 406, the valley sampling clock signal VALS_CLK 408, and the update clock signal UP_CLK 410. As shown in FIG. Figure 3As described herein, SLPS_CLK 406 is used to control the sampling of I_SNS and I_EM by the sample and hold circuits 320 and 322 of the charge generator circuit 122. VALS_CLK is used to control the sampling of I_SNS and I_EM by the sample and hold circuits 330 and 332 of the discharge generator circuit 124. The update clock signal UP_CLK is used to control when the counter adjustment is performed in response to the output of the corresponding comparator 324 and 334. As described herein, during the inductance detection process, the second clock signal CLK2 is generated in each cycle to control the reset circuit 340.

[0048] Figure 5 An example power converter system 500 is shown, which is configured to provide a regulated output voltage VOUT at the output 102. The system 500 may implement the inductance detection circuit system 112, as described herein with reference to Figure 1-3 Therefore, Figure 5 The description also refers to Figure 1-3 The system includes one or more instances of a power stage 502 having a corresponding switch output 106. An inductor L1 is coupled between the switch output 106 and the output 102. The power stage 502 includes an output stage 104 having a high-side switch and a low-side switch coupled between a supply voltage terminal VIN and ground. Figure 5 In the example of , the driver 508 (e.g., a gate driver when the switches 504 and 506 are implemented as FETs) has an output coupled to the control input of the respective switches 504 and 506. The driver is configured to provide a drive signal to turn on and off the switches 504 and 506 in response to a PWM signal provided by the control circuit 110. For example, the control circuit 110 is configured to implement one or more control loops to regulate the output voltage VOUT to a reference voltage. The power stage 502 is configured to control the output stage 104 in response to the drive signal to provide the output voltage VOUT.

[0049] The power stage 502 can be configured to implement a type of power converter topology (e.g., buck boost, buck-boost, etc.) depending on the application requirements. In some examples, the power converter system 500 includes multiple power stages 502 configured as a multi-phase power system, wherein each respective power stage has an inductor coupled to its switching output and output 102. In the multi-phase power system, each power stage 502 can be configured to implement the inductance detection circuit system 112. In one example, the control circuit 110 can be implemented as an IC chip, and each power stage 502 can be implemented as a respective IC chip having a switching output terminal (e.g., a pin) to which the output inductor is coupled. In another example, the control circuit 110 and the power stage can be implemented on a single IC chip.

[0050] Figure 6 is a flow chart illustrating an example method 600 for detecting inductance. The method may be Figure 1-3 and Figure 5 1 is implemented by the inductance detection circuit system 112 shown in FIG. Therefore, Figure 6 The description also refers to Figure 1-3 and Figure 5 The method 600 begins at 610 when the power converter circuit 100, 200, 300, 500 is powered on, for example, in response to power supplied from a battery, an inverter, or other power source. At power-on, the counters 134, 150, and 152 may be initialized to respective starting values, such as a maximum count value, or a count value between a maximum count value and a minimum count value.

[0051] At 604, it is determined whether the simulated inductor current I_EM is greater than the sensed inductor current I_SNS. For example, the comparator 116, 324, 334 is configured to provide a comparator output signal based on the difference between the simulated inductor current I_EM and the sensed inductor current I_SNS. At 604, if I_EM is less than I_SNS, the method proceeds to 606 to reduce the slope of the simulated current I_EM. For example, the inductor code counter 134 decrements its count value, which causes the charging current generator circuit 122 and the discharging current generator circuit 124 to reduce the slope of the corresponding charging current I_CHARGE and the discharging current I_DISCHARGE, so the simulated current generator 114 correspondingly reduces the slope of I_EM.

[0052] In response to detecting that I_EM is greater than I_SNS at 604, the method proceeds to 608 to increase the slope of the emulated current I_EM. For example, at 608, the inductor code counter 134 increments its count value, which causes the charging current generator circuit 122 and the discharging current generator circuit 124 to increase the slope of the corresponding charging current I_CHARGE and the discharging current I_DISCHARGE. The emulated current generator 114 increases the slope of I_EM accordingly. The method 600 proceeds to 610 from 606 or 608 to determine whether the inductance detection process has been completed. For example, the determination at 610 can be based on a number of cycles (e.g., PWM cycles), a fixed time period, or detection of convergence (e.g., jitter) between I_EM and I_SNS. If the process is not completed, the method returns to 604 for the next cycle. If it is determined that the process is completed, the method proceeds from 610 to 612. At 612, the inductor code can be set. For example, the last inductor code value from the inductor counter 134 can be stored in a memory (e.g., register 314) to fix the slope of the emulated inductor current I_EM. From 612, the method can end, or in some examples, the method 600 can further include a next stage of fine-tuning the emulated inductor current I_EM, such as by tuning an adjustable offset in response to I_EM and I_SNS, as described herein.

[0053] Figure 7 700 is a graph of current versus time showing how the simulated currents I_EM and I_SNS change over time (eg, cycle by cycle) during inductance sensing. Figure 7 In the example of , samples of I_EM and I_SNS are shown as points 702 and 704 of each cycle, respectively. Samples of I_EM and I_SNS can be compared in each cycle. For example, the simulated current 702 starts with a shallow slope, for example in response to initializing the inductor code counter to a maximum count value. The slope of the simulated current signal I_EM can increase (indicated by an upward arrow 706) or decrease (indicated by a downward arrow 708) until the two samples match (e.g., converge to the same value). The sampled values ​​702 and 704 converge over time, and as shown at 710, after several cycles, the slope of the simulated signal I_EM jitters around the optimal slope. After N cycles of jittering, the inductor code can be stored in a memory (where N is a positive integer).

[0054] Figure 8is a graph 800 of simulation results of signals implemented by the inductance detection circuit 112. Graph 800 shows a low side conduction signal 802, which is applied, for example, to the gate of Q2 or the control input of switch 506. Graph 800 also shows a simulated current signal 804 and a sensed current signal 806 in the example power stage 502 during inductance detection.

[0055] Fig. 9 FIG. 9 is another graph 900 showing simulation results of signals implemented by the inductance detection circuit 112. Fig. 9 In the example of , the controller 144 can provide an enable signal 902 to enable the inductor code counter 134. The comparator 134 can provide a count signal 904 to indicate that the inductor code counter 134 is counting up or down, and provide a multi-bit count value shown at 906. For example, the graph 900 also shows a sense current signal 910 and an emulated current signal 912 during multiple cycles of inductance detection. As shown in the graph, the counter signal 906 can be adjusted in response to the comparison of the emulated current 912 with the sense current 910 at each cycle.

[0056] In this specification, the term "couple" or "couples" means an indirect or direct connection. Thus, if a first device is coupled to a second device, the connection may be through a direct connection, or through an indirect connection via other devices and connections. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first instance, device A is coupled to device B; or (b) in the second instance, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0057] Reference to “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0058] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A circuit comprising: an emulated current generator having a current output; a current sensor having a sensor output; a comparator having a first comparator input coupled to the current output and a second comparator input coupled to the sensor output and a comparator output; an inductor code counter having a counter input and a counter output, the counter input being coupled to the comparator output; a charging circuit having an input coupled to the comparator output, the charging circuit comprising a variable slope resistor having a trim input coupled to the counter output; as well as A discharge circuit has an input coupled to the comparator output, the discharge circuit comprising a variable valley resistor having a trim input coupled to the counter output.

2. The circuit according to claim 1, wherein: The emulated current generator is configured to provide an emulated current signal at the current output that is representative of an emulated current through the output inductor, the current sensor being configured to provide a sensed current signal at the sensor output representing a measure of the current through the output inductor, The comparator is configured to provide a comparator signal at the comparator output in response to the emulated current signal and the sensed current signal, The inductor code counter is configured to adjust an inductor code value at the counter output in response to the comparator signal, and The resistance of a variable slope resistor and the resistance of the variable valley resistor are set in response to the inductor code value.

3. The circuit according to claim 2, further comprising: A controller has a control output and a power input, the control output coupled to the enable input of the inductor code counter, the controller being configured to provide a control signal at the control output to enable the inductor code counter in response to a voltage at the power input.

4. The circuit of claim 3 , wherein the controller is configured to enable the inductor code counter for a duration that is (i) responsive to a number of cycles of a pulse width modulation signal, or (ii) responsive to a difference between the emulated current signal and the sensed current signal being less than a threshold.

5. The circuit of claim 3, wherein: The charging circuit comprises: a charge counter having an input and an output, the charge counter input coupled to the comparator output; and a first offset voltage source having a trim input coupled to the charge counter output and an output coupled to the variable slope resistor; and The discharge circuit comprises: a discharge counter having an input and an output, the discharge counter input being coupled to the comparator output; and A second offset voltage source has a trim input coupled to the discharge counter output and an output coupled to the variable valley resistor.

6. The circuit of claim 5, wherein: The charge counter is configured to set a first variable offset voltage for the charging circuit in response to the charge counter output, and The discharge counter is configured to set a second variable offset voltage for the discharge circuit in response to the discharge counter output.

7. The circuit of claim 5, wherein the control output of the controller is a first control output, the controller further comprising a second control output coupled to respective enable inputs of the charge counter and the discharge counter.

8. The circuit of claim 7 , wherein the controller is configured to enable the inductor code counter and disable the charge counter and the discharge counter during a first portion of an inductance detection phase, and to disable the inductor code counter and enable the charge counter and the discharge counter during a second portion of the inductance detection phase.

9. The circuit of claim 1, further comprising: The output stage includes: a high-side switch coupled between the voltage supply terminal and the switch output terminal; A low-side switch is coupled between the switch output terminal and a ground terminal, the current sensor is coupled to the low-side switch and is configured to provide a sensed current signal representative of a current through an inductor coupled to the switch output terminal when the low-side switch is turned on.

10. The circuit of claim 9, wherein the emulated current generator comprises: a first current source; a third switch having a corresponding control input, the third switch being coupled in series with the first current source between a first voltage terminal and the current output; a second current source coupled between the current output and the ground terminal; a timing capacitor coupled between the current output and the ground terminal; as well as a detector circuit having a detector output and a detector input, the detector input being coupled to the switch output terminal, the detector output being coupled to the control input of the third switch, and the detector circuit being configured to activate the third switch in response to a voltage at the switch output terminal.

11. The circuit of claim 9, further comprising: an inductor coupled to the switch output terminal; a gate driver having a pulse width modulation (PWM) input and a driver output coupled to respective control inputs of respective low-side and high-side switches; as well as A power control circuit has a PWM output coupled to the PWM input, the power control circuit being configured to provide a PWM control signal to the gate driver to provide a regulated voltage at VOUT.

12. The circuit of claim 11, further comprising reset circuitry coupled between the current output and the sensor output, the reset circuitry configured to connect the current output and the sensor output in response to a clock signal.

13. The circuit of claim 1, wherein the emulated current generator, the current sensor, the comparator, the inductor code counter, the charging circuit, and the discharging circuit are implemented on a semiconductor substrate of an integrated circuit.

14. A circuit comprising: an emulated current generator configured to provide an emulated current signal in response to a charging current and a discharging current that respectively charges or discharges the timing capacitor, the emulated current signal representing an emulated current through the output inductor; a comparator configured to provide a comparator signal in response to the emulated current signal and a sensed current signal representing a measure of current through the output inductor; as well as An inductor code counter is configured to adjust an inductor code count value in response to the comparator signal, wherein a slope of the emulated current signal is adjusted in response to the inductor code count value.

15. The circuit of claim 14, further comprising: a charging current generator circuit including a variable slope resistor having a resistance set in response to the inductor code count value, the charging current generator circuit being configured to provide the charging current having a value responsive to the resistance of the variable slope resistor; as well as A discharge current generator circuit includes a variable valley resistor having a resistance set in response to the inductor code count value, the discharge current generator circuit being configured to provide the discharge current having a value responsive to the resistance of the variable valley resistor.

16. The circuit of claim 15, further comprising a controller configured to provide a control signal to enable the inductor code counter in response to a voltage at a power supply terminal.

17. The circuit of claim 16, wherein the controller is configured to enable the inductor code counter during an inductance detection phase having a duration, the duration being at least one of: (i) in response to a number of cycles of a pulse width modulation signal, or (ii) in response to a difference between the emulated current signal and the sensed current signal being less than a threshold.

18. The circuit of claim 16, wherein: The charging current generator circuit includes a first variable offset voltage source and a charge counter, the charge counter being configured to set a voltage of the first variable offset voltage source in response to the emulation current and a first sample of the sense current, and The discharge current generator circuit includes a second variable offset voltage source and a discharge counter configured to set a voltage of the second variable offset voltage source in response to the emulated current and a second sample of the sensed current.

19. The circuit of claim 18, wherein the controller is configured to enable the inductor code counter and disable the charge counter and the discharge counter during a first portion of an inductance detection phase, and to disable the inductor code counter and enable the charge counter and the discharge counter during a second portion of the inductance detection phase.

20. The circuit of claim 19, further comprising reset circuitry configured to short the emulated current signal and the sensed current signal together for a portion of each cycle of the inductance detection phase.

21. The circuit of claim 14, further comprising: The output stage includes: a high-side switch coupled between the voltage supply terminal and the switch output terminal; a low-side switch coupled between the switch output terminal and a ground terminal; The output inductor is coupled to the switch output terminal; a driver configured to control the high-side switch and the low-side switch in response to a pulse width modulation control signal; and A current sensor is coupled to the low-side switch and is configured to provide the sensed current signal representative of the measure of current through the output inductor when the low-side switch is turned on.

22. The circuit of claim 21, wherein the emulated current generator comprises: a first current source configured to provide the charging current; a second current source coupled to the current output of the emulated current generator, the second current source being configured to provide the discharge current; a switch coupled between the first current source and the second current source and configured to connect the first current source to the current output; a capacitor coupled between the current output and the ground terminal; as well as A detector circuit is configured to activate the switch to provide the emulated current in response to a switch voltage at an output terminal of the switch.

23. A system comprising: Inductors; as well as The power stage includes: a high-side switch coupled between a voltage supply terminal and a switch output terminal, the inductor being coupled to the switch output terminal; a low-side switch coupled between the switch output terminal and a ground terminal; a driver configured to control the high-side switch and the low-side switch in response to a pulse width modulation control signal; and An inductance detection circuit system, comprising: an emulated current generator having a current output; a comparator having a first comparator input coupled to the current output and a second comparator input configured to receive a measure of the current through the inductor and a comparator output; an inductor code counter having a counter input and a counter output, the counter input being coupled to the comparator output; a charging circuit having an input coupled to the comparator output, the charging circuit comprising a variable slope resistor having a trim input coupled to the counter output; and A discharge circuit has an input coupled to the comparator output, the discharge circuit comprising a variable valley resistor having a trim input coupled to the counter output.

24. The system of claim 23, further comprising: a current sensor configured to provide a sensed current signal representative of the measure of current through the output inductor, the emulated current generator configured to provide an emulated current signal representative of the emulated current through the inductor at the current output, wherein: The comparator is configured to provide a comparator signal at the comparator output in response to the emulated current signal and the sensed current signal, The inductor code counter is configured to adjust an inductor code value at the counter output in response to the comparator signal, and The resistance of a variable slope resistor and the resistance of the variable valley resistor are set in response to the inductor code value.

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