Output waveform control device and method, test device and test system

Abstract

The invention relates to an output waveform control device and method, a test device and a test system, and the device comprises an output data source module which is used for outputting an original data stream; the waveform synthesis module is connected with the output data source module and is used for performing waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform; and the output signal delay module is connected with the waveform synthesis module and is used for carrying out delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform. The output waveform is obtained in the mode that waveform synthesis is conducted firstly and then delay processing is conducted, the output waveform can be obtained without adjusting the phase of a driving clock, the waveform output function can be achieved through a universal chip, and the design complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an output waveform control device, method, test device and test system. Background Art

[0002] Timing Generator (TG) is an important component of the tester, responsible for synthesizing the output waveform according to the user's requirements and sampling the input signal according to the sampling time configured by the user. When the traditional Timing Generator is testing the chip, the control of the placement time of the output signal edge is achieved by adjusting the clock phase, and a dedicated IC (Integrated Circuit) must be used, and the implementation structure is complex, which has the disadvantage of high design complexity. Summary of the invention

[0003] Based on this, it is necessary to provide an output waveform control device, method, test device and test system that can reduce the design complexity in order to address the above problems.

[0004] An output waveform control device, comprising:

[0005] Output data source module, used to output original data stream;

[0006] A waveform synthesis module, connected to the output data source module, is used to synthesize the waveform format of the original data stream according to the configured waveform format to obtain a synthesized waveform;

[0007] The output signal delay module is connected to the waveform synthesis module and is used to perform delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform.

[0008] In one embodiment, the output waveform control device further comprises:

[0009] An output configuration module is connected to the waveform synthesis module and the output signal delay module, and is used to configure the waveform format and the output delay value.

[0010] In one of the embodiments, the output configuration module is further used to configure the time length of the test cycle; the waveform synthesis module performs waveform format synthesis on the original data stream according to the configured waveform format in each of the test cycles to obtain the synthesized waveform.

[0011] In one of the embodiments, the output signal delay module determines the signal edge placement position according to the configured output delay value, places the edge of the synthesized waveform at the signal edge placement position, and obtains the output waveform.

[0012] In one of the embodiments, the output signal delay module includes a CARRY module or an IODELAY module.

[0013] In one of the embodiments, the CARRY module includes a tap setting unit, a data selector and at least two CARRY units, the CARRY units are connected in series in sequence, the CARRY unit located at the head end is connected to the waveform synthesis module, and the CARRY unit located at the end is used to connect to the device to be tested; the data selector connects the taps of each CARRY unit and the tap setting unit, and the tap setting unit is connected to the output configuration module.

[0014] In one of the embodiments, the IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit located at the head end is connected to the waveform synthesis module, the ODELAY unit located at the tail end is used to connect the device to be tested, and the tap configuration unit connects the IDELAY unit, the ODELAY unit and the output configuration module.

[0015] An output waveform control method, comprising:

[0016] The output configuration module configures the waveform format of the waveform synthesis module;

[0017] The output configuration module configures the output delay value of the output signal delay module;

[0018] The output data source module outputs the original data stream;

[0019] The waveform synthesis module performs waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform;

[0020] The output signal delay module performs delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform.

[0021] In one embodiment, the output configuration module configures the output delay value of the output signal delay module, including: determining the output delay value and configuring the output signal delay module according to the actual required delay time and the correspondence between the delay time and the delay value.

[0022] A testing device comprises a PE module and the above-mentioned output waveform control device, wherein the output signal delay module is connected to a device to be tested via the PE module.

[0023] A test system, comprising an input signal delay module, an input signal sampling module, a comparison processing module and the above-mentioned test device, wherein the input signal delay module is connected to the PE module and the input signal sampling module, and the input signal sampling module is connected to the comparison processing module;

[0024] The PE module is used to compare and judge the input signal fed back by the device to be tested according to the preset level threshold value, and output the comparison signal to the input signal delay module;

[0025] The input signal delay module is used to delay the comparison signal and send the delayed comparison signal to the input signal sampling module;

[0026] The input signal sampling module is used to sample the delayed comparison signal according to the set sampling time, and obtain the sampling signal and send it to the comparison processing module;

[0027] The comparison processing module is used to determine the actual sampling value according to the sampling signal analysis, and to compare and judge the actual sampling value with a preset expected value to obtain a comparison result.

[0028] In one embodiment, the testing system further comprises:

[0029] An input configuration module is connected to the input signal delay module and is used to set the delay time of the input signal delay module according to a set sampling time.

[0030] The output waveform control device, method, test device and test system first synthesize the waveform format of the original data stream according to the configured waveform format through the waveform synthesis module to obtain a synthesized waveform, and then delay the synthesized waveform according to the configured output delay value through the output signal delay module to obtain the output waveform. The output waveform is obtained by first synthesizing the waveform and then delaying it. The output waveform can be obtained without adjusting the driving clock phase. The waveform output function can be realized by using a general chip, which reduces the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a structural block diagram of an output waveform control device in one embodiment;

[0032] Figure 2 A schematic diagram of the structure of a CARRY module in one embodiment;

[0033] Figure 3 A schematic diagram of the structure of an IODELAY module in an embodiment;

[0034] Figure 4 A schematic diagram of timing synthesis in one embodiment;

[0035] Figure 5 is a flow chart for implementing output waveform control in one embodiment;

[0036] Figure 6 A schematic diagram of waveform format conversion and signal delay in one embodiment;

[0037] Figure 7 is a structural block diagram of a test system in one embodiment;

[0038] Figure 8 is a structural block diagram of an input signal delay module and an input signal sampling module in one embodiment;

[0039] Fig. 9 is a flow chart for implementing input signal delayed sampling control in one embodiment;

[0040] Fig.10 A schematic diagram of signal conversion of a PE module in one embodiment;

[0041] Fig.11 A schematic diagram of the timing sequence of input signal delay control sampling position in one embodiment;

[0042] Fig.12 A comparison truth table and a comparison processing principle diagram in one embodiment. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0045] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.

[0047] The current Timing Generator has a functional architecture that first adjusts the time delay of the data, and then converts the adjusted signal into the required waveform format for output. The control of the placement moment of the output signal edge is achieved by adjusting the clock phase. When testing a chip, if you want to adjust the phase of the signal output to the chip, you usually adjust the drive clock phase first, and then drive the signal output to the chip. This requires that the waveform format conversion circuit delay of each channel be as consistent as possible, or that the circuit delay difference between channels be compensated to the data delay. In addition, in order to achieve the control of the placement moment of the output signal edge by adjusting the clock phase, a dedicated chip must be designed and implemented, and it cannot be implemented using a general-purpose FPGA (Field Programmable Gate Array), and the dedicated chip implementation structure is complex.

[0048] Based on this, in order to solve the problem of equal delay requirements for waveform format conversion circuits between channels introduced by delaying data first and then performing waveform format conversion, or introducing additional circuit delay difference compensation, the present application provides an output waveform control device, which first uses a waveform synthesis module to synthesize the waveform format of the original data stream according to the configured waveform format to obtain a synthesized waveform, and then uses an output signal delay module to delay the synthesized waveform according to the configured output delay value to obtain an output waveform. The output waveform is obtained by first synthesizing the waveform and then delaying it. It is insensitive to the delay of the waveform format conversion part. When performing delay compensation between channels, the format conversion part does not need to be calculated, thereby reducing the delay compensation error. The position of the edge of the output waveform is finely controlled by signal delay rather than clock phase control. A general FPGA chip can be used to implement the waveform output function, thereby reducing the design cost.

[0049] In one embodiment, Figure 1 As shown, an output waveform control device is provided, comprising: an output data source module 110, a waveform synthesis module 120 and an output signal delay module 130, wherein the waveform synthesis module 120 is connected to the output data source module 110, and the output signal delay module 130 is connected to the waveform synthesis module 120. The output data source module 110 is used to output the original data stream; the waveform synthesis module 120 is used to perform waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform; the output signal delay module 130 is used to perform delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform.

[0050] Among them, according to the different output waveforms actually required, the waveform format configured by the waveform synthesis module 120 and the output delay value configured by the output signal delay module 130 will also be different accordingly, and can be adjusted according to the actual situation. After the waveform synthesis module 120 synthesizes the waveform format of the original data stream output by the output data source module 110 according to the configured waveform format, it outputs the synthesized waveform to the output signal delay module 130. The output signal delay module 130 delays the synthesized waveform according to the configured output delay value and the internal clock to obtain the output waveform. The output waveform is used to be transmitted to the device under test DUT to test the device under test DUT. The device under test DUT can be a chip under test or other devices. In addition, the output data source module 110 can also output an expected signal as a reference for waveform synthesis and signal delay.

[0051] The types of waveform formats are not unique, and may include NRZ, RZ, XORBC, etc. The waveform format mapping relationship is shown in Table 1, where RZ and XORBC waveform formats are DDR rate waveform formats, that is, a data unit is divided into two parts, front and back.

[0052] Table 1

[0053]

[0054] In one embodiment, the output waveform control device further includes an output configuration module 140, which is connected to the waveform synthesis module 120 and the output signal delay module 130, and is used to configure the waveform format and the output delay value. The tester can configure the waveform format and the output delay value through the output configuration module 140 according to the actual test needs, so that the output waveform control device generates the corresponding output waveform according to the actual needs. Among them, the output configuration module 140 determines the output delay value and configures the output signal delay module 130 according to the actual required delay time and the corresponding relationship between the delay time and the delay value.

[0055] Furthermore, the output configuration module 140 is also used to configure the time length of the test cycle; the waveform synthesis module 120 performs waveform format synthesis on the original data stream according to the configured waveform format in each test cycle to obtain a synthesized waveform. In each test cycle Test Rate, the waveform synthesis module 120 performs waveform format synthesis according to the original data stream and the corresponding waveform format setting to obtain a corresponding synthesized waveform.

[0056] The signal delay mode of the output signal delay module 130 is not unique. In one embodiment, the output signal delay module 130 determines the signal edge placement position according to the configured output delay value, places the edge of the synthesized waveform at the signal edge placement position, and obtains the output waveform. After receiving the synthesized waveform output by the waveform synthesis module 120, the output signal delay module 130 delays according to the configured output delay value, and places the edge of the synthesized waveform at the appropriate time to achieve the correct timing relationship.

[0057] It can be understood that the specific structure of the output signal delay module 130 is not unique, and can be a combination of one or more of IDELAY (input delay unit), ODELAY (output delay unit) and CARRY modules. Specifically, the delay width of the output signal delay module 130 covers the clock cycle, and the signal delay can be achieved through dedicated resources such as IDELAY, ODELAY, and CARRY inside the FPGA. In other embodiments, the output signal delay module 130 can also use general resources, such as a lookup table to achieve signal delay, or use a CNC delay chain chip to achieve signal delay. When the output signal delay module 130 uses IDELAY, ODELAY or CARRY, the output delay value configured by the output signal delay module 130 is specifically a tap value.

[0058] The output waveform control device first synthesizes the waveform format of the original data stream according to the configured waveform format through the waveform synthesis module 120 to obtain a synthesized waveform, and then delays the synthesized waveform according to the configured output delay value through the output signal delay module 130 to obtain the output waveform. The output waveform is obtained by first synthesizing the waveform and then delaying it. The output waveform can be obtained without adjusting the driving clock phase, and a general chip can be used to implement the waveform output function, which reduces the design complexity.

[0059] In one embodiment, the output signal delay module 130 includes a CARRY module or an IODELAY module. It is understood that the specific structures of the CARRY module and the IODELAY module are not unique. Specifically, Figure 2As shown, the CARRY module may include a CARRY unit 132, a data selector MUX and a tap setting unit 134, wherein the delay span of the CARRY unit 132 covers the clock cycle, and the signal edge can be placed at any position within the clock cycle. The number of CARRY units 132 is at least two, and each CARRY unit 132 is connected in series in sequence. The CARRY unit 132 at the head end is connected to the waveform synthesis module 120, and the CARRY unit 132 at the end is used to connect the device under test DUT; the data selector MUX connects the taps of each CARRY unit 132 and the tap setting unit 134, and the tap setting unit 134 is connected to the output configuration module 140. Among them, the CARRY unit 132 can be a CARRY8 unit, which leads out 8 taps to connect the data selector MUX, and the tap setting unit 134 controls the delay of the connected waveform according to the tap value configured by the output configuration module 140, and the delayed waveform is output through the data selector MUX.

[0060] In one embodiment, Figure 3 As shown, the IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit 136. The number of IDELAY units and ODELAY units can be one or at least two. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit at the head end is connected to the waveform synthesis module 120, the ODELAY unit at the tail end is used to connect the device to be tested DUT, and the tap configuration unit 136 connects the IDELAY unit, the ODELAY unit and the output configuration module 140. The tap configuration unit 136 controls the delay of the connected waveform according to the IDELAY tap value and the ODELAY tap value configured by the output configuration module 140, and the delayed waveform is output through the ODELAY unit at the tail end.

[0061] Specifically, in the internal logic implementation of FPGA or digital circuit design, in order to ensure the speed and reliability of the operation of the digital circuit, it is often necessary to use a timing circuit to implement the circuit function. However, the digital circuit will cause all signal edges to be aligned with the edges of the clock signal, that is, all digital sequential logic circuits are operated according to the beat of the clock, and all signal edges are at the corresponding clock signal edge (although in the actual circuit, due to factors such as process, power supply, temperature, etc., the position of the signal edge will be deviated relative to the clock signal, but the basic beat is referenced to the working main clock frequency). Since the signal transition edges in the digital sequential circuit are all referenced to the signal edge of the working clock, all signal transition edges are aligned with the rising edge of the clock. In the field of test machines, when synthesizing the test signal that stimulates the device under test DUT, the signal transition edge needs to be controllable and requires a higher resolution. If the signal is simply based on the reference clock, the resolution of the signal edge placement cannot be guaranteed.

[0062] like Figure 4 In the figure, DataIn is the data stream after waveform format synthesis, EdgePosition is the desired edge placement position, all signal edge transitions of DataIn are on the rising edge of the clock DomainClock, and the desired signal edge position is between the clock edges. In the current mainstream chip testers, waveform synthesis is divided into waveform format synthesis and waveform timing synthesis, where waveform format synthesis is implemented through a dedicated chip, and timing synthesis is implemented by adjusting the clock frequency or implementing the phase. The adjustment of the clock phase is achieved by designing a multi-phase clock output in the chip, and using clocks of different phases to generate the signal during waveform format synthesis. This implementation method is relatively complex and requires dedicated chip support.

[0063] To ensure that it can be implemented inside the FPGA, the output waveform control device provided in the present application first performs waveform format synthesis on the signal, and then performs timing synthesis. Figure 4 In the example, the first edge of DataIn is placed at the position of EdgePosition, which is equivalent to delaying and widening the first low-level segment of the signal, so that the first edge of the signal moves to the desired position, and the output waveform DataOut is obtained. The delay time is the time difference from the first edge of DataIn to the first desired position. This implementation method of delaying the signal edge requires that the delay width of the output signal delay module 130 can cover the clock cycle, and adjust the signal edge by widening or narrowing the fixed level delay. This delay that is less than the clock cycle can be implemented by using some dedicated resources such as IDELAY, ODELAY, and Carry inside the FPGA, or by using general resources such as a lookup table, or by using a CNC delay chain chip outside the FPGA.

[0064] like Figure 5 As shown in the figure, the specific execution process of output waveform control is as follows:

[0065] 1. The output data source module 110 feeds the original data stream into the waveform synthesis module 120, and the waveform synthesis module 120 converts the data into a waveform format according to the configured waveform format. See the typical waveform format conversion Figure 6 In each test cycle Test Rate, the corresponding synthetic waveform is obtained according to the original data stream Pattern and the corresponding waveform format setting. Clock is the clock signal, Edge_Position is the placement position of the expected edge, and NRZ_format, RZ_format and XORBC_format are synthetic waveforms of corresponding formats respectively.

[0066] 2. The output signal delay module 130 delays the format-converted data according to the delay requirements, and places the signal edge output by the waveform synthesis module 120 at the appropriate time to achieve the correct timing relationship, such as Figure 6 The edge of the signal is dynamically modulated by delay, and NRZ_timing, RZ_timing and XORBC_timing are the output waveforms after delaying the synthetic waveforms of the corresponding formats.

[0067] 3. The signal after signal delay is fed into the device under test DUT as the excitation signal of the device under test DUT.

[0068] In one embodiment, an output waveform control method is also provided, including: an output configuration module configures the waveform format of a waveform synthesis module; an output configuration module configures the output delay value of an output signal delay module; an output data source module outputs an original data stream; a waveform synthesis module performs waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform; and an output signal delay module performs delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform.

[0069] In one embodiment, the output configuration module configures the output delay value of the output signal delay module, including: determining the output delay value and configuring the output signal delay module according to the actually required delay time and the correspondence between the delay time and the delay value.

[0070] It can be understood that the specific implementation of the above-mentioned output waveform control method has been explained in detail in the above-mentioned output waveform control device, and will not be repeated here.

[0071] In one embodiment, Figure 7As shown, a test device is also provided, including a PE (Pin Electronics Driver / Comparator) module 210 and the above-mentioned output waveform control device, and the output signal delay module 130 is connected to the device under test DUT through the PE module 210.

[0072] Specifically, the output data source module 110, the waveform synthesis module 120, the output signal delay module 130, the PE module 210 and the device under test DUT are connected in sequence, the waveform format synthesis is first performed on the original data stream and then the signal delay is performed, and finally the excitation signal is output to the device under test DUT through the PE module 210. Among them, the output data source module 110 can be ALPG (Algorithmic Pattern Generator, algorithmic graphic generation module), which automatically generates the original data stream according to the written program. The output data source module 110 can also be PG (Pattern Generator, graphic generation module), which generates the original data stream according to the specified test vector. The PE module 210 receives the output waveform obtained by the output signal delay module 130, converts it according to the set level threshold value (VIH\VIL) to obtain the excitation signal and sends it to the device under test DUT.

[0073] In one embodiment, Figure 7 As shown, a test system is also provided, including an input signal delay module 220, an input signal sampling module 230, a comparison processing module 240 and the above-mentioned test device, the input signal delay module 220 is connected to the PE module 210 and the input signal sampling module 230, and the input signal sampling module 230 is connected to the comparison processing module 240.

[0074] Among them, the PE module 210 is used to compare and judge the input signal fed back by the device under test DUT according to the preset level threshold value, and output the comparison signal to the input signal delay module 220; the input signal delay module 220 is used to delay the comparison signal, and send the delayed comparison signal to the input signal sampling module 230; the input signal sampling module 230 is used to sample the delayed comparison signal according to the set sampling time, and the obtained sampling signal is sent to the comparison processing module 240; the comparison processing module 240 is used to determine the actual sampling value based on the sampling signal analysis, and compare and judge based on the actual sampling value and the preset expected value to obtain a comparison result.

[0075] Furthermore, the test system also includes an input configuration module 250, which is connected to the input signal delay module 220 and is used to set the delay time of the input signal delay module 220 according to the set sampling time. Specifically, the output configuration module 140 and the input configuration module 250 belong to the TC (Timing Controller) module of the test system; the output signal delay module 130, the input signal delay module 220 and the input signal sampling module 230 belong to the TG module of the test system. The signal delay function of the input signal delay module 220 can also be implemented by using dedicated resources inside the FPGA, such as IDELAY, ODELAY, and CARRY, or by using general resources such as a lookup table, or by using a CNC delay chain chip outside the FPGA, which will not be elaborated here.

[0076] The way in which the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value is not unique. In one embodiment, the preset level threshold value includes a threshold value VOH and a threshold value VOL. The values ​​of the threshold value VOH and the threshold value VOL are not unique and can be set according to actual needs, as long as the threshold value VOH is greater than the threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. The output signal of the PE module 210 is delayed by the input signal delay module 220, and the delayed signal is sent to the input signal sampling module 230. The input signal sampling module 230 samples the two input signals based on the main sampling clock frequency according to the set sampling time, and obtains the sampling signal and sends it to the comparison processing module 240. Among them, the delay span of the input signal delay module 220 can cover the clock cycle range, ensuring that any position within the clock cycle can be sampled.

[0077] In one embodiment, Figure 8As shown, the comparison signal output by the PE module 210 includes two output signals, the input signal delay module 220 includes a first delay unit 222 and a second delay unit 224, and the input signal sampling module 230 includes a first signal sampling unit 232 and a second signal sampling unit 234. The first delay unit 222 is connected to the PE module 210, the first signal sampling unit 232 and the input configuration module 250, the second delay unit 224 is connected to the PE module 210, the second signal sampling unit 234 and the input configuration module 250, and the comparison processing module 240 is connected to the first signal sampling unit 232 and the second signal sampling unit 234. The output signal CA and the output signal CB of the PE module 210 are delayed by the first delay unit 222 and the second delay unit 224, respectively, and the two delayed signals are sampled by the first signal sampling unit 232 and the second signal sampling unit 234, respectively, to obtain two sampling signals and send them to the comparison processing module 240. The first signal sampling unit 232 and the second signal sampling unit 234 have the same set sampling time, and synchronously perform signal delay and sampling on the two output signals of the PE module 210. Further, the comparison processing module 240 can analyze the two sampling signals according to the set comparison truth table to determine the actual sampling value, and then compare and judge according to the actual sampling value and the preset expected value to obtain the comparison result.

[0078] Specifically, Fig. 9 As shown, the execution process of delayed sampling of the input signal is as follows:

[0079] 1. The device under test (DUT) generates a signal and feeds it into the PE module 210 .

[0080] 2. The PE module 210 compares and judges the input signal according to the two set comparison threshold values ​​(VOH\VOL), and outputs the required comparison results after comparison: output signal CA and output signal CB. Output signal CA\output signal CB are standard high and low level digital signals, such as Fig.10 When the input signal is less than the threshold value VOL, the output signal CA is low level, and the output signal CB is low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is low level, and the output signal CB is high level; when the input signal is greater than the threshold value VOH, the output signal CA is high level, and the output signal CB is high level.

[0081] 3. According to the set sampling position information, the input configuration module 250 configures the signal delay time.

[0082] 4. The input signal delay module 220 performs delay processing on the signal to ensure that the sampling time of the input signal sampling module 230 is the set time.

[0083] 5. The output signals CA and CB of the PE module 210 are fed into the input signal sampling module 230 after delay. The input signal sampling module 230 samples the two delayed signals according to the set sampling time and transmits the sampling results to the comparison processing module 240. The sampling principle is as follows Fig.11 As shown, Clock is the clock signal, DataIn is the original input signal before signal delay, Sample_Position is the sampling position, DataIn_Delay is the signal after delay, and DataIn_Sample is the sampling signal.

[0084] 6. The sampling signal is input to the comparison processing module 240, which first uses the comparison truth table to determine the actual sampling value according to the state value of the output signal CA\output signal CB, and then uses the actual sampling value to perform parallel comparison and judgment with the expected value, and outputs the corresponding comparison result. Fig.12 As shown, the corresponding comparison result is given according to the actual sampling values ​​of the output signal CA\output signal CB.

[0085] By delaying the input signal fed back by the device under test DUT before sampling the signal, the signal sampling position can be dynamically controlled. When delaying the signal, there is no need to switch the clock phase, which reduces the complexity of the design. In addition, the parallel matching truth table method is used to implement the signal parallel comparison and judgment processing. There is no need to decompose the output signal CA\output signal CB to gradually judge whether the output signal CA is consistent with the expected value, and then judge whether the output signal CB is consistent with the expected value. Instead, the actual value is directly determined by matching and comparing through a table lookup method, and then the actual value and the expected value are matched and compared to analyze whether the output result is consistent with the expectation, which has high detection efficiency.

[0086] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An output waveform control device, characterized in that: include: Output data source module, used to output original data stream; A waveform synthesis module, connected to the output data source module, is used to synthesize the waveform format of the original data stream according to the configured waveform format to obtain a synthesized waveform; The output signal delay module is connected to the waveform synthesis module and is used to perform delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform.

2. The output waveform control device according to claim 1, characterized in that: Also includes: An output configuration module is connected to the waveform synthesis module and the output signal delay module, and is used to configure the waveform format and the output delay value.

3. The output waveform control device according to claim 2, characterized in that: The output configuration module is also used to configure the time length of the test cycle; the waveform synthesis module performs waveform format synthesis on the original data stream according to the configured waveform format in each test cycle to obtain the synthesized waveform.

4. The output waveform control device according to claim 2, characterized in that: The output signal delay module determines the signal edge placement position according to the configured output delay value, places the edge of the synthetic waveform at the signal edge placement position, and obtains the output waveform.

5. The output waveform control device according to claim 2, characterized in that: The output signal delay module includes a CARRY module or an IODELAY module.

6. The output waveform control device according to claim 5, characterized in that: The CARRY module includes a tap setting unit, a data selector and at least two CARRY units, each of the CARRY units is connected in series in sequence, the CARRY unit located at the head end is connected to the waveform synthesis module, and the CARRY unit located at the end is used to connect to the device to be tested; the data selector is connected to the taps of each of the CARRY units and the tap setting unit, and the tap setting unit is connected to the output configuration module.

7. The output waveform control device according to claim 5, characterized in that: The IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit located at the head end is connected to the waveform synthesis module, the ODELAY unit located at the tail end is used to connect the device to be tested, and the tap configuration unit connects the IDELAY unit, the ODELAY unit and the output configuration module.

8. An output waveform control method, characterized in that: include: The output configuration module configures the waveform format of the waveform synthesis module; The output configuration module configures the output delay value of the output signal delay module; The output data source module outputs the original data stream; The waveform synthesis module performs waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform; The output signal delay module performs delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform.

9. The output waveform control method according to claim 8, characterized in that: The output configuration module configures the output delay value of the output signal delay module, including: determining the output delay value and configuring the output signal delay module according to the actually required delay time and the corresponding relationship between the delay time and the delay value.

10. A testing device, characterized in that: It comprises a PE module and the output waveform control device according to any one of claims 1 to 7, wherein the output signal delay module is connected to the device to be tested through the PE module.

11. A testing system, characterized in that: The test device comprises an input signal delay module, an input signal sampling module, a comparison processing module and the test device according to claim 10, wherein the input signal delay module is connected to the PE module and the input signal sampling module, and the input signal sampling module is connected to the comparison processing module; The PE module is used to compare and judge the input signal fed back by the device to be tested according to the preset level threshold value, and output the comparison signal to the input signal delay module; The input signal delay module is used to delay the comparison signal and send the delayed comparison signal to the input signal sampling module; The input signal sampling module is used to sample the delayed comparison signal according to the set sampling time, and obtain the sampling signal and send it to the comparison processing module; The comparison processing module is used to determine the actual sampling value according to the sampling signal analysis, and to compare and judge the actual sampling value with a preset expected value to obtain a comparison result.

12. The test system according to claim 11, characterized in that: Also includes: An input configuration module is connected to the input signal delay module and is used to set the delay time of the input signal delay module according to a set sampling time.

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