A method for manufacturing a space converter of a probe card

Abstract

The present invention provides a method for manufacturing a space converter of a probe card, comprising: sequentially forming a titanium layer and a first copper layer on the upper surface of a ceramic substrate; forming a first circuit pattern on the upper surface of the first copper layer; forming a second copper layer on the first circuit pattern; removing the titanium layer and the first copper layer except those located below the second copper layer; sequentially forming a nickel layer and a first gold layer on the upper surface of the structure; forming a polyimide layer on the upper surface of the structure; removing the polyimide layer on the upper surface of the target position of the first gold layer to form a second circuit pattern; forming a first nickel-cobalt alloy layer on the second circuit pattern, and then forming a third circuit pattern; forming a second nickel-cobalt alloy layer on the third circuit pattern, and then forming a fourth circuit pattern; forming a second gold layer on the fourth circuit pattern; removing the photoresist to obtain a space converter. The method for manufacturing a space converter of a probe card provided by the present invention can accurately adjust the probe installation position and improve the probe alignment accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for manufacturing a space converter of a probe card. Background Art

[0002] The probe card is a key device used for electronic testing and analysis. During the test process, the probe card contacts the test points of the semiconductor circuit or device to measure and analyze the electrical signal. The probe card usually includes a space transformer, on which multiple probes are installed, and the probes contact the test points of the circuit or device to be tested. Traditional space transformers use a single-layer substrate, and the probe card is manufactured by manually assembling probes, which cannot flexibly respond to various semiconductor wafer designs. Due to the high integration and miniaturization of wafers, the number of test points increases and the intervals become narrower. The probe card manufactured using traditional space transformers has the problem of not being able to guarantee precise alignment and contact, and the possibility of poor contact and increased test errors will occur. In addition, for probe cards manufactured using traditional space transformers, signal distortion increases as the signal transmission path lengthens, and the electrical characteristics may degrade, especially during high-speed signal processing. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a method for manufacturing a space converter of a probe card, which can accurately adjust the probe installation position, improve the probe alignment accuracy, and flexibly respond to various semiconductor wafer designs.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing a spatial transformer of a probe card, comprising the following steps:

[0005] Step 10, pre-treating the ceramic substrate;

[0006] Step 20, sputtering to form a titanium layer on the upper surface of the ceramic substrate, and sputtering to form a first copper layer on the upper surface of the titanium layer;

[0007] Step 30, coating a photoresist on the upper surface of the first copper layer to form a first photoresist layer, and performing exposure and development to form a first circuit pattern;

[0008] Step 40, forming a second copper layer by electroplating on the first circuit pattern;

[0009] Step 50, removing the first photoresist layer;

[0010] Step 60, removing the titanium layer and the first copper layer except for those located below the second copper layer;

[0011] Step 70, forming a nickel layer by electroplating on the upper surface of the second copper layer, and forming a first gold layer by electroplating on the upper surface of the nickel layer and around the titanium layer, the first copper layer, the second copper layer and the nickel layer;

[0012] Step 80, coating the ceramic substrate and the first gold layer to form a polyimide layer;

[0013] Step 90, removing the polyimide layer on the upper surface of the target position of the first gold layer;

[0014] Step 100, coating photoresist at the target position of the first gold layer and the upper surface of the polyimide layer to form a second photoresist layer, and performing exposure and development to form a second circuit pattern;

[0015] Step 110, forming a first nickel-cobalt alloy layer by electroplating on the second circuit pattern, and performing a planarization process on the first nickel-cobalt alloy layer;

[0016] Step 120, coating photoresist on the first nickel-cobalt alloy layer and the second photoresist layer to form a third photoresist layer, and performing exposure and development to form a third circuit pattern;

[0017] Step 130, forming a second nickel-cobalt alloy layer on the third circuit pattern by electroplating, and performing a planarization process on the second nickel-cobalt alloy layer;

[0018] Step 140, coating photoresist on the second nickel-cobalt alloy layer and the third photoresist layer to form a fourth photoresist layer, and performing exposure and development to form a fourth circuit pattern;

[0019] Step 150, forming a second gold layer by electroplating on the fourth circuit pattern;

[0020] Step 160 , removing all photoresist layers to obtain the spatial transformer of the probe card.

[0021] As a further improvement of the present invention, the ceramic substrate is made of multilayer ceramics.

[0022] As a further improvement of the present invention, step 10 specifically includes: laminating and exposing the lower surface of the ceramic substrate with a dry film; polishing the upper surface of the ceramic substrate; and removing the dry film on the lower surface of the ceramic substrate.

[0023] As a further improvement of the present invention, in step 30, before applying photoresist on the upper surface of the first copper layer, the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure; in step 100, before applying photoresist on the target position of the first gold layer and the upper surface of the polyimide layer, the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure; in step 120, before applying photoresist on the upper surfaces of the first nickel-cobalt alloy layer and the second photoresist layer, the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure.

[0024] As a further improvement of the present invention, in step 60, a wet etching process is used to first etch and clean the first copper layer, then etch and clean the titanium layer, then etch and clean the first copper layer, and finally etch the titanium layer.

[0025] As a further improvement of the present invention, in step 60, after removing the titanium layer and the first copper layer except those located below the second copper layer, the lower surface of the ceramic substrate is dry-film laminated and exposed.

[0026] As a further improvement of the present invention, in step 100, after forming the second circuit pattern, a plasma surface treatment method is used to treat the surface of the second circuit pattern; in step 120, after forming the third circuit pattern, a plasma surface treatment method is used to treat the surface of the third circuit pattern; in step 140, after forming the fourth circuit pattern, a plasma surface treatment method is used to treat the surface of the fourth circuit pattern.

[0027] As a further improvement of the present invention, in step 110, before electroplating on the second circuit pattern, the oxide film on the second circuit pattern is first removed; in step 130, before electroplating on the third circuit pattern, the oxide film on the third circuit pattern is first removed; in step 150, before electroplating on the fourth circuit pattern, the oxide film on the fourth circuit pattern is first removed.

[0028] As a further improvement of the present invention, in step 130, when removing the oxide film on the second circuit pattern, the oxide film removal process is performed at least three times.

[0029] As a further improvement of the present invention, in step 110, the first nickel-cobalt alloy layer is planarized, specifically comprising:

[0030] Firstly, the portion of the first nickel-cobalt alloy layer that is higher than the target height is ground, then the metal chips are removed by soaking, then the residual soaking liquid is removed, and finally, the soaking liquid is cleaned;

[0031] In the step 130, the second nickel-cobalt alloy layer is planarized, specifically including:

[0032] First, the portion of the second nickel-cobalt alloy layer that is higher than the target height is ground, and then the metal chips are removed by immersion, and then the residual immersion liquid is removed, and finally cleaned.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the present invention provides a method for manufacturing a space converter of a probe card, which utilizes micro-electromechanical system (MEMS) technology to manufacture the space converter, and uses lithography, etching and other technologies. The probe installation position can be flexibly adjusted according to various semiconductor wafer designs, and the position, size and arrangement of the probe and the circuit can be accurately controlled to ensure the precise alignment of the wafer pad and the probe, and the interval between the circuit and the probe can be accurately adjusted to achieve precise space conversion and precise measurement of the probe card; high-density and high-integration circuits can be configured in a limited space of the space converter, and fast response speed and high-speed data processing can be achieved; through automated equipment manufacturing, process changes can be minimized, product consistency can be improved, defective rate can be reduced, manufacturing process consistency can be achieved, quality control can be facilitated, and the stability and reliability of the space converter can be greatly improved; it is conducive to mass production, reducing the production cost of the unit probe card, and the automated process shortens the production time and improves production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic structural diagram of a ceramic substrate after pre-processing in an embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of a structure after a titanium layer and a first copper layer are sequentially formed on a ceramic substrate in an embodiment of the present invention;

[0036] Figure 3 is a schematic structural diagram after a first circuit pattern is formed in an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of a structure after a second copper layer is formed on a first circuit pattern in an embodiment of the present invention;

[0038] Figure 5 is a schematic diagram of the structure after the first photoresist layer is removed in an embodiment of the present invention;

[0039] Figure 6 is a schematic diagram of the structure after the titanium layer and the first copper layer except those located below the second copper layer are removed in an embodiment of the present invention;

[0040] Figure 7 is a schematic diagram of the structure after the nickel layer and the first gold layer are formed in an embodiment of the present invention;

[0041] Figure 8 is a schematic diagram of the structure after a polyimide layer is formed in an embodiment of the present invention;

[0042] Fig. 9 is a schematic diagram of the structure after the polyimide layer on the upper surface of the target position of the first gold layer is removed in an embodiment of the present invention;

[0043] Fig.10 is a schematic structural diagram after forming a second circuit pattern in an embodiment of the present invention;

[0044] Fig.11 is a schematic diagram of a structure after a first nickel-cobalt alloy layer is formed on a second circuit pattern in an embodiment of the present invention;

[0045] Fig.12 is a schematic structural diagram of the first nickel-cobalt alloy layer after planarization treatment in an embodiment of the present invention;

[0046] Fig.13 is a schematic structural diagram after a third circuit pattern is formed in an embodiment of the present invention;

[0047] Fig.14 is a schematic structural diagram of a second nickel-cobalt alloy layer formed on a third circuit pattern in an embodiment of the present invention;

[0048] Fig.15 is a schematic structural diagram of the second nickel-cobalt alloy layer after planarization treatment in an embodiment of the present invention;

[0049] Fig.16 is a schematic structural diagram after a fourth circuit pattern is formed in an embodiment of the present invention;

[0050] Fig.17 is a schematic structural diagram of forming a second gold layer on a fourth circuit pattern in an embodiment of the present invention;

[0051] Fig.18 Schematic diagram of the structure of the spatial converter of the probe card obtained in the embodiment of the present invention.

[0052] The figure includes: ceramic substrate 1, titanium layer 2, first copper layer 3, first photoresist layer 4, second copper layer 5, nickel layer 6, first gold layer 7, polyimide layer 8, second photoresist layer 9, first nickel-cobalt alloy layer 10, third photoresist layer 11, second nickel-cobalt alloy layer 12, fourth photoresist layer 13, second gold layer 14, first dry film 15, second dry film 16, third dry film 17, fourth dry film 18, and fifth dry film 19. DETAILED DESCRIPTION

[0053] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0054] An embodiment of the present invention provides a method for manufacturing a spatial transformer of a probe card, comprising the following steps:

[0055] Step 10, pre-treating the ceramic substrate 1. Preferably, the ceramic substrate 1 is a multi-layer ceramic, in which a plurality of interlayer molybdenum is formed.

[0056] Specifically include:

[0057] Step 101 , performing dry film lamination and exposure on the lower surface of the ceramic substrate 1 to passivate the lower surface of the ceramic substrate.

[0058] Using a laminating device, the pressing plate is heated to 100-110°C, 0.2-0.5 MPa is applied to the lower surface of the ceramic substrate 1 for dry film lamination, and then exposure is performed to cure the dry film to complete the passivation of the lower surface of the ceramic substrate. Figure 1 In the structure shown, a first dry film 15 is formed on the lower surface of the ceramic substrate 1. The first dry film 15 can protect the lower surface of the ceramic substrate during the polishing process of the ceramic substrate 1 in step 102 to prevent the lower surface of the ceramic substrate from being corroded.

[0059] Step 102 , polishing the upper surface of the ceramic substrate 1 .

[0060] Place the ceramic substrate on the tray, spray the grinding liquid between the ceramic substrate and the tray, and use the grinder to process the upper surface of the ceramic substrate. During the polishing process, the tray drives the ceramic substrate to rotate, and the polisher also rotates at the same speed. The ceramic substrate and the polisher rotate in the same direction.

[0061] Step 103, removing the dry film on the lower surface of the ceramic substrate, that is, removing Figure 1 The first dry film 15 in.

[0062] Step 20, sputtering to form a titanium layer 2 on the upper surface of the ceramic substrate 1, and sputtering to form a first copper layer 3 on the upper surface of the titanium layer 2, to obtain Figure 2 The structure shown.

[0063] Step 30, coating photoresist on the upper surface of the first copper layer 3 to form a first photoresist layer 4, and performing exposure and development to form a first circuit pattern.

[0064] Specifically, liquid photoresist is applied on the upper surface of the first copper layer 3. During the photoresist application process, the tray drives the ceramic substrate to rotate at a uniform speed of 1000 to 2000 rpm to make the photoresist layer uniform in thickness. After applying the photoresist, the ceramic substrate is pre-baked at a temperature of 90 to 110° C. to remove the liquid. According to the designed first circuit pattern, the exposure amount is set to meet the design requirements of the photolithography thickness and the first circuit pattern. The stencil corresponding to the designed first circuit pattern is covered on the first photoresist layer 4 and exposed. In order to remove the photoresist in the exposed area, tetramethylammonium hydroxide TMAH developer is used to develop by spraying and stirring to form the first circuit pattern. The remaining first photoresist layer is solidified by heating the ceramic substrate to harden the film.

[0065] Preferably, before applying photoresist on the upper surface of the first copper layer 3, the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure. Specifically, using a laminating device, the pressing plate is heated to 100-110°C, 0.2-0.5MPa is applied to the lower surface of the ceramic substrate for dry film lamination, and then exposure is performed to cure the dry film to complete the passivation of the lower surface of the ceramic substrate. Figure 3 In the structure shown, a second dry film 16 is formed on the lower surface of the ceramic substrate. The second dry film 16 can protect the lower surface of the ceramic substrate during the electroplating process in step 40.

[0066] Step 40, electroplating to form a second copper layer 5 on the first circuit pattern. Figure 4 The structure shown in FIG. is cleaned by pure water spraying and then dried. During the drying process, the ceramic substrate rotates at a constant speed of 500 to 1000 rpm to improve the drying efficiency.

[0067] Step 50, removing the first photoresist layer 4, obtaining Figure 5 The structure shown.

[0068] Specifically, firstly, the ceramic substrate is placed in an acetone solution and soaked at room temperature for 30 to 60 minutes, and the second dry film 16 on the lower surface of the ceramic substrate will fall off. Then, the ceramic substrate is placed in a photoresist remover and soaked at 50 to 60°C for 10 to 20 minutes to remove the first photoresist layer 4. Pure water is sprayed and then dried. During the drying process, the ceramic substrate rotates at a constant speed of 500 to 1000 rpm to improve the drying efficiency. Then, the ceramic substrate is heated in an oven to further remove moisture.

[0069] Step 60 , removing the titanium layer 2 and the first copper layer 3 except for the layer below the second copper layer 5 .

[0070] Preferably, a wet etching process is used to first etch and clean the first copper layer 3 , then etch and clean the titanium layer 2 , then etch and clean the first copper layer 3 , and finally etch and clean the titanium layer 2 .

[0071] Specifically, first Figure 5The structure shown is immersed in a mixed solution of acetic acid, hydrogen peroxide and DI for etching the first copper layer 3. Then, in the trough (QDR Bath), the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated many times. Finally, it is cleaned with DIW pure water. The cleaned structure is immersed in a mixed solution of Ti3991, hydrogen peroxide and DI for etching the titanium layer 2. Then, in the trough (QDR Bath), the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated many times. Finally, it is cleaned with DIW pure water. Repeat the etching process once more, that is, the cleaned structure is immersed in a mixed solution of acetic acid, hydrogen peroxide and DI for etching the first copper layer 3. Then, in the QDR Bath, the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated many times. Finally, it is cleaned with DIW pure water. The cleaned structure is immersed in a mixed solution of Ti3991, hydrogen peroxide and DI to etch the titanium layer 2. Then, in the QDR Bath, the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated many times. Finally, it is cleaned with DIW pure water.

[0072] Spray with pure water and then dry. During the drying process, the ceramic substrate rotates at a constant speed of 500 to 1000 rpm to improve the drying efficiency.

[0073] Preferably, after removing the titanium layer 2 and the first copper layer 3 except those located below the second copper layer 5, the lower surface of the ceramic substrate is subjected to dry film lamination and exposure to obtain a Figure 6 In the structure shown, a third dry film 17 is formed on the lower surface of the ceramic substrate. The third dry film 17 can protect the lower surface of the ceramic substrate during the electroplating process in step 70.

[0074] Step 70 , forming a nickel layer 6 by electroplating on the upper surface of the second copper layer 5 , and forming a first gold layer 7 by electroplating on the upper surface of the nickel layer 6 and around the titanium layer 2 , the first copper layer 3 , the second copper layer 5 and the nickel layer 6 .

[0075] Remove the third dry film 17 on the lower surface of the ceramic substrate to obtain Figure 7 The structure shown.

[0076] Specifically, the lower surface of the ceramic substrate is titrated with an acetone solution at room temperature, and then the ceramic substrate is placed in a photoresist remover and soaked at a temperature of 50 to 60° C. to remove the third dry film 17. Pure water is sprayed and then dried. During the drying process, the ceramic substrate rotates at a constant speed of 500 to 1000 rpm to improve the drying efficiency. The ceramic substrate is then heated in an oven to further remove moisture.

[0077] Step 80, a polyimide layer 8 is formed on the ceramic substrate 1 and the first gold layer 7 by coating. Figure 8 The structure shown.

[0078] Specifically, liquid polyimide is coated on the ceramic substrate 1 and the upper surface of the first gold layer 7. During the coating process, the tray drives the ceramic substrate to rotate at a constant speed of 1000-2000 rpm, so that the thickness of the formed polyimide layer is uniform. The thickness of the polyimide layer is about 30-40 um. The polyimide layer is heated to solidify.

[0079] Step 90, removing the polyimide layer 8 on the target position of the first gold layer 7, and obtaining Fig. 9 The target position of the first gold layer 7 corresponds to the installation position of the probe.

[0080] Specifically, ultraviolet light is used to remove the polyimide layer 8 on the upper surface of the target position of the first gold layer 7 .

[0081] Step 100, coating photoresist at the target position of the first gold layer 7 and the upper surface of the polyimide layer 8 to form a second photoresist layer 9, and performing exposure and development to form a second circuit pattern.

[0082] Specifically, a laminating device is used to heat a press plate, and a dry film is applied under pressure to the target position of the first gold layer 7 and the upper surface of the polyimide layer 8 to form a second photoresist layer 9. According to the designed second circuit pattern, the exposure amount is set to meet the requirements of the photolithography thickness and the designed second circuit pattern. A stencil corresponding to the designed second circuit pattern is covered on the second photoresist layer 9 and exposed. In order to remove the photoresist in the exposed area, a tetramethylammonium hydroxide TMAH developer is used to develop in a spraying and stirring manner to remove unnecessary photoresist and form a second circuit pattern. The second photoresist layer is hardened by heating the press plate.

[0083] Preferably, before applying the photoresist, the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure. Specifically, using a laminating device, the pressing plate is heated to 100-110°C, 0.2-0.5MPa is applied to the lower surface of the ceramic substrate for dry film lamination, and then exposure is performed to cure the dry film to complete the passivation of the lower surface of the ceramic substrate. Fig.10In the structure shown, a fourth dry film 18 is formed on the lower surface of the ceramic substrate. The fourth dry film 18 can protect the lower surface of the ceramic substrate during the electroplating process in step 110.

[0084] Preferably, after forming the second circuit pattern, a plasma surface treatment method is used to treat the surface of the second circuit pattern. The residual photoresist on the surface of the second circuit pattern is removed, so that the surface of the second circuit pattern changes from hydrophobic to hydrophilic. This is beneficial to the subsequent deposition of the first nickel-cobalt alloy layer and enhances the bonding force between the first nickel-cobalt alloy layer and the surface of the second circuit pattern.

[0085] Step 110, electroplating to form a first nickel-cobalt alloy layer 10 on the second circuit pattern, Fig.11 The structure shown.

[0086] Preferably, before electroplating on the second circuit pattern, the oxide film on the second circuit pattern is removed first, thereby ensuring the interface stability between the first nickel-cobalt alloy layer and the second circuit pattern.

[0087] Specifically, diluted 17% hydrochloric acid was used for titration at room temperature to remove the oxide film on the second circuit pattern. In order to remove the residual chemical reagents, the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble was repeated several times in the bath (QDR Bath), and finally washed with DIW pure water.

[0088] Preferably, before electroplating on the second circuit pattern, the first gold layer is immersed in a gold stripper to remove contaminants on the surface, and the process sequence of bubbling (Bubble) + supply (Supply) → drain (Drain) + shower (Shower) → supply (Supply) + bubbling (Bubble) is repeated for multiple times in the tank (QDR Bath), and finally cleaned with DIW pure water.

[0089] Preferably, before electroplating on the second circuit pattern, nickel is first plated on the surface of the second circuit pattern for the bonding of the first nickel-cobalt alloy interface. In the QDR Bath, the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated for multiple times, and finally washed with DIW pure water.

[0090] The first nickel-cobalt alloy layer 10 is planarized. Fig.12 The structure shown.

[0091] Specifically, the portion of the first nickel-cobalt alloy layer 10 that is higher than the target height is first ground, and then the metal chips are removed by soaking, and then the residual soaking liquid is removed, and finally the layer is cleaned.

[0092] In step 120, photoresist is coated on the upper surfaces of the first nickel-cobalt alloy layer 10 and the second photoresist layer 9 to form a third photoresist layer 11, and exposure and development are performed to form a third circuit pattern.

[0093] Specifically, a laminating device is used to heat a press plate, and a dry film is applied to the upper surface of the first nickel-cobalt alloy layer 10 and the second photoresist layer 9 under pressure to form a third photoresist layer 11. According to the designed third circuit pattern, the exposure amount is set to meet the requirements of the photolithography thickness and the designed third circuit pattern. A stencil corresponding to the designed third circuit pattern is covered on the third photoresist layer 11 and exposed. In order to remove the photoresist in the exposed area, a tetramethylammonium hydroxide TMAH developer is used to develop in a spraying and stirring manner to form a third circuit pattern. The third photoresist layer is hardened by heating the press plate to harden the film.

[0094] Preferably, before applying the photoresist, the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure. Specifically, using a laminating device, the pressing plate is heated to 100-110°C, 0.2-0.5MPa is applied to the lower surface of the ceramic substrate for dry film lamination, and then exposure is performed to cure the dry film to complete the passivation of the lower surface of the ceramic substrate. Fig.13 In the structure shown, a fifth dry film 19 is formed on the lower surface of the fourth dry film 18. The lower surface of the ceramic substrate has two layers of dry films, which are strong and can better protect the lower surface of the ceramic substrate in subsequent steps.

[0095] Preferably, after forming the third circuit pattern, a plasma surface treatment method is used to treat the surface of the third circuit pattern. The residual photoresist on the surface of the third circuit pattern is removed, so that the surface of the third circuit pattern changes from hydrophobic to hydrophilic. This is beneficial to the subsequent deposition of the second nickel-cobalt alloy layer and enhances the bonding force between the second nickel-cobalt alloy layer and the first nickel-cobalt alloy layer.

[0096] Step 130, electroplating to form a second nickel-cobalt alloy layer 12 on the third circuit pattern, to obtain Fig.14 The structure shown.

[0097] Preferably, before electroplating on the third circuit pattern, the oxide film on the third circuit pattern is removed first, thereby ensuring the interface stability between the second nickel-cobalt alloy layer and the third circuit pattern.

[0098] Specifically, a first oxide film removal process is performed.

[0099] The oxide film on the third circuit pattern is removed by titration with diluted 17% hydrochloric acid at room temperature. In order to remove the residual chemical reagents, the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated several times in the tank (QDR Bath), and DIW pure water is used for cleaning. In order to increase the bonding area between the second nickel-cobalt alloy layer and the first nickel-cobalt alloy layer, a reverse current is applied to the surface of the third circuit pattern for etching using an electrolytic degreasing process. In the tank (QDR Bath), the process sequence of Bubble + Supply → Drain + Shower → Supply + Bubble is repeated several times, and DIW pure water is used for cleaning.

[0100] A second treatment of oxide film removal is performed.

[0101] Titrate with diluted 17% hydrochloric acid at room temperature to remove the oxide film on the third circuit pattern. To remove the residual chemical reagents, repeat the process of Bubble + Supply → Drain + Shower → Supply + Bubble in the QDR Bath several times, and wash with DIW pure water. To increase the bonding area between the second nickel-cobalt alloy layer and the first nickel-cobalt alloy layer, repeat the process of Bubble + Supply → Drain + Shower → Supply + Bubble in the QDR Bath several times, and wash with DIW pure water.

[0102] The third treatment of oxide film removal is performed.

[0103] At room temperature, diluted 17% hydrochloric acid is used to titrate to remove the oxide film on the third circuit pattern. In order to remove the residual chemical reagents, the process sequence of bubble + supply → drain + shower → supply + bubble is repeated several times in the tank (QDR Bath), and DIW pure water is used for cleaning.

[0104] The second nickel-cobalt alloy layer 12 is planarized to obtain Fig.15 The structure shown.

[0105] Specifically, the portion of the second nickel-cobalt alloy layer 12 that is higher than the target height is first ground, and then the metal chips are removed by soaking, and then the residual soaking liquid is removed, and finally the layer is cleaned.

[0106] Step 140, coating photoresist on the second nickel-cobalt alloy layer 12 and the third photoresist layer 11 to form a fourth photoresist layer 13, and performing exposure and development to form a fourth circuit pattern.

[0107] Specifically, a laminating device is used to heat a press plate, and a dry film is applied to the upper surface of the second nickel-cobalt alloy layer 12 and the third photoresist layer 11 under pressure to form a fourth photoresist layer 13. According to the designed fourth circuit pattern, an exposure amount is set to meet the requirements of the photolithography thickness and the designed fourth circuit pattern. A stencil corresponding to the designed fourth circuit pattern is covered on the fourth photoresist layer 13 and exposed. In order to remove the photoresist in the exposed area, a tetramethylammonium hydroxide TMAH developer is used to develop in a spraying and stirring manner to form a fourth circuit pattern. The fourth photoresist layer is hardened by heating the press plate to harden the film.

[0108] Preferably, after forming the fourth circuit pattern, a plasma surface treatment method is used to treat the surface of the fourth circuit pattern. The residual photoresist on the surface of the fourth circuit pattern is removed, so that the surface of the fourth circuit pattern changes from hydrophobic to hydrophilic. This is beneficial to the subsequent deposition of the second gold layer and enhances the bonding force between the second gold layer and the second nickel-cobalt alloy layer.

[0109] Step 150, electroplating a second gold layer 14 on the fourth circuit pattern to obtain Fig.17 The structure shown.

[0110] Preferably, before electroplating on the fourth circuit pattern, the oxide film on the fourth circuit pattern is removed first, so as to ensure the interface stability between the second gold layer and the second nickel-cobalt alloy layer.

[0111] Specifically, an electrolytic degreasing process is used to apply a reverse current to the surface of the fourth circuit pattern for etching to increase the bonding area between the second gold layer and the second nickel-cobalt alloy layer, and hydrochloric acid titration is used to remove the oxide film on the fourth circuit pattern.

[0112] Step 160, remove the second photoresist layer 9, the third photoresist layer 11 and the fourth photoresist layer 13 to obtain a spatial converter of the probe card, such as Fig.18 shown.

[0113] Specifically, first Fig.17The structure shown is placed in an acetone solution and soaked for 30 to 60 minutes at room temperature. The dry film on the lower surface of the ceramic substrate will fall off. Then it is placed in a photoresist remover and soaked for 10 to 20 minutes at 50 to 60°C to remove all photoresist layers. It is sprayed with pure water and then dried. During the drying process, the ceramic substrate rotates at a constant speed of 500 to 1000 rpm to improve the drying efficiency. It is then heated in an oven to further remove moisture.

[0114] The space transformer manufactured by the method of the embodiment of the present invention is as follows: Fig.18 As shown. The titanium layer 2, the first copper layer 3, the second copper layer 5, the nickel layer 6, the first gold layer 7, the first nickel-cobalt alloy layer 10, the second nickel-cobalt alloy layer 12 and the second gold layer 14 arranged on the ceramic substrate 1 from bottom to top constitute a probe connection structure. Multiple probes are installed on the probe connection structure, one end of the probe is bonded to the second gold layer 14, and is connected to the second nickel-cobalt alloy layer 12 and the first nickel-cobalt alloy layer 10. The second gold layer 14 located at the top is not easy to oxidize, which enhances the binding ability of the probe. The second nickel-cobalt alloy layer 12 and the first nickel-cobalt alloy layer 10 can play a supporting role when the probe tip is subjected to excessive pressure, and can also meet the height requirements of the probe connection structure. The polyimide layer 8 protects the structural parts formed by the titanium layer 2, the first copper layer 3, the second copper layer 5, the nickel layer 6 and the first gold layer 7 covered by it to prevent them from being damaged. The first copper layer 3 and the second copper layer 5 are arranged to play a conductive role. The titanium layer 2 is arranged between the copper layer and the ceramic substrate to enhance the bonding force between the first copper layer 3 and the ceramic substrate 1. A nickel layer 6 and a first gold layer 7 are arranged between the second copper layer 5 and the first nickel-cobalt alloy layer 10 . The first gold layer 7 can enhance the bonding force with the first nickel-cobalt alloy layer 10 and reduce impedance. The nickel layer 6 can protect the second copper layer 5 .

[0115] This application uses multilayer ceramics to minimize signal distortion, improve the positioning accuracy of the probe, and improve the transmission performance of high-speed signals. Through the design of the multilayer structure, various circuits and connecting electrical graphics can be integrated, so that the arrangement of the probes can be adjusted more accurately, the alignment problems that may occur on the existing single-layer substrate can be minimized, and the high-density test points of the wafer can be accurately matched. The use of a multilayer ceramic structure can reduce electrical interference, maintain the quality of the test signal, and can flexibly respond to various wafer designs. The use of a multilayer ceramic spatial converter solves the problems of signal distortion and poor contact that may occur in conventional probe cards. Due to its inherent electrothermal properties, multilayer ceramics can provide the low loss and high insulation properties required for high-speed signal transmission, greatly improving the performance of the probe card.

[0116] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for manufacturing a space transformer of a probe card, characterized in that: The following steps are involved: Step 10, pre-treating the ceramic substrate (1); Step 20, sputtering to form a titanium layer (2) on the upper surface of the ceramic substrate (1), and sputtering to form a first copper layer (3) on the upper surface of the titanium layer (2); Step 30, coating a photoresist on the upper surface of the first copper layer (3) to form a first photoresist layer (4), and performing exposure and development to form a first circuit pattern; Step 40, forming a second copper layer (5) by electroplating on the first circuit pattern; Step 50, removing the first photoresist layer (4); Step 60, removing the titanium layer (2) and the first copper layer (3) except for the layer below the second copper layer (5); Step 70, electroplating a nickel layer (6) on the upper surface of the second copper layer (5), and electroplating a first gold layer (7) on the upper surface of the nickel layer (6) and around the titanium layer (2), the first copper layer (3), the second copper layer (5) and the nickel layer (6); Step 80, coating the ceramic substrate (1) and the first gold layer (7) to form a polyimide layer (8); Step 90, removing the polyimide layer (8) on the upper surface of the target position of the first gold layer (7); Step 100, coating a photoresist at a target position of the first gold layer (7) and on the upper surface of the polyimide layer (8) to form a second photoresist layer (9), and performing exposure and development to form a second circuit pattern; Step 110, forming a first nickel-cobalt alloy layer (10) by electroplating on the second circuit pattern, and performing a planarization process on the first nickel-cobalt alloy layer (10); Step 120, coating a photoresist on the upper surface of the first nickel-cobalt alloy layer (10) and the second photoresist layer (9) to form a third photoresist layer (11), and performing exposure and development to form a third circuit pattern; Step 130, forming a second nickel-cobalt alloy layer (12) by electroplating on the third circuit pattern, and performing a planarization process on the second nickel-cobalt alloy layer (12); Step 140, coating photoresist on the upper surfaces of the second nickel-cobalt alloy layer (12) and the third photoresist layer (11) to form a fourth photoresist layer (13), and performing exposure and development to form a fourth circuit pattern; Step 150, forming a second gold layer (14) by electroplating on the fourth circuit pattern; Step 160 , removing all photoresist layers to obtain the spatial transformer of the probe card.

2. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: The ceramic substrate (1) is made of multilayer ceramics.

3. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: The step 10 specifically comprises: laminating and exposing the lower surface of the ceramic substrate (1) with a dry film; polishing the upper surface of the ceramic substrate (1); and removing the dry film on the lower surface of the ceramic substrate.

4. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: In the step 30, before applying photoresist on the upper surface of the first copper layer (3), the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure; in the step 100, before applying photoresist on the target position of the first gold layer (7) and the upper surface of the polyimide layer (8), the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure; in the step 120, before applying photoresist on the upper surface of the first nickel-cobalt alloy layer (10) and the second photoresist layer (9), the lower surface of the ceramic substrate is first subjected to dry film lamination and exposure.

5. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: In step 60, a wet etching process is used to firstly etch and clean the first copper layer (3), then etch and clean the titanium layer (2), then etch and clean the first copper layer (3), and finally etch and clean the titanium layer (2).

6. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: In step 60, after removing the titanium layer (2) and the first copper layer (3) except those located below the second copper layer (5), the lower surface of the ceramic substrate is subjected to dry film lamination and exposure.

7. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: In step 100, after forming the second circuit pattern, a plasma surface treatment method is used to treat the surface of the second circuit pattern; in step 120, after forming the third circuit pattern, a plasma surface treatment method is used to treat the surface of the third circuit pattern; in step 140, after forming the fourth circuit pattern, a plasma surface treatment method is used to treat the surface of the fourth circuit pattern.

8. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: In step 110, before electroplating on the second circuit pattern, the oxide film on the second circuit pattern is first removed; in step 130, before electroplating on the third circuit pattern, the oxide film on the third circuit pattern is first removed; in step 150, before electroplating on the fourth circuit pattern, the oxide film on the fourth circuit pattern is first removed.

9. The method for manufacturing a spatial transformer of a probe card according to claim 8, characterized in that: In step 130, when removing the oxide film on the second circuit pattern, the oxide film removal process is performed at least three times.

10. The method for manufacturing a spatial transformer of a probe card according to claim 1, characterized in that: In the step 110, the first nickel-cobalt alloy layer (10) is planarized, specifically comprising: Firstly, the portion of the first nickel-cobalt alloy layer (10) that is higher than the target height is ground, then the metal chips are removed by soaking, then the residual soaking liquid is removed, and finally, the layer is cleaned; In the step 130, the second nickel-cobalt alloy layer (12) is planarized, specifically comprising: First, the portion of the second nickel-cobalt alloy layer (12) that is higher than the target height is ground, then the metal chips are removed by soaking, then the residual soaking liquid is removed, and finally, the layer is cleaned.

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