Integrated chip with calibration function and chip calibration method

Abstract

The invention discloses an integrated chip with a calibration function and a chip calibration method, and belongs to the field of semiconductors. The storage module is used for storing the target identifier and a target parameter for adjusting an analog circuit of the integrated chip; wherein the target identifier is used for representing whether the target parameter passes the CP test and the FT test; the signal control module is arranged in the digital circuit of the integrated chip and is used for reading the target identifier and comparing the target identifier with a preset identifier; when the target identifier is consistent with the preset identifier, judging that the target parameter passes the CP test and the FT test, and sending the target parameter to an analog circuit; or, when the target identifier is inconsistent with the preset identifier, determining that the target parameter does not pass the CP test and the FT test, and sending the preset parameter to the analog circuit; the target parameter and the preset parameter are both used for ensuring normal work of the integrated chip. Through the method, the yield of the chips in the test stage can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an integrated chip with a calibration function and a chip calibration method. Background Art

[0002] There will be deviations in the process of integrated chip production, which will cause parameter deviations such as power supply voltage and clock frequency in the integrated chip. Therefore, it is necessary to adjust the parameters of the integrated chip during the CP test (Chip Probing) and FT test (Final Test) stages so that the integrated chip can operate under accurate and reliable performance parameters.

[0003] Under normal circumstances, the parameters that have been tested by CP and FT will be stored in the memory of the integrated chip, so that when the integrated chip is powered on, the tested parameters can be imported from the memory into the actual working circuit of the integrated chip, and the circuit of the integrated chip can be guaranteed to operate normally and stably. However, when some process manufacturers produce integrated chips, the parameters stored in their memories have not been tested by CP and FT, and some parameters are stored randomly. In this case, if the parameters that have not been tested by CP and FT are directly imported into the integrated chip, there is a risk that the circuit of the integrated chip cannot operate normally, reducing the yield rate of the integrated chip. At present, there is no more effective solution to this technical problem.

[0004] It can be seen that how to improve the yield rate of integrated chips is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide an integrated chip with a calibration function and a chip calibration method to solve the problem of low yield rate of integrated chips in the prior art. The specific scheme is as follows:

[0006] In order to solve the above technical problems, the present invention provides an integrated chip with a calibration function, comprising:

[0007] Analog circuits;

[0008] A storage module, used to store a target identifier and a target parameter for adjusting the analog circuit of the integrated chip; wherein the target identifier is used to indicate whether the target parameter passes the CP test and the FT test;

[0009] A signal control module is arranged in the digital circuit of the integrated chip, and is used to read the target identifier and compare it with a preset identifier; when the target identifier is consistent with the preset identifier, it is determined that the target parameter has passed the CP test and the FT test, and the target parameter is sent to the analog circuit; or, when the target identifier is inconsistent with the preset identifier, it is determined that the target parameter has not passed the CP test and the FT test, and the preset parameter is sent to the analog circuit; both the target parameter and the preset parameter are used to ensure the normal operation of the integrated chip.

[0010] Preferably, the signal control module comprises: a first signal selector, a second signal selector and a signal control submodule; the signal control submodule is used for determining that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, sending an enable signal to the signal selection port of the first signal selector, and parsing the target parameter to obtain a target parsed parameter;

[0011] Among them, the input end of the signal control submodule is connected to the storage module, the output end of the signal control submodule is respectively connected to the signal selection port of the first signal selector, the output end of the first signal selector is connected to the signal selection port of the second signal selector, and the output end of the second signal selector is connected to the analog circuit; the first input end of the second signal selector is used to receive the preset parameters, and the second input end of the second signal selector is used to receive the target analysis parameters.

[0012] Preferably, the signal control submodule includes:

[0013] a control unit, configured to determine that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, send an enable signal to the signal selection port of the first signal selector, and send the target parameter to the parsing unit;

[0014] The parsing unit is used to parse the target parameter to obtain the target parsing parameter.

[0015] Preferably, the storage module includes:

[0016] A first storage unit, configured to store the target identifier;

[0017] The second storage unit is used to store the target parameters for adjusting the integrated chip.

[0018] Preferably, it also includes:

[0019] A software trigger module is provided in the digital circuit and is used for sending the target parameters after the CP test and the FT test to the analog circuit.

[0020] Preferably, the software trigger module comprises: a third signal selector, an OR gate and a central processing unit, wherein the central processing unit sends an enable signal to a signal selection port of the third signal selector;

[0021] The signal output end of the third signal selector is connected to the first input end of the OR gate, and the output end of the first signal selector is connected to the signal selection port of the second signal selector through the OR gate.

[0022] Preferably, the central processing unit is controlled by a software application.

[0023] Preferably, the debugging effect of the target parameter is better than that of the preset parameter.

[0024] Preferably, the complexity of the preset identifier is inversely correlated with the probability of failure of the integrated chip.

[0025] In order to solve the above technical problems, the present invention also provides a chip calibration method, wherein the chip has completed CP test and FT test, and the calibration method comprises the following steps performed in sequence:

[0026] Step S201: determine whether the target identifier of the memory in the integrated chip is consistent with the preset identifier; if so, execute step S202; if not, execute step S204;

[0027] Step S202: sending target parameters to the analog circuit of the integrated chip;

[0028] Step S203: the integrated chip operates with the target parameters;

[0029] Step S204: Sending instructions to the central processing unit through the software application;

[0030] Step S205: the central processing unit controls the analog circuit of the integrated chip to operate under the target parameters;

[0031] Step S206: the integrated chip operates with the target parameters.

[0032] Beneficial effect: In the integrated chip with calibration function provided by the present invention, an analog circuit, a storage module and a digital circuit are set in the integrated chip, and a signal control module is set in the digital circuit. Among them, the storage module is used to store the target identifier and the target parameters for adjusting the integrated chip. The target identifier is used to characterize whether the target parameter has passed the CP test and the FT test. When the signal control module determines that the target identifier in the storage module is consistent with the preset identifier, it means that the target parameter in the storage module has passed the CP test and the FT test. At this time, the signal control module will send the target parameters that have passed the CP test and the FT test to the analog circuit for use by the analog circuit. When the signal control module determines that the target identifier in the target storage module is inconsistent with the preset identifier, it means that the target parameters in the storage module have not passed the CP test and the FT test, and are some parameters stored randomly. At this time, the signal control module will send the preset parameters used to trigger the normal operation of the integrated chip to the analog circuit, thereby ensuring the normal operation of the integrated chip.

[0033] Under this setting architecture, the integrated chip can avoid the phenomenon that the parameters randomly stored in the memory enter the analog circuit no matter before or after the CP test and the FT test. Therefore, this architecture can ensure that the integrated chip can operate normally and stably, thereby further improving the yield rate of the integrated chip in the testing phase.

[0034] Correspondingly, a chip calibration method provided by the present invention also has the above beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0036] Figure 1 A structural diagram of an integrated chip with a calibration function provided by an embodiment of the present invention;

[0037] Figure 2 A structural diagram of another integrated chip with a calibration function provided by an embodiment of the present invention;

[0038] Figure 3 A structural diagram of another integrated chip with a calibration function provided by an embodiment of the present invention;

[0039] Figure 4The present invention provides a flowchart of an integrated chip with a calibration function performing a calibration function. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] See also Figure 1 , Figure 1 A structural diagram of an integrated chip with a calibration function provided by an embodiment of the present invention, the chip includes:

[0042] Analog circuit 11;

[0043] The storage module 12 is used to store a target identifier and a target parameter for adjusting the analog circuit of the integrated chip; wherein the target identifier is used to indicate whether the target parameter passes the CP test and the FT test;

[0044] The signal control module 14 is arranged in the digital circuit 13 of the integrated chip, and is used to read the target identifier and compare it with the preset identifier; when the target identifier is consistent with the preset identifier, it is determined that the target parameter has passed the CP test and the FT test, and the target parameter is sent to the analog circuit 11; or, when the target identifier is inconsistent with the preset identifier, it is determined that the target parameter has not passed the CP test and the FT test, and the preset parameter is sent to the analog circuit 11; both the target parameter and the preset parameter are used to ensure the normal operation of the integrated chip.

[0045] In this embodiment, an integrated chip with a calibration function is provided, which can reduce the probability of producing defective chips in the test link. The integrated chip with a calibration function is provided with an analog circuit 11, a storage module 12 and a digital circuit 13, and a signal control module 14 is provided in the digital circuit 13.

[0046] Specifically, the storage module 12 stores a target identifier and target parameters for adjusting the integrated chip. The storage module 12 can be either an Eflash (Embedded Flash) or an OTP (One Time Programable) or other storage medium. The target identifier is used to characterize whether the target parameter has passed the CP test and the FT test. That is, if the target identifier is consistent with the preset identifier, it means that the target parameters stored in the storage module 12 have passed the CP test and the FT test. If the target identifier is inconsistent with the preset identifier, it means that the target parameters stored in the storage module 12 are some randomly generated parameters. When these parameters enter the analog circuit 11 of the integrated chip, the normal and stable operation of the integrated chip cannot be guaranteed.

[0047] When the signal control module 14 determines that the target identifier in the storage module 12 is consistent with the preset identifier, it means that the target parameters in the storage module 12 have passed the CP test and the FT test, and the signal control module 14 will send the target parameters that have passed the CP test and the FT test to the analog circuit 11. The analog circuit 11 uses the target parameters that have passed the CP test and the FT test to avoid parameter deviations such as the power supply voltage and the clock frequency in the integrated chip, thereby ensuring the operating performance of the integrated chip.

[0048] When the signal control module 14 determines that the target identifier in the target storage module 12 is inconsistent with the preset identifier, it means that the target parameters in the storage module 12 have not passed the CP test and the FT test, and are some randomly generated parameters. At this time, the preset parameters used to trigger the normal operation of the integrated chip can be sent to the analog circuit 11, thereby ensuring the normal operation of the integrated chip.

[0049] It should be noted that the target parameters that have undergone CP testing and FT testing can ensure that the integrated chip works in a more stable and excellent state, while the preset parameters are some parameters set in advance. These parameters are generally in the middle value. When the process deviation of the integrated chip is not particularly large, the preset parameters can make the integrated chip work normally, but not at the optimal operating parameters.

[0050] In addition, it should be noted that the integrated chip described in the present application can be a TP IC chip (Touch Panel Driver Integrated Circuit) or other types of chips. As long as the parameters stored in the control memory of the integrated chip are imported into the analog circuit 11 of the integrated chip for parameter adjustment under the premise of meeting the conditions during operation, the calibration architecture provided in the present application can be used.

[0051] Obviously, under this setting architecture, the integrated chip can avoid importing the parameters randomly stored in the memory into the analog circuit regardless of whether it is before the CP test and the FT test or after the CP test and the FT test. Therefore, this architecture can ensure that the integrated chip can operate normally and stably, thereby further improving the yield rate of the integrated chip in the test link.

[0052] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the storage module 12 includes:

[0053] A first storage unit, used to store a target identifier;

[0054] The second storage unit is used to store target parameters for adjusting the integrated chip.

[0055] In this embodiment, in order to make the execution logic of the signal control module 14 clearer and more orderly, the storage module 12 can also be divided into a first storage unit and a second storage unit. The first storage unit is used to store the target identifier, and the second storage unit is used to store the target parameters for adjusting the integrated chip.

[0056] As a preferred implementation, the signal control module 14 includes: a first signal selector MUX1, a second signal selector MUX2 and a signal control submodule 100; the signal control submodule 100 is used to determine that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, send an enable signal to the signal selection port of the first signal selector MUX1, and parse the target parameter to obtain the target parsed parameter;

[0057] Among them, the input end of the signal control submodule 100 is connected to the storage module 12, the output end of the signal control submodule 100 is respectively connected to the signal selection port of the first signal selector MUX1, the output end of the first signal selector MUX1 is connected to the signal selection port of the second signal selector MUX2, and the output end of the second signal selector MUX2 is connected to the analog circuit 11; the first input end of the second signal selector MUX2 is used to receive preset parameters, and the second input end of the second signal selector MUX2 is used to receive target analysis parameters.

[0058] In this embodiment, the internal structure of the signal control module 14 is specifically described. The signal control module 14 is provided with a first signal selector MUX1 , a second signal selector MUX2 and a signal control submodule 100 .

[0059] Assume that the storage module is an N-bit register, and the names of these N registers are reg0, reg1, reg2, ... regN-1, regN. Among them, register reg0 is used to store the target identifier, and the other registers except register reg0 are used to store the target parameters. In this case, register reg0 is the first storage unit, and the other registers except register reg0 are the second storage unit.

[0060] If the target identifier stored in the first storage unit is defined as whether to turn on the switch to import the target parameters into the analog circuit 11, and the preset identifier is set to 16'h5aa5. Then when the target identifier stored in the first storage unit is equal to the preset identifier 16'h5aa5, it means that the target parameters stored in the second storage unit have passed the CP test and the FT test, and the target parameters stored in the second storage unit can be sent to the analog circuit 11. When the target identifier stored in the first storage unit is not equal to the preset identifier 16'h5aa5, it means that the target parameters stored in the second storage unit have not passed the CP test and the FT test. At this time, the target parameters stored in the second storage unit cannot be sent to the analog circuit 11, and only the preset parameter default_code can be sent to the analog circuit 11.

[0061] Specifically, when the signal control submodule 100 detects that the target identifier stored in the first storage unit in the memory 12 is consistent with the preset identifier 16'h5aa5, it means that the target parameter stored in the first storage unit has passed the CP test and the FT test. At this time, the signal control submodule 100 will send an enable signal to the signal selection port of the first signal selector MUX1, so that the output signal trimcode_enable_hw of the first signal selector MUX1 is high. When the output signal trimcode_enable_hw of the first signal selector MUX1 is high, it is equivalent to the first signal selector MUX1 sending an enable signal to the signal selection port of the second signal selector MUX2. At this time, the second signal selector MUX2 will receive the target parsing parameter trim_code output by the signal control submodule 100, and send the target parsing parameter trim_code to the analog circuit 11 of the integrated chip, so that the integrated chip can use the target parameters that have passed the CP test and the FT test to better tune the parameters of the integrated chip.

[0062] When the signal control submodule 100 detects that the target identifier stored in the first storage unit in the memory is inconsistent with the preset identifier 16'h5aa5, it means that the target parameters stored in the first storage unit have not passed the CP test and the FT test, and are still some random parameters. At this time, the second signal selector MUX2 will receive the preset parameter default_code by default, and send the preset parameter default_code to the analog circuit 11 of the integrated chip, so as to ensure the normal operation of the integrated circuit.

[0063] As a preferred implementation, the signal control submodule 100 includes:

[0064] The control unit 101 is used for determining that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, sending an enable signal to the signal selection port of the first signal selector MUX1, and sending the target parameter to the parsing unit 102;

[0065] The parsing unit 102 is used to parse the target parameters to obtain target parsing parameters.

[0066] In this embodiment, a control unit 101 and a parsing unit 102 may also be provided in the signal control submodule 100. When the control unit 101 detects that the target identifier stored in the memory is consistent with the preset identifier, it indicates that the target parameter stored in the memory has passed the CP test and the FT test. At this time, the control unit 101 may send an enable signal to the signal selection port of the first signal selector MUX1, and send the target parameter that has passed the CP test and the FT test to the parsing unit 102. When the parsing unit 102 receives the target parameter sent by the control unit 101, the parsing unit 102 will parse the target parameter to obtain the target parsing parameter trim_code.

[0067] Obviously, through the technical solution provided in this embodiment, the target parameters that have passed the CP test and the FT test can be quickly imported into the analog circuit of the integrated circuit through hardware methods.

[0068] As a preferred implementation, the calibration device further includes:

[0069] The software trigger module 15 is disposed in the digital circuit 13 and is used to send the target parameters after the CP test and the FT test to the analog circuit 11 .

[0070] In practical applications, in addition to using the signal control module 14 in hardware form to import the target parameters that have undergone the CP test and the FT test into the analog circuit 11 of the integrated chip, the target parameters that have undergone the CP test and the FT test can also be imported into the analog circuit 11 of the integrated chip in the form of software. Specifically, a software trigger module 15 can be set in the digital circuit 13 of the integrated chip, and the software trigger module 15 can be used to send the target parameters that have undergone the CP test and the FT test to the analog circuit 11 of the integrated chip.

[0071] See also Figure 3 , Figure 3 A structural diagram of another integrated chip with calibration function provided by an embodiment of the present invention. As a preferred implementation, the software trigger module 15 includes: a third signal selector MUX3, an OR gate OR, and a central processor 103, the central processor 103 sends an enable signal to the signal selection port of the third signal selector MUX3;

[0072] The signal output end of the third signal selector MUX3 is connected to the first input end of the OR gate OR, and the output end of the first signal selector MUX1 is connected to the signal selection port of the second signal selector MUX2 through the OR gate OR.

[0073] In this embodiment, the software trigger module 15 is specifically described. The software trigger module 15 is provided with a central processing unit 103 (CPU), a third signal selector MUX3 and an OR gate OR.

[0074] In actual applications, if it is encountered that although the target parameters in the storage module 12 have passed the CP test and the FT test, due to some reasons, these parameters cannot be imported into the analog circuit 11 of the integrated chip through the signal control module 14 in hardware form, at this time, the target parameters that have passed the CP test and the FT test can be imported into the analog circuit 11 of the integrated chip through the software trigger module 15.

[0075] Specifically, when the target identifier is consistent with the preset identifier, the central processor 103 can send an enable signal to the signal selection port of the third signal selector MUX3, so that the output signal trimcode_enable_sw of the third signal selector MUX3 is a high-level signal. In this case, the OR gate OR will output a high-level signal, and the second signal selector MUX2 will send the target parameters that pass the CP test and the FT test to the analog circuit 11, so that the integrated chip can use the target parameters that pass the CP test and the FT test to adjust the parameters, thereby ensuring the stable and reliable operation of the integrated chip.

[0076] Obviously, through the technical solution provided in this embodiment, the target parameters that pass the CP test and the FT test can be sent to the analog circuit of the integrated chip through a software control method.

[0077] In actual applications, the central processor 103 can be controlled by a software application. The software application can be an APP (Application) application or a boot application. In this setting mode, when the software application is running, the target parameters that pass the CP test and the FT test can be sent to the analog circuit 11 of the integrated chip through the central processor 103.

[0078] Obviously, through the technical solution provided by this embodiment, the convenience of sending adjustment parameters to the analog circuit of the integrated chip can be further improved.

[0079] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the integrated chip is specifically a TP IC. TP IC chips are very common in smart phones, tablet computers, touch screen computers and other touch devices. The TP IC chip is a mixed digital-analog SOC (System on Chip) chip. The main function of its internal analog circuit is to control each sensor element on the touch screen. It also provides power, clock and other signals for the digital circuit, thereby ensuring the normal and stable operation of the digital circuit.

[0080] Since the TP IC chip may have process deviations during the production process, this will cause the power supply voltage, clock frequency and other parameters in the TPIC chip to shift, thereby affecting the operating performance of the TP IC chip. The TPIC provided in this application can avoid the random stored parameters from being imported into the actual working circuit of the TP IC chip, affecting the stable operation of the TP IC chip.

[0081] In addition, it should be noted that in this application, the tuning effect of the target parameters is better than that of the preset parameters. That is, the preset parameters are some parameters set in advance, which are generally at intermediate values. When the process deviation of the integrated chip is not particularly large, the preset parameters can make the integrated chip work normally, but not at the optimal operating parameters. After the target parameters pass the CP test and the FT test, the target parameters are imported into the analog circuit of the integrated chip, which can ensure that the integrated chip works in the optimal working state.

[0082] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation method, the complexity of the preset identifier is inversely correlated with the probability of failure of the integrated chip. That is, the higher the complexity of the preset identifier, the lower the probability of failure of the integrated chip. Conversely, the lower the complexity of the preset identifier, the higher the probability of failure of the integrated chip. It is not difficult to imagine that if the complexity of the preset identifier is higher, the target identifier randomly stored in the memory of the integrated chip will hardly be consistent with the preset identifier. In this way, the probability of the integrated chip being misjudged as a good product can be further reduced.

[0083] See also Figure 4 , Figure 4 The present invention provides a flowchart of an integrated chip with a calibration function performing a calibration function. The integrated chip has passed the CP test and the FT test. The calibration method includes the following steps in sequence:

[0084] Step S201: determine whether the target identifier of the memory in the integrated chip is consistent with the preset identifier; if so, execute step S202; if not, execute step S204;

[0085] Step S202: sending target parameters to the analog circuit of the integrated chip;

[0086] Step S203: the integrated chip operates with target parameters;

[0087] Step S204: Sending instructions to the central processing unit through the software application;

[0088] Step S205: the central processing unit controls the analog circuit of the integrated chip to operate under target parameters;

[0089] Step S206: the integrated chip operates with target parameters.

[0090] After the integrated chip passes the CP test and the FT test, if the target identifier in the memory is inconsistent with the preset identifier, it means that due to some abnormal reasons, the target parameters that have passed the CP test and the FT test cannot be sent to the analog circuit of the integrated chip through the signal control module in the form of hardware. In this case, the parameters that have passed the CP test and the FT test can be sent to the analog circuit of the integrated chip manually in the form of software triggering, and the integrated chip can be adjusted with the target parameters that have passed the CP test and the FT test, thereby ensuring the stable and reliable operation of the integrated chip.

[0091] In addition, in the prior art, in order to prevent parameters that have not been tested by CP and FT from directly entering the analog circuit of the integrated chip, which may cause the integrated chip to malfunction, a particularly complex circuit is sometimes designed to avoid the above-mentioned problem. However, the more complex the circuit structure is, the more likely it is to have omissions in the design. In this way, it is still impossible to 100% avoid the introduction of random parameters into the analog circuit of the integrated chip, and it is impossible to ensure the stable and reliable operation of the integrated chip.

[0092] The calibration architecture provided by the present application can avoid importing the parameters randomly stored in the memory into the analog circuit of the integrated chip with a relatively simple circuit structure. In addition, the calibration architecture provided by the present application can import the target parameters after CP test and FT test into the analog circuit of the integrated chip by hardware method, and can also import the preset parameters after CP test and FT test into the analog circuit of the integrated chip by software method, thereby further improving the stability and reliability of the integrated chip during operation.

[0093] Obviously, the technical solution provided in this embodiment can reduce the probability of the integrated chip being introduced into a defective product due to random parameters during the test phase, and can also improve the stability and reliability of the integrated chip during operation.

[0094] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0095] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0096] The above is a detailed introduction to an integrated chip with a calibration function and a chip calibration method provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An integrated chip with calibration function, characterized in that: include: Analog circuits; A storage module, used to store a target identifier and a target parameter for adjusting the analog circuit of the integrated chip; wherein the target identifier is used to indicate whether the target parameter passes the CP test and the FT test; A signal control module is arranged in the digital circuit of the integrated chip, and is used to read the target identifier and compare it with a preset identifier; when the target identifier is consistent with the preset identifier, it is determined that the target parameter has passed the CP test and the FT test, and the target parameter is sent to the analog circuit; or, when the target identifier is inconsistent with the preset identifier, it is determined that the target parameter has not passed the CP test and the FT test, and the preset parameter is sent to the analog circuit; both the target parameter and the preset parameter are used to ensure the normal operation of the integrated chip.

2. The integrated chip with calibration function according to claim 1, characterized in that: The signal control module comprises: a first signal selector, a second signal selector and a signal control submodule; the signal control submodule is used to determine that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, send an enable signal to the signal selection port of the first signal selector, and parse the target parameter to obtain a target parsed parameter; Among them, the input end of the signal control submodule is connected to the storage module, the output end of the signal control submodule is respectively connected to the signal selection port of the first signal selector, the output end of the first signal selector is connected to the signal selection port of the second signal selector, and the output end of the second signal selector is connected to the analog circuit; the first input end of the second signal selector is used to receive the preset parameters, and the second input end of the second signal selector is used to receive the target analysis parameters.

3. The integrated chip with calibration function according to claim 2, characterized in that: The signal control submodule includes: a control unit, configured to determine that the target parameter passes the CP test and the FT test when the target identifier is consistent with the preset identifier, send an enable signal to the signal selection port of the first signal selector, and send the target parameter to the parsing unit; The parsing unit is used to parse the target parameter to obtain the target parsing parameter.

4. The integrated chip with calibration function according to claim 2, characterized in that: The storage module comprises: A first storage unit, configured to store the target identifier; The second storage unit is used to store the target parameters for adjusting the integrated chip.

5. The integrated chip with calibration function according to claim 2, characterized in that: Also includes: A software trigger module is provided in the digital circuit and is used for sending the target parameters after the CP test and the FT test to the analog circuit.

6. The integrated chip with calibration function according to claim 5, characterized in that: The software trigger module includes: a third signal selector, an OR gate and a central processing unit, wherein the central processing unit sends an enable signal to a signal selection port of the third signal selector; The signal output terminal of the third signal selector is connected to the first input terminal of the OR gate, and the output terminal of the first signal selector is connected to the signal selection port of the second signal selector through the OR gate.

7. The integrated chip with calibration function according to claim 6, characterized in that: The central processing unit is controlled by a software application.

8. The integrated chip with calibration function according to claim 1, characterized in that: The debugging effect of the target parameters is better than that of the preset parameters.

9. An integrated chip with calibration function according to any one of claims 1 to 8, characterized in that: The complexity of the preset identifier is inversely correlated with the probability of failure of the integrated chip.

10. A chip calibration method, wherein the chip has completed CP test and FT test, characterized in that: The calibration method comprises the following steps which are performed in sequence: Step S201: determine whether the target identifier of the memory in the integrated chip is consistent with the preset identifier; if so, execute step S202; if not, execute step S204; Step S202: sending target parameters to the analog circuit of the integrated chip; Step S203: the integrated chip operates with the target parameters; Step S204: Sending instructions to the central processing unit through the software application; Step S205: the central processing unit controls the analog circuit of the integrated chip to operate under the target parameters; Step S206: the integrated chip operates with the target parameters.

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