A Fault Sensitivity Calculation Method Based on Voltage Glitch

Abstract

The present application is applicable to the field of chip testing technology, and in particular to a method for calculating fault sensitivity based on voltage glitches, the method comprising: obtaining parameter scanning information of a security chip, and determining multiple voltage glitches parameter combinations of the security chip based on the parameter scanning information, so as to improve test efficiency and coverage; controlling a glitch injection device to inject glitches into the security chip according to each voltage glitches parameter combination of the security chip, and obtaining the number of fault occurrences corresponding to each voltage glitches parameter combination, so as to ensure the accuracy and repeatability of the test results; determining the fault sensitivity corresponding to each voltage glitches parameter combination based on the number of fault occurrences corresponding to each voltage glitches parameter combination; determining the test result of the security chip according to the fault sensitivity corresponding to each voltage glitches parameter combination, quickly identifying the parameter combinations and conditions under which the chip is vulnerable to attack, and providing clear guidance and data support for chip design optimization and protection improvement.

Description

Technical Field

[0001] The present application belongs to the field of chip testing technology, and in particular relates to a fault sensitivity calculation method based on voltage glitch. Background Art

[0002] With the growing demand for information security, integrated circuits and security chips have been widely used in various applications, such as smart cards, payment terminals, encryption devices, etc. However, these security chips face different types of physical attack threats, among which voltage fault injection (VFI) attack is a common fault injection attack method. The attacker briefly applies glitches to the power supply voltage of the chip during its operation, interfering with its normal operation, trying to cause it to produce erroneous outputs or leak sensitive information during execution. Fault injection testing based on voltage glitches can help the design team identify and improve potential weaknesses in the design, and improve the chip's anti-interference ability by optimizing circuit layout, adding protection measures, and other means.

[0003] Existing chip testing methods require a lot of testing time and resources to cover all possible attack parameters, which cannot meet the needs of large-scale chip security assessment. There is also a lack of a systematic method to evaluate the comprehensive anti-attack capabilities of the chip under different voltage glitch conditions. It is difficult to find the most sensitive point of the chip within a limited testing time, resulting in low test efficiency, lack of specificity and poor test repeatability. Summary of the invention

[0004] The embodiment of the present application provides a method for calculating fault sensitivity based on voltage glitches, which can solve the problems in the prior art of low test efficiency, lack of specificity and poor test repeatability due to the need for a large amount of test time and resources to cover all possible attack parameters.

[0005] In a first aspect, an embodiment of the present application provides a method for calculating fault sensitivity based on voltage glitch, comprising:

[0006] Acquire parameter scanning information of the security chip, and determine multiple voltage glitch parameter combinations of the security chip based on the parameter scanning information; wherein the parameter scanning information is preliminary voltage glitch related parameters obtained according to the result of voltage glitch fault injection;

[0007] According to each voltage glitch parameter combination of the safety chip, controlling the glitch injection device to inject glitch into the safety chip, and obtaining the number of fault occurrences corresponding to each voltage glitch parameter combination;

[0008] Determine the fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences corresponding to each voltage glitch parameter combination;

[0009] The test result of the safety chip is determined according to the fault sensitivity corresponding to each voltage glitch parameter combination.

[0010] The above technical solutions in the embodiments of the present application have at least the following technical effects:

[0011] The fault sensitivity calculation method based on voltage glitches provided in the embodiment of the present application obtains parameter scanning information of the security chip, and determines multiple voltage glitches parameter combinations of the security chip based on the parameter scanning information, so as to ensure that all possible glitches conditions are covered within a limited time, thereby improving the test efficiency and coverage. According to each voltage glitches parameter combination of the security chip, the glitch injection device is controlled to inject glitches into the security chip, and the number of faults corresponding to each voltage glitches parameter combination is obtained, so as to ensure the accuracy and repeatability of the test results. Based on the number of faults corresponding to each voltage glitches parameter combination, the fault sensitivity corresponding to each voltage glitches parameter combination is determined. According to the fault sensitivity corresponding to each voltage glitches parameter combination, the test results of the security chip are determined, and the parameter combinations and conditions that the chip is most vulnerable to attack are quickly identified, so as to improve the test efficiency, enhance the test repeatability and pertinence, and provide clear guidance and data support for chip design optimization and protection measures improvement.

[0012] In a second aspect, an embodiment of the present application provides a fault sensitivity calculation system based on voltage glitch, comprising:

[0013] An acquisition unit, used to acquire parameter scanning information of the security chip, and determine multiple voltage glitch parameter combinations of the security chip based on the parameter scanning information; wherein the parameter scanning information is preliminary voltage glitch related parameters obtained according to the result of voltage glitch fault injection;

[0014] An injection unit, configured to control a glitch injection device to perform glitch injection on the security chip according to each voltage glitch parameter combination of the security chip, and obtain a number of fault occurrences corresponding to each voltage glitch parameter combination;

[0015] An analyzing unit, configured to determine a fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences corresponding to each voltage glitch parameter combination;

[0016] The result unit is used to determine the test result of the safety chip according to the fault sensitivity corresponding to each voltage glitch parameter combination.

[0017] In a third aspect, an embodiment of the present application provides a fault sensitivity calculation device based on voltage glitch, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method as described in any one of the above aspects when executing the computer program.

[0018] In a fourth aspect, an embodiment of the present application provides a computer program product, which, when executed on a terminal device, enables the terminal device to execute the method of any one of the above aspects.

[0019] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the above aspects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 It is a flow chart of a method for calculating fault sensitivity based on voltage glitches provided in one embodiment of the present application;

[0022] Figure 2 It is a schematic diagram of the operation flow of a method for calculating fault sensitivity based on voltage glitches provided in an embodiment of the present application;

[0023] Figure 3 It is a schematic diagram of a hardware acquisition device of a fault sensitivity calculation method based on voltage glitch provided in an embodiment of the present application;

[0024] Figure 4 This is a diagram showing the operation of steps in a method for calculating fault sensitivity based on voltage glitches provided in an embodiment of the present application;

[0025] Figure 5 This is a diagram showing the operation of steps in a method for calculating fault sensitivity based on voltage glitches provided in an embodiment of the present application;

[0026] Figure 6 This is a diagram showing the operation of steps in a method for calculating fault sensitivity based on voltage glitches provided in an embodiment of the present application;

[0027] Figure 7 It is a structural schematic diagram of a fault sensitivity calculation system based on voltage glitch provided in one embodiment of the present application;

[0028] Figure 8It is a structural schematic diagram of a fault sensitivity calculation device based on voltage glitch provided in one embodiment of the present application. DETAILED DESCRIPTION

[0029] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0030] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0031] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] As used in the specification of this application and the appended claims, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if the described condition or event is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce the described condition or event is detected" or "in response to detecting the described condition or event" depending on the context.

[0033] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0034] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0035] Existing chip testing methods require a lot of testing time and resources to cover all possible attack parameters, which cannot meet the needs of large-scale chip security assessment. There is also a lack of a systematic method to evaluate the comprehensive anti-attack capabilities of the chip under different voltage glitch conditions. It is difficult to find the most sensitive point of the chip within a limited testing time, resulting in low test efficiency, lack of specificity and poor test repeatability.

[0036] To solve the above problems, an embodiment of the present application provides a method for calculating fault sensitivity based on voltage glitches. In this method, by obtaining parameter scanning information of the security chip, and determining multiple voltage glitch parameter combinations of the security chip based on the parameter scanning information, it is ensured that all possible glitch conditions are covered within a limited time, thereby improving the test efficiency and coverage. According to each voltage glitch parameter combination of the security chip, the glitch injection device is controlled to inject glitch into the security chip, and the number of faults corresponding to each voltage glitch parameter combination is obtained, thereby ensuring the accuracy and repeatability of the test results. Based on the number of faults corresponding to each voltage glitch parameter combination, the fault sensitivity corresponding to each voltage glitch parameter combination is determined. According to the fault sensitivity corresponding to each voltage glitch parameter combination, the test results of the security chip are determined, and the parameter combinations and conditions that the chip is most vulnerable to attack are quickly identified, thereby improving the test efficiency, enhancing the test repeatability and pertinence, and providing clear guidance and data support for chip design optimization and protection measures improvement.

[0037] The fault sensitivity calculation method based on voltage glitch provided in the embodiment of the present application can be applied to a fault sensitivity calculation device based on voltage glitch. At this time, the fault sensitivity calculation device based on voltage glitch is the executor of the fault sensitivity calculation method based on voltage glitch provided in the embodiment of the present application. The embodiment of the present application does not impose any restrictions on the specific type of terminal equipment.

[0038] For example, a voltage glitch-based fault sensitivity calculation device may include a processor, a communication device (e.g., a serial interface, a parallel interface, a USB), a network device, a hardware acquisition device (e.g., an oscilloscope, a digital-to-analog converter, a sensor), a glitch injection device (e.g., a signal generator, a pulse generator, a coupling network), a memory, etc.

[0039] In order to better understand the fault sensitivity calculation method based on voltage glitches provided in the embodiment of the present application, the specific implementation process of the fault sensitivity calculation method based on voltage glitches provided in the embodiment of the present application is exemplarily introduced below.

[0040] Figure 1 A schematic flow chart of a method for calculating fault sensitivity based on voltage glitches provided in an embodiment of the present application is shown. Figure 2The operating flow chart of the fault sensitivity calculation method based on voltage glitch provided in the embodiment of the present application is shown. The fault sensitivity calculation method based on voltage glitch includes:

[0041] S100, acquiring parameter scanning information of the safety chip, and determining multiple voltage glitch parameter combinations of the safety chip based on the parameter scanning information; wherein the parameter scanning information is preliminary voltage glitch related parameters obtained according to the result of voltage glitch fault injection.

[0042] It can be understood that parameter scanning information refers to a series of data obtained by real-time monitoring of the operating status of the security chip under different working conditions, which can be the relevant parameters of the preliminary voltage glitch obtained according to the results of voltage glitch fault injection. Parameter scanning information can include parameters such as power supply voltage, clock frequency, operating temperature, current consumption and signal integrity. Parameter scanning information can be obtained by using test equipment such as oscilloscopes and logic analyzers, combined with dedicated software and hardware interfaces (such as JTAG, SPI) for data acquisition, and the collected data can be obtained through USB or network connection. Based on the collected parameter scanning information, certain algorithm signal processing algorithms (such as Fourier transform or wavelet transform) can be applied to identify the parameter characteristic data of the voltage glitch, and the parameter characteristic data will serve as the basis for the subsequent voltage glitch parameter combination. For example, the application of Fourier transform can convert the time domain signal into a mathematical tool represented by the frequency domain, which can reveal the frequency component of the signal, so as to identify the most representative voltage glitch characteristics and generate all possible voltage glitch parameter combinations, which is beneficial to subsequent analysis and testing.

[0043] In a possible implementation, S100, acquiring parameter scanning information of the security chip, and determining multiple voltage glitch parameter combinations of the security chip based on the parameter scanning information, including:

[0044] S110, acquiring parameter scanning information of the security chip, and determining parameter characteristic data of the security chip based on the parameter scanning information.

[0045] It is understood that the parameter scan information may include parameters such as supply voltage, clock frequency, operating temperature, current consumption, and signal integrity. The parameter scan information can be acquired by using hardware data acquisition devices such as oscilloscopes and logic analyzers (see Figure 3), combined with dedicated software and hardware interfaces (such as JTAG, SPI) for data acquisition, and obtain parameter scanning information through USB or network connection. Parameter feature data can be obtained from the parameter scanning information. Parameter feature data refers to information used to describe the statistical characteristics of a data set. For example, signal processing algorithms (such as Fourier transform or wavelet transform) can be used to analyze the frequency domain performance of time domain signals. Fourier transform is a mathematical tool that converts time domain signals into frequency domain representations, which can reveal the frequency components of the signal. After extracting parameter feature data, feature vectors can be constructed to capture the statistical characteristics of the parameters, such as mean, standard deviation, peak factor, etc. The parameter feature data will form a parameter feature data set, which is conducive to determining the performance of the security chip and laying the foundation for subsequent analysis.

[0046] S120, dividing the security chip into glitch parameter levels based on the parameter characteristic data of the security chip to obtain a plurality of glitch parameter layers.

[0047] It can be understood that for the extracted parameter feature data, Hierarchical Clustering Analysis can be applied to stratify the parameter feature data. Hierarchical clustering is a method of grouping data by building a tree structure. In this process, a suitable distance metric (such as Euclidean distance) can be selected to calculate the similarity between data points, and the data points can be gradually merged in a bottom-up manner. Each level represents a group of similar voltage glitch features. The glitch parameter level helps to construct the subsequent voltage parameter combination, and the tree structure is formed to facilitate the selection of different parameter layers for testing.

[0048] Optionally, S120, based on the parameter characteristic data of the security chip, the security chip is divided into glitch parameter levels to obtain multiple glitch parameter layers, including:

[0049] S121, determining parameter characteristic information of multiple parameters of the security chip based on the parameter characteristic data of the security chip.

[0050] It is understandable that the parameter characteristic data can be directly extracted for analysis to determine the parameter characteristic information of various parameters related to the security chip. The parameter characteristic information may include:

[0051] Mean, standard deviation: describes the average value and fluctuation of each parameter during the test period

[0052] Distribution characteristics: distribution of parameters (such as normal distribution, skewed distribution, etc.)

[0053] Outlier Analysis: Identify and analyze abnormal parameter values ​​to determine possible failures or abnormal conditions.

[0054] S122, dividing each parameter of the security chip into glitch parameter levels according to parameter characteristic information of each parameter, and obtaining a plurality of glitch initial parameter layers corresponding to each parameter.

[0055] It can be understood that a mapping relationship between scanning parameters and glitch parameters can be established in advance. The mapping relationship between scanning parameters and glitch parameters can be achieved through experimental data analysis and statistical modeling. For example, a formula or function is set to map a specific scanning parameter (such as voltage amplitude) to a corresponding glitch parameter (such as glitch amplitude and width). Based on the parameter characteristic information of various parameters of the security chip, the corresponding glitch parameters can be obtained through mapping relationships, and clustering algorithms (such as K-means or hierarchical clustering) can be used to group the glitch parameters. The clustering algorithm classifies similar glitch parameters into one category and forms multiple initial parameter layers through mapping. According to the parameter characteristic information of each level, the boundary of the glitch parameter layer can be determined by presetting the mapping relationship. The boundary of the glitch parameter layer can be preset based on historical data or experimental results to ensure that each level can represent a specific voltage glitch behavior. For example, for voltage amplitude, it can be divided into "low voltage (0V-1V)", "medium voltage (1V-3V)" and "high voltage (3V-5V)" levels according to different voltage values; for width, it can be divided into "short width (1μs-10μs)", "medium width (10μs-50μs)" and "long width (50μs-100μs)" levels; the application time can be divided into "early application", "mid-term application" and "late application" levels according to its change point relative to the signal. That is, each parameter has multiple parameter levels, and each parameter level is the initial parameter level of the burr.

[0056] S123, summarizing the multiple burr initial parameter layers corresponding to all parameters to obtain multiple burr parameter layers; wherein the burr parameter layers include burr initial parameter layers of at least two parameters.

[0057] It can be understood that the initial parameter layers extracted from each parameter (such as voltage amplitude, width, and application time) will be integrated together. These initial parameter layers are defined based on the characteristic data of each parameter and represent the voltage glitch behavior under different conditions. The aggregation process can be achieved by creating a multi-dimensional data structure, where each dimension corresponds to a parameter. By cross-combining the initial layers of different parameters, multiple comprehensive glitch parameter layers are formed. For example, for the combination of "low voltage amplitude" and "short width", a new glitch parameter layer can be defined, which combines the joint effects of the two parameters in a specific situation. Based on experimental data, statistical methods (such as mean and standard deviation) can be used to determine the correlation between different levels and identify combinations that have a significant impact on chip performance. Through such aggregation, the final glitch parameter layer will not only cover the independent characteristics of each parameter, but also reveal the interaction between parameters, thereby providing a more comprehensive test solution.

[0058] S130, determining a plurality of voltage glitch parameter combinations of the security chip according to the plurality of glitch parameter layers.

[0059] It can be understood that by analyzing all glitch parameter layers, voltage glitch parameter combinations for the safety chip to be tested can be systematically generated. The voltage glitch parameter combination will provide a basis for subsequent tests, covering various possible voltage glitch conditions, so as to comprehensively evaluate the fault sensitivity of the chip.

[0060] Optionally, S130, determining multiple voltage glitch parameter combinations of the security chip according to multiple glitch parameter layers, includes:

[0061] S131, determining the sample importance of each burr parameter layer according to the multiple burr parameter layers; wherein the sample importance is used to reflect the importance of the burr parameter layer in the test process.

[0062] It can be understood that sample importance is used to evaluate the relative importance of different parameter layers in a specific task or model, reflecting the importance of the burr parameter layer in the test process. The evaluation of sample importance can rely on historical test data to calculate the frequency of failures in each parameter layer during the test or the significance of its response to failures. This can be done through a variety of statistical methods, such as using weighted indicators or information gain, to determine the importance of each layer to the final result. Layers with high sample importance indicate that they may have a greater impact in fault testing, so they should be given more attention and resource allocation.

[0063] Exemplarily, information gain is used to evaluate the importance of a sample, and a known data set (e.g., data containing different voltage glitch parameter combinations and their corresponding fault occurrences) can be used to build a sample importance model. The entropy of the entire data set can be calculated to represent the uncertainty of the information. The entropy formula is: , where p i is the probability of each category (such as fault or normal). Calculate the entropy under the given parameter combination conditions, which represents the uncertainty of the system after the known parameter combination. The information gain formula is: IG(S,A)=H(S)−H(S|A) where IG(S,A is the information gain of sample S through parameter A, H(S) is the total entropy, and H(S|A) is the conditional entropy. After calculating the information gain, the parameter combination with higher information gain indicates that it contributes more to fault prediction, and thus its sample importance is higher. Parameter combinations with high importance can be selected for more tests.

[0064] S132, determining the number of samples of each burr parameter layer according to the sample importance of each burr parameter layer.

[0065] It can be understood that by calculating the sample importance of each glitch parameter layer, a relative weight can be provided for each layer, and this weight reflects the importance of the layer in the entire test. The sample importance can be regarded as an indicator, which reflects the degree of influence that each glitch parameter layer may have on the performance and failure of the security chip during the test. The higher the sample importance, the greater the importance of the layer in revealing the potential failure or performance bottleneck of the chip. Therefore, more sampling numbers should be allocated to parameter layers with higher sample importance in order to collect sufficient data to ensure the credibility of their results. When determining the number of samples, the total number of samples can be set, and the total number of samples can be pre-set based on factors such as test resources, time constraints, and experimental design. According to the sample importance of each glitch parameter layer, the total number of samples is weighted and allocated. The proportion of each layer can be calculated by dividing the sample importance of each layer by the sum of the sample importance of all layers, so as to determine the specific number of samples based on the proportion. For example, if the total number of samples is set to 100, and the sample importance of parameter layer A is 0.4, the sample importance of parameter layer B is 0.3, and the sample importance of parameter layer C is 0.3, then the number of samples of layer A can be calculated as: number of samples A = 100 × 0.4 / (0.4 + 0.3 + 0.3) = 40. Similarly, the number of samples of layers B and C can also be calculated accordingly.

[0066] S133, based on the number of samples in each glitch parameter layer, performing random parameter combinations in each glitch parameter layer to determine a plurality of voltage glitch parameter combinations of the security chip.

[0067] It can be understood that each glitch parameter layer determines a specific number of samples, which reflects the importance and necessity of each parameter layer in the entire test. The process of random parameter combination in each glitch parameter layer is mainly to randomly extract a certain number of sample parameters from each layer, and then combine these parameters to form a new voltage glitch parameter combination. The importance of this process lies in the ability to simulate the working state of the safety chip under various voltage conditions, so as to more comprehensively observe and analyze the response behavior of the chip under various conditions. A certain number of samples can be randomly selected from each glitch parameter layer, and the number of samples is based on the number of samples determined in the previous step. The random selection method can ensure the diversity of samples, thereby avoiding potential deviations. After the samples are selected, these samples are combined according to preset rules to form multiple voltage glitch parameter combinations. The combination rules may include but are not limited to cross-combinations of different parameters, series or parallel connections under specific conditions, etc. For example, if the parameters included in a glitch parameter layer are voltage amplitude, application width, and application time, the randomly selected samples may be:

[0068] Voltage range: 2V, 3V, 5V

[0069] Width: 1ms, 2ms

[0070] When to apply: Early, mid, late

[0071] By combining these random samples, one can form:

[0072] Combination 1: Voltage amplitude 2V, width 1ms, early application time

[0073] Combination 2: Voltage amplitude 3V, width 2ms, application time mid-term

[0074] Combination 3: Voltage amplitude 5V, width 1ms, late application time

[0075] The random combination method can generate a large number of voltage glitch parameter combinations to ensure that as many working scenarios as possible are covered, which facilitates the subsequent systematic testing and evaluation of the performance of the security chip under various voltage glitch conditions.

[0076] S200, according to each voltage glitch parameter combination of the safety chip, controlling the glitch injection device to inject glitch into the safety chip, and obtaining the number of fault occurrences corresponding to each voltage glitch parameter combination.

[0077] It can be understood that the voltage glitch parameter combination can be input into the glitch injection device according to the predefined voltage glitch parameter combination. The function of the glitch injection device is to inject glitch into the security chip to ensure that the impact of voltage glitch is accurately simulated under the conditions of each combination. The glitch injection device is usually used to test the robustness of electronic equipment under non-ideal power supply conditions. It can simulate the instantaneous voltage change (the so-called "glitch" or "transient") on the power line to detect the response of electronic equipment under such conditions. The glitch injection device can simulate the voltage fluctuations that may be encountered in the real environment, has high-precision voltage regulation capabilities, and can quickly switch between different voltage states. After each glitch injection, the response of the security chip can be received and recorded in real time, including whether a fault occurs, the type of fault, and other performance indicators, which can not only help identify the fault, but also be used to further optimize the parameter settings of the glitch injection.

[0078] In a possible implementation, S200, according to each voltage glitch parameter combination of the security chip, controlling the glitch injection device to inject glitch into the security chip, and obtaining the number of fault occurrences corresponding to each voltage glitch parameter combination, includes:

[0079] S210, controlling a glitch injection device to perform glitch injection on the security chip according to each voltage glitch parameter combination of the security chip, and receiving glitch injection data of the security chip.

[0080] It can be understood that the voltage glitch parameter combination can be sent to the glitch injection device to start the voltage glitch injection experiment. In this link, the controller will apply the glitch signal to the security chip one by one according to the preset voltage glitch parameter combination. When the glitch injection device injects glitch into the security chip, the response data of the security chip can be received in real time. The received response data may include working status, current change, integrity of output signal, etc. It can be collected and stored by the data acquisition system for subsequent data analysis.

[0081] S220, determining a fault event corresponding to each voltage glitch parameter combination based on the glitch injection data of the safety chip and a preset fault determination rule.

[0082] It is understood that after acquiring the glitch injection data, the glitch injection data can be analyzed and compared with the preset fault judgment rules. The fault judgment rules are set based on historical data and the working characteristics of the safety chip to determine which situation will cause a fault under different voltage glitch conditions. The fault judgment rules may include thresholds for certain key parameters, such as the maximum current, temperature, waveform of the output signal, etc. of the chip. When the injected voltage glitch exceeds a certain threshold, or under certain conditions, it is recorded as a fault event (see Figure 4 ). During the analysis process, a variety of data analysis methods, such as statistical analysis, anomaly detection methods, etc., can be used to improve the accuracy of fault detection. Statistical analysis may involve descriptive statistics of the collected data to find out the fault frequency and mode under different voltage glitches. The anomaly detection method can calculate the probability of occurrence by building a statistical model (such as normal distribution) under normal operating conditions and comparing new data points with the model. If the probability of a data point is lower than the preset threshold, it is judged to be abnormal. By comparing the glitch injection data with the fault judgment rules, it can be determined whether each voltage glitch parameter combination will cause a fault, and the corresponding fault event can be recorded.

[0083] S230, calculating the number of fault events corresponding to each voltage glitch parameter combination to obtain the number of fault occurrences corresponding to each voltage glitch parameter combination.

[0084] It can be understood that after completing the glitch injection and obtaining the injection data, the injection data can be sorted to determine that the relevant fault events of each voltage glitch parameter combination are correctly recorded. A data structure (such as a data table or database) can be constructed to associate each parameter combination with the corresponding fault event. The fault events can be classified and counted. For each voltage glitch parameter combination, all recorded fault events are checked and classified and counted. A simple counter can also be used to track the number of occurrences of each fault event under each parameter combination, so that the fault data of each parameter combination can fully reflect its performance in actual testing.

[0085] Optionally, the fault event includes a plurality of different types of preset fault events. S230, the number of fault events corresponding to each voltage glitch parameter combination is calculated to obtain the number of fault occurrences corresponding to each voltage glitch parameter combination, including:

[0086] S231, calculating the number of each preset fault event corresponding to each voltage glitch parameter combination to obtain the number of fault occurrences of each preset fault event corresponding to each voltage glitch parameter combination.

[0087] It can be understood that the preset fault events are determined based on previous experimental data and theoretical analysis, and include various types of faults that may occur under different voltage glitch conditions. For example, these fault events may include chip response timeout, too long response, too short response, etc. The fault event records related to each voltage glitch parameter combination can be screened out from the collected glitch injection data. For each preset fault event, its occurrence frequency under the corresponding voltage glitch parameter combination is counted. Visual tools can be used to display the number of fault occurrences in the form of a chart to make the results more intuitive. Through the statistical results, it is possible to clearly understand which voltage glitch parameter combinations are most likely to cause specific fault events, providing an important basis for subsequent fault analysis and safety design optimization.

[0088] In a possible implementation, S200, according to each voltage glitch parameter combination of the security chip, controls the glitch injection device to inject glitch into the security chip, and obtains the number of fault occurrences corresponding to each voltage glitch parameter combination, and also includes:

[0089] S240, determining the total number of tests for each voltage glitch parameter combination according to the glitch injection data of the safety chip.

[0090] It can be understood that the total number of tests refers to the total number of complete test operations performed under a specific voltage glitch parameter combination, and relevant information can be extracted from the collected glitch injection data. All glitch injection data can be traversed to extract the test conditions of each voltage glitch parameter combination. Data analysis tools, such as Python's Pandas library or Excel, can be used to organize and process the data. For each voltage glitch parameter combination, a counter can be created to count the number of times the combination appears in the data set, indicating the number of tests under the combination. The statistical results will provide strong data support for subsequent fault analysis, evaluation, and optimization of the design of safety chips.

[0091] S300, determining the fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences corresponding to each voltage glitch parameter combination.

[0092] It can be understood that fault sensitivity is an indicator that reflects the degree of system response to fault events under specific voltage conditions, and can evaluate the possibility of safety chip failure under specific voltage glitches. The corresponding fault sensitivity can be calculated based on the number of faults for each voltage glitch parameter combination and the total number of tests for each voltage glitch parameter combination. By determining the fault sensitivity corresponding to each voltage glitch parameter combination, we can better understand the impact of different parameter combinations on safety chips and provide guidance for design and improvement.

[0093] In a possible implementation, S300, based on the number of fault occurrences corresponding to each voltage glitch parameter combination, determines the fault sensitivity corresponding to each voltage glitch parameter combination, including:

[0094] S310, determining the fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences and the total number of tests of each preset fault event corresponding to each voltage glitch parameter combination.

[0095] It can be understood that the corresponding fault sensitivity can be calculated based on the number of faults occurring for each voltage glitch parameter combination and the total number of tests for each voltage glitch parameter combination. By determining the fault sensitivity corresponding to each voltage glitch parameter combination, the impact of different parameter combinations on the security chip can be better understood, providing guidance for design and improvement.

[0096] Optionally, S310, determining the fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences and the total number of tests of each preset fault event corresponding to each voltage glitch parameter combination, includes:

[0097] S311, based on the number of fault occurrences and the total number of tests of each preset fault event corresponding to each voltage glitch parameter combination, determine the fault sensitivity corresponding to each voltage glitch parameter combination by a first formula; wherein the first formula is: , S is the fault sensitivity, is the number of fault occurrences of each preset fault event corresponding to the voltage glitch parameter combination, It is the total number of tests corresponding to the voltage glitch parameter combination.

[0098] It can be understood that the fault sensitivity corresponding to each voltage glitch parameter combination can be calculated by a preset first formula, and the first formula is: , S is the fault sensitivity, is the number of fault occurrences of each preset fault event corresponding to the voltage glitch parameter combination, It is the total number of tests corresponding to the voltage glitch parameter combination.

[0099] S400, determining a test result of the safety chip according to the fault sensitivity corresponding to each voltage glitch parameter combination.

[0100] It can be understood that by analyzing the fault sensitivity corresponding to each voltage glitch parameter combination, the fault sensitivity can be combined with a specific fault type to form a comprehensive test evaluation model. Fault type information and environmental path information can be received. Fault type information comes from preset fault events, is associated with the fault phenomenon observed in the actual test, and can help evaluate the nature and impact of the fault. Environmental path information refers to the saved path, which contains information such as parameter settings, test steps and environmental conditions used in the test process. According to the fault type information and fault sensitivity, a fault sensitivity curve of the security chip is generated. The fault sensitivity curve is the result of presenting the fault sensitivity data of different voltage glitch parameter combinations in a graphical manner, which can intuitively show the reliability and vulnerability of the chip under different conditions. By analyzing the curve, parameter vulnerability points and sensitive points can be identified. Parameter vulnerability points refer to parameter combinations that are prone to failure under specific conditions, and parameter combinations may cause problems such as design defects or material fatigue. Through statistical methods such as linear feature extraction, the mutation points and inflection points of the curve can be identified, and the test results of the security chip can be comprehensively evaluated.

[0101] In a possible implementation, S400, determining the test result of the security chip according to the fault sensitivity corresponding to each voltage glitch parameter combination, includes:

[0102] S410, receiving fault type information and environmental path information; wherein the fault type information is used to associate with a preset fault event.

[0103] It can be understood that the fault type information is the fault type information that has a one-to-one correspondence with the preset fault event (see Figure 5 ), which is used to associate and generate fault sensitivity curves corresponding to different types of preset fault events. It can be obtained by receiving the user's input or selection in the input interface. The user can select the corresponding fault type from the preset fault list, and the user selection is recorded as fault type information. Environmental path information refers to the document storage path used to save the generated fault sensitivity curve and the related information of the generated operating environment. The environmental path points to a specific file storage location, so that the data can be correctly saved and convenient for subsequent access when generating and recording the fault sensitivity curve. Users can select the storage path as needed, such as selecting a specific folder. The acquisition of environmental path information can also be completed through user selection. When the user selects a storage path in the system, the information is recorded so that the data can be quickly accessed during subsequent analysis and report generation, which helps to improve test efficiency and the reliability of data analysis, and provide a scientific basis for subsequent evaluation.

[0104] S420 , generating a fault sensitivity curve of the safety chip according to the fault type information, the environmental path information, and the fault sensitivity corresponding to each voltage glitch parameter combination.

[0105] It can be understood that the fault sensitivity value can be paired with the corresponding voltage parameter combination. The sensitivity value of each parameter combination will be used as a data point in the curve. Through data fitting methods (such as linear regression, spline interpolation, etc.), targeted sensitivity curve data points will be generated according to the fault type information and connected into a curve (see Figure 6 ), and save the generated fault sensitivity curve according to the environmental path information. The generated sensitivity curve can be plotted, for example, using a chart tool (such as Matplotlib, Excel, etc.) for visualization. The fault sensitivity curve can not only intuitively reflect the fault sensitivity under different voltage conditions, but also help identify the critical threshold for the occurrence of faults under specific conditions.

[0106] S430, analyzing the fault sensitivity curve of the security chip to determine the parameter sensitive points of the security chip.

[0107] It can be understood that the fault sensitivity curve is formed by visualizing the combination of voltage glitch parameters and the corresponding fault sensitivity data, reflecting the degree of response of the security chip to faults under different voltage conditions. By analyzing this curve, the performance of the chip under different working conditions can be revealed, and the parameter sensitivity points of the security chip can be determined. Parameter sensitivity points refer to the vulnerable points in a specific system or component (such as a security chip) where a slight change in certain parameters may cause a significant degradation of system performance or failure.

[0108] Optionally, S430, analyzing the fault sensitivity curve of the security chip to determine the parameter vulnerability of the security chip includes:

[0109] S431, extracting linear features from the fault sensitivity curve of the safety chip to determine the linear transformation trend of the fault sensitivity curve.

[0110] It can be understood that statistical methods such as linear regression analysis can be applied to extract features from the fault sensitivity curve. The purpose of linear feature extraction is to identify the linear change area in the curve and determine its slope and intercept. The trend of these linear transformations can reveal the response characteristics of the chip within a specific voltage range. For example, if the curve shows a relatively stable linear feature in a certain voltage range, it means that the fault response of the chip is relatively stable within this range. Conversely, if the slope of the curve increases significantly in certain areas, it means that the change of parameters in this interval will have a greater impact on the failure rate.

[0111] S432, determining a mutation point and an inflection point of the fault sensitivity curve according to the linear transformation trend of the fault sensitivity curve; wherein the mutation point is used to indicate a point where the linear transformation trend changes.

[0112] It can be understood that the linear feature extraction results can be analyzed to locate the mutation points and inflection points in the curve. The mutation point refers to the location where the linear transformation trend of the fault sensitivity curve changes significantly, which usually means that the response characteristics of the system have changed near this point. The inflection point is the point where the slope of the curve changes, marking a change in system behavior. By determining the mutation points and inflection points of the fault sensitivity curve, we can have a deeper understanding of the potential vulnerability of the security chip under different working conditions and lay the foundation for subsequent sensitivity analysis.

[0113] S433, performing sensitivity analysis on the mutation points and inflection points of the fault sensitivity curve to determine parameter vulnerability points of the security chip.

[0114] It can be understood that the identified mutation points and inflection points can be analyzed in depth through sensitivity analysis methods to determine specific parameter vulnerabilities. It can involve calculating the impact of small changes in parameters on failure rates or performance indicators near these key points. For example, the percentage change in failure rate when the parameters change can be calculated to further confirm which parameters are most sensitive under specific conditions. Through sensitivity analysis methods, the parameters that have the greatest impact on system performance can be effectively identified and provide a basis for subsequent evaluation.

[0115] Exemplarily, by determining the specific locations of the mutation point and the inflection point, several voltage values ​​can be selected before and after the mutation point and the inflection point to construct the range of analysis. For example, if the mutation point is at 5V, a value between 4.5V and 5.5V can be selected for analysis. Within the selected voltage range, a small change in the parameter is made. Several different change amplitudes (such as ±0.1V or ±0.2V) can be set, and the failure rate at each voltage value can be recorded. For each voltage value, the failure rate is calculated under the condition of a small change in the parameter. For example, assuming that the failure rate is 3% at 5V, when the voltage is fine-tuned to 4.9V and 5.1V, the failure rates are 2.5% and 3.5%, respectively. The percentage change can be calculated using the following formula: Percentage change = (new failure rate-original failure rate) / original failure rate × 100%, and the relative change in failure rate under different voltage changes is obtained. The calculated failure rate change is combined with the corresponding voltage change to obtain the sensitivity index of each parameter. The sensitivity coefficient can be used to quantify the impact of parameter changes on system performance. The calculation formula of the sensitivity coefficient is: S=ΔY / ΔX, where S is the sensitivity coefficient, ΔY is the change in failure rate, and ΔX is the change in parameter (voltage). By analyzing the sensitivity coefficients of different parameters, we can determine which parameters are most sensitive under specific conditions. Usually, the parameters with larger sensitivity coefficient values ​​are the vulnerable points.

[0116] S440, determining a test result of the security chip according to the parameter sensitivity points and the fault sensitivity curve of the security chip.

[0117] It can be understood that all test data can be integrated into a database or spreadsheet based on the parameter sensitivity points and fault sensitivity curves of the security chip. Test scripts such as Python can be used to execute test cases and record results. Complete test reports can be automatically generated through scripts or tools. Combined with the fault sensitivity curve, the fault sensitivity curve can be used to evaluate the performance of the chip under different fault conditions, and the reliability and stability of the security chip under various working conditions can be output. For example, it can identify situations where the failure rate increases significantly under specific voltages or other conditions. Based on all the integrated data, the final test report of the security chip is output to quickly and accurately evaluate the fault sensitivity of the chip and find its most vulnerable point under different conditions, thereby providing a scientific basis for improving chip design and optimizing protective measures.

[0118] Corresponding to the fault sensitivity calculation method based on voltage glitches in the above embodiment, the embodiment of the present application also provides a fault sensitivity calculation system based on voltage glitches, and each unit of the system can implement each step of the fault sensitivity calculation method based on voltage glitches. Figure 7 A structural block diagram of a fault sensitivity calculation system based on voltage glitches provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0119] Reference Figure 7 , the voltage glitch-based fault sensitivity calculation system includes:

[0120] An acquisition unit, used to acquire parameter scanning information of the security chip, and determine multiple voltage glitch parameter combinations of the security chip based on the parameter scanning information; wherein the parameter scanning information is preliminary voltage glitch related parameters obtained according to the result of voltage glitch fault injection;

[0121] An injection unit, configured to control a glitch injection device to perform glitch injection on the security chip according to each voltage glitch parameter combination of the security chip, and obtain a number of fault occurrences corresponding to each voltage glitch parameter combination;

[0122] An analyzing unit, configured to determine a fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences corresponding to each voltage glitch parameter combination;

[0123] The result unit is used to determine the test result of the safety chip according to the fault sensitivity corresponding to each voltage glitch parameter combination.

[0124] It should be noted that the information interaction, execution process, etc. between the above-mentioned systems / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0125] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit module can exist physically separately, or two or more unit modules can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0126] The embodiment of the present application also provides a fault sensitivity calculation device based on voltage glitch, Figure 8 This is a schematic diagram of a fault sensitivity calculation device based on voltage glitch provided in one embodiment of the present application. Figure 8 As shown, the voltage glitch-based fault sensitivity calculation device 6 of this embodiment includes: at least one processor 60 ( Figure 8 Only one is shown), at least one memory 61 ( Figure 8 Only one is shown in the figure) and a computer program 62 stored in the at least one memory 61 and executable on the at least one processor 60. When the processor 60 executes the computer program 62, the fault sensitivity calculation device 6 based on voltage glitch implements the steps in any of the above-mentioned fault sensitivity calculation method embodiments based on voltage glitch, or the fault sensitivity calculation device 6 based on voltage glitch implements the functions of each unit in the above-mentioned system embodiments.

[0127] Exemplarily, the computer program 62 may be divided into one or more units, which are stored in the memory 61 and executed by the processor 60 to complete the present application. The one or more units may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program 62 in the voltage glitch-based fault sensitivity calculation 6.

[0128] For example, the voltage glitch-based fault sensitivity calculation device 6 may include a processor, a communication device (e.g., a serial interface, a parallel interface, a USB), a network device, a hardware acquisition device (e.g., an oscilloscope, a digital-to-analog converter, a sensor), a glitch injection device (e.g., a signal generator, a pulse generator, a coupling network), a memory, etc. The voltage glitch-based fault sensitivity calculation device may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art may understand that Figure 8 It is only an example of the fault sensitivity calculation device 6 based on voltage glitch, and does not constitute a limitation of the fault sensitivity calculation device 6 based on voltage glitch. It may include more or less components than shown in the figure, or a combination of certain components, or different components, for example, it may also include input and output devices, network access devices, buses, etc.

[0129] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0130] In some embodiments, the memory 61 may be an internal storage unit of the fault sensitivity calculation device 6 based on voltage glitch, such as a hard disk or memory of the fault sensitivity calculation device 6 based on voltage glitch. In other embodiments, the memory 61 may also be an external storage device of the fault sensitivity calculation device 6 based on voltage glitch, such as a plug-in hard disk, a smart memory card (SmartMedia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the fault sensitivity calculation device 6 based on voltage glitch. Further, the memory 61 may also include both the internal storage unit of the fault sensitivity calculation device 6 based on voltage glitch and an external storage device. The memory 61 is used to store an operating system, an application program, a boot loader (BootLoader), data and other programs, such as the program code of the computer program. The memory 61 may also be used to temporarily store data that has been output or is to be output.

[0131] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0132] An embodiment of the present application provides a computer program product. When the computer program product runs on a fault sensitivity calculation device based on voltage glitch, the fault sensitivity calculation device based on voltage glitch implements the steps in any of the above method embodiments.

[0133] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the fault sensitivity calculation device based on voltage glitch, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, disk or optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0134] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0135] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0136] In the embodiments provided in the present application, it should be understood that the disclosed voltage glitch-based fault sensitivity calculation system / voltage glitch-based fault sensitivity calculation device and method can be implemented in other ways. For example, the above-described voltage glitch-based fault sensitivity calculation system / voltage glitch-based fault sensitivity calculation device embodiments are merely schematic. For example, the division of the units is merely a logical function division. There may be other division methods in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.

[0137] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0138] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for calculating fault sensitivity based on voltage glitch, characterized in that: include: Acquire parameter scanning information of the security chip, and determine multiple voltage glitch parameter combinations of the security chip based on the parameter scanning information; wherein the parameter scanning information is preliminary voltage glitch related parameters obtained according to the result of voltage glitch fault injection; According to each voltage glitch parameter combination of the safety chip, controlling the glitch injection device to inject glitch into the safety chip, and obtaining the number of fault occurrences corresponding to each voltage glitch parameter combination; Determine the fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences corresponding to each voltage glitch parameter combination; Determining a test result of the security chip according to the fault sensitivity corresponding to each combination of the voltage glitch parameters; Wherein, according to each voltage glitch parameter combination of the security chip, controlling the glitch injection device to perform glitch injection on the security chip to obtain the number of fault occurrences corresponding to each voltage glitch parameter combination includes: According to each voltage glitch parameter combination of the security chip, controlling a glitch injection device to perform glitch injection on the security chip, and receiving glitch injection data of the security chip; Determine the fault event corresponding to each voltage glitch parameter combination based on the glitch injection data of the safety chip and a preset fault determination rule; Counting the number of the fault events corresponding to each combination of the voltage glitch parameters to obtain the number of fault occurrences corresponding to each combination of the voltage glitch parameters; The fault event includes multiple different types of preset fault events, and the number of the fault events corresponding to each voltage glitch parameter combination is calculated to obtain the number of fault occurrences corresponding to each voltage glitch parameter combination, including: Counting the number of each of the preset fault events corresponding to each of the voltage glitch parameter combinations to obtain the number of fault occurrences of each of the preset fault events corresponding to each of the voltage glitch parameter combinations; According to each voltage glitch parameter combination of the security chip, controlling the glitch injection device to inject glitch into the security chip to obtain the number of fault occurrences corresponding to each voltage glitch parameter combination, further comprising: Determine the total number of tests for each voltage glitch parameter combination according to the glitch injection data of the security chip; The determining, based on the number of fault occurrences corresponding to each voltage glitch parameter combination, the fault sensitivity corresponding to each voltage glitch parameter combination, comprises: Determine the fault sensitivity corresponding to each voltage glitch parameter combination based on the number of fault occurrences of each of the preset fault events corresponding to each voltage glitch parameter combination and the total number of tests; The determining the fault sensitivity corresponding to each voltage glitch parameter combination based on the fault occurrence number and the total test number of each preset fault event corresponding to each voltage glitch parameter combination includes: Based on the number of fault occurrences and the total number of tests for each of the preset fault events corresponding to each of the voltage glitch parameter combinations, the fault sensitivity corresponding to each of the voltage glitch parameter combinations is determined by a first formula; wherein the first formula is: , S is the fault sensitivity, is the number of fault occurrences of each of the preset fault events corresponding to the voltage glitch parameter combination, It is the total number of tests corresponding to the voltage glitch parameter combination.

2. The method for calculating fault sensitivity based on voltage glitch according to claim 1, characterized in that: The acquiring parameter scanning information of the security chip and determining a plurality of voltage glitch parameter combinations of the security chip based on the parameter scanning information includes: Acquire parameter scanning information of the security chip, and determine parameter characteristic data of the security chip based on the parameter scanning information; Based on the parameter characteristic data of the security chip, the security chip is divided into burr parameter levels to obtain a plurality of burr parameter layers; A plurality of voltage glitch parameter combinations of the security chip are determined according to the plurality of glitch parameter layers.

3. The fault sensitivity calculation method based on voltage glitch according to claim 2, characterized in that: The step of dividing the security chip into glitch parameter levels based on the parameter characteristic data of the security chip to obtain a plurality of glitch parameter layers includes: Determining parameter characteristic information of multiple parameters of the security chip based on the parameter characteristic data of the security chip; According to the parameter characteristic information of each parameter, the glitch parameter level is divided for each parameter of the security chip to obtain a plurality of glitch initial parameter layers corresponding to each parameter; According to the multiple burr initial parameter layers corresponding to all parameters, multiple burr parameter layers are summarized; wherein the burr parameter layers include the burr initial parameter layers of at least two parameters.

4. The method for calculating fault sensitivity based on voltage glitch according to claim 2, characterized in that: Determining a plurality of voltage glitch parameter combinations of the security chip according to the plurality of glitch parameter layers includes: According to the plurality of burr parameter layers, determining the sample importance of each burr parameter layer; wherein the sample importance is used to reflect the importance of the burr parameter layer in the test process; Determining the number of samples of each burr parameter layer according to the sample importance of each burr parameter layer; Based on the sampling quantity of each glitch parameter layer, random parameter combinations are performed in each glitch parameter layer to determine a plurality of voltage glitch parameter combinations of the security chip.

5. The method for calculating fault sensitivity based on voltage glitch according to claim 1, characterized in that: The step of determining the test result of the security chip according to the fault sensitivity corresponding to each voltage glitch parameter combination includes: Receiving fault type information and environmental path information; wherein the fault type information is used to associate with the preset fault event; Generate a fault sensitivity curve of the safety chip according to the fault type information, the environmental path information and the fault sensitivity corresponding to each voltage glitch parameter combination; Analyzing the fault sensitivity curve of the safety chip to determine the parameter sensitive points of the safety chip; A test result of the security chip is determined according to the parameter sensitive point and the fault sensitivity curve of the security chip.

6. The method for calculating fault sensitivity based on voltage glitch according to claim 5, characterized in that: The analyzing the fault sensitivity curve of the security chip to determine the parameter vulnerability point of the security chip includes: Performing linear feature extraction on the fault sensitivity curve of the safety chip to determine a linear transformation trend of the fault sensitivity curve; According to the linear transformation trend of the fault sensitivity curve, determining the mutation point and the inflection point of the fault sensitivity curve; wherein the mutation point is used to indicate the point where the linear transformation trend changes; A sensitivity analysis is performed on the mutation point and the inflection point of the fault sensitivity curve to determine the parameter vulnerability point of the security chip.

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