Reference voltage source circuit and chip
By independently generating positive and negative temperature coefficient currents in the reference voltage source and generating the reference voltage, the problem of currents in the reference voltage source affecting each other is solved, and flexible and effective regulation and high versatility are achieved.
Patent Information
- Application Number
- CN202310770791.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-27
- Publication Date
- 2024-12-27
AI Technical Summary
The positive temperature coefficient current and the negative temperature coefficient current in the existing reference voltage source affect each other, resulting in the output reference voltage not meeting the actual use scenario and cannot be adjusted in a timely and flexibly.
Design a reference voltage source circuit, and generates a first current with a positive temperature coefficient and a second current with a negative temperature coefficient through two independent circuit structures, and generates a reference voltage based on these two currents, using NMOS and PMOS tubes and can The variable resistor realizes the regulation of current and voltage.
Overcome the mutual influence of currents, realize the timeliness, flexibility and effective regulation of the reference voltage, improve the versatility of the reference voltage source, is suitable for more occasions, and reduces temperature drift and power consumption.
Smart Images
Figure CN119200736A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a reference voltage source circuit and chip. Background Art
[0002] The reference voltage source is an important module in the chip. The purpose of using the reference voltage source is to obtain a DC voltage that is independent of the power supply and process and has certain temperature characteristics. The power consumption and stability of the reference voltage source directly determine the service life of the entire chip.
[0003] Figure 1 It is a traditional voltage mode bandgap reference voltage source. The negative temperature coefficient voltage V CTAT Complementary to absolute temperature, the forward bias voltage through the PN junction (an interface of an impurity semiconductor), that is, the transistor Q 1a The emitter-base voltage (V be ,Q 1a ) is generated. The positive temperature coefficient voltage V PTAT Proportional to absolute temperature, the two transistors Q working at different current densities 1a and Q 2a The emitter-base voltage difference (ΔV BE )supply.
[0004] Figure 2 It is an improved bootstrap bandgap reference voltage source. This type of reference voltage source is derived from the traditional bandgap reference voltage source. The bootstrap bandgap reference voltage source uses a MOS (metal oxide semiconductor) tube working in the subthreshold region, which only requires a small current and has the advantage of low power consumption. In addition, the gate-source differential pair ΔV of the MOS tube working in the subthreshold region gs The MOS tube has a positive temperature coefficient, so a voltage proportional to absolute temperature (PTAT) generating circuit can be designed. The subthreshold region is also called the weak inversion working region. According to the relationship between current and voltage, the V gs It can be equivalent to the V of a PNP transistor (a type of transistor). be .
[0005] However, the positive temperature coefficient current and the negative temperature coefficient current generated by the above two reference voltage sources will affect and interfere with each other, resulting in the output reference voltage not meeting the actual usage scenario and the inability to flexibly and effectively adjust the reference voltage in a timely manner. Summary of the invention
[0006] The technical problem to be solved by the present disclosure is to overcome the defects in the prior art that the current with a positive temperature coefficient and the current with a negative temperature coefficient generated by the reference voltage source will affect and interfere with each other, resulting in the output reference voltage not conforming to the actual usage scenario and the inability to flexibly and effectively adjust the reference voltage in time, and to provide a reference voltage source circuit and chip.
[0007] The present invention solves the above technical problems through the following technical solutions:
[0008] The present disclosure provides a reference voltage source circuit, the reference voltage source circuit comprising a first current generating circuit, a second current generating circuit and a reference voltage output circuit;
[0009] The first current generating circuit and the second current generating circuit are electrically connected to the reference voltage output circuit respectively;
[0010] The first current generating circuit is used to generate a first current and output the first current to the reference voltage output circuit; wherein the first current is a current with a positive temperature coefficient;
[0011] The second current generating circuit is used to generate a second current and output the second current to the reference voltage output circuit; wherein the second current is a current with a negative temperature coefficient;
[0012] The reference voltage output circuit is used to generate a reference voltage based on the first current and the second current.
[0013] Preferably, the first current generating circuit comprises a first current generating module;
[0014] The first current generating module includes a first NMOS (N-type metal oxide semiconductor) tube, a second NMOS tube, a first PMOS (P-type metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube and a first resistor;
[0015] The gate end of the first NMOS transistor is electrically connected to one end of the first resistor and the drain end of the first PMOS transistor respectively, and the drain end of the first NMOS transistor is electrically connected to the other end of the first resistor and the gate end of the second NMOS transistor respectively;
[0016] The drain end of the second NMOS tube is electrically connected to the gate end of the first PMOS tube, the gate end of the second PMOS tube, the drain end of the second PMOS tube, and the gate end of the third PMOS tube respectively;
[0017] The drain end of the first NMOS tube is used to receive a first control signal to drive the first current generating module to generate the first current;
[0018] The drain end of the third PMOS tube is used to output the first current.
[0019] Preferably, the first current generating circuit further includes a first starting circuit;
[0020] The output end of the first startup circuit is electrically connected to the drain end of the first NMOS transistor, and the input end of the first startup circuit is electrically connected to the gate end of the first PMOS transistor;
[0021] The first startup circuit is used to output the first control signal to control the first current generating module to generate the first current.
[0022] Preferably, the first current generating circuit further includes a current stabilizing module;
[0023] The current stabilization module includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and a third NMOS tube;
[0024] The gate end of the fourth PMOS tube is electrically connected to the drain end of the fourth PMOS tube, the gate end of the fifth PMOS tube, the gate end of the sixth PMOS tube, the gate end of the seventh PMOS tube, and the drain end of the third NMOS tube respectively;
[0025] The source end of the fifth PMOS tube is electrically connected to the drain end of the first PMOS tube, and the drain end of the fifth PMOS tube is electrically connected to one end of the first resistor;
[0026] The source end of the sixth PMOS tube is electrically connected to the drain end of the second PMOS tube, and the drain end of the sixth PMOS tube is electrically connected to the drain end of the second NMOS tube and the gate end of the second PMOS tube respectively;
[0027] The source end of the seventh PMOS tube is electrically connected to the drain end of the third PMOS tube, and the drain end of the seventh PMOS tube is electrically connected to the reference voltage output circuit;
[0028] The gate terminal of the third NMOS tube is electrically connected to the drain terminal of the first NMOS tube;
[0029] The drain end of the seventh PMOS tube is used to output the first current after stabilization to the reference voltage output circuit.
[0030] Preferably, the first current generating circuit further includes a first working state control module;
[0031] The first working state control module includes a fourth NMOS tube and an eighth PMOS tube;
[0032] The drain terminal of the fourth NMOS tube is electrically connected to the gate terminal of the second NMOS tube;
[0033] The drain terminal of the eighth PMOS tube is electrically connected to the gate terminal of the second PMOS tube;
[0034] The first working state control module is used to control the working state of the first current generating circuit.
[0035] Preferably, the second current generating circuit comprises a second current generating module;
[0036] The second current generating module includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a fifth NMOS tube, a second resistor, a third resistor and an amplifier;
[0037] The gate end of the ninth PMOS tube is electrically connected to the gate end of the tenth PMOS tube, the gate end of the eleventh PMOS tube, and the output end of the amplifier respectively;
[0038] The positive input terminal of the amplifier is electrically connected to the drain terminal of the ninth PMOS tube and one end of the second resistor, and the negative input terminal of the amplifier is electrically connected to one end of the third resistor and the drain terminal of the fifth NMOS tube;
[0039] The gate end of the fifth NMOS tube is electrically connected to the other end of the third resistor and the drain end of the tenth PMOS tube respectively;
[0040] The gate terminal of the ninth PMOS tube is used to receive the second control signal to drive the second current generating module to generate the second current;
[0041] The drain end of the eleventh PMOS tube is used to output the second current.
[0042] Preferably, the second current generating circuit further includes a second starting circuit;
[0043] The output end of the second startup circuit is electrically connected to the gate end of the ninth PMOS tube, and the input end of the second startup circuit is electrically connected to the reference voltage output circuit;
[0044] The second startup circuit is used to output the second control signal to control the second current generating module to generate the second current.
[0045] Preferably, the second current generating circuit further includes a second working state control module;
[0046] The second working state control module includes a twelfth PMOS tube, a sixth NMOS tube, a thirteenth PMOS tube and a fourteenth PMOS tube;
[0047] The source end of the twelfth PMOS tube is electrically connected to the drain end of the ninth PMOS tube, and the drain end of the twelfth PMOS tube is electrically connected to the positive input end of the amplifier;
[0048] The drain end of the sixth NMOS tube is electrically connected to the output end of the amplifier;
[0049] The source end of the thirteenth PMOS tube is electrically connected to the drain end of the tenth PMOS tube, and the drain end of the thirteenth PMOS tube is electrically connected to the gate end of the fifth NMOS tube;
[0050] The source end of the fourteenth PMOS tube is electrically connected to the drain end of the eleventh PMOS tube, and the drain end of the fourteenth PMOS tube is electrically connected to the reference voltage output circuit;
[0051] The second working state control module is used to control the working state of the second current generating circuit.
[0052] Preferably, the second current generating circuit further includes a capacitor;
[0053] The capacitor is electrically connected to the output terminal of the amplifier;
[0054] The capacitor is used to stabilize the second current.
[0055] Preferably, the first NMOS transistor, the second NMOS transistor and the fifth NMOS transistor all operate in a subthreshold region.
[0056] Preferably, the first resistor, the second resistor and the third resistor are all resistors with variable resistance values;
[0057] Wherein, the first resistor corresponds to a first resistance value; the second resistor and the third resistor correspond to a second resistance value;
[0058] Different first resistance values and / or different second resistance values correspond to the reference voltages with different temperature coefficients.
[0059] Preferably, the reference voltage output circuit comprises a fourth resistor;
[0060] The reference voltage output circuit is used to obtain the reference voltage according to the first current, the second current and the fourth resistor.
[0061] Preferably, the fourth resistor is a resistor with a variable resistance value, and different resistance values of the fourth resistor correspond to the reference voltages of different magnitudes.
[0062] The present disclosure also provides a chip, which includes the reference voltage source circuit as described above.
[0063] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0064] The positive and progressive effects of this disclosure are:
[0065] The present invention adopts two independent circuit structures to respectively generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and obtains a reference voltage based on the first current and the second current, thereby overcoming the problem that the first current and the second current influence and interfere with each other, resulting in the output reference voltage not conforming to the actual usage scenario. The present invention ensures the timeliness, flexibility and effectiveness of adjusting the reference voltage while achieving low temperature drift and high power supply rejection ratio, is suitable for more usage scenarios, and improves the versatility of the reference voltage source. BRIEF DESCRIPTION OF THE DRAWINGS
[0066] Figure 1 The figure is a schematic diagram of the structure of a voltage-mode bandgap reference voltage source in the prior art.
[0067] Figure 2 The figure is a schematic diagram of the structure of a bootstrap bandgap reference voltage source in the prior art.
[0068] Figure 3 This is a module schematic diagram of the reference voltage source circuit of Example 1 of the present disclosure.
[0069] Figure 4 This is a first structural schematic diagram of the reference voltage source circuit of embodiment 2 of the present disclosure.
[0070] Figure 5 This is a second structural schematic diagram of the reference voltage source circuit of Embodiment 2 of the present disclosure.
[0071] Figure 6 This is a module diagram of the chip of Example 3 of the present disclosure. DETAILED DESCRIPTION
[0072] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0073] Example 1
[0074] This embodiment provides a reference voltage source circuit, such as Figure 3 As shown, the reference voltage source circuit includes a first current generating circuit 1, a second current generating circuit 2 and a reference voltage output circuit 3;
[0075] The first current generating circuit 1 and the second current generating circuit 2 are electrically connected to the reference voltage output circuit 3 respectively;
[0076] The first current generating circuit 1 is used to generate a first current and output the first current to the reference voltage output circuit 3; wherein the first current is a current with a positive temperature coefficient;
[0077] The second current generating circuit 2 is used to generate a second current and output the second current to the reference voltage output circuit 3; wherein the second current is a current with a negative temperature coefficient;
[0078] The reference voltage output circuit 3 is used to generate a reference voltage based on the first current and the second current.
[0079] In the present embodiment, two independent circuit structures are adopted to generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient respectively, and a reference voltage is obtained based on the first current and the second current. This overcomes the problem that the first current and the second current influence and interfere with each other, resulting in the output reference voltage not conforming to the actual usage scenario. While achieving low temperature drift and high power supply rejection ratio, the timeliness, flexibility and effectiveness of adjusting the reference voltage are guaranteed. This makes it suitable for more usage scenarios and improves the versatility of the reference voltage source.
[0080] Example 2
[0081] This embodiment provides a reference voltage source circuit, which is a further improvement on the first embodiment.
[0082] In an implementable solution, the first current generating circuit 1 includes a first current generating module 11;
[0083] like Figure 4 As shown, the first current generating module 11 includes a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, a third PMOS transistor M5 and a first resistor R1;
[0084] The source terminals of the first NMOS transistor M1 and the second NMOS transistor M2 are grounded to VSS;
[0085] The source terminals of the first PMOS tube M3, the second PMOS tube M4 and the third PMOS tube M5 are connected to the power supply voltage VCC;
[0086] The gate end of the first NMOS transistor M1 is electrically connected to one end of the first resistor R1 and the drain end of the first PMOS transistor M3, and the drain end of the first NMOS transistor M1 is electrically connected to the other end of the first resistor R1 and the gate end of the second NMOS transistor M2;
[0087] The drain end of the second NMOS tube M2 is electrically connected to the gate end of the first PMOS tube M3, the gate end of the second PMOS tube M4, the drain end of the second PMOS tube M4, and the gate end of the third PMOS tube M5 respectively;
[0088] The drain end of the first NMOS tube M1 is used to receive a first control signal to drive the first current generating module 11 to generate a first current;
[0089] The drain end of the third PMOS tube M5 is used to output the first current.
[0090] Among them, the parameters of the first PMOS tube M3 and the second PMOS tube M4 are consistent, and it can be obtained that Figure 4 In which I1=I2.
[0091] In this solution, based on the first control signal, the first current generating circuit reaches a new equilibrium point, so that the first current generating module generates the first current with a positive temperature coefficient, thereby ensuring the efficiency of the first current generation and the reliability of the first current.
[0092] In an implementable solution, the first current generating circuit 1 further includes a first starting circuit 12;
[0093] The output end of the first startup circuit 12 is electrically connected to the drain end of the first NMOS transistor M1, and the input end of the first startup circuit 12 is electrically connected to the gate end of the first PMOS transistor;
[0094] The first start-up circuit 12 is used to output a first control signal to control the first current generating module 11 to generate a first current.
[0095] Specifically, Figure 5 As shown, the first startup circuit 12 includes a fifteenth PMOS tube M21, a sixteenth PMOS tube M22, a seventeenth PMOS tube M23, ... a thirtieth PMOS tube M36, and a thirty-first PMOS tube M37 and a thirty-second PMOS tube M38. Among them, M21-M36 are connected in series, the gate end of the fifteenth PMOS tube M21 is electrically connected to the gate end of the thirty-first PMOS tube M37 and the gate end of the thirty-second PMOS tube M38 respectively; the gate end of the thirty-first PMOS tube M37 is electrically connected to the gate end of the first PMOS tube M3, and the drain end of the thirty-second PMOS tube M38 is electrically connected to the drain end of the first NMOS tube M1.
[0096] The working principle of the first startup circuit is: M21-M36 provides a low voltage to M38, so that it can provide a current to the drain of M1, thereby getting rid of the "0" degenerate point; after the circuit works normally, M37 is turned on and the first startup circuit is closed.
[0097] In this solution, accurate control of the first current generating module is achieved through the first starting circuit, thereby ensuring the efficiency of generating the first current with a positive temperature coefficient.
[0098] In an implementable solution, the first current generating circuit 1 further includes a current stabilizing module 13;
[0099] The current stabilization module 13 includes a fourth PMOS tube M6, a fifth PMOS tube M7, a sixth PMOS tube M8, a seventh PMOS tube M9 and a third NMOS tube M10;
[0100] The gate terminal of the fourth PMOS tube M6 is electrically connected to the drain terminal of the fourth PMOS tube M6, the gate terminal of the fifth PMOS tube M7, the gate terminal of the sixth PMOS tube M8, the gate terminal of the seventh PMOS tube M9, and the drain terminal of the third NMOS tube M10 respectively;
[0101] A source terminal of the fourth PMOS tube M6 is connected to a power supply voltage VCC;
[0102] The source end of the fifth PMOS tube M7 is electrically connected to the drain end of the first PMOS tube M3 , and the drain end of the fifth PMOS tube M7 is electrically connected to one end of the first resistor R1 ;
[0103] The source end of the sixth PMOS tube M8 is electrically connected to the drain end of the second PMOS tube M4, and the drain end of the sixth PMOS tube M8 is electrically connected to the drain end of the second NMOS tube M2 and the gate end of the second PMOS tube M4 respectively;
[0104] The source end of the seventh PMOS tube M9 is electrically connected to the drain end of the third PMOS tube M5, and the drain end of the seventh PMOS tube M9 is electrically connected to the reference voltage output circuit 3;
[0105] The gate terminal of the third NMOS transistor M10 is electrically connected to the drain terminal of the first NMOS transistor M1;
[0106] The source terminal of the third NMOS tube M10 is connected to the ground VSS;
[0107] The drain end of the seventh PMOS tube M9 is used to output the stabilized first current to the reference voltage output circuit 3 .
[0108] In this solution, the fourth PMOS tube M6, the fifth PMOS tube M7, the sixth PMOS tube M8, and the seventh PMOS tube M9 are of a common source and common gate circuit structure, which significantly reduces the influence of the channel length modulation effect, improves the accuracy of the subthreshold reference currents I1 and I2, and improves the power supply rejection ratio of the reference voltage source circuit.
[0109] In an implementable solution, the first current generating circuit 1 further includes a first working state control module 14;
[0110] The first working state control module 14 includes a fourth NMOS transistor M11 and an eighth PMOS transistor M12;
[0111] The drain terminal of the fourth NMOS transistor M11 is electrically connected to the gate terminal of the second NMOS transistor M2;
[0112] The drain terminal of the eighth PMOS tube M12 is electrically connected to the gate terminal of the second PMOS tube M4;
[0113] The first working state control module 14 is used to control the working state of the first current generating circuit 1 .
[0114] In this solution, accurate control of the working state of the first current generating circuit is achieved through the fourth NMOS tube M11 and the eighth PMOS tube M12.
[0115] In an implementable solution, the second current generating circuit 2 includes a second current generating module 21;
[0116] like Figure 4 As shown, the second current generating module 21 includes a ninth PMOS tube M13, a tenth PMOS tube M14, an eleventh PMOS tube M15, a fifth NMOS tube M16, a second resistor R2, a third resistor R3 and an amplifier D;
[0117] The source ends of the ninth PMOS tube M13, the tenth PMOS tube M14 and the eleventh PMOS tube M15 are connected to the power supply voltage VCC;
[0118] The gate end of the ninth PMOS tube M13 is electrically connected to the gate end of the tenth PMOS tube M14, the gate end of the eleventh PMOS tube M15, and the output end of the amplifier D respectively;
[0119] The positive input terminal of the amplifier D is electrically connected to the drain terminal of the ninth PMOS tube M13 and one end of the second resistor R2, and the negative input terminal of the amplifier D is electrically connected to one end of the third resistor R3 and the drain terminal of the fifth NMOS tube M16;
[0120] The gate terminal of the fifth NMOS transistor M16 is electrically connected to the other end of the third resistor R3 and the drain terminal of the tenth PMOS transistor M14 respectively;
[0121] The gate terminal of the ninth PMOS tube M13 is used to receive the second control signal to drive the second current generating module 21 to generate the second current;
[0122] The drain end of the eleventh PMOS tube M15 is used to output the second current.
[0123] Among them, the resistance value of R2 is the same as the resistance value of R3; the parameters of the ninth PMOS tube M13, the tenth PMOS tube M14 and the eleventh PMOS tube M15 are consistent, therefore, Figure 4 I3=I4=I CTAT .
[0124] In this solution, the second control signal is used to enable the second current generating circuit to reach a new equilibrium point, so that the second current generating module generates a second current with a negative temperature coefficient, thereby ensuring the efficiency of the second current generation and the reliability of the second current.
[0125] In an implementable solution, the second current generating circuit 2 further includes a second starting circuit 22;
[0126] The output end of the second startup circuit 22 is electrically connected to the gate end of the ninth PMOS transistor M13, and the input end of the second startup circuit 22 is electrically connected to the reference voltage output circuit 3;
[0127] The second starting circuit 22 is used to output a second control signal to control the second current generating module 21 to generate a second current.
[0128] Specifically, Figure 5 As shown, the second startup circuit 22 includes a 33rd PMOS tube M39, a 34th PMOS tube M40, a 35th PMOS tube M41 ... a 44th PMOS tube M50, and a 7th NMOS tube M51 and an 8th NMOS tube M52. Among them, M39-M50 are connected in series, the gate ends of M39-M50 are electrically connected, the drain end of the 33rd PMOS tube M39 is electrically connected to the gate end of the 33rd PMOS tube M39, the drain end of the 7th NMOS tube M51, and the gate end of the 8th NMOS tube M52; the drain end of the 8th NMOS tube M52 is electrically connected to the gate end of the 9th PMOS tube M13.
[0129] The working principle of the second starting circuit is similar to that of the first starting circuit, and will not be described in detail here.
[0130] In this solution, accurate control of the second current generating module is achieved through the second starting circuit, thereby ensuring the efficiency of generating the second current with a negative temperature coefficient.
[0131] In an implementable solution, the second current generating circuit 2 further includes a second working state control module 23;
[0132] The second working state control module 23 includes a twelfth PMOS tube M17, a sixth NMOS tube M18, a thirteenth PMOS tube M19 and a fourteenth PMOS tube M20;
[0133] The source end of the twelfth PMOS tube M17 is electrically connected to the drain end of the ninth PMOS tube M13, and the drain end of the twelfth PMOS tube M17 is electrically connected to the positive input end of the amplifier D;
[0134] The drain terminal of the sixth NMOS tube M18 is electrically connected to the output terminal of the amplifier D;
[0135] The source end of the thirteenth PMOS tube M19 is electrically connected to the drain end of the tenth PMOS tube M14, and the drain end of the thirteenth PMOS tube M19 is electrically connected to the gate end of the fifth NMOS tube M16;
[0136] The source end of the fourteenth PMOS tube M20 is electrically connected to the drain end of the eleventh PMOS tube M15, and the drain end of the fourteenth PMOS tube M20 is electrically connected to the reference voltage output circuit 3;
[0137] The second working state control module 23 is used to control the working state of the second current generating circuit 2 .
[0138] In this solution, accurate control of the working state of the second current generating circuit is achieved through the twelfth PMOS tube M17, the sixth NMOS tube M18, the thirteenth PMOS tube M19 and the fourteenth PMOS tube M20.
[0139] In an practicable solution, the second current generating circuit 2 further includes a capacitor C;
[0140] The capacitor C is electrically connected to the output terminal of the amplifier D;
[0141] The capacitor C is used to stabilize the second current.
[0142] In this solution, by setting the capacitor C, the second current generating circuit works stably, ensuring the accurate output of the second current.
[0143] In an implementable solution, the first NMOS transistor M1 , the second NMOS transistor M2 , and the fifth NMOS transistor M16 all operate in a subthreshold region.
[0144] In this solution, the first NMOS transistor M1, the second NMOS transistor M2 and the fifth NMOS transistor M16 working in the subthreshold region are used to reduce the power consumption of the circuit.
[0145] In an implementable solution, the first resistor R1, the second resistor R2 and the third resistor R3 are all resistors with variable resistance values;
[0146] The first resistor R1 corresponds to a first resistance value; the second resistor R2 and the third resistor R3 correspond to a second resistance value;
[0147] Different first resistance values and / or different second resistance values correspond to reference voltages with different temperature coefficients.
[0148] In this solution, by using a first resistor, a second resistor and a third resistor with variable resistance values, the temperature coefficients of the first current with a positive temperature coefficient and the second current with a negative temperature coefficient can be adjusted, thereby ensuring the timeliness, flexibility and effectiveness of adjusting the reference voltage.
[0149] In an implementable solution, the reference voltage output circuit 3 includes a fourth resistor R4;
[0150] The reference voltage output circuit 3 is used to obtain a reference voltage according to the first current, the second current and the fourth resistor R4.
[0151] In this solution, the stable output of the reference voltage is ensured by the first current, the second current and the fourth resistor.
[0152] In an implementable solution, the fourth resistor R4 is a resistor with a variable resistance value, and different resistance values of the fourth resistor R4 correspond to reference voltages of different magnitudes.
[0153] In this solution, by providing a fourth resistor with a variable resistance value, the flexibility of adjusting the reference voltage is ensured, the solution is applicable to more use occasions, and the versatility of the reference voltage source is improved.
[0154] in addition, Figure 4 and Figure 5 In the figure, VCC represents the power supply voltage, VSS represents the ground, enb and en represent switching signals, and the switching signals represented by enb and en are opposite.
[0155] The working principle of the reference voltage source circuit of this embodiment is explained below with reference to specific examples:
[0156] In the first current generating circuit, M1 and M2 are MOS transistors working in the subthreshold region, and the gate-source differential pair ΔV of M1 and M2 is GS With the characteristic of positive temperature coefficient, a current generating circuit (PTAT) proportional to absolute temperature can be designed, that is, a first current generating circuit. M1, M2 and R1 constitute a subthreshold reference current generating circuit, which can generate subthreshold reference currents I1 and I2, and further generate a first current I with a positive temperature coefficient. PTAT .
[0157] According to the subthreshold conduction formula:
[0158]
[0159] Among them, V GS is the gate-source voltage; V th is the threshold voltage; K = W / L is the width-to-length ratio of the transistor; V T =kT / q is the thermal voltage; k is the Boltzmann constant; T is the absolute temperature; q is the charge per unit electron; I0 is the characteristic current, which represents the drain current when the width-to-length ratio of the MOS tube W / L=1 and the potential of each electrode to the ground is zero; η represents the subthreshold slope factor, and η>1.
[0160] Can get,
[0161]
[0162] Where I1=I2, V GS1 represents the gate-source voltage of M1, V GS2 represents the gate-source voltage of M2, K1 represents the width-to-length ratio of M1, and K2 represents the width-to-length ratio of M2.
[0163]
[0164] The first current I can be obtained PTAT , which is a current with a positive temperature coefficient.
[0165] In the second current generating circuit, M16 is a MOS tube operating in the subthreshold region. When it is lower than a specific bias point related to temperature, its gate-source voltage V gs16 It decreases with the increase of temperature and has a negative temperature coefficient. Adding an operational amplifier can keep the voltage at its input consistent, playing the role of clamping the voltage and replicating the voltage more accurately. gs16 This voltage replaces the V of the transistor in the prior art. be This voltage is used to design a negative temperature coefficient (CTAT) current generating circuit, ie, the second current generating circuit.
[0166] According to the amplifier's virtual short and virtual disconnect principle, we can get
[0167] V1=I3*R2=V3=V2-I4*R3
[0168] Among them, Figure 5 As shown, V1 represents the voltage at the positive input terminal of the amplifier, I3 represents the current flowing out of the drain terminal of M17, V3 represents the voltage at the negative input terminal of the amplifier, I4 represents the current flowing out of the drain terminal of M19, and V2 represents the gate-source voltage of M16.
[0169] V2=V gs16 , R2=R3, I3=I4=I CTAT
[0170] I CTAT =V gs16 / 2R2
[0171] The second current I can be obtained CTAT , which is a current with a negative temperature coefficient.
[0172] Finally, the reference voltage can be obtained by passing through the fourth resistor R4. By adjusting the resistance values of the first resistor, the second resistor and the third resistor, reference voltages with different temperature coefficients can be obtained. In some application scenarios, by adjusting the resistance values of the first resistor, the second resistor and the third resistor, a reference voltage V with a zero temperature coefficient can be obtained. ref.
[0173]
[0174] V ref =(ΔV GS / R1+V gs16 / 2R2)*R4
[0175] In the present embodiment, two independent circuit structures are adopted to respectively generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and a reference voltage is obtained based on the first current and the second current, thereby overcoming the problem that the first current and the second current have a mutual influence and interference with each other, resulting in the output reference voltage not conforming to the actual usage scenario. The timeliness, flexibility and effectiveness of adjusting the reference voltage are guaranteed under the premise of achieving low temperature drift and high power supply rejection ratio, and the circuit area is effectively reduced. The circuit can work at a low voltage, reduce power consumption, save costs, and be suitable for more usage occasions, thereby improving the versatility of the reference voltage source. The key components in the reference voltage source circuit are all set as MOS tubes, and there is no need to use BiCMOS (bimetal oxide semiconductor) technology, which effectively reduces the circuit area and saves chip costs.
[0176] Example 3
[0177] This embodiment provides a chip such as Figure 6 As shown, the chip includes the reference voltage source circuit as described in Embodiment 1 or 2. The chip can be used in a wireless wearable device sensor.
[0178] The chip in this embodiment integrates the above-mentioned reference voltage source circuit, specifically adopts two independent circuit structures to respectively generate a corresponding first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and obtains a reference voltage based on the first current and the second current, thereby overcoming the mutual influence and interference between the first current and the second current, which causes the output reference voltage to not conform to the actual usage scenario. While achieving low temperature drift and high power supply rejection ratio, the chip ensures the timeliness, flexibility and effectiveness of adjusting the reference voltage, effectively reduces the circuit area, can operate at low voltage, reduces power consumption, saves costs, is suitable for more usage scenarios, and improves the versatility of the reference voltage source.
[0179] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A reference voltage source circuit, characterized in that: The reference voltage source circuit comprises a first current generating circuit, a second current generating circuit and a reference voltage output circuit; The first current generating circuit and the second current generating circuit are electrically connected to the reference voltage output circuit respectively; The first current generating circuit is used to generate a first current and output the first current to the reference voltage output circuit; wherein the first current is a current with a positive temperature coefficient; The second current generating circuit is used to generate a second current and output the second current to the reference voltage output circuit; wherein the second current is a current with a negative temperature coefficient; The reference voltage output circuit is used to generate a reference voltage based on the first current and the second current.
2. The reference voltage source circuit according to claim 1, wherein: The first current generating circuit includes a first current generating module; The first current generating module includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a first resistor; The gate end of the first NMOS transistor is electrically connected to one end of the first resistor and the drain end of the first PMOS transistor respectively, and the drain end of the first NMOS transistor is electrically connected to the other end of the first resistor and the gate end of the second NMOS transistor respectively; The drain end of the second NMOS tube is electrically connected to the gate end of the first PMOS tube, the gate end of the second PMOS tube, the drain end of the second PMOS tube, and the gate end of the third PMOS tube respectively; The drain end of the first NMOS tube is used to receive a first control signal to drive the first current generating module to generate the first current; The drain end of the third PMOS tube is used to output the first current.
3. The reference voltage source circuit according to claim 2, characterized in that: The first current generating circuit further includes a first starting circuit; The output end of the first startup circuit is electrically connected to the drain end of the first NMOS transistor, and the input end of the first startup circuit is electrically connected to the gate end of the first PMOS transistor; The first startup circuit is used to output the first control signal to control the first current generating module to generate the first current.
4. The reference voltage source circuit according to claim 3, characterized in that: The first current generating circuit further includes a current stabilizing module; The current stabilization module includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and a third NMOS tube; The gate end of the fourth PMOS tube is electrically connected to the drain end of the fourth PMOS tube, the gate end of the fifth PMOS tube, the gate end of the sixth PMOS tube, the gate end of the seventh PMOS tube, and the drain end of the third NMOS tube respectively; The source end of the fifth PMOS tube is electrically connected to the drain end of the first PMOS tube, and the drain end of the fifth PMOS tube is electrically connected to one end of the first resistor; The source end of the sixth PMOS tube is electrically connected to the drain end of the second PMOS tube, and the drain end of the sixth PMOS tube is electrically connected to the drain end of the second NMOS tube and the gate end of the second PMOS tube respectively; The source end of the seventh PMOS tube is electrically connected to the drain end of the third PMOS tube, and the drain end of the seventh PMOS tube is electrically connected to the reference voltage output circuit; The gate terminal of the third NMOS tube is electrically connected to the drain terminal of the first NMOS tube; The drain end of the seventh PMOS tube is used to output the first current after stabilization to the reference voltage output circuit.
5. The reference voltage source circuit according to claim 4, characterized in that: The first current generating circuit also includes a first working state control module; The first working state control module includes a fourth NMOS tube and an eighth PMOS tube; The drain terminal of the fourth NMOS tube is electrically connected to the gate terminal of the second NMOS tube; The drain terminal of the eighth PMOS tube is electrically connected to the gate terminal of the second PMOS tube; The first working state control module is used to control the working state of the first current generating circuit.
6. The reference voltage source circuit according to claim 5, characterized in that: The second current generating circuit includes a second current generating module; The second current generating module includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a fifth NMOS tube, a second resistor, a third resistor and an amplifier; The gate end of the ninth PMOS tube is electrically connected to the gate end of the tenth PMOS tube, the gate end of the eleventh PMOS tube, and the output end of the amplifier respectively; The positive input terminal of the amplifier is electrically connected to the drain terminal of the ninth PMOS tube and one end of the second resistor, and the negative input terminal of the amplifier is electrically connected to one end of the third resistor and the drain terminal of the fifth NMOS tube; The gate end of the fifth NMOS tube is electrically connected to the other end of the third resistor and the drain end of the tenth PMOS tube respectively; The gate terminal of the ninth PMOS tube is used to receive the second control signal to drive the second current generating module to generate the second current; The drain end of the eleventh PMOS tube is used to output the second current.
7. The reference voltage source circuit according to claim 6, characterized in that: The second current generating circuit further includes a second starting circuit; The output end of the second startup circuit is electrically connected to the gate end of the ninth PMOS tube, and the input end of the second startup circuit is electrically connected to the reference voltage output circuit; The second startup circuit is used to output the second control signal to control the second current generating module to generate the second current.
8. The reference voltage source circuit according to claim 7, characterized in that: The second current generating circuit further includes a second working state control module; The second working state control module includes a twelfth PMOS tube, a sixth NMOS tube, a thirteenth PMOS tube and a fourteenth PMOS tube; The source end of the twelfth PMOS tube is electrically connected to the drain end of the ninth PMOS tube, and the drain end of the twelfth PMOS tube is electrically connected to the positive input end of the amplifier; The drain end of the sixth NMOS tube is electrically connected to the output end of the amplifier; The source end of the thirteenth PMOS tube is electrically connected to the drain end of the tenth PMOS tube, and the drain end of the thirteenth PMOS tube is electrically connected to the gate end of the fifth NMOS tube; The source end of the fourteenth PMOS tube is electrically connected to the drain end of the eleventh PMOS tube, and the drain end of the fourteenth PMOS tube is electrically connected to the reference voltage output circuit; The second working state control module is used to control the working state of the second current generating circuit.
9. The reference voltage source circuit according to claim 8, characterized in that: The second current generating circuit further includes a capacitor; The capacitor is electrically connected to the output terminal of the amplifier; The capacitor is used to stabilize the second current.
10. The reference voltage source circuit according to any one of claims 6 to 9, characterized in that: The first NMOS transistor, the second NMOS transistor and the fifth NMOS transistor all operate in a subthreshold region.
11. The reference voltage source circuit according to any one of claims 6 to 9, characterized in that: The first resistor, the second resistor and the third resistor are all resistors with variable resistance values; Wherein, the first resistor corresponds to a first resistance value; the second resistor and the third resistor correspond to a second resistance value; Different first resistance values and / or different second resistance values correspond to the reference voltages with different temperature coefficients.
12. The reference voltage source circuit according to any one of claims 1 to 8, characterized in that: The reference voltage output circuit includes a fourth resistor; The reference voltage output circuit is used to obtain the reference voltage according to the first current, the second current and the fourth resistor.
13. The reference voltage source circuit according to claim 12, wherein: The fourth resistor is a resistor with a variable resistance value, and different resistance values of the fourth resistor correspond to different reference voltages.
14. A chip, characterized in that: The chip includes the reference voltage source circuit according to any one of claims 1-13.