Medium interface controller for improving XOR cache utilization rate

Abstract

The invention provides a media interface controller for improving the utilization rate of an XOR cache, and a command distribution method applied to the media interface controller comprises the following steps: in response to a received media interface command, obtaining an operation type indicated by the media interface command; determining an LUN controller associated with the media interface command and the operation type, distributing the media interface command to the LUN controller, and processing the media interface command by the LUN controller; wherein the operation type comprises P1 operation or R operation, the P1 operation indicates that specified data in the memory is moved to the NVM chip, the R operation indicates that XOR calculation is executed on the specified data in the memory, and a calculation result is reserved in the XOR cache. According to the method, the P1 operation and the R operation are mutually independent and do not influence each other, and after XOR calculation is completed and data in the XOR cache are moved, the XOR cache can be released in time, so that the occupation time of the XOR cache is shortened, and the utilization efficiency of the XOR cache is improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a medium interface controller for improving XOR cache utilization. Background Art

[0002] Figure 1A The block diagram of the storage device is shown. The storage device 102 is coupled to the host to provide storage capacity for the host. The host and the storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the storage device 102 through a variety of storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] Figure 1B A detailed block diagram showing the control components of a storage device.

[0008] The host accesses the storage device with IO commands that follow the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, and erase commands) that follow the interface protocol of the NVM chip based on the media interface commands. The control component also tracks that all media interface commands generated from an IO command have been executed and indicates the processing results of the IO command to the host.

[0009] See also Figure 1BThe control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a medium interface controller, and a storage medium management unit. The host interface obtains the IO command provided by the host, and generates a storage command to provide to the storage command processing unit. The storage command, for example, accesses storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. The physical page records one or more data frames. For example, the size of the physical page is 17664 bytes, and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0010] The storage medium management unit maintains the conversion of logical addresses to physical addresses for each storage command. For example, the storage medium management unit includes an FTL table. For a read command, the storage medium management unit outputs the physical address corresponding to the logical address accessed by the storage command. For a write command, the storage medium management unit allocates an available physical address and records the mapping relationship between the logical address accessed and the allocated physical address. The storage medium management unit also maintains functions required to manage the NVM chip, such as garbage collection and wear leveling.

[0011] The storage command processing unit operates the media interface controller to issue a storage media access command to the NVM chip according to the physical address provided by the storage media management unit. For the purpose of clarity, the command sent by the host to the storage device is called an IO command, the command sent by the host command processing unit to the storage command processing unit is called a storage command, the command sent by the storage command processing unit to the media interface controller is called a media interface command, and the command sent by the media interface controller to the NVM chip is called a storage media access command. The storage media access command follows the interface protocol of the NVM chip. SSD (Solid State Drives) includes multiple NVM chips. Each NVM chip includes one or more LUNs (Logical UNit), and each logical unit includes multiple physical blocks (Blocks). As the storage capacity increases, the number of NVM chips / LUNs / Blocks increases, and the probability of storage media failure also increases. In order to ensure the reliability of the stored data delivered to users, enterprise-level SSDs use technologies similar to RAID (Redundant Arrays of Independent Disks) (RAID technology for short) to construct data protection units across NVM chips / logic units, so that even if a single NVM chip / logic unit fails, data can still be protected from loss. This can also handle occasional data errors that occur during SSD operation.

[0012] Page stripes are data protection units in SSDs that are constructed based on RAID technology. Page stripes are constructed in large blocks. Large blocks include physical blocks from multiple logical units. Multiple logical units that provide physical blocks for large blocks are called logical unit groups. Each logical unit in a logical unit group can provide a physical block for a large block. For example, in Figure 2A In the schematic diagram of the large block shown, the large block is constructed on N+1 logical units. Each large block includes N+1 physical blocks respectively from the N+1 logical units. The large block stores user data and verification data. The verification data of the large block is calculated based on the user data stored in the large block. As an example, the verification data is stored in the last physical block of the large block. Other physical blocks of the large block can also be selected to store the verification data. Other construction methods can also be used to construct the large block, such as referring to Figure 2B As shown, an implementation method of constructing large blocks in multi-plane logic units.

[0013] A large block is used as the allocation and recovery unit of storage medium resources in SSD. When allocating storage medium resources to carry written data, an idle large block is selected. Data is written sequentially inside the selected large block. When reclaiming storage medium resources, the large block is reclaimed as a whole, and after the valid data is reclaimed, all physical blocks of the large block are erased. Therefore, in an SSD, all physical blocks in a large block usually always have the same number of erase and write times.

[0014] See also Figure 3A as well as Figure 3B As shown, a large block includes multiple page stripes, and a page stripe includes multiple physical pages, which are from different physical blocks of the same large block. For example, among the multiple physical pages of a page stripe, P pages are used to store user data, and Q pages are used to store check data ( Figure 3A and Figure 3B In the example, Q=1). The data written to page i is recorded as D(i). The check data D(Q) is generated by the P page user data according to the specified error correction algorithm. For example, the check data is determined based on the XOR operation, then D(Q)=D(0)XOR D(1)XOR...XOR D(P-1). Therefore, when writing data to the page stripe, D(Q) can only be calculated if D(0) to D(P-1) are known. The size of D(i) is typically 2KB, 4KB, 16KB, etc.

[0015] In TLC (Triple-Level Cell) flash memory, the One-Shot programming mode is usually used, which requires programming three physical pages on the same word line in one ONFI command, which makes a single programming command to operate three physical pages. Accordingly, in order to improve write performance, page stripes are constructed in groups of three physical pages, so that the size of D(Q) is typically 48KB. In multi-plane TLB (Translation Lookaside Buffer) flash memory, a multi-plane programming mode can be used to improve write performance. This makes a single programming command operate, for example, 12 physical pages (each logical unit includes 4 planes). Accordingly, the size of D(Q) is typically 192KB.

[0016] In order to use RAID technology, it is necessary to calculate the check data D(Q) for the data written to the page stripe. The calculation of the check data involves a large number of XOR operations. In order to speed up this process, a dedicated hardware unit (called an XOR calculation unit) is usually used to complete the calculation of D(Q) = D(0) XOR D(1) XOR ... XOR D(P-1). The XOR calculation unit also includes an XOR cache, which is used to cache the data D(i) and the intermediate results of each XOR calculation, such as the result of D(0) XOR D(1), the result of D(0) XOR D(1) XOR D(2), until the final D(Q) is obtained, and then D(Q) is written to the page stripe. Therefore, the size of the XOR cache needs to be able to accommodate the entire D(i), and when a page stripe is allocated, from the beginning of writing data to this page stripe to the time when this page stripe is full, the entire XOR cache needs to be occupied to serve the operation of writing data to this page stripe.

[0017] In order to improve the performance of SSD, data can be written to multiple page stripes of multiple large blocks at the same time. Accordingly, an exclusive XOR cache needs to be allocated to each page stripe that is written concurrently. As mentioned above, the size of D(Q) can reach 192KB (including some out-of-band data), so a single XOR cache requires a capacity of about 200KB. However, the internal cache resources of the chip are very expensive, so the number of XOR caches of the XOR calculation unit is usually small (for example, 1-4).

[0018] In Chinese patent applications such as 201610861793.5, 2016108365313, 201720947480.1, 2020106151782, and 2020106130343, a medium interface controller is provided. In the prior art, the XOR calculation unit is located in the medium interface controller, see Figure 4A and Figure 4BAs shown. By operating the XOR calculation unit, page stripes with different data protection capabilities are adapted. The data protection level of the page stripe is determined by the size relationship between the check data and the user data, that is, the values ​​of P and Q represent the data protection capability of the page stripe. In addition, when the media interface controller provides data (e.g., D(0)) to the NVM chip (e.g., physical page P0-0) through a (Program) programming command, the XOR calculation is completed. For example, suppose that XOR cache 0 (initialized to all 0s) is allocated to page stripe 0. In the process of moving D(0) to physical page P0-0 of page stripe 0, 0XOR D(0) is calculated, and the result is D(0) and saved in XOR cache 0. Next, D(1) is moved to physical page P0-1 of page stripe 0, and D(0)XOR D(1) is calculated, where D(0) is inside XOR cache 0 and D(1) is obtained during data movement. Subsequently, the result of D(0)XOR D(1) is recorded in XOR cache 0. Next, D(2) is moved to physical page P0-2 of page stripe 0, and the result of D(0)XOR D(1) recorded in XOR cache 0 is XORed with the moved D(2), and the result is still saved in XOR cache 0. Similarly, after D(P-1) is moved to physical page P0-(P-1) of page stripe 0, D(Q) is obtained in XOR cache 0, and then D(Q) is moved to physical page P0-P of page stripe 0. At this point, page stripe 0 is full and XOR cache 0 is released.

[0019] As an optimization method, the media interface command received by the media interface controller may only include an instruction to write D(0) to D(P-1) into the physical addresses of the pages of the page stripe, but not include an instruction to write D(Q) into the page stripe. The media interface controller automatically calculates D(Q) and writes it into the page stripe.

[0020] For media interface controllers, which need to manage multiple logical units (LUNs), see Figure 5 . For the purpose of performance, for example, it is necessary to give full play to the ability of multiple logical units to process commands in parallel, as well as to control the cost of the media interface controller and reduce its circuit scale. In the prior art (such as Chinese patent application 201610861793.5), a media interface controller including multiple threads is provided. As a schedulable task processing unit, a thread can be dynamically bound to a logical unit, and commands to the logical unit bound to it are processed through the thread. In the Chinese patent application with application number "2022117373066", the coroutine is used as a task processing unit corresponding to the logical unit, and a microinstruction sequence is executed through the coroutine to operate access to the logical unit, such as, see Figure 5 . Figure 5In the present invention, the host interface obtains the IO command provided by the host, and generates a storage command to provide to the storage command processing unit. The storage command, for example, accesses the storage space of the same size, such as 4KB. In the prior art, a corresponding flash controller (Flash Controller) is provided for each flash channel or logic unit, and the logic unit bound thereto is operated by providing a command to the flash controller.

[0021] Whether it is a software or firmware-based thread, coroutine, or a hardware-based flash memory controller, it is a task processing unit that can operate to access the logical unit bound to it. Multiple task processing units can work in parallel, thereby operating multiple logical units at the same time. For the purpose of clarity, it is referred to as a LUN controller. Its implementation method includes threads, coroutines, flash memory controllers and other implementation methods with similar functions of the media interface controller in the prior art, and also includes implementation methods for operating access to logical units in media interface controllers that will appear in the future and are bound to logical units. Therefore, in the media interface command provided to the media interface controller, the LUN controller is specified to process the media interface command and access the logical unit by describing the logical unit to be accessed.

[0022] In the existing scheme, in addition to completing the XOR calculation in the process of the media interface controller providing data (such as D(0)) to the NVM chip through a programming command, a function is added to the media interface controller. For example, the media interface controller provided in the Chinese patent application with application number 201911367405.8 can perform an XOR operation on the specified data in the DRAM, but does not necessarily write the specified data to the NVM chip. Therefore, when operating a page stripe with a larger P value, the calculation of D(Q) is divided into multiple segments. For example, in the first segment, D(0)XOR D(1)XOR(D2)...XOR D(m) (the result is temp) is calculated, and in the second segment, temp XOR D(m+1)XOR...XOR D(P-1) is calculated to obtain D(Q). Among them, the temp transmitted to the XOR calculation unit in the second segment is not written into the NVM chip.

[0023] The operation of performing XOR calculation on the specified data in the DRAM by the XOR calculation unit but not writing the specified data into the NVM chip is called the verification data calculation operation (abbreviated as R operation). The two operations involved in the XOR calculation in the R operation are one from the XOR cache and one from the DRAM, so that the media interface command that instructs the media interface controller to perform the R operation needs to describe the DRAM address, and also needs to specify the XOR cache to be used in the operation. In the R operation, the result of the XOR calculation is retained in the XOR cache.

[0024] The media interface command that instructs the media interface controller to perform a programming operation means writing the specified data in the DRAM to the specified physical address of the NVM chip through the Program command, and incidentally performing an XOR calculation on the specified data and the data in the XOR cache, and the calculation result is retained in the XOR cache. This operation is referred to as the P operation.

[0025] Usually, the P operation is coordinated with the operation of writing the data in the XOR cache into the NVM chip, and the verification data is generated using the specified data in the DRAM and written into the page stripe. Summary of the invention

[0026] When erasing a physical block within a large block, the previous erase operation needs to occupy the NVM chip for a long time, which causes the subsequent program command on the NVM chip to be delayed, and the XOR cache corresponding to the page stripe to which the physical page operated by the program command belongs cannot be released in time, which increases the XOR cache occupancy time and reduces the utilization rate of the XOR cache.

[0027] Moreover, when recycling storage medium resources, the large block is recycled as a whole, and after the valid data is recycled, all physical blocks of the large block are erased. The power consumption required when the NVM chip performs the erase operation is relatively large, and the simultaneous erasing of all physical blocks of the large block further increases the instantaneous power consumption of the storage device, which may even exceed the power supply capacity of the storage device. The fluctuation of power consumption also poses a challenge to the power supply capacity of the data center. Therefore, it is hoped that the fluctuation of power consumption during the operation of the storage device can be suppressed.

[0028] On the other hand, the XOR cache resources in the storage device are limited, and it is hoped that the processing performed using the XOR cache resources will be completed as soon as possible to release the XOR cache as soon as possible to improve resource utilization. However, when there is an erase operation, the LUN controller that performs the erase operation is also occupied, so that the subsequent programming operations and / or processing of operations using the XOR cache by the LUN controller are delayed. This problem can be alleviated to a certain extent by scheduling the LUN controller. However, when a large block is recycled and all physical blocks of the large block are erased, all LUN controllers are occupied by the erase operation, resulting in an inability to find an idle LUN controller to process operations using the XOR cache, which in turn leads to an increase in the occupancy time of the XOR cache, a decrease in utilization efficiency, and a decrease or fluctuation in the read / write performance of the storage device. The present application hopes to provide a method to solve one or more of the above-mentioned technical problems.

[0029] In a first aspect, an embodiment of the present application provides a command allocation method, including:

[0030] In response to the received media interface command, obtaining an operation type indicated by the media interface command;

[0031] Determine a LUN controller associated with the media interface command and the operation type, distribute the media interface command to the LUN controller, and allow the LUN controller to process the media interface command;

[0032] The operation type includes a P1 operation or an R operation, wherein the P1 operation indicates moving specified data in the memory to the NVM chip, and the R operation indicates performing an XOR calculation on the specified data in the memory and retaining the calculation result in the XOR cache.

[0033] Optionally, the operation type further includes a P2 operation, and the P2 operation indicates moving the data in the XOR cache to the NVM chip.

[0034] Optionally, obtaining the operation type indicated by the media interface command includes:

[0035] Based on the operation type field included in the media interface command, the operation type corresponding to the media interface command is determined.

[0036] Optionally, in the case where the operation type is a P1 operation or a P2 operation, the medium interface command includes a field indicating a physical address of an NVM chip to be accessed and a field indicating data to be moved;

[0037] The determining a LUN controller associated with the media interface command and the operation type includes:

[0038] Determining the accessed logical unit based on the physical address indicated by the media interface command;

[0039] Based on the mapping relationship between the logical unit and the LUN controller, the LUN controller corresponding to the accessed logical unit is determined.

[0040] Optionally, in the case where the operation type is a P1 operation, in response to the accessed physical page and the specified data in the memory, the LUN controller generates a storage medium access command and sends it to the corresponding logical unit to write the specified data to the corresponding physical page to perform the P1 operation;

[0041] The accessed physical page is determined based on the physical address indicated by the media interface command, and the designated data is the data to be moved in the memory indicated by the media interface command.

[0042] Optionally, when the operation type is a P2 operation, in response to the accessed physical page and the check data in the XOR cache, the LUN controller generates a storage medium access command and sends it to the corresponding logical unit to write the check data to the corresponding physical page to perform the P2 operation;

[0043] The accessed physical page is determined based on the physical address indicated by the media interface command, the verification data is the data to be moved in the XOR cache indicated by the media interface command, and the verification data is determined based on multiple specified data to be moved in the memory, and the multiple specified data are written into the same page stripe.

[0044] Optionally, when the operation type is an R operation, determining a LUN controller associated with the media interface command and the operation type includes:

[0045] A LUN controller determined from among the multiple LUN controllers and having no uncompleted erase operation is determined as a LUN controller associated with the media interface command and the operation type.

[0046] Optionally, when the media interface command includes a field indicating a LUN controller, determining a LUN controller without an uncompleted erase operation as a LUN controller associated with the media interface command and the operation type includes:

[0047] Determine a first LUN controller based on the LUN controller indicated by the media interface command;

[0048] If there is no uncompleted erase operation on the first LUN controller, determining the first LUN controller as a LUN controller associated with the media interface command and the operation type; and

[0049] If the first LUN controller has an uncompleted erase operation, a second LUN controller determined from a plurality of LUN controllers and having no uncompleted erase operation is determined as the LUN controller associated with the media interface command and the operation type.

[0050] Optionally, the field indicating the LUN controller is a field indicating a logical unit to be accessed.

[0051] Optionally, the media interface command includes a source address field and a destination address field indicating data to be operated; the method further includes:

[0052] Applying for an XOR cache based on a destination address indicated by the media interface command;

[0053] In case the application is successful, the determined LUN controller performs an XOR operation on the data to be operated indicated by the source address field and the data in the applied XOR cache, and retains the calculation result in the applied XOR cache.

[0054] Optionally, the method further comprises:

[0055] In the case of application failure, the XOR cache is repeatedly applied based on the destination address indicated by the media interface command until the application is successful.

[0056] Optionally, the method further comprises:

[0057] In response to the determined LUN controller completing the R operation, the applied XOR buffer is released.

[0058] Optionally, if the LUN controller has an uncompleted erase operation, the LUN controller processes the media interface command whose operation type is a P1 operation or a P2 operation after processing the erase operation.

[0059] Optionally, if the operation type indicates an erase operation, obtaining the number of erase operations being processed by one or more LUN controllers;

[0060] If the number of erase operations being processed by one or more LUN controllers is greater than a threshold, suspending processing of the media interface command whose operation type is an erase operation; and

[0061] If the number of erase operations being processed by all LUN controllers is not greater than a threshold, determining the accessed logical unit based on the physical address indicated by the media interface command;

[0062] Based on the mapping relationship between the logical unit and the LUN controller, the LUN controller corresponding to the accessed logical unit is determined.

[0063] In a second aspect, an embodiment of the present application provides a media interface controller, including: a command allocation unit and a plurality of LUN controllers;

[0064] The command allocation unit obtains, in response to the received media interface command, an operation type indicated by the media interface command, determines a LUN controller associated with the media interface command and the operation type among the multiple LUN controllers, allocates the media interface command to the LUN controller, and the LUN controller processes the media interface command;

[0065] The operation type is a P1 operation or an R operation, the P1 operation indicates moving specified data in the memory to the NVM chip, and the R operation indicates performing an XOR calculation on the specified data in the memory and retaining the calculation result in the XOR cache.

[0066] Optionally, the operation type further includes a P2 operation, and the P2 operation indicates moving the data in the XOR cache to the NVM chip.

[0067] Optionally, the command allocation unit determines the operation type corresponding to the media interface command based on an operation type field included in the media interface command.

[0068] Optionally, in the case where the operation type is a P1 operation or a P2 operation, the medium interface command includes a field indicating a physical address of an NVM chip to be accessed and a field indicating data to be moved;

[0069] The command allocation unit determines the accessed logical unit based on the physical address indicated by the media interface command; and determines the LUN controller corresponding to the accessed logical unit based on the mapping relationship between the logical unit and the LUN controller.

[0070] Optionally, in the case where the operation type is a P1 operation, in response to the accessed physical page and the specified data in the memory, the LUN controller generates a storage medium access command and sends it to the corresponding logical unit to write the specified data to the corresponding physical page to perform the P1 operation;

[0071] The accessed physical page is determined based on the physical address indicated by the media interface command, and the designated data is the data to be moved in the memory indicated by the media interface command.

[0072] Optionally, when the operation type is a P2 operation, in response to the accessed physical page and the check data in the XOR cache, the LUN controller generates a storage medium access command and sends it to the corresponding logical unit to write the check data to the corresponding physical page to perform the P2 operation;

[0073] The accessed physical page is determined based on the physical address indicated by the media interface command, the verification data is the data to be moved in the XOR cache indicated by the media interface command, and the verification data is determined based on multiple specified data to be moved in the memory, and the multiple specified data are written into the same page stripe.

[0074] Optionally, when the operation type is an R operation, the command allocation unit determines a LUN controller that does not have an uncompleted erase operation from among a plurality of LUN controllers as the LUN controller associated with the media interface command and the operation type.

[0075] Optionally, in a case where the media interface command includes a field indicating a LUN controller, the command allocation unit determines the first LUN controller based on the LUN controller indicated by the media interface command;

[0076] If there is no uncompleted erase operation on the first LUN controller, the command allocation unit determines the first LUN controller as a LUN controller associated with the media interface command and the operation type; and

[0077] If the first LUN controller has an uncompleted erase operation, the command allocation unit determines a second LUN controller determined from the plurality of LUN controllers and having no uncompleted erase operation as the LUN controller associated with the media interface command and the operation type.

[0078] Optionally, the field indicating the LUN controller is a field indicating a logical unit to be accessed.

[0079] Optionally, the media interface command includes a source address field and a destination address field indicating data to be operated; the determined LUN controller applies for an XOR cache based on the destination address indicated by the media interface command;

[0080] In case the application is successful, the determined LUN controller performs an XOR operation on the data to be operated indicated by the source address field and the data in the applied XOR cache, and retains the calculation result in the applied XOR cache.

[0081] Optionally, in the case of application failure, the XOR cache is repeatedly applied based on the destination address indicated by the media interface command until the application succeeds.

[0082] Optionally, in response to the determined LUN controller completing the R operation, the applied XOR cache is released.

[0083] Optionally, if the LUN controller has an uncompleted erase operation, the LUN controller processes the media interface command whose operation type is a P1 operation or a P2 operation after processing the erase operation.

[0084] Optionally, if the operation type indicates an erase operation, the command allocation unit obtains the number of erase operations being processed by one or more LUN controllers;

[0085] If the number of erase operations being processed by one or more LUN controllers is greater than a threshold, the command allocation unit suspends processing of the media interface command whose operation type is an erase operation; and

[0086] If the number of erase operations being processed by all LUN controllers is not greater than a threshold, the command allocation unit determines the accessed logical unit based on the physical address indicated by the media interface command; and determines the LUN controller corresponding to the accessed logical unit based on a mapping relationship between the logical unit and the LUN controller.

[0087] In a third aspect, an embodiment of the present application provides a data access method, including:

[0088] In response to writing designated data to each first physical page of the first page stripe, generating a pair of P1 operation and R operation, wherein the P1 operation indicates moving the designated data in the memory to the NVM chip, and the R operation indicates performing an XOR calculation on the designated data in the memory, and retaining the calculation result in a first XOR cache corresponding to the first page stripe; wherein the first page stripe includes a second physical page and a plurality of first physical pages;

[0089] In response to data being written to the second physical page of the first page stripe, a P2 operation is generated, the P2 operation indicating writing the check data in the first XOR buffer to the second physical page of the first page stripe.

[0090] Optionally, after the check data corresponding to the first page stripe is determined according to the R operations respectively corresponding to the multiple first physical pages, the P2 operation is processed.

[0091] Optionally, the method further comprises:

[0092] The first XOR buffer is allocated for the first page stripe of designated data to be written into the memory.

[0093] Optionally, when processing the generated P1 operation and the R operation, the method includes:

[0094] When processing each of the P1 operations, determining a corresponding first LUN controller according to the logical unit to which the first physical page indicated by the P1 operation belongs, and processing the P1 operation through the first LUN controller to write the specified data in the memory indicated by the P1 operation into the first physical page indicated by the P1 operation;

[0095] When processing each of the R operations, a second LUN controller for processing the R operation is determined, and the R operation is processed by the second LUN controller to perform an XOR operation on the designated data indicated by the R operation and store the operation result in the first XOR cache.

[0096] Optionally, the determining a second LUN controller for processing the R operation includes:

[0097] A LUN controller having no uncompleted erase operation among the multiple LUN controllers is determined as the second LUN controller.

[0098] Optionally, if there is an uncompleted erase operation on the first LUN controller, a LUN controller on which there is no uncompleted erase operation is determined from multiple LUN controllers, and the LUN controller is determined as the second LUN controller;

[0099] If the first LUN controller does not have any uncompleted erase operation, the first LUN controller is determined as the second LUN controller.

[0100] Optionally, before processing the R operation through the second LUN controller, applying for the first XOR cache;

[0101] If the first XOR cache is applied for, the second LUN controller moves the designated data to be operated to the first XOR cache, and performs an XOR operation with the data in the first XOR cache.

[0102] Optionally, the method further comprises:

[0103] If the first XOR buffer is not applied for, the first XOR buffer is applied for repeatedly until the application is successful.

[0104] Optionally, the method further comprises:

[0105] When the R operation is completed, the first XOR buffer is released.

[0106] Optionally, if the first LUN controller has an uncompleted erase operation, after the first LUN controller completes the erase operation, the first LUN controller processes the P1 operation.

[0107] Optionally, if the P1 operation is allocated to the second LUN controller during the process of the second LUN controller processing the R operation, the second LUN controller processes the P1 operation after the second LUN controller completes processing the R operation.

[0108] Optionally, the relationship between the first LUN controller and the second LUN controller is one of the following:

[0109] The logical units corresponding to the first LUN controller and the second LUN controller belong to the same logical unit group;

[0110] The logical units corresponding to the first LUN controller and the second LUN controller belong to different logical unit groups;

[0111] Each logical unit group includes a plurality of logical units, each logical unit corresponds to a LUN controller, and logical units belonging to the same logical unit group correspond to the same large block.

[0112] Optionally, when generating the paired P1 operation and the R operation, the method further includes:

[0113] Obtaining whether the first LUN controller corresponding to the P1 operation has an uncompleted erase operation;

[0114] If the first LUN controller has no unprocessed erase operation, indicating the first LUN controller in the generated R operation;

[0115] If the first LUN controller has an unprocessed erase operation, a LUN controller other than the first LUN controller and having no unprocessed erase operation is indicated in the generated R operation.

[0116] Optionally, after generating the P2 operation, the method further includes:

[0117] A corresponding third LUN controller is determined according to the logical unit to which the second physical page belongs, and the third LUN controller processes the P2 operation to write the verification data into the second physical page.

[0118] Optionally, when there is an erase operation being processed by the third LUN controller, the method further includes:

[0119] Move the check data in the first XOR buffer indicated by the P2 operation to an external memory, and release the first XOR buffer;

[0120] After the third LUN controller completes the processing of the erase operation, the first XOR cache is applied for, the verification data is moved to the first XOR cache, and the verification data in the first XOR cache is written into the second physical page.

[0121] Optionally, multiple LUN controllers process multiple pairs of P1 operations, R operations, and one P2 operation in parallel.

[0122] Optionally, when allocating a LUN controller for the P1 operation, if a first LUN controller is determined based on the logical unit corresponding to the P1 operation and there is at least one operation to be processed in the first LUN controller, continue to allocate the P1 operation to the first LUN controller;

[0123] When allocating a LUN controller for the P2 operation, if a third LUN controller is determined based on the logical unit corresponding to the P2 operation and the third LUN controller has at least one operation to be processed, continue to allocate the P2 operation to the third LUN controller.

[0124] Optionally, when allocating a LUN controller for the R operation, if a LUN controller that does not have any unprocessed erase operations is determined from multiple LUN controllers as the second LUN controller, and if the second LUN controller has at least one operation to be processed, the R operation continues to be allocated to the second LUN controller.

[0125] Optionally, when writing designated data to a plurality of first physical pages of the first page stripe, a plurality of pairs of P1 operations and R operations are generated and allocated to corresponding LUN controllers;

[0126] In parallel, LUN controllers are allocated to multiple pairs of P1 operations and R operations.

[0127] Optionally, the multiple LUN controllers each independently processes the assigned P1 operation regardless of the working status of other LUN controllers;

[0128] Each of the multiple LUN controllers independently processes the assigned R operation when applying for the first XOR cache, regardless of the working status of other LUN controllers.

[0129] Optionally, if the first page stripe is not allocated to the first XOR cache, the generation of the P1 operation and the R operation is suspended; after being allocated to the first XOR cache, the generation of the P1 operation and the R operation continues.

[0130] Optionally, after completing the P2 operation, the first XOR cache is set to an allocatable state.

[0131] Optionally, in the case of writing data to multiple page stripes, P1 operations and R operations corresponding to the multiple page stripes are generated and allocated, and processed in parallel by multiple LUN controllers;

[0132] The LUN controller processes only one operation each time, multiple page stripes correspond to multiple XOR caches, and the R operations corresponding to the same page stripe use the same XOR cache.

[0133] In a fourth aspect, an embodiment of the present application provides a control component, including a storage command processing unit and a medium interface controller;

[0134] In response to writing designated data to each first physical page of the first page stripe, the storage command processing unit generates a medium interface command indicating a pair of P1 operation and R operation and provides the command to the medium interface controller, wherein the P1 operation indicates that the designated data in the memory is moved to the NVM chip, and the R operation indicates that an XOR calculation is performed on the designated data in the memory, and the calculation result is retained in a first XOR cache corresponding to the first page stripe; wherein the first page stripe includes a second physical page and a plurality of first physical pages;

[0135] In response to writing data to the second physical page of the first page stripe, the storage command processing unit generates a media interface command indicating a P2 operation and provides it to the media interface controller. The P2 operation indicates writing the check data in the first XOR cache to the second physical page of the first page stripe.

[0136] Optionally, the media interface controller processes the P2 operation after determining the check data corresponding to the first page stripe according to the R operations respectively corresponding to the multiple first physical pages.

[0137] Optionally, the storage command processing unit allocates the first XOR buffer for the first page stripe of designated data to be written into the memory.

[0138] Optionally, when processing the generated P1 operation and the R operation, the media interface controller includes:

[0139] When processing each of the P1 operations, the media interface controller determines the corresponding first LUN controller according to the logical unit to which the first physical page indicated by the P1 operation belongs, and processes the P1 operation through the first LUN controller to write the specified data in the memory indicated by the P1 operation into the first physical page indicated by the P1 operation;

[0140] When processing each of the R operations, the media interface controller determines a second LUN controller for processing the R operation, processes the R operation through the second LUN controller, performs an XOR operation on the designated data indicated by the R operation, and stores the operation result in the first XOR cache.

[0141] Optionally, the media interface controller determines a LUN controller having no uncompleted erase operation from among the multiple LUN controllers as the second LUN controller.

[0142] Optionally, if the first LUN controller has an uncompleted erase operation, the media interface controller determines a LUN controller from among the multiple LUN controllers that has no uncompleted erase operation, and determines the LUN controller as the second LUN controller;

[0143] If the first LUN controller does not have any uncompleted erase operation, the media interface controller determines the first LUN controller as the second LUN controller.

[0144] Optionally, before processing the R operation through the second LUN controller, the media interface controller applies for the first XOR cache;

[0145] If the first XOR cache is applied for, the second LUN controller moves the designated data to be operated to the first XOR cache, and performs an XOR operation with the data in the first XOR cache.

[0146] Optionally, if the first XOR buffer is not applied for, the media interface controller repeatedly applies for the first XOR buffer until the application is successful.

[0147] Optionally, the media interface controller releases the first XOR buffer when completing the R operation.

[0148] Optionally, if the first LUN controller has an uncompleted erase operation, after the first LUN controller completes the erase operation, the first LUN controller processes the P1 operation.

[0149] Optionally, if the media interface controller allocates the P1 operation to the second LUN controller during the process of the second LUN controller processing the R operation, then after the second LUN controller completes processing the R operation, the second LUN controller processes the P1 operation again.

[0150] Optionally, the relationship between the first LUN controller and the second LUN controller is one of the following:

[0151] The logical units corresponding to the first LUN controller and the second LUN controller belong to the same logical unit group;

[0152] The logical units corresponding to the first LUN controller and the second LUN controller belong to different logical unit groups;

[0153] Each logical unit group includes a plurality of logical units, each logical unit corresponds to a LUN controller, and logical units belonging to the same logical unit group correspond to the same large block.

[0154] Optionally, when generating the paired P1 operation and R operation, the storage command processing unit obtains whether the first LUN controller corresponding to the P1 operation has an unprocessed erase operation;

[0155] If the first LUN controller has no unprocessed erase operation, indicating the first LUN controller in the generated R operation;

[0156] If the first LUN controller has an unprocessed erase operation, a LUN controller other than the first LUN controller and having no unprocessed erase operation is indicated in the generated R operation.

[0157] Optionally, the media interface controller determines a corresponding third LUN controller according to the logical unit to which the second physical page belongs, and the third LUN controller processes the P2 operation to write the verification data into the second physical page.

[0158] Optionally, in the case that there is an erase operation being processed by the third LUN controller, the media interface controller moves the check data in the first XOR buffer indicated by the P2 operation to an external memory, and releases the first XOR buffer;

[0159] After the third LUN controller completes processing of the erase operation, the media interface controller applies for the first XOR cache, moves the verification data to the first XOR cache, and writes the verification data in the first XOR cache into the second physical page.

[0160] Optionally, multiple LUN controllers process multiple pairs of P1 operations, R operations, and one P2 operation in parallel.

[0161] Optionally, when allocating a LUN controller for the P1 operation, the media interface controller continues to allocate the P1 operation to the first LUN controller if a first LUN controller is determined based on a logical unit corresponding to the P1 operation and the first LUN controller has at least one operation to be processed;

[0162] When allocating a LUN controller for the P2 operation, the media interface controller continues to allocate the P2 operation to the third LUN controller if a third LUN controller is determined based on the logical unit corresponding to the P2 operation and the third LUN controller has at least one operation to be processed.

[0163] Optionally, when allocating a LUN controller for the R operation, the media interface controller determines from multiple LUN controllers that a LUN controller that does not have an unprocessed erase operation is the second LUN controller, and if the second LUN controller has at least one operation to be processed, the media interface controller continues to allocate the R operation to the second LUN controller.

[0164] Optionally, when the storage command processing unit writes designated data to a plurality of first physical pages of the first page stripe, a plurality of pairs of P1 operations and R operations are generated and allocated to corresponding LUN controllers;

[0165] In parallel, LUN controllers are allocated to multiple pairs of P1 operations and R operations.

[0166] Optionally, the multiple LUN controllers each independently processes the assigned P1 operation regardless of the working status of other LUN controllers;

[0167] Each of the multiple LUN controllers independently processes the assigned R operation when applying for the first XOR cache, regardless of the working status of other LUN controllers.

[0168] Optionally, if the first page stripe is not allocated to the first XOR cache, the storage command processing unit suspends generating P1 operations and R operations; after being allocated to the first XOR cache, the storage command processing unit continues generating P1 operations and R operations.

[0169] Optionally, after completing the P2 operation, the media interface controller sets the first XOR buffer to an allocatable state.

[0170] Optionally, in the case of writing data to multiple page stripes, P1 operations and R operations corresponding to the multiple page stripes are generated and allocated, and processed in parallel by multiple LUN controllers;

[0171] The LUN controller processes only one operation each time, multiple page stripes correspond to multiple XOR caches, and the R operations corresponding to the same page stripe use the same XOR cache.

[0172] In a fifth aspect, an embodiment of the present application provides an erasure control method, including:

[0173] In response to a received media interface command, determining that the media interface command indicates an erase operation;

[0174] Determining a first LUN controller associated with the media interface command and the erase operation;

[0175] When the number of unprocessed erase operations meets a first preset condition and the first LUN controller has no unprocessed erase operations, the media interface command is allocated to the first LUN controller, and the first LUN controller processes the erase operation based on the media interface command.

[0176] Optionally, in response to the received media interface command, determining that the media interface command indicates an erase operation includes:

[0177] Based on the operation type field included in the media interface command, it is determined that the media interface command indicates an erase operation.

[0178] Optionally, the media interface command includes a field indicating an address of a physical block to be erased, and the determining a first LUN controller associated with the media interface command and the erase operation includes:

[0179] Determining a logical unit corresponding to the erase operation based on a physical block address indicated by the media interface command;

[0180] Based on the mapping relationship between the logical unit and the LUN controller, a first LUN controller matching the logical unit corresponding to the erase operation is determined.

[0181] Optionally, the method further comprises:

[0182] When the number of uncompleted erase operations meets a second preset condition, the medium interface command is received.

[0183] Optionally, when the number of uncompleted erase operations meets a second preset condition, receiving the medium interface command comprises one of the following steps:

[0184] In the absence of an uncompleted erase operation, receiving the medium interface command;

[0185] When the number of the uncompleted erase operations is less than or equal to a second threshold, the medium interface command is received.

[0186] Optionally, before or after determining the first LUN controller, the method further includes:

[0187] Get the number of outstanding erase operations;

[0188] If the acquired number of unprocessed erase operations does not satisfy the first preset condition, suspending the processing of the medium interface command;

[0189] If the acquired number of unprocessed erase operations meets the first preset condition, the medium interface command continues to be processed.

[0190] Optionally, if the acquired number of unprocessed erase operations does not satisfy the first preset condition, suspending processing of the media interface command includes:

[0191] When the number of the acquired uncompleted erase operations is greater than a first threshold, the processing of the media interface command is suspended.

[0192] Optionally, after pausing the processing of the media interface command, the method further includes:

[0193] When it is monitored that the number of the uncompleted erase operations is less than or equal to the first threshold, the processing of the media interface command is resumed.

[0194] Optionally, if the number of erase operations obtained satisfies the first preset condition, continuing to process the media interface command comprises one of the following steps:

[0195] In the case that there is no uncompleted erase operation, continue to process the medium interface command;

[0196] When the acquired number of the uncompleted erase operations is less than or equal to the first threshold, the medium interface command continues to be processed.

[0197] Optionally, if before determining the first LUN controller, it is determined that the number of erase operations obtained meets the first preset condition, the first LUN controller is determined, and if there is no unprocessed erase operation in the first LUN controller, the first LUN controller processes the media interface command to complete the erase operation.

[0198] Optionally, if after determining the first LUN controller, it is determined that the number of erase operations obtained meets the first preset condition, the first LUN controller processes the media interface command to complete the erase operation if there is no uncompleted erase operation.

[0199] Optionally, in the case where a plurality of media interface commands indicating erase operations are received, the method further comprises:

[0200] Determine N logical unit groups corresponding to multiple LUN controllers corresponding to multiple media interface commands, each logical unit group corresponds to a large block, and N is an integer greater than or equal to 2;

[0201] The number of erase commands corresponding to the N logical unit groups at the same time is controlled to meet a third preset condition.

[0202] Optionally, the controlling the number of erase commands corresponding to the N logical unit groups at the same time to meet a third preset condition comprises at least one of the following steps:

[0203] Control the total number of erase commands corresponding to the N logical unit groups at the same time to be less than or equal to a third threshold;

[0204] The number of erase commands corresponding to each logical unit group at the same time is controlled to be less than or equal to a fourth threshold.

[0205] Optionally, the method further comprises:

[0206] In response to receiving a media interface command indicating a P1 operation, determining a fifth LUN controller associated with the P1 operation, allocating the media interface command indicating the P1 operation to the fifth LUN controller, and having the fifth LUN controller process the media interface command indicating the P1 operation;

[0207] In response to receiving the media interface command indicating the R operation, obtaining a sixth LUN controller that does not have an unprocessed erase operation, allocating the media interface command indicating the R operation to the sixth LUN controller, and having the sixth LUN controller process the media interface command indicating the R operation;

[0208] The P1 operation indicates that the specified data in the memory is moved to the NVM chip, and the R operation indicates that an XOR calculation is performed on the specified data in the memory and the calculation result is retained in the XOR cache.

[0209] In a sixth aspect, an embodiment of the present application further provides a media interface controller, comprising a command allocation unit and a plurality of LUN controllers;

[0210] The command allocation unit determines, in response to the received media interface command, that the media interface command indicates an erase operation, and determines, among a plurality of LUN controllers, a first LUN controller associated with the media interface command and the erase operation;

[0211] When the number of unprocessed erase operations meets a first preset condition and the first LUN controller has no unprocessed erase operations, the command allocation unit allocates the media interface command to the first LUN controller, and the first LUN controller processes the erase operation based on the media interface command.

[0212] Optionally, the command allocation unit determines that the media interface command indicates an erase operation based on an operation type field included in the media interface command.

[0213] Optionally, the media interface command includes a field indicating a physical block address to be erased, and the command allocation unit determines the logical unit corresponding to the erase operation based on the physical block address indicated by the media interface command;

[0214] Based on the mapping relationship between the logical unit and the LUN controller, a first LUN controller matching the logical unit corresponding to the erase operation is determined.

[0215] Optionally, when the number of unprocessed erase operations meets a second preset condition, the command allocation unit receives the medium interface command sent by the storage command processing unit.

[0216] Optionally, in the case that there is no uncompleted erase operation, the command allocation unit receives the medium interface command; or

[0217] When the number of the uncompleted erase operations is less than or equal to a second threshold, the command allocation unit receives the medium interface command.

[0218] Optionally, before or after determining the first LUN controller, the command allocation unit obtains the number of uncompleted erase operations;

[0219] If the acquired number of unprocessed erase operations does not satisfy the first preset condition, the command allocation unit suspends processing of the medium interface command;

[0220] If the acquired number of unprocessed erase operations meets the first preset condition, the command allocation unit continues to process the media interface command.

[0221] Optionally, when the number of the acquired uncompleted erase operations is greater than a first threshold, the command allocation unit suspends processing of the media interface command.

[0222] Optionally, after pausing the processing of the media interface command, the method further includes:

[0223] When it is detected that the number of the uncompleted erase operations is less than or equal to the first threshold, the command allocation unit resumes processing the media interface command.

[0224] Optionally, in the case that there is no uncompleted erase operation, the command allocation unit continues to process the medium interface command; or

[0225] When the acquired number of the uncompleted erase operations is less than or equal to the first threshold, the command allocation unit continues to process the media interface command.

[0226] Optionally, if before determining the first LUN controller, it is determined that the number of erase operations obtained meets the first preset condition, the command allocation unit determines the first LUN controller, and if there is no unprocessed erase operation in the first LUN controller, the first LUN controller processes the media interface command to complete the erase operation.

[0227] Optionally, if after determining the first LUN controller, it is determined that the number of erase operations obtained meets the first preset condition, the first LUN controller processes the media interface command to complete the erase operation if there is no uncompleted erase operation.

[0228] Optionally, in the case of receiving multiple media interface commands indicating erase operations, the command allocation unit determines N logical unit groups corresponding to multiple LUN controllers corresponding to the multiple media interface commands, each logical unit group corresponds to a large block, and N is an integer greater than or equal to 2;

[0229] The command allocation unit controls the number of erase commands corresponding to the N logic unit groups at the same time to meet a third preset condition.

[0230] Optionally, the command allocation unit controls the total number of erase commands corresponding to the N logical unit groups at the same time to be less than or equal to a third threshold; or

[0231] The command allocation unit controls the number of erase commands corresponding to each logical unit group at the same time to be less than or equal to a fourth threshold.

[0232] Optionally, in response to receiving a media interface command indicating a P1 operation, the command allocation unit determines a fifth LUN controller associated with the P1 operation, allocates the media interface command indicating the P1 operation to the fifth LUN controller, and the fifth LUN controller processes the media interface command indicating the P1 operation;

[0233] In response to receiving the media interface command indicating the R operation, the command allocation unit acquires a sixth LUN controller that does not have an unprocessed erase operation, allocates the media interface command indicating the R operation to the sixth LUN controller, and the sixth LUN controller processes the media interface command indicating the R operation;

[0234] The P1 operation indicates that the specified data in the memory is moved to the NVM chip, and the R operation indicates that an XOR calculation is performed on the specified data in the memory and the calculation result is retained in the XOR cache.

[0235] In a seventh aspect, an embodiment of the present application provides a method executed by a storage device, comprising:

[0236] In response to erasing a large block, the large block includes a plurality of physical blocks from a plurality of logical units;

[0237] If the number of uncompleted erase operations corresponding to the multiple LUN controllers is less than a specified threshold, providing a media interface command indicating an erase operation to the media interface controller;

[0238] The step of providing a media interface command indicating an erase operation to the media interface controller if the number of uncompleted erase operations corresponding to the plurality of LUN controllers is less than a specified threshold is repeatedly performed until all physical blocks of the large block are erased.

[0239] Optionally, the method further comprises:

[0240] In response to writing designated data to each first physical page of the first page stripe, generating a pair of P1 operation and R operation, wherein the P1 operation indicates moving the designated data in the memory to the NVM chip, and the R operation indicates performing an XOR calculation on the designated data in the memory, and retaining the calculation result in a first XOR cache corresponding to the first page stripe; wherein the first page stripe includes a second physical page and a plurality of first physical pages;

[0241] In response to data being written to the second physical page of the first page stripe, a P2 operation is generated, the P2 operation indicating writing the check data in the first XOR buffer to the second physical page of the first page stripe.

[0242] Optionally, the method further comprises:

[0243] To process the P1 operation, determine a second LUN controller according to the logical unit indicated by the P1 operation, and process the P1 operation through the second LUN controller;

[0244] To process the R operation, a third LUN controller having no uncompleted erase operation is obtained, and the R operation is processed by the third LUN controller;

[0245] To process the P2 operation, a fourth LUN controller is determined according to the logical unit indicated by the P2 operation, and the P2 operation is processed by the fourth LUN controller.

[0246] Optionally, the method further comprises:

[0247] To generate the R operation, a third LUN controller having no uncompleted erase operation is obtained, and in the R operation, it is indicated to use the third LUN controller to process the R operation.

[0248] Optionally, the method further comprises:

[0249] To generate the paired P1 operation and R operation, determine a second LUN controller according to a logical unit to which a first physical page to be accessed by the P1 operation belongs;

[0250] If the second LUN controller does not have an uncompleted erase operation, indicating in the R operation that the second LUN controller is used to process the R operation;

[0251] If the second LUN controller has an uncompleted erase operation, a third LUN controller without an uncompleted erase operation is obtained, and in the R operation, it is indicated to use the third LUN controller to process the R operation.

[0252] In an eighth aspect, an embodiment of the present application further provides a control component, including a storage command processing unit and a medium interface controller;

[0253] The storage command processing unit is responsive to erasing a large block, the large block comprising a plurality of physical blocks from a plurality of logical units;

[0254] If the number of unprocessed erase operations corresponding to the plurality of LUN controllers is less than a specified threshold, the storage command processing unit provides a media interface command indicating an erase operation to the media interface controller;

[0255] Repeat the step of providing a media interface command indicating an erase operation to the media interface controller by the storage command processing unit if the number of unprocessed erase operations corresponding to the plurality of LUN controllers is less than a specified threshold until all physical blocks of the large block are erased.

[0256] Optionally, in response to writing designated data to each first physical page of the first page stripe, the storage command processing unit generates a pair of P1 operations and R operations, wherein the P1 operation indicates that the designated data in the memory is moved to the NVM chip, and the R operation indicates that an XOR calculation is performed on the designated data in the memory, and the calculation result is retained in a first XOR cache corresponding to the first page stripe; wherein the first page stripe includes a second physical page and a plurality of first physical pages;

[0257] In response to writing data to the second physical page of the first page stripe, the storage command processing unit generates a P2 operation instructing to write the check data in the first XOR buffer to the second physical page of the first page stripe.

[0258] Optionally, to process the P1 operation, the media interface controller determines a second LUN controller according to a logical unit indicated by the P1 operation, and processes the P1 operation through the second LUN controller;

[0259] To process the R operation, the media interface controller obtains a third LUN controller that does not have any uncompleted erase operations, and processes the R operation through the third LUN controller;

[0260] To process the P2 operation, the media interface controller determines a fourth LUN controller according to the logical unit indicated by the P2 operation, and processes the P2 operation through the fourth LUN controller.

[0261] Optionally, to generate the R operation, the storage command processing unit obtains a third LUN controller that does not have any unprocessed erase operations, and indicates in the R operation to use the third LUN controller to process the R operation.

[0262] Optionally, to generate the paired P1 operation and R operation, the storage command processing unit determines the second LUN controller according to the logical unit to which the first physical page to be accessed by the P1 operation belongs;

[0263] If the second LUN controller does not have an uncompleted erase operation, the storage command processing unit instructs the second LUN controller to process the R operation in the R operation;

[0264] If the second LUN controller has an uncompleted erase operation, the storage command processing unit obtains a third LUN controller that has no uncompleted erase operation, and indicates in the R operation to use the third LUN controller to process the R operation.

[0265] According to the embodiments of the present application, a P1 operation indicating that specified data in a memory is moved to an NVM chip but no XOR operation is performed, and a P2 operation indicating that data in an XOR cache is moved to an NVM chip are introduced. While supporting an R operation that performs an XOR calculation on specified data in a memory and retains the result in an XOR cache, the writing of specified data in a memory and corresponding verification data to an NVM chip can be completed in three stages based on the coordination of the P1 operation, the P2 operation, and the R operation. The operations in the three stages are independent of each other and do not affect each other. After completing the XOR calculation and moving the data in the XOR cache, the XOR cache can be released in time, thereby reducing the occupied time of the XOR cache and improving the utilization efficiency of the XOR cache.

[0266] Furthermore, the present application can limit the number of erase operations processed simultaneously, thereby avoiding the power consumption fluctuation of the storage device caused by the erase operations generated by large-block recovery, and / or the problem that the XOR cache cannot be released in time due to the R operation not being scheduled in time due to the erase operation occupying multiple or all LUN controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0267] Figure 1A A block diagram representing a storage device;

[0268] Figure 1B A detailed block diagram showing the control components of a storage device;

[0269] Figure 2A Schematic diagram 1 showing a large block;

[0270] Figure 2B Schematic diagram 2 showing a large block;

[0271] Figure 3A Schematic diagram 1 showing page striping;

[0272] Figure 3B Schematic diagram 2 showing page striping;

[0273] Figure 4A Schematic diagram 1 showing the interaction between the media interface controller, DRAM and NVM chip;

[0274] Figure 4B Schematic diagram 2 showing the interaction between the media interface controller, DRAM and NVM chip;

[0275] Figure 5 A schematic diagram showing the interaction between the media interface controller and the host and logic unit;

[0276] Figure 6 A schematic diagram showing a media interface controller according to an embodiment of the present application accessing a logic unit based on a media interface command;

[0277] Figure 7 Schematic diagram 1 showing that the media interface controller of the embodiment of the present application allocates a LUN controller to a media interface command;

[0278] Figure 8 Schematic diagram 2 showing the media interface controller according to an embodiment of the present application allocating a LUN controller to a media interface command;

[0279] Fig. 9 Schematic diagram 3 showing the media interface controller according to an embodiment of the present application allocating a LUN controller to a media interface command;

[0280] Fig.10 A schematic diagram showing the LUN controllers for paired P1 and R operations corresponding to different logical unit groups in an embodiment of the present application;

[0281] Fig.11 A schematic diagram showing a method for writing user data to a specified page stripe of an NVM chip according to an embodiment of the present application;

[0282] Fig.12 It shows a specific example of writing data to page stripe PS0 according to an embodiment of the present application;

[0283] Fig.13A Schematic diagram 1 showing that the embodiment of the present application includes a large block including physical blocks provided by each logical unit;

[0284] Fig. 13B Schematic diagram 2 showing that the embodiment of the present application includes a large block including physical blocks provided by each logical unit;

[0285] Fig. 13C It shows an example of erasing a physical block in a large block according to an embodiment of the present application;

[0286] Fig.14 This shows an example in which different logical unit groups correspond to different erase commands at the same time in an embodiment of the present application. DETAILED DESCRIPTION

[0287] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0288] According to the embodiment of the present application, a P1 operation and a P2 operation processed by a media interface controller are introduced. The P1 operation instructs the media interface controller to move the specified data in the memory (such as DRAM) to the NVM chip, but does not perform an XOR operation, which is equivalent to forming a data channel between the memory and the NVM chip. The P2 operation instructs the media interface controller to move the data in the XOR cache to the NVM chip. The media interface controller also supports the R operation (performs an XOR calculation on the specified data in the memory and retains the result in the XOR cache). The same function or effect as the P operation of the prior art is achieved through paired P1 and R operations. By coordinating the P1 operation, the P2 operation and the R operation, the specified data in the memory and the corresponding verification data can be written into the NVM chip based on three stages. The operations of the three stages are independent of each other and do not affect each other. After completing the XOR calculation and moving the data in the XOR cache, the XOR cache can be released in time, thereby reducing the occupied time of the XOR cache and improving the utilization efficiency of the XOR cache.

[0289] According to an embodiment of the present application, the media interface controller includes multiple LUN controllers, each of which may correspond to a logical unit. When executing a P1 operation, the corresponding LUN controller is determined based on the physical address of the NVM chip accessed by the P1 operation, so that the media interface controller uses the LUN controller to process the P1 operation to write specified data in the memory to the specified physical address of the NVM chip. The embodiment of the present application is described by taking the memory as DRAM as an example.

[0290] According to an embodiment of the present application, a status of whether an erase command is being processed is recorded for each logical unit. Since the logical unit corresponds to the LUN controller one by one, the LUN controller can carry the corresponding status (whether an erase operation is being processed). After the LUN controller sends an erase command to the corresponding logical unit, the status is set, and after the erase command is processed, the status is cleared.

[0291] According to an embodiment of the present application, based on the status of whether an erase operation is being processed as recorded by the LUN controller, a suitable LUN controller (whose status indicates that there is no erase operation being processed) is selected for the R operation to avoid the situation where the R operation is blocked by the erase command.

[0292] In the process of writing data to the page stripe, the P1 operation and R operation received by the media interface controller appear in pairs, and the P2 operation is used to move the data in the XOR cache to the NVM chip, and only appears once for each page stripe. Through one or more pairs of P1 operations and R operations, the data in the DRAM is written to the page stripe, and the verification data for the page stripe is generated in the XOR cache. And the data in the XOR cache is written to the page stripe through the P2 operation. The data D(i) targeted by the paired P1 operation and R operation are the same, that is, in the paired P1 operation and R operation, the P1 operation indicates that the data D(i) is written to the NVM chip, and the corresponding R operation indicates that the same data D(i) is moved to the XOR cache for XOR calculation. And according to the embodiments of the present application, the P1 operation and the R operation can be scheduled and executed separately, so that the processing order of the paired P1 operation and R operation will not be restricted, and they can be processed simultaneously or one after another. Although the P1 operation limits the LUN controller that processes the P1 operation, the corresponding R operation does not limit the LUN controller, but can be processed by any LUN controller in the media interface controller, and the paired P1 operation and R operation can be processed by the same LUN processor. Preferably, the R operation is processed by the LUN controller that is not currently processing an erase operation to avoid blocking the R operation.

[0293] Still optionally or further, all R operations (each operating on different data D(i)) used when writing data to the same page stripe use the same XOR cache. Therefore, even if all R operations used when writing data to the same page stripe are processed by different LUN controllers, they will not be processed simultaneously because they use the same XOR cache, but will be processed one after another to use the same XOR cache.

[0294] After the R operation performs an XOR operation on the specified data in the DRAM and stores it in the XOR cache, the verification data needs to be written to the specified location in the NVM chip. According to an embodiment of the present application, the order in which multiple P1 operations and a P2 operation that write data to the same page stripe are executed is not limited, and the P2 operation may even be processed before all P1 operations (for example, the P1 operation is blocked by the erase operation). Therefore, writing the verification data corresponding to the page stripe to the NVM chip may occur before writing the specified data (user data) in the DRAM to the NVM chip (the write operation of the user data is blocked), and the release of the XOR cache can also occur before writing the user data to the NVM chip, thereby reducing the time occupied by the XOR cache, thereby reducing the time for subsequent write commands to wait for the XOR cache to be allocated, and improving the utilization rate of the XOR cache. It also reduces the time waiting for the XOR cache to be allocated when processing write commands, so that users experience that the write command processing performance of the SSD is stable, and the performance jitter of the write command processing will not be caused by the occurrence of the erase operation.

[0295] The media interface controller provided in the embodiment of the present application can process three types of media interface commands corresponding to P1 operation, P2 operation and R operation. The media interface controller receives the media interface command, and distributes the media interface command to the corresponding LUN controller based on the operation type indicated by the media interface command, and the LUN controller performs the P1 operation, P2 operation or R operation.

[0296] See also Figure 6 As shown, the media interface controller includes a command allocation unit, multiple LUN controllers and an XOR calculation unit. The command allocation unit receives a media interface command, each of which includes multiple fields. The field indicates the operation type corresponding to the media interface command and other related information.

[0297] When the media interface controller receives a media interface command, it determines whether the media interface command corresponds to a P1 operation, a P2 operation, or an R operation according to the operation type field.

[0298] The media interface command indicating the P1 operation includes, in addition to the operation type field, a field indicating the physical address of the NVM chip to be accessed and a field indicating the data to be moved. The logical unit to be accessed can also be determined based on the physical address indicated by the media interface command, and the physical page to be accessed can also be determined based on the physical address field. The field indicating the data to be moved indicates, for example, a DRAM index.

[0299] As an example, the media interface command corresponding to the P1 operation is represented as:<OPCODE,LUN,PPA,Data> The OPCODE field is an operation type field, and its content is used to indicate that it is a P1 operation. The LUN field indicates the logical unit to be accessed, the PPA field indicates the physical address to be accessed (e.g., the physical page to be accessed), and the content corresponding to the Data field is the data to be written to the physical address PPA, such as a pointer to a DRAM or the data to be written itself. Optionally, the LUN field and the PPA field are represented as a single field indicating the physical address of the NVM chip to be accessed.

[0300] After the media interface controller identifies the P1 operation in response to the received media interface command, it determines the LUN controller to process the P1 operation according to the content of the LUN field. For example, the corresponding logical unit is determined according to the content of the LUN field, and the P1 operation is assigned to the LUN controller corresponding to the determined logical unit. Next, the LUN controller can execute the P1 operation, generate a storage medium access command (programming command) according to the Data field and the PPA field, and send it to the corresponding logical unit to write the data in the DRAM to the corresponding physical page of the logical unit.

[0301] The media interface command indicating the P2 operation includes an operation type field, a field indicating the physical address of the NVM chip to be accessed, and a field indicating the data to be moved. The difference from the P1 operation is that the data indicated by the field indicating the data to be moved is located in the XOR cache.

[0302] As an example, the media interface command corresponding to the P2 operation is represented as:<OPCODE,LUN,PPA,XOR BufferIndex> ; The OPCODE field is the operation type field, and its content is used to indicate that it is a P2 operation. The content corresponding to the LUN field is the logical unit to be accessed, the content corresponding to the PPA field is the physical address to be accessed (i.e., the physical page to which the check data is to be written), and the content corresponding to the XOR Buffer Index field is the index of the XOR cache. For example, XOR cache 0 is allocated to page stripe PS1. When the check data of page stripe PS1 is calculated to be Parity (PS1) and the check data Parity (PS1) is stored in XOR cache 0, the check data Parity (PS1) needs to be moved from XOR cache 0 to the corresponding physical page of page stripe PS1. The XORBuffer Index field is the index of XOR cache 0.

[0303] In response to receiving the media interface command, the media interface controller identifies the P2 operation and determines the LUN controller to process the P2 operation according to the content of the LUN field. The LUN controller performs the P2 operation and generates a storage medium access command (programming command) according to the XOR Buffer Index field and the PPA field, and sends it to the corresponding logical unit to write the data in the XOR buffer to the corresponding physical page of the logical unit.

[0304] A media interface command indicating an R operation includes an operation type field, a source address field indicating data to be operated, and a destination address field indicating data to be operated. Optionally, a field indicating a logical unit or LUN controller is also included. The source address of the data in the R operation is, for example, a DRAM, and the destination address is an XOR cache.

[0305] As an example, the media interface command corresponding to the R operation is represented as:<OPCODE,LUN,XOR BufferIndex,Data> , the OPCODE field is an operation type field, and its content is used to indicate that it is an R operation. The LUN field indicates a logical unit. The LUN controller that processes the R operation is determined based on the LUN field. The XOR Buffer Index field is the index of the XOR buffer that is the destination address. The Data field is the source address. Optionally, the R operation may not include the LUN field, and the command allocation unit selects a suitable LUN controller to process the R operation, for example, selects a LUN controller whose corresponding logical unit is not executing an erase command. Still optionally, the R operation indicates a LUN field, and the LUN field is the same as the LUN field of the paired P1 operation (thereby indicating a paired P1 operation and R operation), but the command allocation unit allocates the R operation to other LUN controllers for processing based on the fact that the LUN controller corresponding to the LUN field is processing an erase operation.

[0306] In response to the received media interface command, the media interface controller identifies the R operation, determines the LUN controller to process the R operation, and applies for an XOR cache. The XOR cache is the XOR cache indicated by the destination address field indicating the data to be operated in the R operation. When the XOR cache is applied for, the LUN controller processing the R operation moves the data to be operated indicated by the source address field indicating the data to be operated in the R operation to the XOR cache, and performs an XOR operation with the data in the XOR cache, and the calculation result is retained in the XOR cache.

[0307] The XOR buffer has a state to mark whether the XOR buffer is occupied. The states of the XOR buffer include, for example, "occupied" (denoted as O) and "free" (denoted as F).

[0308] The R operation indicates the XOR cache to be used. When the LUN controller processes the R operation, it checks the status of the XOR cache to be used (also called applying for the XOR cache). When the XOR cache to be used is free, the XOR cache application succeeds, and the subsequent processing of the R operation continues. When the XOR cache to be applied for is occupied, the XOR cache application fails. At this time, the LUN controller repeatedly applies for the XOR cache until the XOR cache application succeeds.

[0309] When assigning a LUN controller to an R operation, it can be detected whether there is an unfinished erase operation on the LUN controller corresponding to the logical unit to be accessed as indicated by the R operation. If not, the R operation can be assigned to the LUN controller corresponding to the logical unit to be accessed, or to other idle LUN controllers that do not have unfinished erase operations. When there is an unfinished erase operation on the LUN controller corresponding to the logical unit to be accessed as indicated by the R operation, in order to avoid long-term occupation of the XOR cache, the R operation is assigned to other LUN controllers.

[0310] The command allocation unit allocates the received media interface command to one of the LUN controllers for processing. For P1 and P2 operations, the command allocation unit always allocates them to the LUN controller corresponding to the logical unit to be accessed. For R operations, the command allocation unit allocates a LUN controller for the R operation according to one or more embodiments provided in the present application.

[0311] According to an embodiment of the present application, in order to write data to a page stripe (PS1), one or more pairs of P1 operations and R operations, and a single P2 operation are provided to the media interface controller. For example, if the page stripe PS1 accommodates N pages of user data and 1 page of check data, then writing data to the page stripe PS1 requires N pairs of P1 operations and R operations, and 1 P2 operation. The N pairs of P1 operations and R operations are denoted as P1(i) and R(i), where 0<=i<=N-1. Optionally, the N R operations here all use the same XOR cache (e.g., XOR cache 0).

[0312] See also Figure 6 As shown, the media interface controller receives media interface command 1 and media interface command 2. For example, media interface command 1 indicates to execute the P1(0) operation, and media interface command 2 indicates to execute the R(0) operation. The P1(0) operation indicates to write data D0 into the physical page P0-0 of the logical unit 0, and the R(0) operation indicates to perform an XOR operation on D0 and the data in the XOR buffer 0.

[0313] Since the P1(0) operation indicates to write the user data D0 to the physical page of the logical unit 0, the LUN controller 0 corresponding to the logical unit 0 is allocated to the media interface command 1, and the LUN controller 1 is allocated to the media interface command 2.

[0314] exist Figure 6In the example, LUN controller 0 has an unfinished erase operation, so a different LUN controller from LUN controller 0 is assigned to media interface command 2. As an example, LUN controller 1 is selected to process media interface command 2. Accordingly, after processing the erase operation, LUN controller 0 processes the P1(0) operation to write D0 to physical page P0-0. LUN controller 1 performs the R(0) operation to XOR the specified value D0 with the data in XOR buffer 0 to obtain the check data (recorded as Parity(0)).

[0315] Still taking the example, when the media interface controller receives media interface command 3 indicating execution of the P1(1) operation and media interface command 4 indicating execution of the R(1) operation, the media interface controller allocates a LUN controller to media interface command 3 and media interface command 4.

[0316] Among them, the P1(1) operation indicates that the data D1 is written to the physical page P0-1 of the logical unit 1, and the R(1) operation indicates that the data in the XOR cache 0 (currently Parity(0)) is XOR-ed with the data D1, thereby allocating the LUN controller 1 corresponding to the logical unit 1 to the media interface command 3. Figure 6 In the example, operation P1(1) indicates writing data D1 to the physical page of logical unit 1, and LUN controller 1 corresponding to logical unit 1 does not have any uncompleted erase operation, so LUN controller 1 is also assigned to media interface command 4 (even though LUN controller 1 has not yet completed processing media interface command 3 at this time).

[0317] When LUN controller 1 executes the R(1) operation, it performs an XOR operation on the check data Parity(0) in XOR cache 0 and D1 to obtain the check data Parity(1) (still located in XOR cache 0); before executing the R(1) operation, LUN controller 1 requests the allocation of XOR cache 0 resources. If the R(0) operation is not completed, the execution of the R(1) operation is suspended. Since there is no unfinished erase operation in LUN controller 1, LUN controller 1 can directly execute the P1(1) operation to write D1 to physical page P0-1. Optionally, while LUN controller 1 is processing the P1(1) operation, it concurrently processes the R(1) operation. For example, after transferring data to logical unit 1, LUN controller 1 processes the R(1) operation during the period of waiting for programming to be completed.

[0318] The process of writing D2 to D(P-1) is similar to the above process and will not be repeated here. After the verification data Parity(PS0) corresponding to the page stripe PS0 is generated through a series of processes, a LUN controller P is allocated to the media interface command based on the media interface command corresponding to the P2 operation, and the P2 operation is executed by the LUN controller P to write Parity(PS0) to the physical page P0-P in the logical unit P. In an embodiment of the present application, paired P1 operations and R operations can be processed by the same or different LUN controllers. The LUN controller corresponding to the P1 operation is determined based on the logical unit corresponding to the P1 operation. In order to reduce the occupancy of the XOR cache, the LUN controller corresponding to the R operation usually requires that no erase operations are being processed. The following introduces the cases where paired P1 operations and R operations correspond to the same LUN controller and different LUN controllers by giving examples.

[0319] The media interface controller receives a media interface command 1 indicating the execution of a P1 operation and a media interface command 2 indicating the execution of an R operation. The P1 operation and the R operation are operations corresponding to user data D0 in the DRAM. Based on the content indicated by the LUN field included in the media interface command 1 (e.g., the identifier of the logical unit 0), the LUN controller to process the P1 operation (e.g., the LUN controller 0 corresponding to the logical unit 0) is determined.

[0320] Check whether there is an unfinished erase operation on LUN controller 0 to determine how to process media interface command 2. Figure 7 If there is no unfinished erase operation on LUN controller 0, the R(D0) operation can also be assigned to LUN controller 0 for processing.

[0321] If there is an unfinished erase operation on LUN controller 0, the R(D0) operation can be assigned to LUN controller 1 which is in idle state (there is no unfinished erase operation on LUN controller 1). LUN controller 0 and LUN controller 1 can process P1(D0) operation and R(D0) operation in parallel.

[0322] It should be noted that, in the case that there is no unfinished erase operation on LUN controller 0, the R(D0) operation may also be assigned to other LUN controllers other than LUN controller 0 that are in an idle state (have no unfinished erase operation).

[0323] In the above example, the P1(D0) operation must be assigned to LUN controller 0 (because the P1(D0) operation and LUN controller 0 both correspond to logical unit 0); the R(D0) operation can be assigned to any LUN controller that does not have an unfinished erase operation, in order to reduce the time the XOR cache is occupied. Because the LUN controller needs to apply for the XOR cache when processing the R operation, and release the XOR cache only after processing the R operation; if there is an unfinished erase operation, the R operation will not be processed and completed, thus occupying the XOR cache for a long time; and it will also cause the page stripe check data to be delayed and calculated, which will cause the XOR cache allocated for the current page stripe to be occupied for a long time.

[0324] In the embodiment of the present application, if there is an unfinished erase operation on the LUN controller that performs the P1 operation, the corresponding R operation needs to be assigned to other LUN controllers. And for the LUN controller that has an unfinished erase operation, the erase operation on the LUN controller needs to be processed and then the P1 operation can be performed by the LUN controller.

[0325] As an example, the media interface controller receives media interface command 1 indicating the execution of a P1 operation and media interface command 2 indicating the execution of an R operation, where the P1 operation and the R operation are operations corresponding to the D0 data in the DRAM. Based on the content indicated by the LUN field included in the media interface command 1 (e.g., the identifier of the logical unit 0), the LUN controller to process the P1 operation (e.g., the LUN controller 0 corresponding to the logical unit 0) is determined. Whether there is an unprocessed erase operation in the LUN controller 0 is detected. See Figure 8 As shown, the LUN controller 0 corresponding to the logical unit 0 has an unfinished erase operation (such as the operation of processing the erase command erase0). Since the P1(D0) operation corresponds to the logical unit 0, the P1(D0) operation is assigned to the LUN controller 0, and the R(D0) operation is assigned to the LUN controller 2 which is in an idle state (there is no unfinished erase operation), and the R(D0) operation is executed by the LUN controller 2. After the erase operation is processed, the LUN controller 0 can execute the P1(D0) operation, that is, the P1(D0) operation and the operation of processing the erase command erase0 are queued on the LUN controller 0, and the LUN controller 0 first processes the erase operation in order, and then executes the P1(D0) operation.

[0326] Since there is an unfinished erase operation on LUN controller 0 corresponding to logical unit 0, by assigning the R(D0) operation to LUN controller 2 which is in an idle state (no unfinished erase operation), it is possible to avoid the erase operation blocking the R(D0) operation. Furthermore, before the erase command erase0 is processed, the calculation of the check data corresponding to the page stripe (such as page stripe PS1) may have been completed and written to the matching physical page, and the XOR cache is released, thereby avoiding the situation where the XOR cache 0 assigned to the page stripe PS1 is occupied for a long time due to the existence of the erase command erase0.

[0327] exist Fig. 9 In the embodiment, LUN controller 0 is processing a P1(D0) operation, and LUN controller 2 is processing an R(D0) operation. At this time, a media interface command indicating a P1(D2) operation and an R(D2) operation is received. Both D0 and D2 are data located in DRAM and are to be written to the same page stripe. Both the R(D0) operation and the R(D2) operation use XOR cache 0. The P1(D2) operation is to write data to logical unit 2.

[0328] Although the R(D0) operation has been assigned to LUN controller 2, since logical unit 2 matches LUN controller 2, the media interface controller still assigns the P1(D2) operation to LUN controller 2, and assigns the R(D2) operation to LUN controller 6 which is in an idle state (there is no unprocessed erase operation), and LUN controller 6 executes the R(D2) operation. The R(D0) operation processed by LUN controller 2 is concurrent with the R(D2) operation processed by LUN controller 6, and both use XOR cache 0. Therefore, when a LUN controller processes an R operation, it needs to apply for the assigned XOR cache (XOR cache 0) first. The LUN controller that applies for XOR cache 0 has the right to use XOR cache 0 and process the R operation. After it processes the R operation and releases XOR cache 0, another LUN controller can apply for XOR cache 0. Therefore, the R operations of LUN controller 2 and LUN controller 6 will be queued based on the application of XOR cache 0, but the processing time of the R operation is relatively short (compared with the P1 operation), so it will not significantly affect the processing delay of the process of writing data to the page stripe.

[0329] According to an embodiment of the present application, multiple logical units of a storage device may be grouped into groups, referred to as logical unit groups. Each logical unit group includes multiple logical units. Large blocks are constructed using logical units within the logical unit group. The LUN controllers still correspond one-to-one to the logical units. These LUN controllers share XOR cache resources.

[0330] For P1 operations, the LUN controller that processes the P1 operations is a fixed LUN controller corresponding to the logical unit accessed by the P1 operations; and for R operations, the LUN controller that processes the R operations can be any LUN controller of the media interface controller. For paired P1 and R operations, the LUN controllers that process the two operations can be the same LUN controller or different LUN controllers, and can be LUN controllers corresponding to logical units of different logical unit groups.

[0331] When the LUN controller corresponding to the R operation and the LUN controller corresponding to the P1 operation correspond to different logical unit groups, the LUN controller corresponding to the R operation and the LUN controller corresponding to the P1 operation correspond to different large blocks, that is, the R operation on a certain large block can be processed by the LUN controllers corresponding to other large blocks, which can avoid the situation where the R operation is delayed due to insufficient LUN controllers corresponding to the current large block. Resource sharing can be achieved by utilizing the LUN controllers corresponding to other large blocks.

[0332] For example, see Fig.10 As shown, the storage device includes 16 logical units (logical unit 0 to logical unit 15). Every 8 logical units form a group (for example, logical unit 0 to logical unit 7 form a group, and logical unit 8 to logical unit 15 form a group). In the group of logical unit 0 to logical unit 7, large block 0 is constructed, and in the group of logical unit 8 to logical unit 15, large block 1 is constructed. Among them, each logical unit corresponds to a LUN controller, logical unit 0 to logical unit 7 correspond to LUN controller 0 to LUN controller 7; logical unit 8 to logical unit 15 correspond to LUN controller 8 to LUN controller 15.

[0333] exist Fig.10 In the example, the control component processes the media interface command 1 indicating the P1 operation corresponding to writing the D0 data to the NVM chip, and processes the media interface command 2 indicating the R operation to be performed on the D0 data. The media interface controller assigns the P1 (D0) operation to the LUN controller 0, and the LUN controller 0 performs the P1 (D0) operation. The R (D0) operation is assigned to the LUN controller 15, and the LUN controller 15 performs the R (D0) operation.

[0334] The following is a detailed description of the process of writing user data and verification data to a specified page stripe of an NVM chip based on the P1 operation, the R operation, and the P2 operation in the embodiment of the present application. Fig.11 As shown, the following steps may be included:

[0335] Step 1101: Allocate a page stripe, and allocate an XOR buffer for the page stripe.

[0336] The allocated page stripe is an idle page stripe in the storage device, and the allocated XOR cache is an XOR cache that is not currently allocated to any page stripe. As an example, the page stripe includes P pages for storing user data, and Q pages for storing verification data. The process of writing data to the page stripe requires providing P pairs of P1 operations and R operations, as well as Q P2 operations to the media interface controller. The media interface controller processes these operations to complete the process of writing data to the page stripe. Here, P P1 operations write user data to the P pages of the page stripe respectively, P R operations all use the allocated XOR cache to calculate the verification data of the page stripe based on the user data, and Q P2 operations write verification data to the Q pages of the page stripe respectively.

[0337] Step 1102 : When writing user data to a physical page in a page stripe, a pair of P1 operation and R operation is generated.

[0338] Step 1103: Determine the LUN controller corresponding to the P1 operation according to the logical unit to which the physical address indicated in the media interface command representing the P1 operation belongs, assign the P1 operation to the LUN controller, and let the LUN controller process the P1 operation.

[0339] The physical address to be accessed is indicated in the media interface command representing the P1 operation, and the corresponding LUN controller (such as LUN controller 1) is determined based on the logical unit to which the physical address belongs. The P1 operation is assigned to LUN controller 1.

[0340] Step 1104: Allocate the R operation to the LUN controller X that is not processing the erase operation, and let the LUN controller process the R operation.

[0341] The R operation may be assigned to LUN controller X. The selection condition of LUN controller X is that there is no erase operation being processed thereon. LUN controller X may be LUN controller 1 or may be different from LUN controller 1. The XOR buffer corresponding to the R operation is the XOR buffer pre-assigned in step 1101.

[0342] The media interface command representing the R operation indicates the XOR buffer (for example, XOR buffer 0) allocated for the page stripe. When LUN controller X processes the R operation, the LUN controller applies for XOR buffer 0 indicated in the R operation. If the XOR buffer 0 cannot be applied for, the LUN controller suspends the processing of the R operation and tries to apply for XOR buffer 0 again. After applying for XOR buffer 0, LUN controller X performs an XOR operation using XOR buffer 0 and leaves the result in XOR buffer 0, and then releases XOR buffer 0.

[0343] Step 1105 : After the check data corresponding to the page stripe is determined according to multiple R operations, the check data is moved to the physical page storing the check data through the P2 operation to complete the writing of the check data.

[0344] Among them, one or more media interface commands representing P pairs of P1 operations and R operations and Q P2 operations are provided to the media interface controller for processing. The media interface controller assigns each P1 operation, P2 operation and / or R operation to an appropriate LUN controller. Each LUN controller processes the operations received in parallel according to the processing method provided in the embodiment of the present application.

[0345] It is understandable that, in the process of writing data to the page stripe (PS1), a media interface command for accessing other page stripes may also be provided to the media interface controller. Thus, the same LUN controller may need to process, for example, multiple P1 operations, multiple P2 operations, and / or multiple R operations at a certain time. The LUN controller may process the multiple operations assigned to it sequentially, alternately, or in other ways.

[0346] As an example, PS0 is a page stripe in block 0, and writing data to page stripe PS0 includes: writing user data D0, D1, D2, D3, D4, D5, and D6 to the corresponding physical page (involving 7 P1 operations), calculating the check data Parity (PS0), and writing Parity (PS0) to the corresponding physical page (involving 7 R operations and 1 P2 operation). According to an embodiment of the present application, in order to write data D0 to the physical page of page stripe PS0, a media interface command representing a pair of P1 operations and R operations is generated and provided to the media interface controller for processing. Thus, for user data D0, D1, D2, D3, D4, D5, and D6 to be written to the page stripe, a total of 7 pairs of media interface commands representing P1 operations and R operations are generated. And in order to write the check data Parity (PS0) to the physical page of the page stripe, 1 media interface command representing a P2 operation is generated, and no R operation is generated at this time.

[0347] The following describes the specific process of writing data to page stripe PS0:

[0348] Writing D0 to the NVM chip includes P1(D0) operation and R(D0) operation. Fig.12 , the P1(D0) operation is used to indicate that D0 is written to the physical page P0-0; the R(D0) operation is used to indicate that the data in the XOR cache 0 is XOR-ed with D0. XOR cache 0 is the XOR cache resource allocated for page stripe PS0. When D0 is the first data written to page stripe PS0, the initial value of XOR cache 0 can be 0 when the R(D0) operation is executed.

[0349] The P1(D0) operation is assigned to the LUN controller 0 corresponding to the logical unit 0, and the data of D0 is written to the physical page P0-0 through the LUN controller 0. The R(D0) operation can be assigned to the LUN controller X. The selection condition of the LUN controller X is that there is no erase operation being processed on it. The R(D0) operation is processed by the LUN controller X. When the LUN controller X processes the R(D0) operation, the XOR cache 0 needs to be used. When the LUN controller X processes the R(D0) operation, the media interface controller needs to apply for the XOR cache (here, XOR cache 0, which is determined when the page stripe PS0 is allocated and carried in the media interface command indicating the R(0) operation). If it cannot be applied for, it will not proceed. After applying for XOR cache 0 and generating the check data Parity(D0), the LUN controller X that processes the R(0) operation releases XOR cache 0, that is, releases the control of the LUN controller X over XOR cache 0. Parity data (D0) = (data in XOR buffer 0) XOR (D0), that is, the parity data associated with D0 is obtained by performing an XOR operation on the data in XOR buffer 0 and D0.

[0350] The process of writing D1, D2, D3, D4, D5 and D6 into the NVM chip is similar to the process of writing D0 into the NVM chip, which will not be described in detail here.

[0351] After generating the check data Parity (PS0) of page stripe PS0 based on D0, D1, D2, D3, D4, D5 and D6, the data in XOR cache 0 is moved to the physical page storing the check data of page stripe PS0 through P2 operation, and XOR cache 0 is released, where Parity (PS0) = D0 XOR D1 XOR D2 XOR D3 XOR D4 XOR D5 XOR D6.

[0352] According to an embodiment of the present application, to write data to a page stripe, a storage command processing unit (see also Figure 1B ) generates one or more pairs of media interface commands carrying P1 operation and R operation respectively and one media interface command carrying P2 operation, and provides them to the media interface controller. And also allocates XOR cache for the page stripe. The allocated XOR cache is not occupied for processing write operations of other page stripes. Optionally, after the R operation is processed, the XOR cache carried by the R operation is released, so that the released XOR cache can be allocated again. The same allocated XOR cache is indicated in all R operations and P2 operations generated by the storage command processing unit for writing data to the same page stripe.

[0353] Still optionally, the paired P1 operation and R operation indicate the same logical unit. The media interface controller allocates a LUN controller for processing the P1 operation and the R operation according to the logical units indicated by the P1 operation and the R operation. And when an erase operation is being processed in the LUN controller corresponding to the logical unit indicated by the R operation, the R operation is allocated to other LUN controllers.

[0354] In another embodiment, in order to generate a pair of P1 operations and R operations, the storage command processing unit obtains the status of the erase operation being processed on one or more LUN controllers of the media interface controller. The storage command processing unit selects an idle LUN controller for the generated R operation and indicates the selected LUN controller in the R operation. Furthermore, even if the storage command processing unit selects an idle LUN controller, the command allocation unit of the media interface controller can still allocate other LUN controllers for processing the R operation. This is because when the command allocation unit processes the R operation, the status of whether there is an erase operation on the LUN controller may change.

[0355] Optionally, the paired P1 operation and R operation generated by the storage command processing unit always indicate the same logical unit, regardless of the state of the erase operation being processed on the LUN controller. The command allocation unit identifies the state of the erase operation being processed on the LUN controller and allocates the R operation to the appropriate LUN controller.

[0356] In still another embodiment, the R operation generated by the storage command processing unit does not indicate the logical unit, so that the command distribution unit completely selects the LUN controller that processes the R operation.

[0357] It can be understood that the storage command processing unit can write data to multiple page stripes at the same time, and generate multiple media interface commands for writing data to multiple page stripes, each carrying a P1 operation, a P2 operation, and an R operation, which are processed by the media interface controller. The storage command processing unit ensures that at any time, an XOR buffer is not allocated to multiple page stripes. If there is no XOR buffer available (for example, all XOR buffers are allocated to page stripes), the storage command processing unit waits for the XOR buffer to be released, and suspends the generation of media interface commands for writing to a new page stripe.

[0358] According to an embodiment of the present application, LUN controller 0 to LUN controller 6 respectively process the P1 operation of writing D0, D1, D2, D3, D4, D5 and D6 to the NVM chip. The timing of each of these P1 operations being processed is not restricted. There may be erase operations being processed on some LUN controllers, so that the processing of the corresponding P1 operations is postponed. Before the processing of one or some P1 operations begins, it is also possible that all R operations and P2 operations of the page stripe are processed, at which time the XOR cache allocated to the page stripe has been released and can be allocated to other page stripes. This avoids the XOR cache being occupied for a long time.

[0359] Still taking the example, there may be an erase operation being processed on the LUN controller N that processes the P2 operation of the page stripe, causing the processing of the P2 operation to be postponed. Optionally, at this time, the P2 operation is suspended, or the P2 operation is not assigned to the LUN controller N, but the data in the XOR cache indicated by the P2 operation is temporarily moved to an external memory such as DRAM. And the XOR cache indicated by the P2 operation is released so that the XOR cache can be allocated to other page stripes. After the erase operation of the LUN controller N is completed, the XOR cache is reapplied for processing the suspended P2 operation, and subsequent processing continues.

[0360] Return to view Fig.11 When executing step 1104, to allocate LUN controller X for the R operation, it is necessary to find a LUN controller X on which no erase operation is being processed. However, in some cases, all LUN controllers may be processing erase operations, resulting in failure to allocate an available LUN controller for the R operation, and causing the processing of the R operation to be delayed.

[0361] For a storage device, when reclaiming a large block, the storage device needs to erase all physical blocks of the large block. In order to erase the physical blocks of the large block, a media interface command indicating an erase operation is provided to the media interface controller. In addition to the operation type field, the erase operation also includes a field indicating the address of the physical block to be erased, and based on the field, the logical unit to which the physical block to be erased belongs can be obtained.

[0362] According to an embodiment of the present application, in order to avoid fluctuations in storage device power consumption caused by erase operations generated by large block recycling, and / or to avoid the problem that the XOR cache cannot be released in time due to the R operation not being scheduled in time due to the erase operation occupying multiple or all LUN controllers, the number of erase operations processed simultaneously is limited. For example, the storage device includes M logical units, and the number of erase operations processed simultaneously is less than M. For another example, the number of erase operations that can be processed simultaneously is limited to 1 or 2.

[0363] In one example, when providing a media interface command to a media interface controller, it is identified whether there is an uncompleted erase operation. Only when there is no uncompleted erase operation, a media interface command indicating an erase operation is provided to the media interface controller. Alternatively, only when the number of uncompleted erase operations is less than a specified threshold (e.g., 2 or 3), a media interface command indicating an erase operation is provided to the media interface controller.

[0364] In one example, when the command allocation unit of the media interface controller allocates the media interface command to the LUN controller, it identifies whether there is an unfinished erase operation. When there is a media interface command indicating an erase operation to be allocated, the media interface command indicating an erase operation is allocated to one of the LUN controllers only when there is no unfinished erase operation on all LUN controllers. Since the media interface command indicating an erase operation is to be processed by the LUN controller corresponding to the logical unit to which the erased physical block belongs, the command allocation unit not only identifies whether the LUN controller has an unfinished erase operation, but also checks whether other LUN controllers have an unfinished erase operation. Optionally, the command allocation unit allocates the media interface command indicating an erase operation to the LUN controller only when the number of unfinished erase operations is less than a specified threshold (e.g., 2 or 3).

[0365] Since each LUN controller records the status of whether it has an unfinished erase operation, based on the status recorded by the LUN controller, a suitable LUN controller (a LUN controller without an unfinished erase operation) can be selected for the R operation to avoid the situation where the R operation is blocked by the erase operation. The erase command processing method adopted in the embodiment of the present application can reduce the number of LUN controllers occupied by the erase command at the same time, and thus can provide more choices when selecting a suitable LUN controller for the R operation.

[0366] For example, see Fig.13A and Fig. 13B As shown, chunk 0 includes physical blocks B1 provided by (logical units) LUN0 to LUN N, respectively, and chunk 1 includes physical blocks B3 provided by (logical units) LUN0 to LUN N, respectively. Fig.13A and 13BIn the example, "LUNx-y" with a border indicates physical block y of logical unit x. When erasing all physical blocks in block 0, each physical block in block 0 is erased separately. When erasing all physical blocks in block 0 and block 1, each physical block is erased separately. For the N+1 physical blocks contained in block 0 and the N+1 physical blocks contained in block 1, N+1 erasing operations need to be performed respectively, and each erasing operation is performed on only one physical block. The N+1 erasing operations are performed separately, not simultaneously. For example, see Fig.13A as well as Fig. 13C As shown, firstly, an erase operation (processing the operation of erase command erase0) is performed on the physical block B1 (LUN0-B1) from the logical unit 0 in the large block 0. At this time, the LUN controller 0 corresponding to the logical unit 0 is processing the erase operation. At this time, if the media interface controller receives a P1 operation to write data to the physical block B2 of the logical unit 0 and a corresponding R operation, the command allocation unit allocates the P1 operation to the LUN controller 0, and allocates the R operation to any LUN controller (such as LUN controller 2) that is in an idle state (there is no unprocessed erase operation). Thus, the P1 operation is blocked by the erase command, but the R operation can be processed immediately. In addition, since the embodiment of the present application limits the number of erase operations that are processed simultaneously at the same time, it is ensured that when the R operation is allocated, there must be a qualified LUN controller (there is no unprocessed erase operation) to process the R operation.

[0367] See also Fig.13A As shown, after the erasing operation (processing the operation of erasing command erase0) of the physical block B1 (LUN0-B1) from the logical unit 0 in the big block 0 is completed, the erasing operation (processing the operation of erasing command erase1) of the physical block B1 (LUN1-B1) from the logical unit 1 in the big block 0 is allowed, and then the erasing operation (processing the operation of erasing command erase2) of the physical block B1 (LUN2-B1) from the logical unit 2 in the big block 0 is successively performed, and the erasing operation (processing the operation of erasing command erase3) of the physical block B1 (LUN3-B1) from the logical unit 3 in the big block 0 is performed, and ..., the erasing operation (processing the operation of erasing command erase N) of the physical block B1 (LUN N-B1) from the logical unit N in the big block 0 is performed.

[0368] Although in Fig.13A In the example, erase operations are processed in the order of LUN numbers (LUN 0, LUN 1, ... LUN N), but this is not necessary. Other orders can be used to process the erase operations of each physical block of a large block, and it is only necessary to ensure that the number of erase operations processed simultaneously is 1 or less than a specified threshold.

[0369] Still optionally, when two or more large blocks are erased, according to an embodiment of the present application, it is also ensured that the number of erase operations processed simultaneously is 1 or less than a specified threshold. Thus, when an erase operation of a physical block of a large block is processed, erase operations of other large blocks are blocked. For example, after all physical blocks of large block 0 are erased, an erase operation of a physical block of another large block is scheduled.

[0370] For example, see FIG. 13A to FIG. 13C As shown, when an erase operation (processing the erase command erase0 operation) is performed on the physical block B1 (LUN0-B1) from the logical unit 0 in the big block 0, the erase operation on LUN0-B1 will not affect the physical blocks of other logical units in the big block 0, nor will it affect the physical blocks of the logical units in the big block 1. At this time, the LUN controller corresponding to the physical block LUN0-B1 has an unprocessed erase operation (processing the erase command erase0 operation). When the media interface controller receives the P1 operation and the R operation for the logical unit 0, the command allocation unit allocates the P1 operation to the LUN controller 0 corresponding to the logical unit 0, and the LUN controller 0 executes the P1 operation after completing the erase operation corresponding to erase0; since the LUN controller 0 has an unprocessed erase operation, if the R operation is allocated to the LUN controller 0, the processing of the R operation needs to wait, resulting in the XOR cache resources being occupied for a long time. When erasing LUN0-B1, only LUN controller 0 corresponding to logical unit 0 will be occupied, and other LUN controllers will not be occupied. To avoid long-term occupation of XOR cache resources, the R operation can be assigned to other idle LUN controllers except LUN controller 0.

[0371] Optionally, the scheduling of the erase operation is performed by a command dispatch unit (see also Figure 6 ) is executed. After the large block is recovered, the storage command processing unit sends a plurality of media interface commands indicating erase operations to erase all physical blocks of the large block to the media interface controller, and the command allocation unit ensures that the erase operations allocated to the LUN controller for processing do not exceed 1 or a specified number at any time. Still optionally, the storage command processing unit ensures that the media interface commands indicating erase operations provided to the media interface controller do not exceed 1 or a specified number at any time.

[0372] According to an embodiment of the present application, by limiting the number of erase operations processed simultaneously to, for example, 1, the probability that a subsequent program operation / read operation accessing the same logical unit is blocked by the erase operation is reduced to 1 / K, where K is the number of logical units in the storage device. Since there may be hundreds or even thousands of IO commands from the host at the same time in the storage device, by reducing the probability that the program operation / read operation is blocked by the erase operation, the jitter of the processing delay of the host IO command is correspondingly reduced, thereby reducing the impact of the erase operation on the QoS (Quality of Service) of the storage device.

[0373] In the above example, the erase operation corresponding to the erase command erase0 is being processed. Assume that the programming operation (P1 operation or P2 operation) of a page stripe (such as page stripe PS1) needs to be processed at the same time. Assume that page stripe PS1 includes N physical pages, of which logical unit 0 contributes 1 physical page. At this time, in the programming operation of page stripe PS1, the programming operation of the physical page of logical unit 0 is blocked by the previous erase operation (the operation of processing the erase command erase0), while the programming (Program) commands of the physical pages of logical unit 1 to logical unit (N-1) can be completed normally. If the scheme of the present application is not adopted, in the programming operation of page stripe PS1, the N physical pages of N logical units are blocked. After adopting the scheme of the present application, the number of blocked programming operations is 1 / N of the previous one.

[0374] Still taking an example, the storage device includes multiple logical unit groups (such as G logical unit groups), allowing each logical unit group to process a maximum of a specified number of erase operations at the same time. For example, at the same time, the G logical unit groups process a maximum of G erase operations (no more than one erase operation is processed simultaneously in each logical unit group), and erase commands in different logical unit groups do not affect each other.

[0375] For example, see Fig.14 As shown, the storage device includes, for example, 16 logical units, which are divided into 2 groups, logical unit 0 to logical unit 7 are group 1 (logical unit group 1), and logical unit 8 to logical unit 15 are group 2 (logical unit group 2).

[0376] At a certain moment, group1 corresponds to an erase command (erase0), and group2 corresponds to an erase command (erase8); specifically, the LUN controller 0 corresponding to the logical unit 0 in group1 has an erase operation (processing the erase command erase0 operation), and the LUN controller 8 corresponding to the logical unit 8 in group2 has an erase operation (processing the erase command erase8 operation). At this time, group1 and group2 correspond to two erase commands at the same time.

[0377] For a logical unit group, by controlling the logical unit group to correspond to only one erase command at the same time, only one LUN controller can have an erase operation, thereby reducing the power consumption consumed by the erase operation and the number of LUN controllers occupied by the erase operation, thereby providing more choices when selecting a suitable LUN controller for the R operation; at the same time, since only one logical unit is blocked by the erase operation, the XOR cache can be prevented from being occupied for a long time.

[0378] The embodiment of the present application provides a media interface controller, including: a command allocation unit and multiple LUN controllers; the command allocation unit responds to the received media interface command, obtains the operation type indicated by the media interface command, determines the LUN controller associated with the media interface command and the operation type among multiple LUN controllers, allocates the media interface command to the LUN controller, and the LUN controller processes the media interface command; wherein the operation type is a P1 operation or an R operation, the P1 operation indicates that the specified data in the memory is moved to the NVM chip, and the R operation indicates that the XOR calculation is performed on the specified data in the memory and the calculation result is retained in the XOR cache. The media interface controller is also used to execute other implementation schemes of the command allocation method, which will not be repeated here.

[0379] Accordingly, when the media interface controller executes the erasure control method, the command allocation unit responds to the received media interface command, determines that the media interface command indicates an erasure operation, and determines the first LUN controller associated with the media interface command and the erasure operation among multiple LUN controllers; when the number of unprocessed erasure operations meets the first preset condition and the first LUN controller does not have an unprocessed erasure operation, the command allocation unit allocates the media interface command to the first LUN controller, and the first LUN controller processes the erasure operation based on the media interface command. The media interface controller is also used to execute other implementation schemes of the erasure control method, which will not be repeated here.

[0380] The embodiment of the present application provides a control component, including a storage command processing unit and a media interface controller; in response to writing specified data to each first physical page of the first page stripe, the storage command processing unit generates a media interface command indicating a paired P1 operation and R operation and provides it to the media interface controller, the P1 operation indicates that the specified data in the memory is moved to the NVM chip, and the R operation indicates that an XOR calculation is performed on the specified data in the memory, and the calculation result is retained in the first XOR cache corresponding to the first page stripe; wherein the first page stripe includes a second physical page and multiple first physical pages; in response to writing data to the second physical page of the first page stripe, the storage command processing unit generates a media interface command indicating a P2 operation and provides it to the media interface controller, and the P2 operation indicates that the check data in the first XOR cache is written to the second physical page of the first page stripe. The control component is also used to execute other implementation schemes of the data access method, which will not be repeated here.

[0381] Accordingly, when the control component executes the method executed by the storage device, the storage command processing unit responds to erasing a large block, the large block includes multiple physical blocks from multiple logical units; if the number of unprocessed erase operations corresponding to multiple LUN controllers is less than a specified threshold, the storage command processing unit provides a medium interface command indicating an erase operation to the medium interface controller; repeatedly execute the step of providing a medium interface command indicating an erase operation to the medium interface controller if the number of unprocessed erase operations corresponding to multiple LUN controllers is less than a specified threshold until all physical blocks of the large block are erased. The control component is also used to execute other implementation schemes of the method executed by the storage device, which will not be repeated here.

[0382] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A command distribution method, characterized in that: include: In response to the received media interface command, obtaining an operation type indicated by the media interface command; Determine a LUN controller associated with the media interface command and the operation type, distribute the media interface command to the LUN controller, and allow the LUN controller to process the media interface command; The operation type includes a P1 operation or an R operation, wherein the P1 operation indicates moving specified data in the memory to the NVM chip, and the R operation indicates performing an XOR calculation on the specified data in the memory and retaining the calculation result in the XOR cache.

2. The method according to claim 1, characterized in that The operation type also includes a P2 operation, and the P2 operation indicates moving the data in the XOR buffer to the NVM chip.

3. The method according to claim 2, characterized in that In the case where the operation type is a P1 operation or a P2 operation, the medium interface command includes a field indicating a physical address of an NVM chip to be accessed and a field indicating data to be moved; The determining a LUN controller associated with the media interface command and the operation type includes: Determining the accessed logical unit based on the physical address indicated by the media interface command; Based on the mapping relationship between the logical unit and the LUN controller, the LUN controller corresponding to the accessed logical unit is determined.

4. The method according to claim 3, characterized in that In the case where the operation type is a P1 operation, in response to the accessed physical page and the designated data in the memory, the LUN controller generates a storage medium access command and sends it to the corresponding logical unit to write the designated data to the corresponding physical page to perform the P1 operation; The accessed physical page is determined based on the physical address indicated by the media interface command, and the designated data is the data to be moved in the memory indicated by the media interface command.

5. The method according to claim 3 or 4, characterized in that: In the case where the operation type is a P2 operation, in response to the accessed physical page and the check data in the XOR cache, the LUN controller generates a storage medium access command and sends it to the corresponding logical unit to write the check data to the corresponding physical page to perform the P2 operation; The accessed physical page is determined based on the physical address indicated by the media interface command, the verification data is the data to be moved in the XOR cache indicated by the media interface command, and the verification data is determined based on multiple specified data to be moved in the memory, and the multiple specified data are written into the same page stripe.

6. The method according to any one of claims 3 to 5, characterized in that: In a case where the operation type is an R operation, determining a LUN controller associated with the media interface command and the operation type includes: A LUN controller determined from among the multiple LUN controllers and having no uncompleted erase operation is determined as a LUN controller associated with the media interface command and the operation type.

7. The method according to claim 6, characterized in that In a case where the media interface command includes a field indicating a LUN controller, determining a LUN controller without an uncompleted erase operation as a LUN controller associated with the media interface command and the operation type includes: Determine a first LUN controller based on the LUN controller indicated by the media interface command; If there is no uncompleted erase operation on the first LUN controller, determining the first LUN controller as a LUN controller associated with the media interface command and the operation type; and If the first LUN controller has an uncompleted erase operation, a second LUN controller determined from a plurality of LUN controllers and having no uncompleted erase operation is determined as the LUN controller associated with the media interface command and the operation type.

8. The method according to any one of claims 6 to 7, characterized in that: The media interface command includes a source address field and a destination address field indicating data to be operated; the method further includes: Applying for an XOR cache based on a destination address indicated by the media interface command; In case the application is successful, the determined LUN controller performs an XOR operation on the data to be operated indicated by the source address field and the data in the applied XOR cache, and retains the calculation result in the applied XOR cache.

9. The method according to any one of claims 1 to 8, characterized in that: If the LUN controller has an uncompleted erase operation, the LUN controller processes the media interface command whose operation type is a P1 operation or a P2 operation after processing the erase operation.

10. A media interface controller, characterized in that: include: Command distribution unit and multiple LUN controllers; The command allocation unit obtains, in response to the received media interface command, an operation type indicated by the media interface command, determines a LUN controller associated with the media interface command and the operation type among the multiple LUN controllers, allocates the media interface command to the LUN controller, and the LUN controller processes the media interface command; The operation type is a P1 operation or an R operation, the P1 operation indicates moving specified data in the memory to the NVM chip, and the R operation indicates performing an XOR calculation on the specified data in the memory and retaining the calculation result in the XOR cache.

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