Wafer-level chip batch burning and testing method

Abstract

The invention discloses a wafer-level chip batch burning and testing method, and relates to the technical field of chip batch burning and testing, and the method comprises the following steps: 1, etching a plurality of chips on a wafer, and reserving scribing channel regions which are distributed in a criss-cross manner and used for deploying a burning communication network and a communication connecting line; and 2, constructing a data communication network on the wafer by using the scribing channel regions which are distributed in a criss-cross manner, and arranging devices and metal connecting wires for chip burning and communication in each scribing channel region by the data communication network. Batch burning and testing are carried out on the wafer level, the burning efficiency and the success rate are improved, the operation steps are reduced, the production efficiency is improved, independent identification and control of the chip are achieved by building the data communication network and using the unique device identifier, comprehensive electrical performance testing is combined with the clustering algorithm, abnormity is accurately detected and analyzed, and the reliability of the chip is improved. And the product quality and the production reliability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip batch burning and testing, and in particular to a wafer-level chip batch burning and testing method. Background Art

[0002] When the RFID tag chip leaves the factory, some device information (TID, EPC, and security information) needs to be burned into the chip's storage area one by one. The traditional burning method is generally to wait until the chip is diced, and then burn it one by one during the chip packaging process or after the packaging is completed. The burning efficiency is low and it is not easy to mass produce and test. In addition, after the chip is packaged into a tag, there is a certain probability of failure to rely on the RFID reader to burn the tag data over the air interface, mainly because the uneven distribution of the air interface radio frequency energy may cause some tags to fail to obtain sufficient burning voltage, resulting in unsuccessful burning.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present invention is to provide a wafer-level chip batch burning and testing method. By performing batch and large-scale burning and testing at the wafer level, data burning is realized before the chip is diced, effectively improving the chip burning efficiency, reducing the operation steps, and significantly improving the production efficiency. By directly constructing a data communication network on the wafer, a stable burning voltage and a reliable communication line are provided to ensure that each chip can obtain sufficient burning voltage, improve the burning success rate, and avoid the burning failure caused by uneven distribution of radio frequency energy. Secondly, it allows the testing and data burning of chips on the wafer at the same time, provides a wide coverage of testing and yield guarantee, reduces the chip abandonment caused by burning failure, and saves costs and materials. The deployment of the serial data communication network makes the communication network of each BLOCK block independent and flexible, and can be independently verified and tested. The independent identification and control of each chip are realized through a unique device identifier (ROM_ID), which improves the accuracy and flexibility of testing and burning. In comprehensive electrical performance testing, the present invention can quickly detect and analyze anomalies, screen out problem areas through clustering algorithms, improve the accuracy and efficiency of fault detection, and enhance overall product quality and production reliability to solve the problems in the above-mentioned background technology.

[0005] In order to achieve the above object, the present invention provides the following technical solution: a wafer-level chip batch burning and testing method, comprising the following steps:

[0006] Step 1: Etch multiple chips on the wafer and reserve scribe lane areas, which are crisscrossed and used to deploy the burning communication network and communication lines;

[0007] Step 2: Using the crisscrossed scribe lanes, a data communication network is constructed on the wafer. The data communication network is equipped with metal wires for chip programming and communication in each scribe lane.

[0008] Step 3: Divide the wafer into multiple BLOCK blocks. Each BLOCK block corresponds to an independent serial communication network. The serial communication network connects all chips in the BLOCK block through metal connections in the dicing area, and divides the blocks according to the maximum area of ​​single illumination.

[0009] Step 4: A serial communication interface controller is set in the dicing lane area in each BLOCK block. The serial communication interface controller is responsible for managing the communication with all chips in the BLOCK block, controlling the data burning logic, and connecting external devices through the port PAD to realize the power supply and data reading and writing operations of the wafer;

[0010] Step 5: Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network;

[0011] Step 6: Set a unique device identifier ROM_ID on each chip, and use ROM_ID to identify and locate each chip in the serial communication network to achieve independent identification and burning control of multiple chips on the wafer.

[0012] Preferably, the process of etching a plurality of chips on a wafer and reserving a scribe line area comprises the following specific steps:

[0013] Thin wafers are cut from high-purity single-crystal silicon ingots, and the surface of the wafers is finely planarized to ensure that the surface of the wafers is smooth and flat;

[0014] A layer of photosensitive photoresist is evenly coated on the cleaned wafer surface. Then, according to the designed chip circuit and scribe line area layout, a mask is used to project light onto the photoresist-coated wafer surface to form a photolithography pattern.

[0015] After the photolithography is completed, the wafer enters the etching process. During the etching process, the unnecessary parts are removed according to the photolithography pattern to form multiple independent chip areas and scribe line areas;

[0016] After etching is completed, the scribe line area is used to deploy the burned-in communication network and communication lines.

[0017] Preferably, the metal connection lines include BURN lines, PROG lines, VCC lines and GND lines to support chip data burning and power supply requirements.

[0018] Preferably, a data communication network is constructed on the wafer using the crisscrossed scribe lane areas, and the specific steps are as follows:

[0019] Determine the layout of the scribe lanes on the wafer. The scribe lanes are reserved on the wafer for future chip separation and communication network layout. According to the size and arrangement of the chips, the scribe lanes are evenly divided on the wafer.

[0020] Coating photoresist on the surface of the wafer and generating a pattern of the communication network in the scribe line area by photolithography;

[0021] Use a mask to project light onto the photoresist to expose the parts where metal connections need to be formed. The photoresist will remain in the areas not exposed to light, protecting the wafer surface below from being etched.

[0022] After photolithography, the wafer enters the dry etching process, using plasma etching technology to remove the exposed part of the photoresist, forming grooves for laying metal wiring. The grooves match the vertical and horizontal layout of the scribe line to build the path of the data communication network;

[0023] Metal material is deposited in the groove formed by etching. After deposition, photolithography and etching are performed again to remove excess metal and retain the part in the groove to form the final metal connection.

[0024] Preferably, the wafer is divided into a plurality of BLOCK blocks, each BLOCK block corresponds to an independent serial communication network, and the specific steps are as follows:

[0025] Determine the maximum area of ​​single illumination of the lithography equipment. According to the size of the chip DIE and the layout on the wafer, the width of the scribe line is set to W. scribe , the chip height is H chip , chip width is W chip , according to A max , W scribe , H chip , W chip Calculate the size of a BLOCK block. The calculation expression is:

[0026]

[0027] , where N block Indicates the number of BLOCK blocks that can be included in a single lighting area, A max It represents the maximum area of ​​single illumination, and represents the maximum effective area of ​​single exposure of the lithography equipment. Represents the rounding symbol;

[0028] After determining the size of the BLOCK, the wafer is divided into several blocks, each of which is an independent BLOCK. Suppose the total area of ​​the wafer is A. wafer , the wafer is divided into multiple BLOCK blocks, and the calculation expression for the total number of BLOCK blocks that can be divided on the wafer is:

[0029] ,

[0030] Where M block Indicates the total number of BLOCK blocks that can be divided on the wafer, A chip Indicates the area of ​​each chip;

[0031] In the dicing area, metal lines for the serial communication network are laid out, including BURN lines, PROG lines, VCC lines, and GND lines. All chips in each BLOCK block are connected to an independent serial communication network controller through metal lines.

[0032] After the serial communication network is built, a comprehensive electrical performance test and verification is carried out to ensure that the independent communication network of each BLOCK block works normally and all metal wires and chip connections are intact. During the test, the communication network of each BLOCK block is independently verified by the controller. The specific verification expression is:

[0033] ,

[0034] T test Represents the total test time of all BLOCK communication networks on the entire wafer, t connect,i Indicates the connection test time of the i-th BLOCK block, t signal,i Indicates the signal transmission test time of the i-th BLOCK block.

[0035] Preferably, the total test time of all BLOCK block communication networks on the entire wafer is compared and analyzed with a pre-set total test time reference threshold range. If the total test time is not within the total test time reference threshold range, it is judged that there is an abnormality in the total test time; if the total test time is within the total test time reference threshold range, it is judged that there is no abnormality in the total test time.

[0036] Preferably, when the total test time of all BLOCK block communication networks on the entire wafer is abnormal, a clustering algorithm is used to screen out the BLOCK blocks with abnormal signal transmission test time. The specific steps are:

[0037] Collect the signal transmission test time t of each BLOCK blocksignal，i , where t signal,i The signal transmission test time of the i-th BLOCK block, calculate the average signal transmission test time μ t and standard deviation σ t Then, the test time of each BLOCK block is standardized to Z-score, and the standardized formula is:

[0038] ,

[0039] Where Zi is the normalized fraction of the signal transmission test time of the i-th BLOCK block;

[0040] In the initial stage of cluster analysis, the clustering algorithm is used to determine the initial cluster center, the standardized data is randomly divided into multiple classes, and the mean and standard deviation of each class are calculated as the initial cluster center. The purpose of this step is to provide a reasonable starting point for subsequent iterative optimization. The calculation expression is: In the formula, represents the initial mean of the kth class, represents the initial standard deviation of the kth class, Indicates the initial set of BLOCK blocks contained in the kth category. Indicates the number of BLOCK blocks in the initial k-th category;

[0041] Through the iterative optimization process, the mean and standard deviation of each class are updated. After each iteration, each BLOCK block is redistributed to its nearest cluster center, and the mean and standard deviation of the new class are calculated. The iteration continues until the category center converges, that is, the clustering result no longer changes significantly. The calculation expression for clustering iterative update is: In the formula, represents the mean of the kth class after the t+1th iteration, represents the standard deviation of the kth category after the t+1th iteration, Indicates the set of BLOCK blocks contained in the k-th category in the t-th iteration, Indicates the number of BLOCK blocks in the kth category at the tth iteration;

[0042] According to the clustering results, determine the mean μ of the abnormal category abnormal and standard deviation σ abnormal , filter out the BLOCK blocks with abnormal signal transmission test time and mark them. The specific expression is: In the formula, A i The abnormal flag of the i-th BLOCK, 1 means abnormal, 0 means normal, μ abnormal represents the mean of the classes marked as abnormal, σ abnormal represents the standard deviation of the category marked as abnormal,

[0043] In the formula, C abnormal represents the set of all data points contained in the abnormal category, |C abnormal | represents the number of data points in the anomaly class.

[0044] Preferably, a serial communication interface controller is provided in the dicing lane area in each BLOCK block, and the specific steps are as follows:

[0045] The layout and size of the scribe lane area in each BLOCK block are determined to accommodate the serial communication interface controller. The scribe lane area is the spacing area between chips and is used as a dividing line when cutting the wafer.

[0046] Once the layout and size of the scribe lane area are determined, the serial communication interface controller is designed. After the design is completed, the controller is integrated into the scribe lane area and the circuit pattern of the controller is printed on the wafer surface using precision lithography and etching processes;

[0047] After the controller is integrated, lay out the connection circuits between the serial communication interface controller and all the chips in the BLOCK block;

[0048] The serial communication interface controller is connected to external devices through the port PAD.

[0049] Preferably, each chip is connected to a communication network through a metal wire and its related PIN node is connected to a communication network, so that each chip can perform data transmission and burning operations through the communication network. The specific steps are as follows:

[0050] Determine the layout and function of each chip's PIN nodes, which are the interface for the chip to electrically connect to the outside world;

[0051] Design the metal wiring path of the communication network. The design of the metal wiring establishes an effective electrical connection between the chip and the communication network to ensure the stability and low latency of signal transmission;

[0052] After the design is completed, the photolithography and metal deposition processes are carried out. First, a layer of photoresist is coated on the surface of the wafer, and then the pre-designed metal connection pattern is exposed to the photoresist through a mask. The exposed area is developed to leave a channel for depositing metal. Next, metal material is deposited on the exposed area to form a metal line connecting the chip PIN node and the communication network;

[0053] After metal deposition is complete, the metal layer is etched and patterned to remove excess metal and retain the designated wiring sections in the design.

[0054] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0055] The present invention burns data before the chip is diced through wafer-level batch and large-scale burning and testing, which significantly improves the chip burning efficiency. Compared with the traditional method, there is no need to wait until the chip is diced and packaged before burning a single chip, which reduces the operation steps and improves the overall production efficiency.

[0056] The present invention directly constructs a data communication network on the wafer, and ensures that each chip can obtain sufficient burning voltage through stable burning voltage and reliable communication lines, thereby improving the success rate of burning and avoiding the problem of burning failure caused by uneven distribution of radio frequency energy.

[0057] The present invention can simultaneously perform chip testing and data burning by performing burning and testing at the wafer level, providing wide coverage testing and yield assurance on and off the chip. Compared with the traditional method of burning and testing each chip one by one, this method not only improves production efficiency, but also reduces the risk of chips being discarded due to burning failure, saving costs and materials.

[0058] The serial data communication network deployed on the wafer of the present invention makes the communication network of each BLOCK block independent and flexible, and each BLOCK block can be independently verified and tested. By using a unique device identifier (ROM_ID) in the communication network, independent identification and burning control of each chip can be achieved, which increases the flexibility and accuracy of data burning and testing, enables the production line to quickly locate and solve abnormal chips, and improves the reliability of the overall product.

[0059] The present invention can ensure the normal operation of the independent communication network of each BLOCK block and verify that the connection between all metal wires and chips is complete and correct by performing comprehensive electrical performance testing and verification after building the serial communication network. This testing method allows accurate monitoring and analysis of the total test time of all BLOCK block communication networks on the entire wafer. If there is an abnormality in the total test time, a clustering algorithm can be quickly used to screen out the BLOCK blocks with abnormal signal transmission test time, which greatly improves the accuracy and efficiency of fault detection, ensures that problems can be identified and solved in a timely manner during mass production, and helps to improve the overall quality of the product and the reliability of production. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0061] Figure 1 The present invention is a method flow chart of a wafer-level chip batch burning and testing method.

[0062] Figure 2 It is a schematic diagram of the wafer-level burning communication network of the present invention.

[0063] In the figure:

[0064] 101. Wafer; 102. Chip; 103. Slice road area; 104. BLOCK block; 105. Port PAD; 106. Slice road; 107. PIN node; 108. Device identifier ROM_ID; 109. Serial communication interface controller. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art.

[0066] The present invention provides Figure 1 A wafer-level chip batch burning and testing method shown includes the following steps:

[0067] Step 1: Etch multiple chips on the wafer and reserve scribe lane areas. The scribe lane areas are crisscrossed and used to deploy the burning communication network and communication lines. The standard chip DIE area is not occupied, making full use of the wafer area.

[0068] The process of etching multiple chips on a wafer and reserving the scribe line area is as follows:

[0069] Thin wafers are cut from high-purity single-crystal silicon ingots. In order to ensure the accuracy of the etching process and the performance of the chip, the surface of the wafer needs to be finely planarized, including chemical mechanical polishing (CMP) and other processes to ensure that the wafer surface is smooth and flat. This step also includes cleaning the wafer surface to remove any tiny particles and contaminants that may affect subsequent etching and processing. Through high-precision cleaning processes such as ultrasonic cleaning and deionized water rinsing, the wafer surface is ensured to be dust-free and dirt-free, laying the foundation for the accuracy of the etching process.

[0070] A layer of photosensitive photoresist is evenly coated on the surface of the cleaned wafer. This layer of photoresist can undergo chemical changes in response to light of a specific wavelength. Subsequently, according to the designed chip circuit and scribe area layout, a mask is used to project light onto the photoresist-coated wafer surface to form a photolithography pattern. The photolithography pattern design not only includes the detailed circuit layout of the chip, but also takes into account the reserved position of the scribe area to ensure that subsequent etching and scribe operations can be carried out accurately. This step is completed by high-precision lithography equipment, usually using deep ultraviolet (DUV) lithography technology to achieve nanometer-level pattern accuracy.

[0071] After the photolithography is completed, the wafer enters the etching process. Etching can be divided into dry etching and wet etching, and the specific choice depends on the required accuracy and material properties. During the etching process, according to the photolithography pattern, the unnecessary parts are removed to form multiple independent chip areas (DIE) and scribe lane areas. The scribe lane areas are usually distributed on the wafer in a matrix form, running through the entire wafer surface to form a grid-like gap. At this time, the precise size and position of the scribe lane area are very critical, because they must not only provide enough space for subsequent chip dicing, but also provide a suitable layout area for burning communication networks and communication connections.

[0072] After etching is completed, the scribe lane area is used to deploy the burn communication network and communication lines. In this step, engineers use the gaps in the scribe lane area to arrange communication lines for data burning and testing in these areas through further photolithography and metal deposition processes. These lines usually include BURN lines (for burning high voltage), PROG lines (for data communication), VCC lines (for power supply) and GND lines (for grounding). These metal lines form an efficient communication network, making subsequent batch chip burning and testing operations more convenient and efficient. This design avoids occupying the standard chip DIE area and effectively saves the use area of ​​the wafer.

[0073] Step 2: Using the crisscrossed scribe lanes, a data communication network is constructed on the wafer. The data communication network is equipped with metal wires for chip burning and communication in each scribe lane. The metal wires include BURN wires, PROG wires, VCC wires, and GND wires to support chip data burning and power supply requirements.

[0074] Using the crisscrossing scribe lanes, a data communication network is constructed on the wafer. The specific steps are as follows:

[0075] Determine the layout of the scribe lanes on the wafer. The scribe lanes are reserved spaces on the wafer for future chip separation and communication network layout. According to the size and arrangement of the chips, the scribe lanes are evenly divided on the wafer. The width and position of these scribe lanes need to be precisely designed to ensure that each chip can be safely separated during the subsequent cutting process, while leaving enough space for the metal wiring of the communication network. This step is usually performed when designing the chip mask to ensure that the scribe lane area can meet the mass production requirements at the wafer level.

[0076] Photoresist is applied to the surface of the wafer, and the pattern of the communication network is generated in the scribe area through the photolithography process. The purpose of the photolithography process is to form precise metal wiring channels in the scribe area to provide a basis for subsequent metal deposition. By using a specific mask, light is projected onto the photoresist to expose the parts where metal wiring needs to be formed. The areas not exposed to light will retain the photoresist, protecting the wafer surface below from being etched. This step ensures that the data communication network can be accurately formed in the scribe area and provides a pattern basis for subsequent circuit wiring.

[0077] After photolithography, the wafer enters the dry etching process. Using plasma etching technology, the exposed parts of the photoresist are removed to form trenches for laying metal wiring. These trenches match the vertical and horizontal layout of the scribe lines to accurately construct the paths of the data communication network. In this process, the depth and width of the etching need to be precisely controlled to ensure that the trench can accommodate the metal layer deposited in subsequent steps while avoiding damage to other parts of the chip. The accuracy of dry etching is crucial because it determines the electrical characteristics and stability of the communication network.

[0078] In the grooves formed by etching, metal materials such as aluminum or copper are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form metal connections. The deposited metal layer needs to be thick enough to ensure its low resistance characteristics when transmitting current and data. After the deposition is completed, photolithography and etching are performed again to remove excess metal, leaving only the part in the groove to form the final metal connection. These metal connections include BURN lines (for providing burning high voltage), PROG lines (for data communication), VCC lines (for power supply) and GND lines (for grounding), which together form a data communication network on the wafer, which can provide the necessary burning and testing functions for each chip.

[0079] Step 3: Divide the wafer into multiple BLOCK blocks. Each BLOCK block corresponds to an independent serial communication network. The serial communication network connects all chips in the BLOCK block through metal connections in the dicing area, and divides the blocks according to the maximum area of ​​single illumination.

[0080] Divide the wafer into multiple BLOCK blocks, each BLOCK block corresponds to an independent serial communication network. The specific steps are as follows:

[0081] Determine the maximum area of ​​a single illumination of the lithography equipment. This parameter depends on the exposure area capability of the lithography machine and is a key factor in determining the area of ​​each BLOCK. According to the size of the chip DIE and the layout on the wafer, the width of the scribe line (the interval between chips) is set to W. scribe , the chip height is H chip , chip width is W chip , according to A max , W scribe , H chip , W chip Calculate the size of a BLOCK block. The calculation expression is:

[0082]

[0083] , where N block Indicates the number of BLOCK blocks that can be included in a single lighting area, A max It indicates the maximum area of ​​single illumination, which represents the maximum effective area of ​​a single exposure of the lithography equipment;

[0084] After determining the size of the BLOCK, the wafer is divided into several blocks, each of which is an independent BLOCK, ensuring that these blocks are evenly distributed on the entire wafer. Suppose the total area of ​​the wafer is A. wafer , the wafer is divided into multiple BLOCK blocks, and the calculation expression for the total number of BLOCK blocks that can be divided on the wafer is:

[0085]

[0086] , where M block Indicates the total number of BLOCK blocks that can be divided on the wafer, A chip Indicates the area of ​​each chip;

[0087] In the dicing area, metal lines for the serial communication network are laid out, including BURN lines, PROG lines, VCC lines, and GND lines. All chips in each BLOCK block are connected to an independent serial communication network controller through metal lines.

[0088] After the serial communication network is built, a comprehensive electrical performance test and verification is carried out to ensure that the independent communication network of each BLOCK block works normally and all metal wires and chip connections are intact. During the test, the communication network of each BLOCK block needs to be independently verified by the corresponding controller. The specific verification expression is:

[0089] ,

[0090] T test Represents the total test time of all BLOCK communication networks on the entire wafer, t connect,i Indicates the connection test time of the i-th BLOCK block, t signal,i Indicates the signal transmission test time of the i-th BLOCK block;

[0091] The total test time of all BLOCK block communication networks on the entire wafer is compared and analyzed with the pre-set total test time reference threshold range. If the total test time is not within the total test time reference threshold range (i.e., lower than the lower limit or higher than the upper limit), it is judged that there is an abnormality in the total test time. If the total test time is within the total test time reference threshold range, it is judged that there is no abnormality in the total test time.

[0092] When the total test time of all BLOCK communication networks on the entire wafer is abnormal, a clustering algorithm is used to screen out the BLOCK blocks with abnormal signal transmission test time. The specific steps are as follows:

[0093] Collect the signal transmission test time t of each BLOCK block signal，i , where t signal,i The signal transmission test time of the i-th BLOCK block, calculate the average signal transmission test time μ t (the average value of all BLOCK block signal transmission test time) and standard deviation σ t (Standard deviation of signal transmission test time of all BLOCK blocks). Then, the test time of each BLOCK block is standardized to Z-score to eliminate the absolute value difference between different BLOCKs, so that different test times are comparable. The standardized formula is:

[0094] ,

[0095] In the formula, Z i The normalized score (Z-score) of the signal transmission test time of the i-th BLOCK block;

[0096] In the initial stage of cluster analysis, the initial cluster center is determined by clustering algorithms such as K-means, the standardized data is randomly divided into multiple classes, and the mean and standard deviation of each class are calculated as the initial cluster center. The purpose of this step is to provide a reasonable starting point for subsequent iterative optimization. The calculation expression is: In the formula, represents the initial mean of the kth class, represents the initial standard deviation of the kth class, Indicates the initial set of BLOCK blocks contained in the kth category. Indicates the number of BLOCK blocks in the initial k-th category;

[0097] Through the iterative optimization process, the mean and standard deviation of each class are updated. After each iteration, each BLOCK block is reallocated to its nearest cluster center, and the mean and standard deviation of the new class are calculated. The iteration continues until the category center converges, that is, the clustering result no longer changes significantly. Through this process, the category containing abnormal data (abnormal category) can be identified. The calculation expression for clustering iterative update is: In the formula, represents the mean of the kth class after the t+1th iteration, represents the standard deviation of the kth category after the t+1th iteration, Indicates the set of BLOCK blocks contained in the k-th category in the t-th iteration, Indicates the number of BLOCK blocks in the kth category at the tth iteration;

[0098] According to the clustering results, determine the mean μ of the abnormal category abnormal and standard deviation σ abnormal , filter out the BLOCK blocks with abnormal signal transmission test time and mark them. The specific expression is: In the formula, A i The abnormal flag of the i-th BLOCK, 1 means abnormal, 0 means normal, μ abnormal represents the mean of the classes marked as abnormal, σ abnormal represents the standard deviation of the category marked as abnormal,

[0099] In the formula, C abnormal represents the set of all data points contained in the abnormal category, |C abnormal | represents the number of data points in the anomaly class.

[0100] Step 4: Set a serial communication interface controller in the dicing lane area in each BLOCK block. The serial communication interface controller is responsible for managing the communication with all chips in the BLOCK block, controlling the data burning logic, and connecting external devices through the port PAD to realize the power supply and data reading and writing operations of the wafer;

[0101] A serial communication interface controller is set up in the dicing lane area within each BLOCK block. The specific steps are as follows:

[0102] Determine the appropriate layout and size of the scribe lane area within each BLOCK block to accommodate the serial communication interface controller. The scribe lane area is the spacing area between chips, usually used as the dividing line when cutting wafers. When designing this area, it is necessary to ensure that its width and length are large enough to accommodate the controller and its connected circuits and metal connections without interfering with the other functional layouts of the chip. This step involves precise calculations and designs to ensure maximum utilization of space and improve the integration of chips and communication lines.

[0103] Once the layout and size of the scribe lane area are determined, the serial communication interface controller can be designed. The design of this controller should take into account multiple functional requirements, including data transmission, signal conversion, and logic control. The controller usually contains multiple input and output ports, which are responsible for communicating with all chips in the BLOCK block. The controller needs to adopt efficient digital circuit design methods when designing it to ensure that it can achieve all the required functions in a limited space. After the design is completed, the controller is integrated into the scribe lane area, and the circuit pattern of the controller is printed on the wafer surface using precision lithography and etching processes.

[0104] After the controller is integrated, it is necessary to lay out the connection circuits between the serial communication interface controller and all the chips in the BLOCK block. The connection circuits are usually composed of metal wires, which are used to connect the output port of the controller to the input port of each chip. The layout and design of the metal wires must take into account signal integrity and transmission efficiency to avoid signal interference and excessive resistance. The wiring process requires the use of processes such as photolithography, deposition, and etching to accurately lay the metal wires in the channels between the scribe lane area and the chips to ensure that all chips can communicate effectively with the controller.

[0105] After ensuring that the communication lines between the controller and the chip are laid out, the serial communication interface controller needs to be connected to the external device through the port PAD. The port PAD is a metal contact point located on the surface of the wafer that allows external devices to be electrically connected to the controller inside the wafer through probes and other means. This connection is used to provide power to the wafer and perform data read and write operations. The design of the port PAD needs to take into account the size, contact pressure and signal transmission requirements of the probe to ensure that a stable electrical connection can be provided when connecting external devices while avoiding damage to the wafer surface.

[0106] Step 5: Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network;

[0107] Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network. The specific steps are as follows:

[0108] The PIN node layout and function of each chip need to be determined. These PIN nodes are the interface for the chip to be electrically connected to the outside world. Each PIN node usually has a specific function, such as power input (VCC), ground (GND), data input and output (PROG), burn control (BURN), etc. During the design phase, engineers will carefully arrange the location and connection paths of these PIN nodes according to the functional requirements of the chip and the requirements of the communication network. Ensuring the location of each PIN node is not only convenient for connection to the metal wire of the communication network, but also requires considering the integrity and electrical performance of signal transmission.

[0109] Next, design the metal wiring path of the communication network. The design of the metal wiring needs to establish an effective electrical connection between the chip and the communication network to ensure the stability and low latency of signal transmission. During the design process, it is necessary to consider the layout of each BLOCK block on the wafer and select the best metal wiring path to avoid crossing and interference with other circuits. At the same time, the width and thickness of the metal line must also be accurately calculated to support the necessary current and signal transmission rate. All these design details must be simulated and optimized in the circuit layout design software to ensure that the final electrical connection meets the design specifications.

[0110] After the design is completed, the photolithography and metal deposition processes are carried out. First, a layer of photoresist is coated on the surface of the wafer, and then the pre-designed metal wiring pattern is exposed to the photoresist through a mask. The exposed area is developed to leave a channel for depositing metal. Next, metal materials (such as aluminum or copper) are deposited on the exposed area through physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods to form metal lines connecting the chip PIN nodes and the communication network. The thickness and uniformity of metal deposition need to be precisely controlled to ensure that the electrical performance and mechanical strength meet the requirements.

[0111] After metal deposition is completed, the metal layer needs to be etched and patterned to remove excess metal and retain only the wiring specified in the design. This step is achieved by immersing the wafer in a chemical etching solution or using plasma etching technology to remove the part of the metal that is not protected by the photoresist. Control during the etching process is critical because it determines the precise width and shape of the metal connection, which directly affects the quality and reliability of signal transmission. The patterned metal connection will form a clear electrical path, connecting the PIN node of each chip to the communication network.

[0112] Step 6: Set a unique device identifier ROM_ID on each chip, use ROM_ID to identify and locate each chip in the serial communication network, and realize independent identification and burning control of multiple chips on the wafer;

[0113] Set a unique device identifier ROM_ID on each chip, use ROM_ID to identify and locate each chip in the serial communication network, and realize independent identification and burning control of multiple chips on the wafer. The specific steps are as follows:

[0114] The format and storage method of ROM_ID need to be designed. ROM_ID is a unique identifier used to distinguish and identify each chip in the communication network. The design of ROM_ID should ensure that it is unique throughout the production batch. It is usually in binary format, such as 8-bit, 16-bit or higher-bit encoding, and its length is determined according to the required uniqueness and security. The storage method depends on the memory structure of the chip. ROM_ID is usually stored in read-only memory (ROM) or electrically erasable programmable read-only memory (EEPROM) to ensure that it cannot be changed. This step requires consideration of the generation rules and allocation strategies of ROM_ID to ensure that each chip obtains a unique identifier during the design phase.

[0115] After determining the format and storage method of ROM_ID, the next step is to write ROM_ID into memory during chip manufacturing. This process is usually performed in the final stage before chip packaging. Using dedicated equipment or test instruments, ROM_ID data is written into the chip's read-only memory through a programming interface. Since ROM_ID is unchangeable, the programming process needs to be strictly controlled to ensure that the ROM_ID of each chip can be written correctly and without duplication. In some high-precision production lines, ROM_ID programming can be completed by automated equipment to ensure speed and accuracy.

[0116] After the ROM_ID is written to the memory, verification and testing are required to ensure that the ROM_ID is written correctly and can be read reliably. The verification process usually uses the same programming interface to verify the integrity and correctness of the ROM_ID by reading back. The test instrument reads the ROM_ID of each chip one by one and compares it with the preset standard value. If there is an error or mismatch, the chip will be marked as a defective product and further inspection or reprogramming is required. This step is very important to ensure that the ROM_ID of each chip is strictly verified before leaving the factory.

[0117] After the chip is installed in the communication network, the serial communication interface controller uses ROM_ID to identify and locate each chip. When an external device interacts with the chip through the communication network, the controller will first send a request command to require all chips to report their ROM_ID. Each chip transmits its ROM_ID back to the controller through the serial communication network according to the command received. The controller determines the unique identity and location of each chip through the received ROM_ID data, and then performs targeted operations such as data reading, writing or burning. Using ROM_ID for identification and positioning can avoid confusion and ensure that the operation of each chip can be performed independently and accurately.

[0118] Finally, ROM_ID is used to realize independent burning control and data management of multiple chips on the wafer. During the chip production process, the external device establishes communication with all chips on the wafer through the serial communication interface controller, and uses ROM_ID to select the target chip to perform specific data burning and programming operations. In this way, the burning control can be accurate to the level of a single chip, ensuring that each chip receives the correct data and stores it in the designated storage area. In addition, ROM_ID can also be used for chip traceability management. In the subsequent testing, assembly and maintenance process, by recording the ROM_ID of each chip and its operation log, quality control and problem tracking can be easily performed.

[0119] The present invention burns data before the chip is diced through wafer-level batch and large-scale burning and testing, which significantly improves the chip burning efficiency. Compared with the traditional method, there is no need to wait until the chip is diced and packaged before burning a single chip, which reduces the operation steps and improves the overall production efficiency.

[0120] The present invention directly constructs a data communication network on the wafer, and ensures that each chip can obtain sufficient burning voltage through stable burning voltage and reliable communication lines, thereby improving the success rate of burning and avoiding the problem of burning failure caused by uneven distribution of radio frequency energy.

[0121] The present invention can simultaneously perform chip testing and data burning by performing burning and testing at the wafer level, providing wide coverage testing and yield assurance on and off the chip. Compared with the traditional method of burning and testing each chip one by one, this method not only improves production efficiency, but also reduces the risk of chips being discarded due to burning failure, saving costs and materials.

[0122] The serial data communication network deployed on the wafer of the present invention makes the communication network of each BLOCK block independent and flexible, and each BLOCK block can be independently verified and tested. By using a unique device identifier (ROM_ID) in the communication network, independent identification and burning control of each chip can be achieved, which increases the flexibility and accuracy of data burning and testing, enables the production line to quickly locate and solve abnormal chips, and improves the reliability of the overall product.

[0123] The present invention can ensure the normal operation of the independent communication network of each BLOCK block and verify that the connection between all metal wires and chips is complete and correct by performing comprehensive electrical performance testing and verification after building the serial communication network. This testing method allows accurate monitoring and analysis of the total test time of all BLOCK block communication networks on the entire wafer. If there is an abnormality in the total test time, a clustering algorithm can be quickly used to screen out the BLOCK blocks with abnormal signal transmission test time, which greatly improves the accuracy and efficiency of fault detection, ensures that problems can be identified and solved in a timely manner during mass production, and helps to improve the overall quality of the product and the reliability of production.

[0124] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0125] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A wafer-level chip batch burning and testing method, characterized in that: The following steps are involved: Step 1: Etch multiple chips on the wafer and reserve scribe lane areas, which are crisscrossed and used to deploy the burning communication network and communication lines; Step 2: Using the crisscrossed scribe lanes, a data communication network is constructed on the wafer. The data communication network is equipped with metal wires for chip programming and communication in each scribe lane. Step 3: Divide the wafer into multiple BLOCK blocks. Each BLOCK block corresponds to an independent serial communication network. The serial communication network connects all chips in the BLOCK block through metal connections in the dicing area, and divides the blocks according to the maximum area of ​​single illumination. Step 4: A serial communication interface controller is set in the dicing lane area in each BLOCK block. The serial communication interface controller is responsible for managing the communication with all chips in the BLOCK block, controlling the data burning logic, and connecting external devices through the port PAD to realize the power supply and data reading and writing operations of the wafer; Step 5: Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network; Step 6: Set a unique device identifier ROM_ID on each chip, and use ROM_ID to identify and locate each chip in the serial communication network to achieve independent identification and burning control of multiple chips on the wafer.

2. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: The process of etching multiple chips on a wafer and reserving the scribe line area is as follows: Thin wafers are cut from high-purity single-crystal silicon ingots, and the surface of the wafers is finely planarized to ensure that the surface of the wafers is smooth and flat; A layer of photosensitive photoresist is evenly coated on the cleaned wafer surface. Then, according to the designed chip circuit and scribe line area layout, a mask is used to project light onto the photoresist-coated wafer surface to form a photolithography pattern. After the photolithography is completed, the wafer enters the etching process. During the etching process, the unnecessary parts are removed according to the photolithography pattern to form multiple independent chip areas and scribe line areas; After etching is completed, the scribe line area is used to deploy the burned-in communication network and communication lines.

3. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Metal connections include BURN lines, PROG lines, VCC lines, and GND lines to support chip data burning and power supply requirements.

4. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Using the crisscrossing scribe lanes, a data communication network is constructed on the wafer. The specific steps are as follows: Determine the layout of the scribe lanes on the wafer. The scribe lanes are reserved on the wafer for future chip separation and communication network layout. According to the size and arrangement of the chips, the scribe lanes are evenly divided on the wafer. Coating photoresist on the surface of the wafer and generating a pattern of the communication network in the scribe line area by photolithography; Use a mask to project light onto the photoresist to expose the parts where metal connections need to be formed. The photoresist will remain in the areas not exposed to light, protecting the wafer surface below from being etched. After photolithography, the wafer enters the dry etching process, using plasma etching technology to remove the exposed part of the photoresist, forming grooves for laying metal wiring. The grooves match the vertical and horizontal layout of the scribe line to build the path of the data communication network; Metal material is deposited in the groove formed by etching. After deposition, photolithography and etching are performed again to remove excess metal and retain the part in the groove to form the final metal connection.

5. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Divide the wafer into multiple BLOCK blocks, each BLOCK block corresponds to an independent serial communication network. The specific steps are as follows: Determine the maximum single illumination area of ​​the lithography equipment. According to the size of the chip DIE and the layout on the wafer, the width of the scribe line is set to w scribe , the chip height is H chip , chip width is W chip , according to A max 、w scribe , H chip , W chip Calculate the size of a BLOCK block. The calculation expression is: ， Where N block Indicates the number of BLOCK blocks that can be included in a single lighting area, A max It represents the maximum area of ​​a single illumination, and represents the maximum effective area of ​​a single exposure of the lithography equipment. Represents the rounding symbol; After determining the size of the BLOCK, the wafer is divided into several blocks, each of which is an independent BLOCK. Suppose the total area of ​​the wafer is A. wafer , the wafer is divided into multiple BLOCK blocks, and the calculation expression for the total number of BLOCK blocks that can be divided on the wafer is: ， Where M block Indicates the total number of BLOCK blocks that can be divided on the wafer, A chip Indicates the area of ​​each chip; In the dicing area, metal lines for the serial communication network are laid out, including BURN lines, PROG lines, VCC lines, and GND lines. All chips in each BLOCK block are connected to an independent serial communication network controller through metal lines. After the serial communication network is built, a comprehensive electrical performance test and verification is carried out to ensure that the independent communication network of each BLOCK block works normally and all metal wires and chip connections are intact. During the test, the communication network of each BLOCK block is independently verified by the controller. The specific verification expression is: ， T test Represents the total test time of all BLOCK communication networks on the entire wafer, t connect,i Indicates the connection test time of the i-th BLOCK block, t signal,i Indicates the signal transmission test time of the i-th BLOCK block.

6. A wafer-level chip batch burning and testing method according to claim 5, characterized in that: The total test time of all BLOCK block communication networks on the entire wafer is compared and analyzed with the pre-set total test time reference threshold range. If the total test time is not within the total test time reference threshold range, it is judged that there is an abnormality in the total test time. If the total test time is within the total test time reference threshold range, it is judged that there is no abnormality in the total test time.

7. A wafer-level chip batch programming and testing method according to claim 6, characterized in that: When the total test time of all BLOCK communication networks on the entire wafer is abnormal, a clustering algorithm is used to screen out the BLOCK blocks with abnormal signal transmission test time. The specific steps are as follows: Collect the signal transmission test time t of each BLOCK block signal，i , where t signal,i The signal transmission test time of the i-th BLOCK block, calculate the average signal transmission test time μ t and standard deviation σ t Then, the test time of each BLOCK block is standardized to Z-score, and the standardized formula is: ， Where Zi is the normalized fraction of the signal transmission test time of the i-th BLOCK block; In the initial stage of cluster analysis, the clustering algorithm is used to determine the initial cluster center, the standardized data is randomly divided into multiple classes, and the mean and standard deviation of each class are calculated as the initial cluster center. The purpose of this step is to provide a reasonable starting point for subsequent iterative optimization. The calculation expression is: In the formula, represents the initial mean of the kth class, represents the initial standard deviation of the kth class, Indicates the initial set of BLOCK blocks contained in the kth category. Indicates the number of BLOCK blocks in the initial k-th category; Through the iterative optimization process, the mean and standard deviation of each class are updated. After each iteration, each BLOCK block is redistributed to its nearest cluster center, and the mean and standard deviation of the new class are calculated. The iteration continues until the category center converges, that is, the clustering result no longer changes significantly. The calculation expression for clustering iterative update is: In the formula, represents the mean of the kth class after the t+1th iteration, represents the standard deviation of the kth category after the t+1th iteration, Indicates the set of BLOCK blocks contained in the k-th category in the t-th iteration, Indicates the number of BLOCK blocks in the kth category at the tth iteration; According to the clustering results, determine the mean μ of the abnormal category abnormal and standard deviation σ abnormal , filter out the BLOCK blocks with abnormal signal transmission test time and mark them. The specific expression is: In the formula, A i The abnormal flag of the i-th BLOCK, 1 means abnormal, 0 means normal, μ abnormal represents the mean of the categories marked as abnormal, σ abnormal represents the standard deviation of the category marked as abnormal, In the formula, C abnormal represents the set of all data points contained in the abnormal category, |C abnormal | represents the number of data points in the anomaly class.

8. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: A serial communication interface controller is set up in the dicing lane area within each BLOCK block. The specific steps are as follows: The layout and size of the scribe lane area in each BLOCK block are determined to accommodate the serial communication interface controller. The scribe lane area is the spacing area between chips and is used as a dividing line when cutting the wafer. Once the layout and size of the scribe lane area are determined, the serial communication interface controller is designed. After the design is completed, the controller is integrated into the scribe lane area and the circuit pattern of the controller is printed on the wafer surface using precision lithography and etching processes; After the controller is integrated, lay out the connection circuits between the serial communication interface controller and all the chips in the BLOCK block; The serial communication interface controller is connected to external devices through the port PAD.

9. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network. The specific steps are as follows: Determine the layout and function of each chip's PIN nodes, which are the interface for the chip to electrically connect to the outside world; Design the metal wiring path of the communication network. The design of the metal wiring establishes an effective electrical connection between the chip and the communication network to ensure the stability and low latency of signal transmission; After the design is completed, the photolithography and metal deposition processes are carried out. First, a layer of photoresist is coated on the surface of the wafer, and then the pre-designed metal connection pattern is exposed to the photoresist through a mask. The exposed area is developed to leave a channel for depositing metal. Next, metal material is deposited on the exposed area to form a metal line connecting the chip PIN node and the communication network; After metal deposition is complete, the metal layer is etched and patterned to remove excess metal and retain the designated wiring sections in the design.

Images