Instruction execution method, processor, chip and electronic equipment

Abstract

The embodiment of the invention provides an instruction execution method, a processor, a chip and electronic equipment. The method comprises the steps of obtaining a dot product calculation instruction; decoding the dot product calculation instruction to obtain a plurality of source operands; the plurality of source operands at least comprise a floating-point number with a first bit width; determining a first intermediate operation result and a second intermediate operation result according to the plurality of source operands; selecting a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result at least based on the index condition determined by the source operand; and combining the sign bit, the index and the mantissa of the target operand to obtain the target operand. According to the embodiment of the invention, dot product calculation can be directly carried out on the floating-point number with the first bit width, the calculation amount of an instruction execution method can be reduced, and the performance of a processor for executing a dot product calculation instruction is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to an instruction execution method, a processor, a chip, and an electronic device. Background Art

[0002] A floating point number is a mathematical format for representing real numbers in a computer. Based on the different bit widths of floating point numbers, floating point numbers have different representation formats, such as BF (Brain Floating point) 16, SP (Single Precision) 32, etc.; among them, BF16 is a 16-bit wide floating point representation format, and SP32 is a representation format that uses 32 bits to represent floating point numbers.

[0003] The dot product calculation instruction of floating point numbers is an instruction that uses floating point numbers as operands and multiplication and addition as calculation logic. The dot product calculation instruction is widely used in scenarios that require calculation accuracy, such as AI (Artificial Intelligence) calculations, engineering and scientific calculations, and graphics calculations. Therefore, how to provide a technical solution to improve the execution performance of the processor to execute the dot product calculation instruction has become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] The embodiments of the present application provide an instruction execution method, a processor, a chip, and an electronic device to improve the execution performance of the processor in executing dot product calculation instructions.

[0005] In a first aspect, an embodiment of the present application provides an instruction execution method, including:

[0006] Get the dot product calculation instruction;

[0007] Decoding the dot product calculation instruction to obtain a plurality of source operands; the plurality of source operands at least include a floating point number of a first bit width, wherein a mantissa bit width of the floating point number of the first bit width is smaller than an exponent bit width;

[0008] Determine a first intermediate operation result and a second intermediate operation result according to the plurality of source operands; select a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operands;

[0009] And, combining the sign bit, exponent and mantissa of the target operand, a target operand is obtained, wherein the target operand is a floating point number with a first bit width.

[0010] In a second aspect, an embodiment of the present application provides a processor, including:

[0011] Instruction fetch unit, used to fetch dot product calculation instructions;

[0012] A decoding unit, configured to decode the dot product calculation instruction to obtain a plurality of source operands; the plurality of source operands at least include a floating point number of a first bit width, wherein a mantissa bit width of the floating point number of the first bit width is smaller than an exponent bit width;

[0013] An execution unit, the execution unit comprising a floating point multiplier and adder;

[0014] The floating point multiplier and adder is used for:

[0015] A first intermediate operation result and a second intermediate operation result are determined according to the multiple source operands; a mantissa of a target operand is selected from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operands; wherein the target operand is obtained by combining the sign bit, the exponent and the mantissa of the target operand.

[0016] In a third aspect, an embodiment of the present application provides a chip, comprising the processor as described in the second aspect above.

[0017] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising the chip as described in the third aspect above.

[0018] The instruction execution method provided in the embodiment of the present application first obtains the dot product calculation instruction and decodes it to obtain multiple source operands, and the multiple source operands at least include the floating point number of the first bit width; then, the first intermediate operation result and the second intermediate operation result are determined according to the multiple source operands; further, at least based on the exponent situation determined by the source operand, the mantissa of the target operand is selected from the first intermediate operation result and the second intermediate operation result; finally, the target operand is obtained by combining the sign bit, exponent and mantissa of the target operand. Since the source operand includes at least the floating point number of the first bit width, and the mantissa bit width in the floating point number of the first bit width is smaller than the exponent bit width, the instruction execution method provided in the embodiment of the present application can directly perform dot product calculation on the floating point number of the first bit width, avoiding the reuse of the floating point multiplication and addition logic of the second bit width to perform the dot product calculation of the first bit width (the second bit width is greater than the first bit width), thereby reducing the amount of calculation of the instruction execution method, reducing the calculation delay, improving the instruction execution efficiency, and thus improving the performance of the processor in executing the dot product calculation instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0020] Figure 1 It is a schematic diagram of dot product calculation for BF16 floating point numbers.

[0021] Figure 2 The invention is a schematic diagram of an instruction execution method for a dot product calculation instruction of a BF16 floating point number.

[0022] Figure 3 It is a flowchart of an instruction execution method provided in an embodiment of the present application.

[0023] Figure 4 It is a schematic diagram of the first calculation logic of an instruction execution method provided in an embodiment of the present application.

[0024] Figure 5 It is a pipeline division diagram of an instruction execution method provided in an embodiment of the present application.

[0025] Figure 6 It is a schematic diagram of the second calculation logic of an instruction execution method provided in an embodiment of the present application.

[0026] Figure 7 It is a schematic diagram of the third calculation logic of an instruction execution method provided in an embodiment of the present application.

[0027] Figure 8 It is a schematic diagram of the fourth calculation logic of an instruction execution method provided in an embodiment of the present application.

[0028] Fig. 9 It is a schematic diagram of a processor provided in an embodiment of the present application.

[0029] Fig.10 It is a schematic diagram of a floating-point multiplier and adder provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] BF16 is a floating-point computing format widely used in AI computing, which contains 1 sign bit, 8 exponent bits, and 7 mantissa bits. On the one hand, BF16 can provide a large dynamic range and sufficient precision representation, and on the other hand, its storage width is small, which reduces the pressure on memory access. This is especially important for AI systems that process large amounts of data and complex computing tasks. And because BF16 can achieve higher computing performance at a lower storage cost, it is widely supported in various AI hardware.

[0032] Modern processors such as CPU, GPU, and various NPUs (Neural Network Processing Units) specifically used for AI computing can support accelerated computing of BF16 format floating point numbers. While performing traditional computing tasks, modern processors can also greatly improve the efficiency of AI computing by supporting the calculation of BF16 format floating point numbers, and can achieve higher performance and energy efficiency when performing reasoning and training of deep learning models.

[0033] In deep learning and other numerical computing-intensive applications, dot product operations are the basis for implementing various algorithms, and their efficiency directly affects the overall performance. Specifically, Figure 1 This is a schematic diagram of dot product calculation for BF16 floating point numbers, refer to Figure 1 , a mathematical expression for the dot product calculation of BF16 floating point numbers is shown as follows:

[0034] F = C + A0*B0 + A1*B1;

[0035] Among them, C is a floating point number in BF16 or SP32 format, and A0, A1, B0, and B1 are all floating point numbers in BF16 format.

[0036] Since the exponent bit width of the floating-point number in the BF16 format is the same as that of the floating-point number in the SP32 format, but the mantissa bit width is 16 bits less, an instruction execution method for the dot product calculation instruction of the BF16 floating-point number is: use the SP32 floating-point number multiplication and addition logic to perform two consecutive floating-point multiplications and additions to implement the BF16 dot product calculation.

[0037] Figure 2 This is a schematic diagram of the instruction execution method for the dot product calculation instruction of BF16 floating point numbers, refer to Figure 2 , the mathematical expression for the dot product calculation of BF16 floating point numbers using the SP32 floating point multiplication and addition logic is as follows:

[0038] Tmp=C+A0*B0;

[0039] F=Tmp+A1*B1.

[0040] Although the above instruction execution method can implement the dot product calculation of BF16 by using the floating-point multiplication and addition logic for SP32 format floating-point numbers, it has the following problems: long execution time and high resource consumption.

[0041] The execution time is long because the bit width of SP32 format floating-point numbers is large, and two floating-point multiplications and additions need to be performed consecutively, resulting in a long execution delay. For example, in some instruction execution methods for dot product calculation instructions for BF16 floating-point numbers, one SP32 floating-point multiplication and addition logic requires 4 beats to complete, and two times require a total of 8 beats to complete the dot product calculation instruction for BF16 floating-point numbers, which significantly increases the overall execution time when performing complex calculation tasks.

[0042] The resource consumption is large. On the one hand, since the mantissa width of the SP32 floating-point number is 23+1 bits, while the mantissa width of the BF16 floating-point number is 7+1 bits, considering only the area of ​​the floating-point multiplication array for the SP32 format floating-point number, the area of ​​the SP32 floating-point number multiplication array is 9 times that of the BF16 floating-point number, and in some instruction execution methods for the dot product calculation instructions of the BF16 floating-point number, it is necessary to execute the SP32 floating-point number multiplication and addition logic twice, which further increases the power consumption; on the other hand, in order to execute these two SP32 floating-point number multiplication and addition logics, it is necessary to read the physical register file twice in succession, one time to read the data required by the first SP32 floating-point number multiplication and addition logic, that is, C, A0 and B0, and the other time to read the data required by the second SP32 floating-point number multiplication and addition logic, that is, A1 and B1, so frequent access to the physical register file also leads to higher power consumption. Although it is possible to obtain A1 and B1 at the same time in one access and save A1 and B1 in a specific register to avoid reading the physical register twice, this method will cause additional hardware overhead and increase the complexity of instruction execution.

[0043] Based on the above content, an embodiment of the present application provides an instruction execution method, firstly obtaining a dot product calculation instruction and decoding it to obtain multiple source operands, wherein the multiple source operands include at least a floating-point number of the first bit width (for example, BF16), that is, by obtaining multiple source operands of the first bit width at one time, the instruction execution efficiency is improved; then, according to the multiple source operands, a first intermediate operation result and a second intermediate operation result are determined. Since the source operand includes at least a floating-point number of the first bit width, and the mantissa bit width in the floating-point number of the first bit width is smaller than the exponent bit width, the instruction execution method provided in the embodiment of the present application can perform the first intermediate operation result on the first intermediate operation result. Directly performing dot product calculation on floating-point numbers of the same bit width can avoid reusing the floating-point multiplication and addition logic of the second bit width (for example, SP32) to perform dot product calculation on the first bit width (the second bit width is larger than the first bit width), thereby reducing the amount of calculation of the instruction execution method, reducing the calculation delay, and improving the instruction execution efficiency; further, according to the exponent and sign bit of the source operand, the mantissa of the target operand is selected from the first intermediate operation result and the second intermediate operation result, and finally the target operand is obtained by combining the sign bit, exponent and mantissa of the target operand, thereby completing the dot product calculation instruction for the floating-point number of the first bit width.

[0044] Figure 3 is a flowchart of an instruction execution method provided by an embodiment of the present application. Figure 3 , an instruction execution method provided by an embodiment of the present application may include the following steps.

[0045] Step S10: Obtain a dot product calculation instruction.

[0046] To execute the dot product calculation instruction, it is necessary to obtain the dot product calculation instruction, which includes at least a plurality of operands. In some implementations, the dot product calculation instruction may also include an operation code or register information, etc. After obtaining the dot product calculation instruction, continue to execute step S11.

[0047] Step S11: Decode the dot product calculation instruction to obtain multiple source operands.

[0048] Wherein, the multiple source operands include at least a floating-point number of the first bit width, and the mantissa bit width of the floating-point number of the first bit width is smaller than the exponent bit width. In some embodiments, the floating-point number of the first bit width can be a floating-point number in the BF16 format, wherein, in the floating-point number in the BF16 format, the sign bit is 1 bit, the exponent bit width is 8 bits, and the mantissa bit width is 7 bits. It can be seen that in the floating-point number in the BF16 format, the mantissa bit width is smaller than the exponent bit width. By decoding the dot product calculation instruction, multiple source operands are obtained at one time, which can avoid reading the physical register multiple times and improve the instruction execution efficiency.

[0049] In some embodiments, the multiple source operands in step S11 include: a first source operand C, a second source operand A0, a third source operand A1, a fourth source operand B0, and a fifth source operand B1. The second source operand A0, the third source operand A1, the fourth source operand B0, and the fifth source operand B1 are floating point numbers with a first bit width, for example, the second source operand A0, the third source operand A1, the fourth source operand B0, and the fifth source operand B1 are all floating point numbers in BF16 format.

[0050] The first source operand C may be a floating point number of the first bit width, or a floating point number of the second bit width. In some embodiments, the first source operand C is a floating point number of the first bit width, for example, a floating point number in a BF16 format. In other embodiments, the first source operand C is a floating point number of the second bit width, and the mantissa bit width in the floating point number of the second bit width is greater than the exponent bit width, for example, the floating point number of the second bit width is a floating point in an SP32 format. In a floating point number in an SP32 format, the sign bit is 1 bit, the exponent bit width is 8 bits, and the mantissa bit width is 23 bits. It can be seen that the mantissa bit width of a floating point number in an SP32 format is greater than the exponent bit width.

[0051] Continue to refer Figure 3 After obtaining multiple source operands, continue to execute step S12.

[0052] Step S12: determining a first intermediate operation result and a second intermediate operation result according to the plurality of source operands, and selecting a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result based at least on an exponent determined by the source operands.

[0053] The first intermediate operation result mnear and the second intermediate operation result mfar are both calculated based on multiple source operands. In order to improve the accuracy of the execution of the dot product calculation instruction, it is necessary to calculate the first intermediate operation result mnear and the second intermediate operation result mfar respectively, and the first intermediate operation result mnear and the second intermediate operation result mfar respectively correspond to different exponents of the source operands to avoid large errors in the final results of subsequent calculations.

[0054] In some embodiments, in order to improve the instruction execution efficiency, the determining of the first intermediate operation result mnear and the second intermediate operation result mfar according to the multiple source operands can be: according to the multiple source operands, parallel calculation is performed to obtain the third intermediate operation result mc1 and the fourth intermediate operation result mc2; according to the third intermediate operation result mc1 and the fourth intermediate operation result mc2, parallel calculation is performed to obtain the first intermediate operation result mnear and the second intermediate operation result mfar.

[0055] For two calculation logics that do not have data dependencies, the efficiency of the calculation can be improved by parallel calculation. In some specific implementations, the embodiment of the present application can determine the third intermediate operation result mc1 with the first calculation logic according to the first source operand C, the second source operand A0 and the fourth source operand B0. In some specific implementations, the embodiment of the present application can determine the fourth intermediate operation result mc2 with the second calculation logic according to the third source operand A1 and the fifth source operand B1. Among them, the first calculation logic and the second calculation logic are parallel calculation logics.

[0056] Since the calculation process of the third intermediate operation result mc1, that is, the first calculation logic, only needs to provide the first source operand C, the second source operand A0 and the fourth source operand B0 for calculation; the calculation process of the fourth intermediate operation result mc2, that is, the second calculation logic, only needs to provide the third source operand A1 and the fifth source operand B1 among the multiple source operands for calculation, the third intermediate operation result mc1 and the fourth intermediate operation result mc2 can be calculated by executing the first calculation logic and the second calculation logic in parallel, thereby improving the efficiency of instruction execution.

[0057] It should be noted that the third intermediate operation result mc1 and the fourth intermediate operation result mc2 respectively represent the mantissa parts of two first-bit width floating-point numbers, that is, the third intermediate operation result mc1 and the fourth intermediate operation result mc2 respectively have their corresponding exponent parts and sign bits.

[0058] After obtaining the third intermediate operation result mc1 and the fourth intermediate operation result mc2, the embodiment of the present application can calculate in parallel the first intermediate operation result mnear and the second intermediate operation result mfar according to the third intermediate operation result mc1 and the fourth intermediate operation result mc2. For example, the embodiment of the present application can use parallel calculation logic to calculate in parallel the first intermediate operation result mnear and the second intermediate operation result mfar according to the third intermediate operation result mc1 and the fourth intermediate operation result mc2. Among them, when calculating the first intermediate operation result mnear according to the third intermediate operation result mc1 and the fourth intermediate operation result mc2, the embodiment of the present application can use the third calculation logic; when calculating the second intermediate operation result mfar according to the third intermediate operation result mc1 and the fourth intermediate operation result mc2, the embodiment of the present application can use the fourth calculation logic; the third calculation logic and the fourth calculation logic do not have data dependency on each other, so the third calculation logic and the fourth calculation logic can be executed in parallel to improve the efficiency of instruction execution.

[0059] Since the first intermediate operation result and the second intermediate operation result respectively correspond to different exponents of the source operand, it is necessary to select a suitable result as the mantissa mres of the target operand from the first intermediate operation result mnear and the second intermediate operation result mfar according to the exponent determined by the source operand after obtaining the first intermediate operation result mnear and the second intermediate operation result mfar.

[0060] Specifically, according to the exponent of the source operand, the exponent part ec1 corresponding to the third intermediate operation result mc1 and the exponent part ec2 corresponding to the fourth intermediate operation result mc2 can be calculated. According to the relationship between ec1 and ec2, and according to the sign bit of the source operand, the sign bit corresponding to the third intermediate operation result mc1 and the sign bit corresponding to the fourth intermediate operation result mc2 can be calculated, so as to select a suitable result as the mantissa mres of the target operand.

[0061] Among them, if the sign bit corresponding to the third intermediate operation result mc1 is different from the sign bit corresponding to the fourth intermediate operation result mc2, and the absolute value of the difference between the exponents corresponding to mc1 and mc2 |ec1-ec2|≤1, the embodiment of the present application can select the first intermediate operation result mnear as the mantissa mres of the target operand; that is, when calculating the first intermediate operation result mnear and the second intermediate operation result mfar, the actual values ​​of mc1 and mc2 are relatively close, and the calculation operation can be performed directly without the need for a large shift operation. At this time, the first intermediate operation result mnear is selected as the mantissa mres of the target operand.

[0062] If the sign bit corresponding to the third intermediate operation result mc1 is the same as the sign bit corresponding to the fourth intermediate operation result mc2, or the sign bit corresponding to the third intermediate operation result mc1 is different from the sign bit corresponding to the fourth intermediate operation result mc2, but the absolute value of the difference between the exponents corresponding to mc1 and mc2 |ec1-ec2|>1, then the embodiment of the present application can select the second intermediate operation result mfar as the mantissa mres of the target operand; that is, when calculating the first intermediate operation result mnear and the second intermediate operation result mfar, it is necessary to consider the shift and possible loss of precision, so a shift operation is required to align mc1 and mc2, and at this time the second intermediate operation result mfar is selected as the mantissa mres of the target operand.

[0063] Continue to refer Figure 3 After determining the mantissa mres of the target operand, continue to execute step S13.

[0064] Step S13: Combine the sign bit, exponent and mantissa of the target operand to obtain the target operand.

[0065] In an optional implementation, the target operand is a floating point number with the first bit width. For example, when the second source operand A0, the third source operand A1, the fourth source operand B0 and the fifth source operand B1 are all floating point numbers in BF16 format, the target operand is also a floating point number in BF16 format.

[0066] In the process of determining the mantissa mres of the target operand, the sign bit and the exponent of the target operand are also determined at the same time, so the target operand is finally obtained by combining the sign bit, the exponent and the mantissa of the target operand.

[0067] According to the above steps and Figure 2 , Figure 3 From the content, it can be seen that the instruction execution method provided in the embodiment of the present application can obtain multiple source operands of the dot product calculation instruction, and directly perform dot product calculation on the floating-point number of the first bit width, which can not only avoid multiple acquisitions of source operands, but also avoid reusing the floating-point multiplication and addition logic of the second bit width to perform dot product calculation of the first bit width, thereby reducing the amount of calculation of the instruction execution method and improving the performance of the processor in executing the dot product calculation instruction.

[0068] Figure 4 is a schematic diagram of the first calculation logic of the instruction execution method provided in an embodiment of the present application, and the first calculation logic is used to calculate and obtain the third intermediate operation result. Figure 4 , the first calculation logic can be set in the first calculation module, that is, the logic module in the processor that executes the first calculation logic can be regarded as the first calculation module. In some embodiments, the first calculation logic includes: data preprocessing logic, first normalization processing logic, and rounding processing logic. Accordingly, the first calculation module may include: a data preprocessing module that executes the data preprocessing logic, a first normalization processing module that executes the first normalization processing logic, and a rounding processing module that executes the rounding processing logic.

[0069] In an optional implementation, combined with Figure 4 As shown, determining the third intermediate operation result according to the first source operand, the second source operand and the fourth source operand with the first calculation logic may include:

[0070] According to the first source operand, the second source operand and the fourth source operand, processing is performed with data preprocessing logic to obtain an intermediate result to be normalized; according to the intermediate result to be normalized, processing is performed with the first normalization processing logic to obtain a first normalized result; according to the first normalized result, processing is performed with the rounding processing logic to obtain a third intermediate operation result.

[0071] In some embodiments, the multiple source operands include: a first source operand C, a second source operand A0, a third source operand A1, a fourth source operand B0, and a fifth source operand B1. Then, in the data preprocessing logic, the embodiment of the present application can calculate the intermediate result to be normalized according to the first source operand C, the second source operand A0, and the fourth source operand B0. The intermediate result to be normalized can include multiple values, for example, they can be recorded as sum1 and car1. That is to say, the data preprocessing logic is used to calculate the intermediate result to be normalized according to the first source operand C, the second source operand A0, and the fourth source operand B0. The intermediate result to be normalized will be normalized in subsequent processing to maximize the use of the representation range of floating-point numbers and improve the efficiency and accuracy of the dot product calculation instruction.

[0072] In some specific embodiments, the processing according to the first source operand, the second source operand, and the fourth source operand with data preprocessing logic to obtain the intermediate result to be normalized may include: generating a shift control signal according to the exponent of the first source operand, the exponent of the second source operand, and the exponent of the fourth source operand; performing a shift operation on the mantissa of the first source operand according to the shift control signal to obtain a first shift result; performing multiplication compression processing on the mantissa of the second source operand and the mantissa of the fourth source operand to obtain a first processing result and a first carry result; performing carry-preserve addition processing on the first shift result, the first processing result, and the first carry result to obtain a second processing result and a second carry result as the intermediate result to be normalized.

[0073] As an optional implementation example, combining Figure 5 As shown, the exponent of the first source operand C is recorded as ec, the exponent of the second source operand A0 is recorded as ea0, and the exponent of the fourth source operand B0 is recorded as eb0. Since the mantissa of the first source operand needs to be shifted, the shift amount, i.e., the shift control signal shift_amt1, needs to be determined. In some embodiments, combined with Figure 5 As shown, ec, ea0, and eb0 are input into the first exponential logic circuit EXP1 to obtain a shift control signal shift_amt1; wherein, shift_amt1=ea0+eb0-bias+26-ec; if ea0+eb0-bias+26-ec<0, the value of shift_amt1 is set to 0, and if ea0+eb0-bias+26-ec>53, the value of shift_amt1 is set to 53, bias is the exponential bias order determined according to the number of exponent bits k of the first source operand C, bias=2 (k-1) -1.

[0074] After the shift control signal shift_amt1 is determined, the mantissa mc of the first source operand is shifted by the first alignment unit Align1 according to the shift control signal shift_amt1 to obtain a first shift result mc_align, which is the mantissa mc of the first source operand after the shift operation.

[0075] Furthermore, in the data preprocessing logic, the mantissa ma0 of the second source operand A0 and the mantissa mb0 of the fourth source operand B0 may be subjected to multiplication compression processing to obtain a first processing result sum0 and a first carry result car0, so as to facilitate the subsequent calculation of the intermediate result to be normalized. In some embodiments, ma0 and mb0 are input into the first multiplication compression unit Mult1 to obtain sum0 and car0 output by the first multiplication compression unit mult1. The first multiplication compression unit Mult1 performs multiplication compression processing on the mantissa ma0 of the second source operand A0 and the mantissa mb0 of the fourth source operand B0, and the output result of the first multiplication compression unit Mult1 is determined according to the mantissa conditions of the multiple source operands.

[0076] For example, when the second source operand A0 and the fourth source operand B0 are both in BF16 format, the lengths of ma0 and mb0 are both 7 bits, and the first multiplication compression unit Mult1 is a multiplication logic for two 7-bit data. Since the processing process of the first multiplication compression unit Mult1 and the process of determining the shift control signal shift_amt1 do not have a data dependency relationship with each other. Therefore, in some specific implementations, the process of calculating the first processing result sum0 and the first carry result car0, and calculating the shift control signal shift_amt1 can be performed in parallel, that is, the processing of the first exponential logic circuit EXP1 and the first alignment unit Align1 is performed in parallel with the processing of the first multiplication compression unit Mult1.

[0077] After obtaining the first shift result mc_align, the first processing result sum0 and the first carry result car0, carry-save addition processing is performed to obtain the intermediate result to be normalized. In some embodiments, the first shift result mc_align, the first processing result sum0 and the first carry result car0 are input into a carry-save adder (CSA), and the output of the carry-save adder is the second processing result sum1 and the second carry result car1, which are the intermediate result to be normalized.

[0078] It can be seen that the data preprocessing logic shifts the mantissa of the first source operand by calculating the shift control signal according to the source operand, and performs multiplication compression on the mantissa of the second source operand and the mantissa of the fourth source operand; then, the intermediate result to be normalized is obtained by carry-preserving addition processing. During the execution of the instruction, the data preprocessing logic preprocesses the source operand and provides the required intermediate data for subsequent processing.

[0079] As an optional implementation, the first calculation logic further includes a first normalization processing logic; and the processing by the first normalization processing logic according to the intermediate result to be normalized to obtain the normalized result may include:

[0080] Performing addition processing on the second processing result and the second carry result to obtain a first addition result; performing leading zero prediction processing on the first addition result to obtain a first prediction result; performing normalization shift processing on the first addition result according to the first prediction result to obtain a first normalized result.

[0081] Since the second processing result sum1 and the second carry result car1 cannot directly represent the result of the calculation, it is necessary to perform addition processing on the second processing result sum1 and the second carry result car1. Specifically, refer to Figure 5 , sum1 and car1 are input into the first adder Adder1, so as to perform addition processing on the second processing result and the second carry result to obtain a first addition result; then, the first leading zero prediction unit LZA1 is used to perform leading zero prediction processing on the first addition result to obtain a first prediction result; then, the output result of the first leading zero prediction unit LZA1 and the output result of the first adder Adder1 are input into the first normalization unit Norm1, so as to use the output result of LZA1 (i.e., the first prediction result) to perform normalization shift on the output result of Adder1 (i.e., the first addition result) to obtain a first normalization result. The purpose of the normalization processing is to ensure the accuracy and standardization of floating-point numbers and avoid introducing unnecessary errors in subsequent calculations.

[0082] As an optional implementation, the first calculation logic also includes rounding processing logic; processing according to the first normalized result with the rounding processing logic to obtain the third intermediate operation result may include: rounding the first normalized result to obtain the first rounding result as the third intermediate operation result.

[0083] Since the format of the first normalized result may not meet the requirements of subsequent processing during the instruction execution, it is also necessary to round the first normalized result. Figure 5, the first normalized result is input into the rounding processing module Round1, and the first rounding result output by the rounding processing module Round1 is the third intermediate operation result mc1. In other words, the third intermediate operation result is the result after the first normalized result is rounded.

[0084] Figure 6 is a schematic diagram of the second calculation logic of the instruction execution method provided in an embodiment of the present application, and the second calculation logic is used to calculate the fourth intermediate operation result. Figure 6 , the second calculation logic can be set in the second calculation module, that is, the logic module that executes the second calculation logic in the processor can be regarded as the second calculation module. In some embodiments, the second calculation module may include a second multiplication compression unit and a second adder. As an optional implementation, the determination of the fourth intermediate operation result based on the third operand and the fifth operand with the second calculation logic includes: performing multiplication compression processing on the mantissa of the third source operand and the mantissa of the fifth source operand to obtain a third processing result and a third carry result; performing addition processing on the third processing result and the third carry result to obtain a second addition result as the fourth intermediate operation result.

[0085] The second multiplication compression unit is used to perform multiplication compression processing on the mantissa of the fourth source operand and the mantissa of the fifth source operand. Specifically, referring to Figure 5 As shown, the mantissa ma1 of the third source operand and the mantissa mb1 of the fifth source operand are input into the second multiplication compression unit Mult2 to obtain a third processing result sum2 and a third carry result car2 for subsequent processing.

[0086] The second adder is used to perform addition processing on the third processing result and the third carry result to obtain a second addition result as a fourth intermediate operation result. Figure 5 After obtaining the third processing result sum2 and the third carry result car2, since the third processing result sum2 and the third carry result car2 cannot directly represent the calculation result, they need to be added. Sum2 and car2 are input into the second adder Adder2, and the second addition result obtained is the fourth intermediate operation result mc2.

[0087] In some specific implementations, after obtaining the third intermediate operation result and the fourth intermediate operation result according to the first calculation logic and the second calculation logic respectively, the embodiment of the present application can obtain the first intermediate operation result and the second intermediate operation result by parallel calculation according to the third intermediate operation result and the fourth intermediate operation result. In an optional implementation, the embodiment of the present application can determine the smaller value and the larger value of the third intermediate operation result and the fourth intermediate operation result; determine the first intermediate operation result according to the smaller value and the larger value with the third calculation logic; determine the second intermediate operation result according to the smaller value and the larger value with the fourth calculation logic; wherein the third calculation logic and the fourth calculation logic are parallel calculation logics.

[0088] For the third intermediate operation result mc1 and the fourth intermediate operation result mc2, it is necessary to determine the relative sizes of the exponents of the two (that is, the exponent parts corresponding to the two) in order to accurately perform subsequent calculations. Therefore, it is necessary to determine the smaller value msmall with a smaller exponent and the larger value mbig with a larger exponent in the third intermediate operation result mc1 and the fourth intermediate operation result mc2.

[0089] It should be noted that the smaller value msmall is the value with the smaller exponent among the third intermediate operation result mc1 and the fourth intermediate operation result mc2, rather than the smaller value among the two. Figure 5 , mc1 and mc2 can be input into the comparison module Switch to determine msmall and mbig. Further, the smaller value of the third intermediate operation result mc1 and the fourth intermediate operation result mc2 can be selected according to the sign bit delta2.sign of the first exponent difference output by the first exponent difference calculation module EXP2. Among them, the sign bit delta2.sign of the first exponent difference is the sign bit of the first exponent difference delta2, which indicates the relationship between the exponents of mc1 and mc2. When delta2.sign is a positive value, it means that the exponent of mc1 is greater than the exponent of mc2, so mc2 is used as the smaller value msmall and mc1 is used as the larger value mbig; when delta2.sign is a negative value, it means that the exponent of mc1 is less than the exponent of mc2, so mc1 is used as the smaller value msmall and mc2 is used as the larger value mbig; when delta2.sign is zero, it means that the exponents of mc1 and mc2 are the same, so either of them can be selected as the smaller value msmall and the other as the larger value mbig.

[0090] After the smaller value and the larger value are determined, a first intermediate operation result is determined according to the smaller value and the larger value using a third calculation logic.

[0091] Figure 7is a schematic diagram of the third calculation logic of the instruction execution method provided in the embodiment of the present application. Figure 7 , the third calculation logic can be set in the third calculation module, that is, the logic module that executes the third calculation logic in the processor can be regarded as the third calculation module. In some embodiments, the third calculation module may include a third adder, a second leading zero prediction unit, and a second normalization unit. As an optional implementation, the determination of the first intermediate operation result according to the smaller value and the larger value with the third calculation logic may include: performing addition processing on the smaller value and the larger value to obtain a third addition result; performing leading zero prediction processing on the third addition result to obtain a second prediction result; performing normalization shift processing on the third addition result according to the second prediction result to obtain a second normalization result as the first intermediate operation result.

[0092] Since the orders of the third intermediate operation result mc1 and the fourth intermediate operation result mc2 are relatively close when calculating the first intermediate operation result mnear, the calculation operation can be performed directly without shift operation. Therefore, in the third calculation logic, the smaller value msmall and the larger value mbig can be directly added. Specifically, refer to Figure 5 , msmall and mbig are input into the third adder Adder3, and the output result is the third addition result.

[0093] After obtaining the third addition result, a leading zero prediction process is performed on the third addition result to obtain a second prediction result. Figure 5 The second leading zero prediction unit LZA2 can perform leading zero prediction processing on the third addition result of the third adder Adder3 to obtain a second prediction result.

[0094] After obtaining the second prediction result, the embodiment of the present application can perform normalized shift processing on the third addition result according to the second prediction result to obtain a second normalized result as the first intermediate operation result mnear. Figure 5 , the second prediction result of the second leading zero prediction unit LZA2 and the third addition result of the third adder Adder3 can be input into the second normalization unit Norm2, and the result obtained by the second normalization unit Norm2 is the first intermediate operation result mnear. The second normalization unit Norm2 is used to perform normalization shift processing on the third addition result according to the second prediction result lza2. The first intermediate operation result calculated by the third calculation logic is a floating point calculation result when the actual values ​​of the third intermediate operation result mc1 and the fourth intermediate operation result mc2 are relatively close.

[0095] As an optional implementation, after determining the smaller value and the larger value of the third intermediate operation result and the fourth intermediate operation result, the embodiment of the present application can also determine the second intermediate operation result according to the smaller value and the larger value using the fourth calculation logic. The third calculation logic and the fourth calculation logic are parallel calculation logics.

[0096] Figure 8 Schematic diagram of the fourth calculation logic of the instruction execution method provided in the embodiment of the present application. Figure 8 , the fourth calculation logic may be set in the fourth calculation module, that is, the logic module executing the fourth calculation logic in the processor may be regarded as the fourth calculation module. In some embodiments, the fourth calculation module may include a shift unit and a fourth adder. As an optional implementation, the second intermediate operation result may be determined according to the smaller value and the larger value by the fourth calculation logic: determining the first exponent difference according to the first exponent result, the exponent of the third source operand and the exponent of the fifth source operand; wherein the first exponent result is determined at least according to the first source operand, the second source operand and the fourth source operand; using the absolute value of the first exponent difference, performing a shift process on the minimum value to obtain a shift result; performing an addition process on the larger value and the shift result to obtain a fourth addition result as the second intermediate operation result. Further, the first exponent difference may be determined by the first exponent difference calculation module in the processor, for example, the first exponent difference calculation module may determine the first exponent difference according to the first exponent result, the exponent of the third source operand and the exponent of the fifth source operand.

[0097] Since the exponent difference between the third intermediate operation result and the fourth intermediate operation result is large when calculating the second intermediate operation result mfar, it is necessary to consider the shift and possible precision loss, so a large shift operation is required to align the third intermediate operation result and the fourth intermediate operation result. Therefore, according to the first exponent result ec1, the exponent ea1 of the third source operand and the exponent eb1 of the fifth source operand, the first exponent difference delta2 is determined; wherein the first exponent result ec1 is determined at least according to the first source operand, the second source operand and the fourth source operand. Specifically, ec1, ea1 and eb1 are input into the first exponent difference calculation module EXP2, and the result obtained is the first exponent difference delta2, delta2=ec1-(ea1+eb1), wherein the first exponent result ec1 is the exponent part corresponding to the third intermediate operation result mc1, ec1=max(ec,ea0+eb0+26-bias)-lza1. The first exponent difference delta2 not only indicates the relationship between the exponent sizes of mc1 and mc2, but is also used for the subsequent order shift processing of the smaller value msmall.

[0098] After obtaining the first exponent difference delta2, it is necessary to use the absolute value of the first exponent difference delta2 to perform a rank shift process on the smaller value msmall to obtain a rank shift result. Figure 5 , the smaller value msmall and the first exponent difference delta2 are input to the order shift unit Align2, and the order shift unit Align2 performs a shift operation on msmall according to delta2, so that the smaller value msmall is aligned with the order code of the larger value mbig, which is convenient for subsequent calculations. The result output by the order shift unit Align2 is the order shift result.

[0099] After obtaining the order shift result, in the fourth adder, the larger value mbig and the order shift result are added to obtain a fourth addition result mfar as the second intermediate operation result. Figure 5 , the larger value mbig and the shift result are input into the fourth adder Adder4, and the obtained result is the fourth addition result mfar.

[0100] Taking into account the shift and possible precision loss of the third intermediate operation result mc1 and the fourth intermediate operation result mc2, the second intermediate operation result calculated by the fourth calculation logic is the corresponding floating-point calculation result under the above considerations.

[0101] In some implementations, selecting the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result according to the exponent and the sign bit of the source operand may include:

[0102] Selecting the mantissa mres of the target operand according to the sign bit corresponding to the third intermediate operation result mc1, the sign bit corresponding to the fourth intermediate operation result mc2, and the first exponent difference delta2;

[0103] When the sign bit corresponding to the third intermediate operation result mc1 is different from the sign bit corresponding to the fourth intermediate operation result mc2, and the absolute value of the first exponent difference delta2 is less than or equal to 1, the first intermediate operation result mnear is selected as the mantissa mres of the target operand;

[0104] When the sign bit corresponding to the third intermediate operation result mc1 is different from the sign bit corresponding to the fourth intermediate operation result mc2, and the absolute value of the first exponent difference delta2 is greater than 1, or the sign bit corresponding to the third intermediate operation result mc1 is the same as the sign bit corresponding to the fourth intermediate operation result mc2, the second intermediate operation result mfar is selected as the mantissa mres of the target operand.

[0105] In the above process, the mantissa mres of the target operand is selected by using a mantissa selection module. Specifically, the mantissa selection module can be Figure 5 The mantissa selector Mux shown in the figure selects the mantissa mres of the target operand according to the sign bit corresponding to the third intermediate operation result mc1, the sign bit corresponding to the fourth intermediate operation result mc2, and the first exponent difference delta2. For example, when the sign bit corresponding to the third intermediate operation result mc1 is 1, the sign bit corresponding to the fourth intermediate operation result mc2 is 0, and delta2 is 1, the first intermediate operation result mnear is used as the mantissa mres of the target operand; when the sign bit corresponding to the third intermediate operation result mc1 and the sign bit corresponding to the fourth intermediate operation result mc2 are both 1, the second intermediate operation result mfar is used as the mantissa mres of the target operand.

[0106] It should also be noted that after determining the mantissa mres of the target operand, the exponent eres of the target operand can be obtained according to the following formula:

[0107] eres=max(ec1,ea1+eb1-bias)–lza2.

[0108] Wherein, lza2 is the second prediction result output by the second leading zero prediction unit LZA2.

[0109] Finally, the destination operand is obtained by combining the mantissa mres of the destination operand, the exponent eres of the destination operand, and the sign bit of the destination operand.

[0110] The solution provided by the embodiment of the present application can effectively reduce the calculation delay of the first bit width dot product calculation instruction, and improve the execution efficiency and accuracy of the floating point dot product calculation instruction. At the same time, through the precise processing of different source operands, the efficient execution of floating point calculation is achieved, which helps to provide a reliable data foundation in complex computing tasks.

[0111] In order to further reduce the execution time of the dot product calculation instructions and improve the execution efficiency of the dot product calculation instructions, in some embodiments, the embodiments of the present application can divide the process of determining the mantissa of the target operand into a multi-stage pipeline, and the multi-stage pipeline is obtained based on the clock cycle and the instruction execution time. For example, the multi-stage pipeline corresponding to the mantissa of the target operand is determined based on the clock cycle and the instruction execution time.

[0112] When executing a calculation instruction, dividing the instruction execution process into multiple pipelines has many advantages, such as improving throughput, optimizing utilization, reducing latency, etc. Therefore, based on the hardware clock cycle of the dot product calculation instruction and the instruction execution time, the process of determining the mantissa of the target operand can be divided into multiple pipelines for execution. For example, in some specific implementations, the hardware clock cycle of the dot product calculation instruction is 10ps, and the instruction execution time is 38ps, then the process of determining the mantissa of the target operand can be divided into 4 pipelines, and the execution time of each pipeline is 10ps; in other specific implementations, the hardware clock cycle of the dot product calculation instruction is 9ps, and the instruction execution time is 44ps, then the process of determining the mantissa of the target operand can be divided into 5 pipelines, and the execution time of each pipeline is 9ps.

[0113] Combination Figure 5 The pipeline division schematic diagram shown, in some embodiments, the multi-stage pipeline includes a first-stage pipeline, a second-stage pipeline, a third-stage pipeline, and a fourth-stage pipeline;

[0114] Wherein, the first stage pipeline is used for data preprocessing logic, multiplication compression processing of the mantissa of the fourth source operand and the mantissa of the fifth source operand;

[0115] The second stage pipeline is used for the first normalization processing logic, and the addition processing of the third processing result and the third carry result;

[0116] The third stage pipeline is used for rounding processing logic, determination of the third addition result, determination of the second prediction result, and determination of the order shift result;

[0117] The fourth stage pipeline is used to perform normalization shift processing on the third addition result according to the second prediction result, perform addition processing on the larger value and the order shift result, and select the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result.

[0118] like Figure 5 As shown, the first-stage pipeline is used for data preprocessing logic, multiplication compression processing of the mantissa ma1 of the third source operand and the mantissa mb1 of the fifth source operand. Specifically, the input of the first-stage pipeline is: the mantissas mc, ma0, ma1, mb0, mb1 of the first to fifth source operands, the exponent ec of the first source operand, the exponent ea0 of the second source operand and the exponent eb0 of the fourth source operand; after being processed by the first-stage pipeline, the output of the first-stage pipeline is the intermediate results sum1 and car1 to be normalized, the third processing result sum2 and the third carry result car3.

[0119] The second-stage pipeline is used for the first normalization processing logic and the addition processing of the third processing result sum2 and the third carry result car2. Specifically, the input of the second-stage pipeline is the output result of the first-stage pipeline, including the intermediate results sum1 and car1 to be normalized and the third processing result sum2 and the third carry result car3; after the processing of the second-stage pipeline, the output of the second-stage pipeline is the first normalization result and the fourth intermediate operation result mc2.

[0120] The third-stage pipeline is used for rounding processing logic, determination of the third addition result, determination of the second prediction result, and determination of the order shift result. Specifically, the input of the third-stage pipeline is the output result of the second-stage pipeline, including the first normalization result and the fourth intermediate operation result mc2; after being processed by the third-stage pipeline, the output of the third-stage pipeline is the second prediction result, the third addition result, the larger value mbig, and the order shift result.

[0121] The fourth-stage pipeline is used to perform normalized shift processing on the third addition result according to the second prediction result, perform addition processing on the larger value mbig and the order shift result, and select the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result. Specifically, the input of the fourth-stage pipeline is the output result of the third-stage pipeline; after being processed by the fourth-stage pipeline, the output of the fourth-stage pipeline is the mantissa mres of the target operand.

[0122] As an optional implementation, the embodiment of the present application divides the pipeline into four levels, and the mantissa of the target operand of the dot product calculation instruction is determined by executing the four-level pipeline, and there is no data dependency between two adjacent pipeline levels except for the input and output of the pipeline stage, and there is no data dependency between each two non-adjacent pipeline levels. Therefore, the dot product calculation instruction can be executed according to the pipeline, thereby improving the efficiency of the instruction execution method.

[0123] Fig. 9 is a schematic diagram of a processor provided in an embodiment of the present application. Fig. 9 As shown, the processor 1 provided in the embodiment of the present application includes:

[0124] An instruction fetch unit 10, used to fetch a dot product calculation instruction;

[0125] A decoding unit 11 is used to decode the dot product calculation instruction to obtain multiple source operands; the multiple source operands include at least a floating point number of the first bit width, and the mantissa bit width of the floating point number of the first bit width is smaller than the exponent bit width;

[0126] An execution unit 12, the execution unit comprising a floating point multiplier and adder;

[0127] The floating point multiplier and adder is used for:

[0128] A first intermediate operation result and a second intermediate operation result are determined according to the multiple source operands; a mantissa of a target operand is selected from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operands; wherein the target operand is obtained by combining the sign bit, the exponent and the mantissa of the target operand.

[0129] In some embodiments, Fig.10 As shown, the floating point multiplier 2 may include:

[0130] A front parallel processing module 20, configured to obtain a third intermediate operation result and a fourth intermediate operation result by parallel calculation according to the plurality of source operands;

[0131] A post-parallel processing module 21, configured to obtain a first intermediate operation result and a second intermediate operation result by parallel calculation according to the third intermediate operation result and the fourth intermediate operation result;

[0132] The mantissa selection module 22 is used to select the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result based on at least the exponent determined by the source operand.

[0133] As an optional implementation, the following combination Figures 4 to 8 As shown, Fig.10 The logical structure of the floating-point multiplier and adder shown is explained.

[0134] In some implementations, the plurality of source operands include: a first source operand, a second source operand, a third source operand, a fourth source operand, and a fifth source operand. The front parallel processing module 20 includes:

[0135] A first calculation module, configured to determine a third intermediate operation result according to the first source operand, the second source operand and the fourth source operand using a first calculation logic;

[0136] The second computing module is used to determine a fourth intermediate operation result according to the third source operand and the fifth source operand using a second computing logic; wherein the first computing module and the second computing module are parallel computing modules.

[0137] In some implementations, the first calculation logic includes: data preprocessing logic, first normalization processing logic, and rounding processing logic. The first calculation module includes:

[0138] A data preprocessing module, used for performing processing according to the first source operand, the second source operand and the fourth source operand using a data preprocessing logic to obtain an intermediate result to be normalized;

[0139] A first normalization processing module, used for processing the intermediate result to be normalized using a first normalization processing logic to obtain a first normalized result;

[0140] The rounding processing module is used to process the first normalized result with a rounding processing logic to obtain a third intermediate operation result.

[0141] In some embodiments, the data preprocessing module includes:

[0142] a first exponential logic circuit EXP1, for generating a shift control signal according to an exponent of a first source operand, an exponent of a second source operand, and an exponent of a fourth source operand;

[0143] A first alignment unit Align1, configured to perform a shift operation on the mantissa of the first source operand according to the shift control signal to obtain a first shift result;

[0144] A first multiplication compression module Mult1, configured to perform multiplication compression processing on the mantissa of the second source operand and the mantissa of the fourth source operand to obtain a first processing result and a first carry result;

[0145] The carry-save addition unit CSA is used to perform carry-save addition processing on the first shift result, the first processing result and the first carry result to obtain a second processing result and a second carry result as intermediate results to be normalized.

[0146] In some embodiments, the first normalization processing module includes:

[0147] A first adder Adder1, used for performing addition processing on the second processing result and the second carry result to obtain a first addition result;

[0148] A first leading zero prediction unit LZA1, configured to perform a leading zero prediction process on the first addition result to obtain a first prediction result;

[0149] The first normalization unit Norm1 is used to perform normalization shift processing on the first addition result according to the first prediction result to obtain a first normalized result.

[0150] In some embodiments, the second computing module includes:

[0151] A second multiplication compression unit Mult2 is used to perform multiplication compression processing on the mantissa of the third source operand and the mantissa of the fifth source operand to obtain a third processing result and a third carry result;

[0152] The second adder Adder2 is used to perform addition processing on the third processing result and the third carry result to obtain a second addition result as a fourth intermediate operation result.

[0153] In some implementations, the post-parallel processing module 21 includes:

[0154] A comparison module Switch, used to determine a smaller value and a larger value of the third intermediate operation result and the fourth intermediate operation result;

[0155] A third calculation module, used for determining the first intermediate operation result according to the smaller value and the larger value by using a third calculation logic;

[0156] The fourth calculation module is used to determine the second intermediate operation result according to the smaller value and the larger value using a fourth calculation logic; wherein the third calculation logic and the fourth calculation logic are parallel calculation logics.

[0157] In some embodiments, the third computing module includes:

[0158] A third adder Adder3 is used to perform addition processing on the smaller value and the larger value to obtain a third addition result;

[0159] A second leading zero prediction unit LZA2, configured to perform a leading zero prediction process on the third addition result to obtain a second prediction result;

[0160] The second normalization unit Norm2 is used to perform normalization shift processing on the third addition result according to the second prediction result to obtain a second normalization result as the first intermediate operation result.

[0161] In some embodiments, the processor further comprises:

[0162] The first exponent difference calculation module EXP2 is used to determine a first exponent difference according to the first exponent result, the exponent of the third source operand and the exponent of the fifth source operand; wherein the first exponent result is determined at least according to the first source operand, the second source operand and the fourth source operand.

[0163] In some embodiments, the fourth calculation module includes:

[0164] An alignment shift unit Align2, configured to perform an alignment shift process on the minimum value by using the absolute value of the first exponential difference to obtain an alignment shift result;

[0165] The fourth adder Adder4 is used to perform addition processing on the larger value and the order-shifted result to obtain a fourth addition result as the second intermediate operation result.

[0166] In some embodiments, the mantissa selection module 22 may be configured to select a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operand.

[0167] Optionally, the mantissa selection module 22 may select the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result according to the corresponding sign bit of the third intermediate operation result, the corresponding sign bit of the fourth intermediate operation result, and the first exponent difference;

[0168] When the sign bit corresponding to the third intermediate operation result is different from the sign bit corresponding to the fourth intermediate operation result, and the absolute value of the first exponent difference is less than or equal to 1, the first intermediate operation result is used as the mantissa of the target operand;

[0169] When the sign bit corresponding to the third intermediate operation result is different from the sign bit corresponding to the fourth intermediate operation result, and the absolute value of the first exponent difference is greater than 1, or when the sign bit corresponding to the third intermediate operation result is the same as the sign bit corresponding to the fourth intermediate operation result, the second intermediate operation result is used as the mantissa of the target operand.

[0170] In some implementations, the floating-point multiplier and adder has a multi-stage pipeline, and the floating-point multiplier and adder determines the mantissa of the target operand through the multi-stage pipeline; wherein the multi-stage pipeline is obtained based on clock cycles and instruction execution time.

[0171] In some embodiments, in combination Figure 5 As shown, the multi-stage pipeline includes a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline;

[0172] Wherein, the first-stage pipeline is provided with the above-mentioned data preprocessing module and the second multiplication compression unit Mult2;

[0173] The second stage pipeline is provided with the first normalization processing module and the second adder Adder2 mentioned above;

[0174] The third-stage pipeline is provided with a rounding processing module Round1, a comparison module Switch, a third adder Adder3, a second leading zero prediction unit LZA2, a first exponent difference calculation module EXP2 and an alignment shift unit Align2;

[0175] The fourth-stage pipeline is provided with a second normalization unit Norm2 , a fourth adder Adder4 , and a mantissa selection module 22 .

[0176] In a further optional implementation, the present application also provides a chip, which includes the processor described in any one of the aforementioned embodiments.

[0177] In a further optional implementation, the present application also provides an electronic device, such as a terminal device or a server device, which includes the chip described in the aforementioned embodiment.

[0178] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0179] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for executing an instruction, characterized in that: include: Get the dot product calculation instruction; Decoding the dot product calculation instruction to obtain a plurality of source operands; the plurality of source operands at least include a floating point number of a first bit width, wherein a mantissa bit width of the floating point number of the first bit width is smaller than an exponent bit width; determining a first intermediate operation result and a second intermediate operation result according to the plurality of source operands; Selecting a mantissa of a destination operand from the first intermediate operation result and the second intermediate operation result based at least on an exponent determined by the source operand; And, the sign bit, exponent, and mantissa of the destination operand are combined to obtain the destination operand.

2. The instruction execution method according to claim 1, characterized in that: Determining the first intermediate operation result and the second intermediate operation result according to the plurality of source operands comprises: According to the multiple source operands, parallel calculation is performed to obtain a third intermediate operation result and a fourth intermediate operation result; According to the third intermediate operation result and the fourth intermediate operation result, a first intermediate operation result and a second intermediate operation result are obtained by parallel calculation.

3. The instruction execution method according to claim 2, characterized in that: The multiple source operands include: a first source operand, a second source operand, a third source operand, a fourth source operand, and a fifth source operand; and the parallel calculation to obtain the third intermediate operation result and the fourth intermediate operation result according to the multiple source operands includes: Determine a third intermediate operation result according to the first source operand, the second source operand and the fourth source operand using the first calculation logic; And, according to the third source operand and the fifth source operand, a fourth intermediate operation result is determined by the second calculation logic; wherein the first calculation logic and the second calculation logic are parallel calculation logics.

4. The instruction execution method according to claim 3, characterized in that: The first calculation logic includes: data preprocessing logic, first normalization processing logic, and rounding processing logic; Determining the third intermediate operation result according to the first source operand, the second source operand and the fourth source operand using the first calculation logic includes: Processing the first source operand, the second source operand, and the fourth source operand using a data preprocessing logic to obtain an intermediate result to be normalized; According to the intermediate result to be normalized, processing is performed using a first normalization processing logic to obtain a first normalized result; According to the first normalized result, a rounding processing logic is used to process to obtain a third intermediate operation result.

5. The instruction execution method according to claim 4, characterized in that: The processing according to the first source operand, the second source operand and the fourth source operand using data preprocessing logic to obtain an intermediate result to be normalized includes: generating a shift control signal according to an exponent of the first source operand, an exponent of the second source operand, and an exponent of the fourth source operand; According to the shift control signal, a shift operation is performed on the mantissa of the first source operand to obtain a first shift result; Performing multiplication compression processing on the mantissa of the second source operand and the mantissa of the fourth source operand to obtain a first processing result and a first carry result; Carry-save addition processing is performed on the first shift result, the first processing result and the first carry result to obtain a second processing result and a second carry result as intermediate results to be normalized.

6. The instruction execution method according to claim 5, characterized in that: The step of processing the intermediate result to be normalized by using the first normalization processing logic to obtain the first normalized result includes: Performing addition processing on the second processing result and the second carry result to obtain a first addition result; Performing leading zero prediction processing on the first addition result to obtain a first prediction result; Performing normalization shift processing on the first addition result according to the first prediction result to obtain a first normalized result; The processing according to the first normalization result using rounding processing logic to obtain a third intermediate operation result includes: A rounding operation is performed on the first normalized result to obtain a first rounding result as a third intermediate operation result.

7. The instruction execution method according to claim 4, characterized in that: Determining the fourth intermediate operation result according to the third source operand and the fifth source operand using the second calculation logic includes: Perform multiplication compression processing on the mantissa of the third source operand and the mantissa of the fifth source operand to obtain a third processing result and a third carry result; An addition process is performed on the third processing result and the third carry result to obtain a second addition result as a fourth intermediate operation result.

8. The instruction execution method according to claim 7, characterized in that: The obtaining the first intermediate operation result and the second intermediate operation result by parallel calculation according to the third intermediate operation result and the fourth intermediate operation result comprises: Determine a smaller value and a larger value of the third intermediate operation result and the fourth intermediate operation result; Determine a first intermediate operation result according to the smaller value and the larger value using a third calculation logic; According to the smaller value and the larger value, the second intermediate operation result is determined by the fourth calculation logic; wherein the third calculation logic and the fourth calculation logic are parallel calculation logics.

9. The instruction execution method according to claim 8, characterized in that: Determining the first intermediate operation result according to the smaller value and the larger value by using the third calculation logic includes: performing an addition process on the smaller value and the larger value to obtain a third addition result; Performing leading zero prediction processing on the third addition result to obtain a second prediction result; The third addition result is subjected to normalization shift processing according to the second prediction result to obtain a second normalized result as the first intermediate operation result.

10. The instruction execution method according to claim 9, characterized in that: Determining the second intermediate operation result according to the smaller value and the larger value with the fourth calculation logic includes: determining a first exponent difference based on a first exponent result, an exponent of a third source operand, and an exponent of a fifth source operand; wherein the first exponent result is determined based on at least the first source operand, the second source operand, and the fourth source operand; Using the absolute value of the first exponential difference, performing a rank shift process on the smaller value to obtain a rank shift result; An addition process is performed on the larger value and the order-shifted result to obtain a fourth addition result as a second intermediate operation result.

11. The instruction execution method according to claim 10, characterized in that: The selecting the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operand comprises: Selecting a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result according to a sign bit corresponding to the third intermediate operation result, a sign bit corresponding to the fourth intermediate operation result, and a first exponent difference; When the sign bit corresponding to the third intermediate operation result is different from the sign bit corresponding to the fourth intermediate operation result, and the absolute value of the first exponent difference is less than or equal to 1, the first intermediate operation result is selected as the mantissa of the target operand; When the sign bit corresponding to the third intermediate operation result is different from the sign bit corresponding to the fourth intermediate operation result, and the absolute value of the first exponent difference is greater than 1, or when the sign bit corresponding to the third intermediate operation result is the same as the sign bit corresponding to the fourth intermediate operation result, the second intermediate operation result is selected as the mantissa of the target operand.

12. The instruction execution method according to claim 11, characterized in that: The mantissa of the target operand is determined by a multi-stage pipeline, wherein the multi-stage pipeline is divided based on a clock cycle and an instruction execution time.

13. The instruction execution method according to claim 12, characterized in that: The multi-stage pipeline includes a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline; Wherein, the first stage pipeline is used for data preprocessing logic and multiplication compression processing of the mantissa of the third source operand and the mantissa of the fifth source operand; The second stage pipeline is used for the first normalization processing logic and the addition processing of the third processing result and the third carry result; The third stage pipeline is used for rounding processing logic, obtaining a third addition result, obtaining a second prediction result, and obtaining a shift result; The fourth stage pipeline is used to perform normalization shift processing on the third addition result according to the second prediction result, perform addition processing on the larger value and the order shift result, and select the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result.

14. The instruction execution method according to claim 3, characterized in that: The second source operand, the third source operand, the fourth source operand, and the fifth source operand are floating-point numbers of the first bit width, and the first source operand is a floating-point number of the first bit width or a floating-point number of the second bit width, wherein the mantissa bit width of the floating-point number of the second bit width is greater than the exponent bit width.

15. A processor, characterized in that: include: Instruction fetch unit, used to fetch dot product calculation instructions; A decoding unit, configured to decode the dot product calculation instruction to obtain a plurality of source operands; the plurality of source operands at least include a floating point number of a first bit width, wherein a mantissa bit width of the floating point number of the first bit width is smaller than an exponent bit width; An execution unit, the execution unit comprising a floating point multiplier and adder; The floating point multiplier and adder is used for: A first intermediate operation result and a second intermediate operation result are determined according to the multiple source operands; a mantissa of a target operand is selected from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operands; wherein the target operand is obtained by combining the sign bit, the exponent and the mantissa of the target operand.

16. The processor according to claim 15, characterized in that The floating point multiplier and adder comprises: A front parallel processing module, used for obtaining a third intermediate operation result and a fourth intermediate operation result by parallel calculation according to the plurality of source operands; A post-parallel processing module, configured to obtain a first intermediate operation result and a second intermediate operation result by parallel calculation according to the third intermediate operation result and the fourth intermediate operation result; The mantissa selection module is used to select the mantissa of the target operand from the first intermediate operation result and the second intermediate operation result based on at least the exponent determined by the source operand.

17. The processor according to claim 16, characterized in that The plurality of source operands include: a first source operand, a second source operand, a third source operand, a fourth source operand and a fifth source operand; the front parallel processing module includes: A first calculation module, configured to determine a third intermediate operation result according to the first source operand, the second source operand and the fourth source operand using a first calculation logic; A second calculation module, configured to determine a fourth intermediate operation result according to the third source operand and the fifth source operand using a second calculation logic; Among them, the first computing module and the second computing module are parallel computing modules.

18. The processor according to claim 17, characterized in that The first calculation logic includes: data preprocessing logic, first normalization processing logic, and rounding processing logic; the first calculation module includes: A data preprocessing module, used for performing processing according to the first source operand, the second source operand and the fourth source operand using a data preprocessing logic to obtain an intermediate result to be normalized; A first normalization processing module, used for processing the intermediate result to be normalized using a first normalization processing logic to obtain a first normalized result; The rounding processing module is used to process the first normalized result with a rounding processing logic to obtain a third intermediate operation result.

19. The processor according to claim 18, characterized in that The data preprocessing module comprises: a first exponential logic circuit for generating a shift control signal according to an exponent of the first source operand, an exponent of the second source operand, and an exponent of the fourth source operand; A first alignment unit, configured to perform a shift operation on the mantissa of the first source operand according to the shift control signal to obtain a first shift result; a first multiplication compression unit, configured to perform multiplication compression processing on the mantissa of the second source operand and the mantissa of the fourth source operand to obtain a first processing result and a first carry result; The carry-save addition unit is used to perform carry-save addition processing on the first shift result, the first processing result and the first carry result to obtain a second processing result and a second carry result as intermediate results to be normalized.

20. The processor according to claim 19, characterized in that The first normalization processing module includes: A first adder, configured to perform addition processing on the second processing result and the second carry result to obtain a first addition result; A first leading zero prediction unit, configured to perform a leading zero prediction process on the first addition result to obtain a first prediction result; The first normalization unit is used to perform normalization shift processing on the first addition result according to the first prediction result to obtain a first normalized result.

21. The processor according to claim 18, wherein: The second calculation module includes: A second multiplication compression unit is used to perform multiplication compression processing on the mantissa of the third source operand and the mantissa of the fifth source operand to obtain a third processing result and a third carry result; The second adder is used to perform addition processing on the third processing result and the third carry result to obtain a second addition result as a fourth intermediate operation result.

22. The processor according to claim 21, characterized in that The post-parallel processing module comprises: A comparison module, used to determine a smaller value and a larger value of the third intermediate operation result and the fourth intermediate operation result; A third calculation module, used for determining the first intermediate operation result according to the smaller value and the larger value by using a third calculation logic; A fourth calculation module, used for determining a second intermediate operation result according to the smaller value and the larger value using a fourth calculation logic; The third calculation logic and the fourth calculation logic are parallel calculation logics.

23. The processor according to claim 22, characterized in that The third calculation module includes: A third adder, configured to perform an addition process on the smaller value and the larger value to obtain a third addition result; A second leading zero prediction unit, configured to perform a leading zero prediction process on the third addition result to obtain a second prediction result; The second normalization unit is used to perform normalization shift processing on the third addition result according to the second prediction result to obtain a second normalization result as the first intermediate operation result.

24. The processor according to claim 23, characterized in that Also includes: a first exponent difference calculation module, configured to determine a first exponent difference according to a first exponent result, an exponent of a third source operand, and an exponent of a fifth source operand; wherein the first exponent result is determined at least according to the first source operand, the second source operand, and the fourth source operand; The fourth calculation module includes: A step shift unit, used to perform a step shift process on a smaller value by using the absolute value of the first exponential difference to obtain a step shift result; The fourth adder is used to perform addition processing on the larger value and the order-shifted result to obtain a fourth addition result as the second intermediate operation result.

25. The processor according to claim 24, characterized in that The mantissa selection module, configured to select a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result based at least on the exponent determined by the source operand, comprises: Selecting a mantissa of a target operand from the first intermediate operation result and the second intermediate operation result according to a sign bit corresponding to the third intermediate operation result, a sign bit corresponding to the fourth intermediate operation result, and a first exponent difference; When the sign bit corresponding to the third intermediate operation result is different from the sign bit corresponding to the fourth intermediate operation result, and the absolute value of the first exponent difference is less than or equal to 1, the first intermediate operation result is selected as the mantissa of the target operand; When the sign bit corresponding to the third intermediate operation result is different from the sign bit corresponding to the fourth intermediate operation result, and the absolute value of the first exponent difference is greater than 1, or when the sign bit corresponding to the third intermediate operation result is the same as the sign bit corresponding to the fourth intermediate operation result, the second intermediate operation result is selected as the mantissa of the target operand.

26. The processor according to claim 25, characterized in that The floating-point multiplier and adder has a multi-stage pipeline, and the floating-point multiplier and adder determines the mantissa of the target operand through the multi-stage pipeline; wherein the multi-stage pipeline is obtained based on the division of clock cycle and instruction execution time.

27. The processor according to claim 26, characterized in that The multi-stage pipeline includes a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline; Wherein, the first-stage pipeline is provided with a data preprocessing module and a second multiplication compression unit; The second-stage pipeline is provided with a first normalization processing module and a second adder; The third-stage pipeline is provided with a rounding processing module, a comparison module, a third adder, a second leading zero prediction unit, a first exponent difference calculation module and an order shift unit; The fourth-stage pipeline is provided with a second normalization unit, a fourth adder and a mantissa selection module.

28. The processor according to claim 17, wherein: The second source operand, the third source operand, the fourth source operand, and the fifth source operand are floating-point numbers of the first bit width, the first source operand is a floating-point number of the first bit width or a floating-point number of the second bit width, and the mantissa bit width of the floating-point number of the second bit width is greater than the exponent bit width.

29. A chip, characterized in that: Comprising a processor as claimed in any one of claims 15-28.

30. An electronic device, characterized in that: Comprising the chip as claimed in claim 29.

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