Hardware acceleration device, method and system and storage medium

Abstract

The invention discloses a hardware acceleration device, method and system and a storage medium, and particularly relates to an FFT (Fast Fourier Transform) and IFFT (Inverse Fast Fourier Transform) hardware acceleration device, method and system for any recursive call of ultra-low delay and a storage medium. The device comprises one or more of an initial module, a read pointer circulation module, a first mirror image address conversion module, an FFT module, a second mirror image address conversion module and an IFFT module, an FFT recursion body module in the FFT module executes butterfly-shaped sleeve doll operation capable of being circulated at any time, data of a time domain signal to be processed is converted into a frequency domain signal with a continuously-replaced period, and the frequency domain signal is converted into a frequency domain signal with a continuously-replaced period. And an IFFT recursion body module in the IFFT module executes butterfly-shaped doll operation which can be circulated for any time, and data of the frequency domain signal to be processed is restored into an original time domain signal. According to the invention, the FFT module and the IFFT module can be described by the same set of codes, and the number of points which are multiples of any 2 can be customized randomly by modifying parameters and changing the number of instantiated nested levels, so that the reusability and flexibility of operators are improved, and the economic and time costs of version maintenance and management are reduced.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a hardware acceleration device, method, system and storage medium, specifically to an FFT and IFFT hardware acceleration device, method, system and storage medium for arbitrary recursive calls with ultra-low latency. Background Art

[0002] Fast Fourier transform (FFT) is a general term for efficient and fast calculation methods of discrete Fourier transform Q (DFT) using computers, referred to as FFT. Fast Fourier transform was proposed by JW Cooley and TW Tukey in 1965. The use of this algorithm can greatly reduce the number of multiplications required for computer calculation of discrete Fourier transform, especially the more the number of sample points N to be transformed, the more significant the savings in the calculation amount of FFT algorithm.

[0003] FFT has a wide range of applications in many fields, including but not limited to signal processing, communications, computer science, audio processing, image processing, machine learning, data encryption and security, etc. Although FFT hardware acceleration has significant advantages in many applications, there are still some disadvantages, including:

[0004] 1. High cost: FFT hardware acceleration usually requires specially designed and manufactured hardware circuits, resulting in high costs. This may not be practical for individual users or small-scale applications.

[0005] 2. Limited flexibility: Once the FFT hardware accelerator is designed and manufactured, its functions and performance are usually fixed, making it difficult to flexibly modify or upgrade it. This may not be suitable for applications that require frequently changing requirements.

[0006] 3. Physical space occupation: FFT hardware accelerators usually require a large physical space. For space-constrained devices or systems, such as embedded systems or mobile devices, it may be difficult to integrate such hardware accelerators.

[0007] 4. Dependence on specific hardware platforms: FFT hardware accelerators are usually designed for specific hardware platforms, and there may be compatibility issues between different platforms. This makes porting or cross-platform development on different platforms more difficult.

[0008] Therefore, FFT hardware accelerators have obvious advantages in certain scenarios, but they also have some limitations and disadvantages. When deciding whether to use FFT hardware acceleration, factors such as application requirements, cost, flexibility, and platform compatibility need to be considered. Summary of the invention

[0009] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a hardware acceleration device, method, system and storage medium, which can change parameter configuration according to the power consumption limit and performance requirements of computing resources, flexibly adjust computing complexity and resource utilization, achieve a balance between accuracy, power consumption and computing power, and push computing delay to the extreme.

[0010] A first aspect of the present disclosure provides a hardware acceleration device, the hardware acceleration device comprising one or more of the following modules:

[0011] The initial module is configured to cache the original time domain signal;

[0012] A read pointer cycle module is configured to generate an initial signal that continuously changes periodically based on the original time domain signal;

[0013] A first mirror address conversion module is configured to convert the initial signal that continuously changes periodically into a pointer timing adapted to the FFT module, so as to continuously provide the FFT module with data of the time domain signal to be processed;

[0014] An FFT module, comprising an FFT recursive body module, wherein the FFT module is configured to receive the data of the time domain signal to be processed in an optimal timing sequence, and convert the data of the time domain signal to be processed into a frequency domain signal that is periodically continuously alternating through the FFT recursive body module, and the FFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times;

[0015] a second mirror address conversion module, configured to receive the periodically continuously alternating frequency domain signal, and convert the periodically continuously alternating frequency domain signal into a pointer timing adapted to an IFFT module, so as to continuously provide the IFFT module with data of the frequency domain signal to be processed; and

[0016] The IFFT module includes an IFFT recursive body module, wherein the IFFT module is configured to receive the data of the frequency domain signal to be processed according to the optimal timing, and restore the data of the frequency domain signal to be processed to the original time domain signal through the IFFT recursive body module, and the IFFT recursive body module is configured to perform a butterfly nesting operation that can be repeated any number of times.

[0017] Optionally, the FFT module implements FFT operations with a number of points from 4 to positive infinity by recursively calling the FFT recursive body module any number of times, so as to convert the data of the time domain signal to be processed into a frequency domain signal that continuously changes periodically;

[0018] The IFFT module implements FFT operations with a number of points from 4 to positive infinity by making any number of recursive calls to the IFFT recursive body module, so as to restore the data of the frequency domain signal to be processed to the original time domain signal.

[0019] Optionally, the FFT recursive body module and the IFFT recursive body module each include a basic recursive unit module and an N-layer recursive body module, where N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module or the IFFT recursive body module.

[0020] The FFT recursive body module and the IFFT recursive body module each include a top-level recursive body module and a bottom-level recursive body module, the top-level recursive body module is a recursive body module that executes the Nth level recursive call, and the bottom-level recursive body module is the basic recursive unit module.

[0021] Optionally, the value of the maximum recursive call nesting level N is determined according to the following formula:

[0022]

[0023] Wherein, M is the number of operation points of FFT or IFFT.

[0024] Optionally, each layer of recursive body modules includes a butterfly pipeline gating timing module with the same sequence but an execution time that is twice the execution time of the recursive body module of the previous layer.

[0025] Optionally, the butterfly pipeline gating timing module includes at least one invisible state machine module, and the triggering condition and output pointer of the invisible state machine module are both controlled by the counter module. Multiple traits are hidden.

[0026] Optionally, the invisible state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the direction of the butterfly pipeline pointer in the four states is consistent, wherein 0 represents multiplication and accumulation of the left front wing of the butterfly, 1 represents multiplication and accumulation of the left rear wing of the butterfly, 2 represents multiplication and accumulation of the right front wing of the butterfly, and 3 represents multiplication and accumulation of the right rear wing of the butterfly.

[0027] Optionally, each layer of recursive body module has butterfly pointers in four directions, wherein the butterfly pointer in any direction contains two small pointers in the same direction in the previous layer of recursive body module; each time the recursive body module performs a pointer operation, the two small pointers in the same direction in the previous layer of recursive body module it contains perform two pointer operations successively at twice the rate.

[0028] Optionally, the state period of the recursive body module of the current layer is twice the state period of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is twice the data bit width of the recursive body module of the previous layer.

[0029] Optionally, the data pipeline with a data bit width of W in each layer of the recursive body module includes two data pipelines with a data bit width of W / 2.

[0030] A second aspect of the present disclosure provides a hardware acceleration method, the method comprising one or more of the following steps:

[0031] Cache the original time domain signal;

[0032] Generating an initial signal with a continuous alternation period based on the original time domain signal;

[0033] Converting the periodically continuously alternating initial signal into a pointer timing sequence adapted to FFT transformation to obtain data of a time domain signal to be processed;

[0034] Receiving the data of the time domain signal to be processed in an optimal time sequence, and converting the data of the time domain signal to be processed into a frequency domain signal that is periodically continuously alternating through an FFT recursive body module, wherein the FFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times;

[0035] Converting the periodically continuously alternating frequency domain signal into a pointer timing sequence adapted to IFFT transformation to obtain data of the frequency domain signal to be processed;

[0036] The data of the frequency domain signal to be processed is received in an optimal time sequence, and the data of the frequency domain signal to be processed is restored to an original time domain signal through an IFFT recursive body module, wherein the IFFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times.

[0037] Optionally, by recursively calling the FFT recursive body module any number of times, an FFT operation with a number of points from 4 to positive infinity is implemented to convert the data of the time domain signal to be processed into a frequency domain signal that continuously changes periodically;

[0038] By recursively calling the IFFT recursive body module any number of times, an FFT operation with a number of points from 4 to positive infinity is implemented to restore the data of the frequency domain signal to be processed to the original time domain signal.

[0039] Optionally, the FFT recursive body module and the IFFT recursive body module each include a basic recursive unit module and an N-layer recursive body module, where N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module or the IFFT recursive body module.

[0040] The FFT recursive body module and the IFFT recursive body module each include a top-level recursive body module and a bottom-level recursive body module, the top-level recursive body module is a recursive body module that executes the Nth level recursive call, and the bottom-level recursive body module is the basic recursive unit module.

[0041] Optionally, the value of the maximum recursive call nesting level N is determined according to the following formula:

[0042]

[0043] Wherein, M is the number of operation points of FFT or IFFT.

[0044] Optionally, each layer of recursive body modules includes a butterfly pipeline gating timing with the same sequence but an execution time that is twice the execution time of the previous layer of recursive body modules.

[0045] Optionally, the butterfly pipeline gating timing includes at least one invisible state machine, and the triggering condition and output pointer of the invisible state machine are both controlled by the counter. Multiple traits are hidden.

[0046] Optionally, the invisible state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the direction of the butterfly pipeline pointer in the four states is consistent, wherein 0 represents multiplication and accumulation of the left front wing of the butterfly, 1 represents multiplication and accumulation of the left rear wing of the butterfly, 3 represents multiplication and accumulation of the right front wing of the butterfly, and 4 represents multiplication and accumulation of the right rear wing of the butterfly.

[0047] Optionally, each layer of recursive body module has butterfly pointers in four directions, wherein the butterfly pointer in any direction contains two small pointers in the same direction in the previous layer of recursive body module; each time the recursive body module performs a pointer operation, the two small pointers in the same direction in the previous layer of recursive body module it contains perform two pointer operations successively at twice the rate.

[0048] Optionally, the state period of the recursive body module of the current layer is twice the state period of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is twice the data bit width of the recursive body module of the previous layer.

[0049] Optionally, the data pipeline with a data bit width of W in each layer of the recursive body module includes two data pipelines with a data bit width of W / 2.

[0050] A third aspect of the present disclosure provides a hardware acceleration system, which includes the hardware acceleration device of the first aspect.

[0051] A fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium, in which computer instructions are stored. The computer instructions are suitable for loading by a processor to implement the hardware acceleration method of the first aspect.

[0052] The implementation of the above scheme has the following beneficial effects:

[0053] In the present disclosure, the architecture of the FFT module is very similar to that of the IFFT module, and the two architectures can be described by the same set of codes. By modifying the define macro definition value, it is determined whether to play the role of FFT or IFFT when instantiated, thereby reducing the difficulty of code maintenance and management.

[0054] The FFT recursive body module is configured to perform a butterfly nesting operation that can be looped any number of times. By calling the FFT recursive body module, an FFT operation of any number of points can be realized. The IFFT recursive body module is configured to perform a butterfly nesting operation that can be looped any number of times. By calling the IFFT recursive body module, an FFT operation of any number of points can be realized. The number of points that is a multiple of 2 can be customized by modifying the parameters and changing the number of levels of instantiation nesting. The reusability and flexibility of the operator are improved, and the economic and time costs of version maintenance and management are reduced.

[0055] The invisible state machine module is used to achieve the same timing for each recursive layer, but the execution cycle is 2 n The incremental data flow state guidance ensures that recursive calls between different levels will not produce any operation gaps, let alone data packet loss, and pushes the operation delay to the extreme within limited resources. In addition, the "jump condition" of the invisible state machine module and the "task execution identification signal" of the current state are completely "hidden", thereby reducing the circuit area and power consumption.

[0056] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In addition, similar numbers in the figures are used to represent similar components, among which:

[0058] Figure 1 is a structural block diagram of the hardware acceleration device disclosed in the present invention;

[0059] Figure 2 This is a schematic diagram of a butterfly nesting doll;

[0060] Figure 3It is a schematic diagram of the areas corresponding to the four states of butterfly operation;

[0061] Figure 4 This is a diagram showing the mirror addressing of an 8-point FFT;

[0062] Figure 5 The diagram is a diagram of implementing 128-point FFT operation through 6 recursive calls in RTL code;

[0063] Figure 6 The timing diagram of a single stream of data being fed into a 16-point FFT (IFFT) operator;

[0064] Figure 7 The timing of feeding two streams of data into the 16-point FFT (IFFT) operator at the same time Figure 1 ;

[0065] Figure 8 The timing of feeding two streams of data into the 16-point FFT (IFFT) operator at the same time Figure 2 ;

[0066] Fig. 9 The timing of feeding two streams of data into the 16-point FFT (IFFT) operator at the same time Figure 3 ;

[0067] Fig.10 It is a flowchart of the hardware acceleration method disclosed in the present invention.

[0068] In the figure:

[0069] 110 initial module, 120 read pointer loop module, 130 first mirror address conversion module, 140 FFT module, 150 second mirror address conversion module, 160 IFFT module,

[0070] 0 left front wing, 1 left rear wing, 2 right front wing, 3 right rear wing. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0072] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0073] The present application embodiment provides a hardware acceleration device, specifically a FFT and IFFT hardware acceleration device for any number of recursive calls with ultra-low latency, see Figure 1 The hardware acceleration device includes one or more of the following modules: an initial module 110, a read pointer loop module 120, a first mirror address conversion module 130, an FFT module 140, a second mirror address conversion module 150, and an IFFT module 160. The initial module 110 is configured to cache the original time domain signal. The read pointer loop module 120 is configured to generate a periodically continuously alternating initial signal based on the original time domain signal. The first mirror address conversion module 130 is configured to convert the periodically continuously alternating initial signal into a pointer timing adapted to the FFT module, so as to continuously provide the FFT module 140 with the data of the time domain signal to be processed. The FFT module 140 includes an FFT recursive body module, which is configured to receive the data of the time domain signal to be processed according to the optimal timing, and convert the data of the time domain signal to be processed into a periodically continuously alternating frequency domain signal through the FFT recursive body module, and the FFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times. The "butterfly nesting operation" can be understood as a nested progressive relationship between the levels of the butterfly operation. The second mirror address conversion module 150 is configured to receive a frequency domain signal that continuously changes periodically, and convert the frequency domain signal that continuously changes periodically into a pointer timing that adapts to the IFFT module 160, so as to continuously provide the IFFT module 160 with data of the frequency domain signal to be processed. The IFFT module 160 includes an IFFT recursive body module, and the IFFT module 160 is configured to receive the data of the frequency domain signal to be processed according to the optimal timing, and restore the data of the frequency domain signal to be processed to the original time domain signal through the IFFT recursive body module, and the IFFT recursive body module is configured to perform a recursive call nested operation that can be looped any number of times.

[0074] In this solution, the number of operation points of FFT and IFFT is equal, both M. The optimal timing is the M / 2th operation cycle. The FFT module 140 receives the data of the time domain signal to be processed according to the optimal timing, which means that when the operation reaches the M / 2th operation cycle, the FFT module starts to receive new time domain signal data to be processed, thereby greatly reducing the delay of the FFT transformation operation. The IFFT module 160 receives the data of the frequency domain signal to be processed according to the optimal timing, which means that when the operation reaches the M / 2th operation cycle, the IFFT module starts to receive new frequency domain signal data to be processed, thereby greatly reducing the delay of the IFFT transformation operation,

[0075] Specifically, the FFT module 140 implements FFT operations with 4 to positive infinity points by recursively calling the FFT recursive body module any number of times, so as to convert the data of the time domain signal to be processed into a periodically continuously alternating frequency domain signal. The IFFT module 160 implements FFT operations with 4 to positive infinity points by recursively calling the IFFT recursive body module any number of times, so as to restore the data of the frequency domain signal to be processed to the original time domain signal.

[0076] The FFT recursive body module and the IFFT recursive body module have the same design structure, both of which include a basic recursive unit module and an N-layer recursive body module, where N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module. The maximum number of nested layers of recursive calls performed by the IFFT recursive body module is equal to the maximum number of nested layers of recursive calls performed by the FFT recursive body module, which is also N. The value of the maximum number of butterfly nesting doll layers N is determined according to the following formula:

[0077]

[0078] Where M is the number of operation points of FFT or IFFT.

[0079] The FFT recursive body module and the IFFT recursive body module each include a top-level recursive body module and a bottom-level recursive body module. In the FFT recursive body module, the top-level recursive body module is the recursive body module that executes the Nth level recursive call in the FFT, and the bottom-level recursive body module is the basic recursive unit module in the FFT. In the IFFT recursive body module, the top-level recursive body module is the recursive body module that executes the Nth level recursive call in the IFFT, and the bottom-level recursive body module is the basic recursive unit module in the IFFT.

[0080] Furthermore, the FFT recursive body module and the IFFT recursive body module also have the following common features:

[0081] 1. Each layer of recursive body modules includes a butterfly pipeline gating timing module with the same sequence but execution time twice that of the previous layer of recursive body modules. The butterfly pipeline gating timing module includes at least one invisible state machine module, and the triggering condition and output pointer of the invisible state machine module are both controlled by the counter module. Multiple traits are hidden.

[0082] 2. The invisible state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the orientation of the butterfly pipeline pointer in the four states is consistent, among which 0 represents the multiplication and accumulation of the left front wing of the butterfly, 1 represents the multiplication and accumulation of the left rear wing of the butterfly, 3 represents the multiplication and accumulation of the right front wing of the butterfly, and 4 represents the multiplication and accumulation of the right rear wing of the butterfly. Figure 2 A schematic diagram of a "butterfly nesting doll" that can be nested any number of times is shown, in which the length and width of the current layer of "butterfly wings" are both twice the length and width of the previous layer of "butterfly wings". Figure 3 The calculation areas corresponding to the four states of butterfly operation 0, 1, 2, and 3 are shown; each layer of recursive body module (i.e. each layer of "butterfly wing") divides the four states of butterfly operation into multiplication and accumulation in different areas. They are: 0 refers to the multiplication and accumulation of the left front wing, 1 refers to the multiplication and accumulation of the left rear wing, 2 refers to the multiplication and accumulation of the right front wing, and 3 refers to the multiplication and accumulation of the right rear wing.

[0083] 3. Each layer of recursive body module has butterfly pointers in four directions, and the butterfly pointer in any direction contains two small pointers in the same direction in the previous layer of recursive body module; every time the recursive body module performs a pointer operation, the two small pointers in the same direction in the previous layer of recursive body module it contains will perform two pointer operations successively at twice the rate.

[0084] 4. The state cycle of the recursive body module of the current layer is twice the state cycle of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is twice the data bit width of the recursive body module of the previous layer. The data pipeline with a data bit width of W for each layer of recursive body module includes two data pipelines with a data bit width of W / 2.

[0085] Figure 1 The overall direction of the signal flow in the disclosed solution is described from a macro perspective. The dotted line in the figure is the watershed between the time domain (TimeDomain) and the frequency domain (FrequencyDomain). Among them, the FFT module and the IFFT module are both core components of this design. Since the architecture of the FFT module and the architecture of the IFFT module are very similar, these two architectures can be described by the same set of codes. By modifying the `define macro definition value to determine whether it plays the role of FFT or IFFT when being instantiated, the difficulty of code maintenance and management is reduced.

[0086] Please continue to see Figure 1 In order to facilitate analysis and testing, the original time domain signal is first cached in the initial module, and the pointer loop of the read pointer loop module is used to generate a periodically continuously changing initial signal (this is a sine wave signal), which is output to the first mirror address conversion module on the left. The periodically continuously changing initial signal is converted into the pointer timing of the FFT module through the mirror pointer ptr_raddr_mirror in the first mirror address conversion module, which continuously provides the FFT module with the data of the time domain signal to be processed.

[0087] The number of FFT operation points can be set to 2n, where n is an integer greater than or equal to 2. For example, the number of FFT operation points can be 4, 8, 16, 32, 64 or 128. Taking 8-point FFT addressing as an example, the original order of the time domain signal address is: x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7]; the reordering before participating in the FFT operation is: x[0], x[4], x[2], x[6], x[1], x[5], x[3], x[7]; the above address order is converted into a three-bit binary of [2:0], as shown in the following table:

[0088]

[0089] From the data in the table, we can see that: the 0th bit of the original binary expression corresponds to the 2nd bit of the reordered binary expression; the 1st bit of the original binary expression corresponds to the 1st bit of the reordered binary expression; the 2nd bit of the original binary expression corresponds to the 0th bit of the reordered binary expression. That is, the binary of the original order and the reordered address just present a mirror relationship. The first mirror address conversion module converts the time domain signal data input in natural order into a code bit inverted arrangement order after address calculation, and then enters the FFT module to perform butterfly operation.

[0090] The FFT module consumes the data of the above-mentioned time domain signal to be processed according to the optimal timing, converts it into a frequency domain signal, and then outputs it to the second mirror address conversion module on the right. The periodically continuously changing frequency domain signal is converted into a pointer timing adapted to the IFFT module through the mirror pointer ptr_raddr_ mirror in the second mirror address conversion module, and continuously provides the IFFT module with the data of the frequency domain signal to be processed. Similar to the first mirror address conversion module, the second mirror address conversion module restores the reordered input frequency domain signal data to the natural order after address calculation, and enters the IFFT module to perform butterfly operation. The IFFT module consumes the data of the above-mentioned frequency domain signal to be processed according to the optimal timing, and restores the original time domain signal.

[0091] Both the FFT module and the IFFT module are the core modules of this design. The FFT recursive body module and the IFFT recursive body module each include a basic recursive unit module and an N-layer recursive body module, where N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module. The maximum number of nested layers of recursive calls performed by the FFT recursive body module is equal to the maximum number of nested layers of recursive calls performed by the IFFT recursive body module, and the number of operation points of the FFT module and the IFFT module are also the same. The FFT module implements FFT operations with 4 to positive infinity points by making any number of recursive calls to the FFT recursive body module, so as to convert the data of the time domain signal to be processed into a periodically continuously alternating frequency domain signal; the IFFT module implements FFT operations with 4 to positive infinity points by making any number of recursive calls to the IFFT recursive body module, so as to restore the data of the frequency domain signal to be processed to the original time domain signal.

[0092] This design uses a recursive call nesting method that can be looped any number of times to implement infinite recursive calls to the corresponding recursive body module from 4 to positive infinity, thereby realizing FFT or IFFT operations of any number of points (default 128 points). The nesting relationship between levels can be modified by modifying the parameter parameter, so that based on the same set of RTL code, logic netlists of different scales and different calculation precisions can be cleverly implemented. For example Figure 4 As shown: The default operation point number of the RTL code is parameter POINT_NUM == 128, so the recursive nesting number of its core code fft_stru_i is [log2(128)]-1. Among them, fft_stru_6 is the top layer, and fft_stru_0 (that is, fft_elmnt) is the bottom layer. Each layer of logic has a set of butterfly pipeline gating timings with exactly the same order, but the execution time is exactly twice the execution time of the next layer. Therefore:

[0093] (1) fft_stru_0~6 can completely share the same set of RTL code fft_stru_i. In other words, to implement a 128-point FFT operation, you only need to instantiate stru_i 6 times by recursive calls. Similarly, to implement a 32-point FFT operation, you only need to instantiate stru_i 4 times by recursive calls.

[0094] (2) Since the time required to execute the same set of butterfly data channel selection operations between levels just presents the 2^n characteristic, this means that the trigger conditions and output pointers of the state machine used for the butterfly channel timing can be hidden by the 2^n multiple characteristics of the counter cnt_seq, which is called an invisible state machine.

[0095] (3) For example, in STRU_5, that is, the operation of the 5th layer, a butterfly operation of the current layer is executed once, and the state of the current layer, current_state, is exactly equal to cnt_seq [5:4]. Similarly, in STRU_3, that is, the operation of the 3rd layer, a butterfly operation of the current layer is executed once, and the state of the current layer, current_state, is exactly equal to cnt_seq [3:2]. Similarly, in STRU_i, that is, the operation of the i-th layer, a butterfly operation of the current layer is executed once, and the state of the current layer, current_state, is exactly equal to cnt_seq [i:i-1].

[0096] No matter which layer the current layer is in, current_state contains four states: 0, 1, 2, and 3. The butterfly channel pointers of these four states are completely consistent. In addition, since the state cycle of the current layer is exactly twice that of the state cycle of its next layer, the data bit width is also exactly twice that of the previous layer. This means that: in the data pipeline with a width of W in the current layer, there are two data pipelines with a width of W / 2. No matter which layer the current layer is in, there are butterfly pointers in four directions, and in any of the butterfly pointers in one direction, there are two small pointers in the same direction in the next layer. Every time the current layer performs a pointer operation, the two small pointers in the same direction in the next layer buried by it will successively perform two pointer operations at a rate twice. And so on.

[0097] The recursive call of FFT module or IFFT module has the following characteristics: in the static call process, the logical upper limit of the number of calls is determined by the top-level STRU_NUM, and the physical upper limit of the number of calls is determined by the physical resources inside the FPGA; the generate if (STRU_NUM == 1) statement in the RTL code is used to determine whether the currently called fft_stru_i module is the bottom layer; if it is the bottom layer, the fft_elmnt module is called to perform basic multiplication and addition operations. In the dynamic call process, the same logical resource can be called any number of times without upper limit in theory.

[0098] The above design can achieve the following technical breakthroughs:

[0099] 1) Arbitrary recursive call technology of computing architecture

[0100] Each time the recursive call is made, the number of operation points increases exponentially. This means that by simply changing the parameterSTRU_NUM, you can implement FFT or IFFT with different operation points in the same code and generate logic netlists of different sizes. For example, to implement an 8192-point FFT or IFFT, just set STRU_NUM = 17. In this embodiment, the FFT operation defaults to 128 points, so parameter STRU_NUM = log2(128)-1 == 6, that is, fft_stru_i is recursively called 6 times, such as Figure 5 The above recursive calls are further divided into the following two categories: recursive calls of extended resources before the RTL code is compiled and synthesized into a logic netlist; and recursive calls of unchanged resources before the RTL code is compiled and synthesized into a logic netlist.

[0101] 2) “Time-sharing and seamless reuse” technology

[0102] Each level consists of only one set of "physical multipliers and adders" which can generate n (n is the number of operation points of FFT transformation) "virtual multipliers and adders" without affecting the computing performance.

[0103] The FFT module starts to consume new data when the calculation reaches the M / 2th calculation cycle, and the IFFT module starts to consume new data when the calculation reaches the M / 2th calculation cycle, thereby greatly reducing the delay of FFT and IFFT transformation operations.

[0104] The "invisible state machine" based on the cnt_seq counter is used to achieve the same timing for each recursive layer, but the execution cycle is guided by the data flow state with 2^n increments. This means that recursive calls between different levels will not produce any operation gaps, let alone data packet loss; the "jump condition" of this "invisible state machine" and the "task execution identification signal" of the current state are completely "hidden", thereby reducing the circuit area and power consumption.

[0105] Take the 16-point FFT or IFFT as an example. First, 32 sets of multiplication and addition units are virtualized by calling the physical resources of 4 sets of multiplication and addition units (1 set in each column) in time-sharing. When the first data stream is calculated to the 8th beat, the multiplication and addition unit in the first column will be idle. However, at this time, the second data stream is seamlessly consumed. Although the operands have changed, the calculation is still carried out according to the path trajectory of the first set of data. Subsequently, the third, fourth, and fifth data will come one after another and connect seamlessly. For details, please refer to the attached manual. Figure 6-9 .

[0106] See also Figure 6 , a single stream of data is fed into the 16-point FFT (IFFT) operator. In the fourth cycle when the first stream of data is fed into the operator, the fifth multiplication-addition unit of the first set of multiplication-addition units and the third multiplication-addition unit of the second set of multiplication-addition units are activated.

[0107] See also Figure 7 , two streams of data are simultaneously fed into the 16-point FFT (IFFT) operator, the first stream of data is fed into the 8th cycle, and the second stream of data is fed into the 0th cycle. When the first stream of data is calculated to the 8th cycle, the first set of multiplication and addition units will be idle, but at this time, the second stream of data is seamlessly fed in. At this time, the first multiplication and addition unit of the first set of multiplication and addition units, the 7th multiplication and addition unit of the second set of multiplication and addition units, and the 4th multiplication and addition unit of the third set of multiplication and addition units are activated. The physical multiplication and addition units that need to be occupied are less than or equal to 4 sets.

[0108] See also Figure 8 , two streams of data are simultaneously fed into the 16-point FFT (IFFT) operator, the first stream of data is fed into the 13th cycle, and the second stream of data is fed into the 5th cycle. At this time, the 6th multiplication-addition unit of the first set of multiplication-addition units, the 4th multiplication-addition unit of the second set of multiplication-addition units, the 1st multiplication-addition unit of the third set of multiplication-addition units, and the 4th multiplication-addition unit of the fourth set of multiplication-addition units are activated. The number of physical multiplication-addition units required is less than or equal to 4 sets.

[0109] See also Fig. 9, two streams of data are simultaneously fed into the 16-point FFT (IFFT) operator. At the 10th cycle of the second stream of data, the output of the first FFT (IFFT) operator has been calculated. At this time, the sixth multiplication-addition unit of the third set of multiplication-addition units and the first multiplication-addition unit of the fourth set of multiplication-addition units are activated. The number of physical multiplication-addition units required is also less than or equal to 4 sets.

[0110] It can be seen that the delay to complete a 16-point FFT (IFFT) is only 10 cycles.

[0111] The number of physical multiplication and addition units required to complete an N-point FFT (IFFT) is where N is the number of points in the FFT (IFFT) operation.

[0112] The number of delay cycles T Latency It can be determined by the following formula:

[0113]

[0114] Where N is the number of points for FFT (IFFT) operation.

[0115] When the number of butterfly operation points disclosed in the present invention is 4, 8, 16, 32, 64, and 128, the corresponding butterfly operation delay is 1, 4, 9, 18, 35, and 68 system clock cycles, respectively, which is better than most similar FFT hardware acceleration operators on the market.

[0116] In addition to the above-mentioned device embodiments, the embodiments of the present application also provide a hardware acceleration method. The hardware acceleration method provided by the embodiments of the present application is exemplarily described below.

[0117] Fig.10 A flowchart of the hardware acceleration method is shown, such as Fig.10 As shown, the hardware acceleration method includes one or more of steps S601-S611.

[0118] S601: Cache the original time domain signal.

[0119] S603: Generate an initial signal that continuously changes periodically based on the original time domain signal.

[0120] S605: Convert the initial signal that continuously changes in period into a pointer timing sequence that is adapted to FFT transformation to obtain data of the time domain signal to be processed.

[0121] S607, receiving the data of the time domain signal to be processed according to the optimal timing, and converting the data of the time domain signal to be processed into a frequency domain signal that continuously changes periodically through the FFT recursive body module, and the FFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times.

[0122] The FFT recursive body module includes a basic recursive unit module and an N-layer recursive body module, where N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module. The recursive body module that performs the Nth layer of recursive calls is the top-level recursive body module, and the basic recursive unit module is the bottom-level recursive body module. By performing any number of recursive calls on the FFT recursive body module, an FFT operation with a number of points from 4 to positive infinity is realized to convert the data of the time domain signal to be processed into a periodically continuously alternating frequency domain signal.

[0123] S609: Convert the frequency domain signal that continuously changes periodically into a pointer timing that is adapted to IFFT transformation to obtain data of the frequency domain signal to be processed.

[0124] S611, receiving data of the frequency domain signal to be processed according to the optimal timing, and restoring the data of the frequency domain signal to be processed to the original time domain signal through the IFFT recursive body module, the IFFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times.

[0125] The IFFT recursive body module includes a basic recursive unit module and an N-layer recursive body module, where N is the maximum number of nested layers of recursive calls performed by the IFFT recursive body module. The recursive body module that performs the Nth layer of recursive calls is the top-level recursive body module, and the basic recursive unit module is the bottom-level recursive body module. By performing any number of recursive calls on the IFFT recursive body module, FFT operations with a number of points from 4 to positive infinity are implemented to restore the data of the frequency domain signal to be processed to the original time domain signal.

[0126] The number of operation points of IFFT is the same as that of FFT, which is M. The value of the maximum number of recursive call nesting layers N is calculated according to the formula Determine. The optimal timing in steps S607 and S611 is the M / 2th operation cycle. When the operation reaches the M / 2th operation cycle, the FFT module starts to receive new time domain signal data to be processed, and the IFFT module starts to receive new frequency domain signal data to be processed, thereby greatly reducing the delay of FFT and IFFT transformation operations.

[0127] In the FFT recursive body module and the IFFT recursive body module, each layer of the recursive body module includes a butterfly pipeline gating sequence with the same sequence but an execution time that is twice the execution time of the previous layer of the recursive body module. The butterfly pipeline gating sequence includes at least one invisible state machine, and the trigger condition and output pointer of the invisible state machine are both controlled by the counter. The multiple characteristics of are hidden. The invisible state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the orientation of the butterfly pipeline pointer in the four states is consistent, where 0 means multiplying and accumulating the left front wing of the butterfly, 1 means multiplying and accumulating the left rear wing of the butterfly, 3 means multiplying and accumulating the right front wing of the butterfly, and 4 means multiplying and accumulating the right rear wing of the butterfly.

[0128] Each layer of recursive body module has butterfly pointers in four directions, and any butterfly pointer in any direction contains two small pointers in the same direction in the previous layer of recursive body module; each time the recursive body module performs a pointer operation, the two small pointers in the same direction in the previous layer of recursive body module it contains perform two pointer operations successively at twice the rate.

[0129] The state cycle of the recursive body module of the current layer is twice the state cycle of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is twice the data bit width of the recursive body module of the previous layer. The data pipeline with a data bit width of W for each layer of recursive body module includes two data pipelines with a data bit width of W / 2.

[0130] In the disclosed embodiment, the FFT recursive body module can perform a butterfly nesting operation that can be looped any number of times, and an FFT operation of any number of points can be realized by calling the FFT recursive body module. The IFFT recursive body module can perform a butterfly nesting operation that can be looped any number of times, and an FFT operation of any number of points can be realized by calling the IFFT recursive body module. The number of points that are multiples of 2 can be arbitrarily customized by modifying parameters and changing the number of levels of instantiation nesting. The reusability and flexibility of the operator are improved, and the economic and time costs of version maintenance and management are reduced.

[0131] The present disclosure utilizes an invisible state machine module to achieve the same timing for each recursive layer, but the execution cycle is 2 n The incremental data flow state guidance ensures that recursive calls between different levels will not produce any operation gaps, let alone data packet loss, and pushes the operation delay to the extreme within limited resources. In addition, the "jump condition" of the invisible state machine module and the "task execution identification signal" of the current state are completely "hidden", thereby reducing the circuit area and power consumption.

[0132] Correspondingly, an embodiment of the present application further provides a hardware acceleration system, which includes the above-mentioned hardware acceleration device.

[0133] Accordingly, an embodiment of the present application further provides a non-transitory computer-readable storage medium, in which computer instructions are stored, and the computer instructions are suitable for loading by a processor to implement the steps in the above-mentioned hardware acceleration method.

[0134] In an embodiment of the present application, the memory is used to store a computer program and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to implement the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0135] In the embodiment of the present application, the processor can be any hardware processing device that can execute the logic of the above method. Optionally, the processor can be a central processing unit (CPU), a graphics processing unit (GPU) or a microcontroller unit (MCU); it can also be a field programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), a complex programmable logic device (CPLD) and other programmable devices; or an advanced reduced instruction set (RISC) processor (Advanced RISC Machines, ARM) or a system on chip (System on Chip, SOC), etc., but not limited to this.

[0136] In an embodiment of the present application, the communication component is configured to facilitate wired or wireless communication between the device in which it is located and other devices. The device in which the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G, 5G or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be implemented based on near field communication (NFC) technology, radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology or other technologies.

[0137] In an embodiment of the present application, the display component may include a liquid crystal display (LCD) and a touch panel (TP). If the display component includes a touch panel, the display component may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0138] In an embodiment of the present application, a power supply component is configured to provide power to various components of the device in which it is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component is located.

[0139] In an embodiment of the present application, the audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal may be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting an audio signal. For example, for a device with a language interaction function, voice interaction with a user may be achieved through an audio component.

[0140] It should be noted that the descriptions such as “first” and “second” in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit “first” and “second” to different types.

[0141] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0142] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0143] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0144] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0145] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0146] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0147] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0148] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0149] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A hardware acceleration device, characterized in that: The hardware acceleration device includes at least one or more of the following modules: The initial module is configured to cache the original time domain signal; A read pointer cycle module is configured to generate an initial signal that continuously changes periodically based on the original time domain signal; A first mirror address conversion module is configured to convert the initial signal that continuously changes periodically into a pointer timing adapted to the FFT module, so as to continuously provide the FFT module with data of the time domain signal to be processed; An FFT module, comprising an FFT recursive body module, wherein the FFT module is configured to receive the data of the time domain signal to be processed in an optimal timing sequence, and convert the data of the time domain signal to be processed into a frequency domain signal that is periodically continuously alternating through the FFT recursive body module, and the FFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times; a second mirror address conversion module, configured to receive the periodically continuously alternating frequency domain signal, and convert the periodically continuously alternating frequency domain signal into a pointer timing adapted to an IFFT module, so as to continuously provide the IFFT module with data of the frequency domain signal to be processed; and / or An IFFT module, comprising an IFFT recursive body module, wherein the IFFT module is configured to receive the data of the frequency domain signal to be processed in an optimal timing sequence, and restore the data of the frequency domain signal to be processed to an original time domain signal through the IFFT recursive body module, and the IFFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times; The FFT recursive body module and the IFFT recursive body module each include a basic recursive unit module and an N-layer recursive body module, N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module or the IFFT recursive body module, The FFT recursive body module and the IFFT recursive body module each include a top-level recursive body module and a bottom-level recursive body module, the top-level recursive body module is a recursive body module that executes the Nth level recursive call, and the bottom-level recursive body module is the basic recursive unit module; Each layer of recursive body module has butterfly pointers in four directions, wherein the butterfly pointer in any direction contains two small pointers in the same direction in the previous layer of recursive body module; each time the recursive body module performs a pointer operation, the two small pointers in the same direction in the previous layer of recursive body module it contains successively perform two pointer operations at twice the rate; and The state cycle of the recursive body module of the current layer is twice the state cycle of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is twice the data bit width of the recursive body module of the previous layer.

2. The hardware acceleration device according to claim 1, characterized in that: The FFT module implements FFT operations with a number of points from 4 to positive infinity by recursively calling the FFT recursive body module any number of times, so as to convert the data of the time domain signal to be processed into a frequency domain signal that continuously changes periodically; The IFFT module implements FFT operations with a number of points from 4 to positive infinity by making any number of recursive calls to the IFFT recursive body module, so as to restore the data of the frequency domain signal to be processed to the original time domain signal.

3. The hardware acceleration device according to claim 1, characterized in that: Each layer of recursive body modules includes a butterfly pipeline gating timing module with the same sequence but an execution time that is twice the execution time of the previous layer of recursive body modules.

4. The hardware acceleration device according to claim 3, characterized in that: The butterfly pipeline selection timing module includes at least one invisible state machine module, and the invisible state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the orientation of the butterfly pipeline pointer in the four states is consistent, wherein 0 represents multiplication and accumulation of the left front wing of the butterfly, 1 represents multiplication and accumulation of the left rear wing of the butterfly, 2 represents multiplication and accumulation of the right front wing of the butterfly, and 3 represents multiplication and accumulation of the right rear wing of the butterfly.

5. The hardware acceleration device according to claim 4, characterized in that: The data pipeline with a data bit width of W in each layer of the recursive body module includes two data pipelines with a data bit width of W / 2.

6. A hardware acceleration method, characterized in that: The method comprises one or more of the following steps: Cache the original time domain signal; Generating an initial signal with a continuous alternation period based on the original time domain signal; Converting the periodically continuously alternating initial signal into a pointer timing sequence adapted to FFT transformation to obtain data of a time domain signal to be processed; Receiving the data of the time domain signal to be processed in an optimal time sequence, and converting the data of the time domain signal to be processed into a frequency domain signal that is periodically continuously alternating through an FFT recursive body module, wherein the FFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times; Converting the periodically continuously alternating frequency domain signal into a pointer timing sequence adapted to IFFT transformation to obtain data of the frequency domain signal to be processed; Receiving the data of the frequency domain signal to be processed in an optimal time sequence, and restoring the data of the frequency domain signal to be processed to an original time domain signal through an IFFT recursive body module, wherein the IFFT recursive body module is configured to perform a butterfly nesting operation that can be circulated any number of times; The FFT recursive body module and the IFFT recursive body module each include a basic recursive unit module and an N-layer recursive body module, N is the maximum number of nested layers of recursive calls performed by the FFT recursive body module or the IFFT recursive body module, The FFT recursive body module and the IFFT recursive body module each include a top-level recursive body module and a bottom-level recursive body module, the top-level recursive body module is a recursive body module that executes the Nth level recursive call, and the bottom-level recursive body module is the basic recursive unit module; Each layer of recursive body module has butterfly pointers in four directions, and any butterfly pointer in any direction contains two small pointers in the same direction in the previous layer of recursive body module; each time the recursive body module performs a pointer operation, the two small pointers in the same direction in the previous layer of recursive body module it contains perform pointer operations twice in succession at twice the rate; The state cycle of the recursive body module of the current layer is twice the state cycle of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is twice the data bit width of the recursive body module of the previous layer.

7. The hardware acceleration method according to claim 6, characterized in that: Each layer of recursive body modules includes a butterfly pipeline gating timing with the same sequence but an execution time that is twice the execution time of the previous layer of recursive body modules.

8. The hardware acceleration method according to claim 6, characterized in that: The butterfly pipeline selection timing module includes at least one invisible state machine module, and the invisible state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the orientation of the butterfly pipeline pointer in the four states is consistent, wherein 0 represents multiplication and accumulation of the left front wing of the butterfly, 1 represents multiplication and accumulation of the left rear wing of the butterfly, 3 represents multiplication and accumulation of the right front wing of the butterfly, and 4 represents multiplication and accumulation of the right rear wing of the butterfly.

9. A hardware acceleration system, characterized in that: The hardware acceleration system comprises the hardware acceleration device according to any one of claims 1 to 4.

10. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are suitable for loading by a processor to implement the hardware acceleration method according to any one of claims 6 to 8.

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