Indicating method, system and equipment for power supply time sequence abnormity in starting process of server and medium

Abstract

The invention provides a method, a system, equipment and a medium for indicating power supply time sequence abnormity in the starting process of a server, and the method comprises the following steps: after a complex programmable logic device detects a starting instruction, executing preset starting power-on time sequence control, and changing the function of an indication module into abnormal time sequence indication; and the complex programmable logic device detects whether the startup time sequence is normally completed or not, displays the abnormal position of the startup time sequence through the indication module when the startup time sequence is not normally completed, and recovers the function of the indication module to indicate the startup state of the basic input / output system when the startup time sequence is normally completed. According to the method, the abnormal position of the power-on time sequence of the server is indicated through the multiplex port 80 indicator lamp, and the occupied area of CPLD pins and the use of the mainboard area are reduced.

Description

Background Art

[0002] With the development of cloud computing, big data and artificial intelligence, servers are becoming more and more important as the core components of data centers. The stability and reliability of servers directly affect the operating efficiency and data security of the overall business system. Therefore, ensuring that the server can successfully and correctly complete the initialization and power-on of various components during the boot process is the key to ensuring the stable operation of the server.

[0003] There are many components on the server motherboard, including CPU, memory, hard disk, various interface controllers, etc., which need to be powered on step by step in a certain order and time interval when booting up. A considerable number of servers fail to boot up due to abnormalities in the power-on timing process during the boot-up process of the server motherboard. However, it is very difficult to troubleshoot power-on timing abnormalities in the server room. Traditional troubleshooting methods often rely on the experience of technicians and complex testing equipment, such as oscilloscopes, etc. However, in large data centers or remote computer room environments, the troubleshooting method that always relies on manpower and equipment is not only inefficient, but also costly. At present, there are technical solutions to achieve power-on timing control through hardware means such as CPLD, but most of these solutions focus on precise control of timing, and are insufficient in abnormality detection and indication. When a timing abnormality occurs during the boot-up process, the system can often only simply report the error, but cannot specifically point out which link or component has a problem, which brings great difficulties to subsequent troubleshooting and repair work.

[0004] Therefore, in view of the above-mentioned defects, it is very necessary to provide a method, system, device and medium for indicating abnormal power supply timing during the server startup process. Summary of the invention

[0005] The troubleshooting of abnormal power-on sequence during the startup process of the above-mentioned server relies on the experience of technicians and advanced instruments, which is costly and inefficient. Hardware means such as CPLD can only control the power-on sequence but cannot locate the specific timing failure. The present invention provides a method, system, device and medium for indicating abnormal power supply sequence during the startup process of the server to solve the above-mentioned technical problems.

[0006] In a first aspect, the present invention provides a method for indicating abnormal power supply timing during a server startup process, comprising the following steps:

[0007] After the complex programmable logic device detects the power-on instruction, it executes the pre-set power-on power-on timing control and changes the indication module function to abnormal timing indication;

[0008] The complex programmable logic device detects whether the power-on sequence is completed normally, and when the power-on sequence is not completed normally, the abnormal position of the power-on sequence is displayed through the indication module, and when the power-on sequence is completed normally, the indication module function is restored to indicate the startup status of the basic input and output system. Through the intelligent control of the complex programmable logic device, real-time monitoring and abnormality detection of the power supply sequence during the server startup process are realized; when an abnormality is detected, it can be quickly displayed through the indication module to help the operation and maintenance personnel quickly locate the problem; at the same time, after the power-on sequence is completed normally, the function of the indication module is automatically restored to ensure continuous monitoring of the system startup status; the present invention improves the automation level and fault handling efficiency of the system and reduces the operation and maintenance costs.

[0009] Furthermore, after the complex programmable logic device detects the power-on instruction, it executes the preset power-on power-on timing control, and before the step of changing the indication module function to the abnormal timing indication, it also includes the following steps:

[0010] Pre-connect the power-on timing-related control signal lines of the central processing unit, each power supply control module and each logic device to the corresponding pins of the complex programmable logic device;

[0011] Preset the specific timing of the timing-related control signal lines of the central processor, each power supply control module, and each logic device during the server startup process, and define the corresponding operation of each control signal line failure;

[0012] The states of the port 80 indicator lights are encoded, and each control signal line fault is bound to a state code of the port 80 indicator light of the indication module and the corresponding operation of the fault, and then the binding relationship generation table is saved in the complex programmable logic device. The present invention realizes the refined control of the server startup process by presetting the timing and binding relationship table of the control signal line, so that the system can be flexibly adjusted according to different hardware configurations and startup requirements, and the compatibility and scalability of the system are improved. At the same time, the introduction of the binding relationship table also makes the troubleshooting more accurate and efficient.

[0013] Furthermore, the power-on timing-related control signal lines of the central processing unit, each power supply control module and each logic device include a first reset signal line, a first reset completion signal line, a first clock enable signal line, a first clock completion signal line of the central processing unit, a power supply enable signal line, a power supply completion signal line of each power supply control module and a second reset signal line, a second reset completion signal line, a second clock enable signal line and a second clock completion signal line of each logic device.

[0014] Furthermore, the steps of executing the preset power-on timing control and changing the indication module function to abnormal timing indication are as follows:

[0015] Execute the specific timing of the timing-related control signal lines of the central processor, each power supply control module, and each logic device during the pre-set server startup process;

[0016] The function of the indicator light of port 80 of the indicator module is changed from the basic input and output system startup status indication to the abnormal timing indication. In the process of executing the startup timing control, by changing the function of the indicator module, the abnormal timing is immediately indicated, so that the system can warn and troubleshoot potential problems during the startup process, avoiding the occurrence of system startup failure or instability caused by abnormal timing.

[0017] Further, the complex programmable logic device detects whether the power-on sequence is completed normally, and when the power-on sequence is not completed normally, displays the abnormal position of the power-on sequence through the indication module, and when the power-on sequence is completed normally, restores the function of the indication module to indicate the startup state of the basic input and output system. The specific steps are:

[0018] The complex programmable logic device detects whether a completion signal of the last control signal of a specific timing in the service startup process is received;

[0019] If the completion signal of the last control signal is received, the function of the port 80 indicator light of the indicator module is changed from the abnormal timing indication to the basic input and output system startup status indication, and the process ends;

[0020] If the completion signal of the last signal is not received, determining whether the currently executed control signal receives the completion signal within a preset time;

[0021] If a completion signal is received within the preset time, the next control signal is executed and the signal detection step of the last control signal is returned to complete;

[0022] If the completion signal is not received within the preset design, the currently executed control signal is used as an abnormal signal, and the control signal line where the abnormal signal is located is used as the abnormal position. The abnormal position is indicated by the indicator light of port 80 of the indication module, and an alarm message containing the name of the abnormal signal is generated and sent to the baseboard management controller. The indication method of the present invention realizes comprehensive monitoring and precise positioning of the power supply timing during the server startup process through detailed timing detection and abnormal judgment logic; when an abnormality is detected, an alarm message can be quickly generated and sent to the baseboard management controller, realizing rapid response and processing of the fault; at the same time, through the completion signal detection mechanism within the preset time, the occurrence of misjudgment caused by signal delay or interference is avoided.

[0023] Furthermore, the control signal line where the abnormal signal is located is taken as the abnormal position, and the steps of indicating the abnormal position through the port 80 indicator light of the indication module are specifically as follows:

[0024] Obtain the binding relationship table, find out the port 80 indicator light status code corresponding to the abnormal signal and the control signal fault and the operation corresponding to the fault;

[0025] The complex programmable logic device controls the indicator light of port 80 according to the found status code, indicates the abnormal position, and generates corresponding alarm information according to the operation corresponding to the fault and sends it to the baseboard management controller. The present invention realizes accurate indication of the abnormal position and instant sending of alarm information through rapid search of the binding relationship table and generation of corresponding operations, making fault troubleshooting more efficient and accurate, and improving the reliability and stability of the system.

[0026] In a second aspect, the present invention provides an indication system for abnormal power supply timing during the server startup process, including a server mainboard, on which a complex programmable logic device, a central processing unit, a basic input and output system, an indication module, a plurality of power supply control modules and a plurality of logic devices are arranged;

[0027] The complex programmable logic device is connected to the central processing unit, the indication module, each power supply control module and each logic device;

[0028] The indication module is also connected to the basic input and output system;

[0029] The complex programmable logic device controls the power-on timing of the central processing unit, each power supply control module and each logic device, changes the function of the indication module, indicates the abnormal position during the execution of the power-on timing according to the pre-set logic, and restores the function of the indication module after the power-on timing is completed, and indicates the startup status of the basic input and output system. The present invention realizes precise control and abnormality detection of the power supply timing during the server startup process by integrating complex programmable logic devices, which not only improves the reliability and stability of the system, but also can quickly locate the problem when the power supply timing is abnormal, avoiding the system startup failure or instability caused by timing confusion in the traditional method. At the same time, by multiplexing the indication module with the basic input and output system, the intuitive display of the system startup status is realized, which is convenient for operation and maintenance personnel to quickly judge the system status, improves maintenance efficiency, and saves the occupation of complex programmable logic device pins and the use of motherboard area.

[0030] Further, the complex programmable logic device is also connected to a baseboard management controller;

[0031] The complex programmable logic device generates alarm information according to the abnormal position of the power-on sequence execution process, and sends and displays the alarm information to the baseboard management controller. By adding a connection with the baseboard management controller, the system can automatically send alarm information to the baseboard management controller when an abnormal power supply sequence is detected, further enhancing the intelligence level of the system, so that the alarm information can be transmitted to the monitoring center or remote operation and maintenance personnel in real time, realizing remote monitoring and immediate response to the server startup process, greatly improving the timeliness and accuracy of fault handling.

[0032] Further, the indicator module uses a port 80 indicator light;

[0033] The complex programmable logic device is connected to the central processing unit through a first reset signal line, a first reset completion signal line, a first clock enable signal line, and a first clock completion signal line.

[0034] The complex programmable logic device is connected to each power supply control module through the power supply enable signal line and the power supply completion signal line, and the complex programmable logic device is connected to each logic device through the second reset signal line, the second reset completion signal line, the second clock enable signal line, and the second clock completion signal line. The port 80 indicator light is used as the indication module, and through the detailed signal line connection design, it is ensured that the complex programmable logic device can accurately control the startup timing of each component, and intuitively display the different states of the indicator light when an abnormality occurs, simplifying the troubleshooting process, reducing the technical requirements for operation and maintenance personnel, and improving the ease of use and user satisfaction of the system.

[0035] In a third aspect, the present invention provides an electronic device, including a processor and a memory;

[0036] The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the electronic device executes the method described in the second aspect above.

[0037] In a fourth aspect, the present invention provides a storage medium,

[0038] The storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the second aspect.

[0039] The beneficial effects of the present invention are:

[0040] The present invention provides a method, system, device and medium for indicating abnormal power supply timing during the server startup process. The abnormal position of the power-on timing is judged while the CPLD itself executes the power-on timing, accurately confirms the cause of the abnormality, and displays it through the multiplexed port 80 indicator light, reducing the occupation of the CPLD pins and the use of the mainboard area. The abnormal information is sent to the BMC for users and support personnel to view and quickly locate the cause of the problem. The indication is made on the server mainboard body. When the BMC is not connected during development and production or the BMC fails, the cause of the problem can be intuitively viewed, and the problem can be quickly checked. In addition, the present invention has a reliable design principle, a simple structure, and a very broad application prospect.

[0041] It can be seen that compared with the prior art, the present invention has outstanding substantive features and significant progress, and the beneficial effects of its implementation are also obvious. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 The present invention is a flow chart of an embodiment of a method for indicating abnormal power supply timing during the server startup process.

[0044] Figure 2 The invention is a flow chart of the method for indicating abnormal power supply timing in the process of starting up a server, for presetting a binding relationship table for a CPLD.

[0045] Figure 3 This is another embodiment of the method for indicating abnormal power supply timing during the server startup process of the present invention.

[0046] Figure 4 It is a schematic diagram of the indication system of the present invention for abnormal power supply timing during the server startup process. DETAILED DESCRIPTION

[0047] The present invention provides a method, system, device and medium for indicating power supply sequence abnormality during server startup. The CPLD determines the abnormal position of the power-on sequence while controlling the power-on sequence, and drives the startup status indicator light to change to indicate the position where the power-on sequence abnormality occurs, thereby completing the indication of the power-on sequence abnormality problem point; at the same time, the alarm information containing the abnormal signal name is sent to the BMC, and the BMC displays the problem on the alarm page.

[0048] The method for indicating power supply timing abnormality during server startup can be applied to one or more electronic devices, wherein the electronic device is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASIC), programmable gate arrays (FPGA), digital signal processors (DSP), embedded devices, etc.

[0049] An electronic device can be any electronic product that can interact with a user, such as a personal computer, a tablet computer, a smart phone, a personal digital assistant (PDA), an interactive network television (IPTV), etc. The network in which the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (VPN), etc.

[0050] BMC, short for Baseboard Management Controller, manages the server out-of-band and performs a series of monitoring and control functions.

[0051] CPLD, short for Complex Programmable Logic Device, is a digital integrated circuit that allows users to construct logic functions according to their needs. In the server, CPLD is responsible for completing power supply timing control, hardware management, key function management and other functions.

[0052] CPU, short for Central Processing Unit, is the core processing unit of the server.

[0053] BIOS is the detection of Basic Input Output System. The basic input and output system stores the computer's most important basic input and output programs, system setting information, power-on self-test programs and system startup programs.

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0055] Embodiment 1:

[0056] like Figure 1 As shown, the method includes:

[0057] S1. After the CPLD detects the power-on instruction, it executes the preset power-on timing control and changes the indication module function to abnormal timing indication;

[0058] S2.CPLD detects whether the power-on sequence is completed normally, and when the power-on sequence is not completed normally, displays the abnormal position of the power-on sequence through the indication module, and when the power-on sequence is completed normally, restores the function of the indication module to indicate the BIOS startup status.

[0059] The present invention realizes real-time monitoring and abnormality detection of the power supply sequence during the server startup process through the intelligent control of complex programmable logic devices; when an abnormality is detected, it can be quickly displayed through the indication module to help operation and maintenance personnel quickly locate the problem; at the same time, after the startup sequence is completed normally, the function of the indication module is automatically restored to ensure continuous monitoring of the system startup status; the present invention improves the system's automation level and fault handling efficiency, and reduces operation and maintenance costs.

[0060] Embodiment 2:

[0061] In certain embodiments, such as Figure 2 As shown, before step S1, the following steps are also included:

[0062] SS1. Pre-connect the power-on timing-related control signal lines of the CPU, each power supply control module and each logic device to the corresponding pins of the CPLD;

[0063] The power-on timing-related control signal lines of the CPU, each power supply control module and each logic device include a first reset signal line, a first reset completion signal line, a first clock enable signal line, a first clock completion signal line of the CPU, a power supply enable signal line, a power supply completion signal line of each power supply control module, and a second reset signal line, a second reset completion signal line, a second clock enable signal line and a second clock completion signal line of each logic device;

[0064] SS2. Preset the specific timing of the timing-related control signal lines of the CPU, each power supply control module, and each logic device during the server startup process, and define the corresponding operation of each control signal line failure;

[0065] SS3. Encode the states of the port 80 indicator lights, and bind each control signal line fault to a state code of the port 80 indicator light of the indication module and the corresponding operation of the fault, and then generate a table of the binding relationship and save it in the CPLD;

[0066] It should be noted that the timing parameters can be adjusted dynamically in the CPLD, including the adjustment of the specific timing sequence of the control signal lines to adapt to different server configurations or optimize performance;

[0067] The present invention realizes refined control of the server startup process by presetting the timing and binding relationship table of the control signal lines, so that the system can be flexibly adjusted according to different hardware configurations and startup requirements, thereby improving the compatibility and scalability of the system. At the same time, the introduction of the binding relationship table also makes troubleshooting more accurate and efficient.

[0068] Embodiment 3:

[0069] In certain embodiments, such as Figure 3 As shown, the steps of executing the preset power-on timing control in step S1 and changing the function of the indication module to abnormal timing indication are specifically as follows:

[0070] S11. Execute the specific timing of the timing-related control signal lines of the CPU, each power supply control module, and each logic device during the pre-set server startup process;

[0071] S12. The indicator function of the port 80 of the indicator module is changed from the BIOS startup status indication to the abnormal timing indication;

[0072] It should be noted that in the process of executing the boot sequence control, by changing the function of the indication module, the instant indication of abnormal timing is realized, so that the system can warn and troubleshoot potential problems during the boot process, avoiding the occurrence of system startup failure or instability caused by abnormal timing;

[0073] The steps of step S2 are specifically as follows:

[0074] S21.CPLD detects whether it has received the completion signal of the last control signal of the specific timing in the service startup process;

[0075] If yes, change the function of the port 80 indicator light of the indicator module from abnormal timing indication to BIOS startup status indication, and end;

[0076] If not, proceed to step S22;

[0077] S22. Determine whether the currently executed control signal receives a completion signal within a preset time;

[0078] If yes, execute the next control signal and return to step S21;

[0079] If not, proceed to step S23;

[0080] S23. The currently executed control signal is used as an abnormal signal, and the control signal line where the abnormal signal is located is used as the abnormal position. The abnormal position is indicated by the indicator light of port 80 of the indicator module, and an alarm message containing the name of the abnormal signal is generated and sent to the BMC;

[0081] The indication method of the present invention realizes comprehensive monitoring and precise positioning of the power supply timing during the server startup process through detailed timing detection and abnormal judgment logic; when an abnormality is detected, an alarm message can be quickly generated and sent to the baseboard management controller, thereby realizing rapid response and processing of the fault; at the same time, through the completion signal detection mechanism within a preset time, the occurrence of misjudgment caused by signal delay or interference is avoided;

[0082] It should be noted that the timing parameters can be dynamically adjusted in the CPLD, including a preset time for determining whether the currently executed control signal receives a completion signal within a preset time, so as to adapt to different server configurations or optimize performance.

[0083] It should be noted that CPLD, as a key component of power-on sequence control, accurately defines the order of each key voltage signal in the power-on sequence. At the same time, CPLD will communicate with BIOS and indicate the server boot process through the port 80 indicator light. However, if BIOS fails to work normally before the mainboard power is powered on, the port 80 indicator light will not start to work normally. In this process, CPLD can use the port 80 indicator light as an indication of power-on sequence abnormalities.

[0084] In some embodiments, in step S23, the control signal line where the abnormal signal is located is taken as the abnormal position, and the step of indicating the abnormal position through the indicator light of port 80 of the indication module is specifically as follows:

[0085] S231 obtains the binding relationship table, finds out the abnormal signal corresponding to the control signal fault corresponding to the port 80 indicator status code and the corresponding operation of the fault;

[0086] S232. CPLD controls the indicator light of port 80 according to the found status code, indicates the abnormal position, and generates corresponding alarm information according to the operation corresponding to the fault and sends it to BMC;

[0087] The present invention realizes accurate indication of abnormal location and instant sending of alarm information through rapid search of binding relationship table and generation of corresponding operation, making fault troubleshooting more efficient and accurate, and improving reliability and stability of the system;

[0088] It should be noted that some timing errors can also be defined as minor timing errors. In the case of some minor timing errors, the CPLD can try to automatically adjust the timing or restart specific modules to try self-repair and reduce the total downtime caused by minor faults.

[0089] The present invention provides a method for indicating abnormal power supply sequence during server startup, which determines the abnormal position of the power-on sequence while executing the power-on sequence by the CPLD itself, accurately confirms the cause of the abnormality, and displays it by reusing the indicator light of port 80, thereby reducing the occupation of CPLD pins and the use of mainboard area. The abnormal information is sent to the BMC for users and support personnel to view, so that the cause of the problem can be quickly located. The indication is made on the server mainboard body, and when the BMC is not connected or a fault occurs in the BMC during development and production, the cause of the problem can be intuitively viewed, so that the problem can be quickly checked.

[0090] It should be understood that the order of execution of the steps in the above embodiment does not mean that the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0091] The following is an embodiment of a system for indicating abnormal power supply timing during server startup provided by an embodiment of the present disclosure. The system and the methods for indicating abnormal power supply timing during server startup in the above-mentioned embodiments belong to the same inventive concept. For details not fully described in the embodiment of the system for indicating abnormal power supply timing during server startup, reference can be made to the embodiments of the methods for indicating abnormal power supply timing during server startup for the above-mentioned embodiments.

[0092] Embodiment 4:

[0093] See also Figure 4 The present invention shows a specific implementation of an indication system for abnormal power supply timing during the server startup process, including a server mainboard, on which a CPLD, a CPU, a BIOS, an indication module, several power supply control modules and several logic devices are arranged;

[0094] The CPLD is connected to the CPU, the indication module, each power supply control module and each logic device;

[0095] The indicator module is also connected to the BIOS;

[0096] CPLD controls the power-on sequence of the CPU, each power supply control module and each logic device, changes the function of the indication module, indicates the abnormal position during the execution of the power-on sequence according to the pre-set logic, and restores the indication module function after the power-on sequence is completed to indicate the BIOS startup status;

[0097] The CPLD is also connected to the BMC.

[0098] It should be noted that the power supply control module is mainly responsible for controlling the power-on process of the power supply according to a preset timing; the power supply control module usually includes multiple power supply modules, which may be divided into different types, such as a first power supply module and a second power supply module, and they may have different requirements for timing accuracy. The power supply control module controls the power-on sequence of the power supply by receiving an enable signal from the CPLD. For example, a common power supply control module includes a power supply module and a power management chip; the power supply module may include power supplies of different voltage levels, such as 3.3V, 1.8V, 1.2V, etc., which are used to power the CPU, memory, other chips on the motherboard, etc.; and the power management chip is responsible for receiving instructions from the CPLD, controlling the switch of the power supply module, and monitoring the power supply status such as the Power Good signal, etc.

[0099] Logic devices play a key role in the power-on sequence. They process signals from the CPLD according to preset logic rules and control the power supply control module and other related components. For example, common logic devices include logic gate circuits such as NAND gates, NOR gates, inverters, etc. These circuits are used to implement specific logic functions, such as signal inversion and delay. Logic devices also include RC circuits for signal delay processing, which control the signal delay time by adjusting the values ​​of resistance and capacitance.

[0100] The present invention realizes precise control and abnormality detection of power supply timing during server startup by integrating complex programmable logic devices, which not only improves the reliability and stability of the system, but also can quickly locate the problem when an abnormality occurs in the power supply timing, avoiding system startup failure or instability caused by timing confusion in traditional methods. At the same time, by multiplexing the indication module with the basic input and output system, an intuitive display of the system startup status is realized, which is convenient for operation and maintenance personnel to quickly judge the system status, improves maintenance efficiency, and saves the occupation of complex programmable logic device pins and the use of mainboard area.

[0101] Embodiment 5:

[0102] In this embodiment, the CPLD generates alarm information according to the abnormal position of the power-on sequence execution process, and sends and displays the alarm information to the BMC;

[0103] The CPU power-on sequence usually includes multiple stages, which need to be carried out strictly according to the preset sequence to ensure that the CPU can start correctly and run stably. For example, the process of a CPU power-on sequence is as follows:

[0104] Preparation stage: including RTC real-time clock reset, STBY power domain power-on, etc.;

[0105] CPU power on: After confirming that all preconditions are met, the CPU power starts to power on;

[0106] Reset and clock stabilization: After the CPU power is powered on, perform a reset operation and wait for the clock signal to stabilize;

[0107] PGOOD signal transmission: After the CPU power supply is stable, a Power Good signal is sent to the CPLD, indicating that the CPU is ready to receive instructions;

[0108] Loading the operating system: After receiving the PGOOD signal, the CPU starts loading the operating system and performs initialization operations;

[0109] It should be noted that detailed error logs can also be recorded in the BMC or external storage, including the time when the abnormality occurred, specific control signals, possible causes, etc., to provide data support for subsequent fault analysis and repair;

[0110] The indicator module uses port 80 indicator light;

[0111] It should be noted that port 80, also known as PORT 80, is an 8-bit output port. During the server startup process, the BIOS will write a series of codes into port 80, and then the CPLD will display the BIOS startup status code of port 80 through 8 LED lights, thereby indicating different status information, such as CPU initialization, memory detection, driver loading, etc.

[0112] Port 80 is usually called POST, which stands for Power-On Self-Test. It is not a traditional network communication port, but a hardware interface or mechanism used to display self-test error codes on a server or computer motherboard. Although the name contains "PORT80", it does not directly correspond to the physical port number 80. The "80" here indicates a memory address, usually memory address 80h. The CPU will write error codes to this address during the self-test process and display these codes through specific hardware such as the POST card or the LED indicator on the motherboard.

[0113] It should be noted that the indication module can also use an LCD display or LED array to describe the error information or status in detail, so that the server administrator can quickly understand the problems in the boot process through a more intuitive interface. A buzzer or other sound alarm device can also be introduced. When an abnormality is detected, it can be reminded not only visually but also auditorily, thereby enhancing the alarm effect of the system.

[0114] The CPLD is connected to the CPU via a first reset signal line, a first reset completion signal line, a first clock enable signal line, and a first clock completion signal line.

[0115] The CPLD is connected to each power supply control module via a power supply enable signal line and a power supply completion signal line, and the CPLD is connected to each logic device via a second reset signal line, a second reset completion signal line, a second clock enable signal line, and a second clock completion signal line;

[0116] The present invention may also define certain timing errors as minor timing errors. In the case of certain minor timing errors, the CPLD may attempt to automatically adjust the timing or restart a specific module to attempt self-repair, thereby reducing the total shutdown caused by minor faults.

[0117] The present invention provides an indication system for abnormal power supply sequence during server startup, which determines the abnormal position of the power-on sequence while executing the power-on sequence by the CPLD itself, accurately confirms the cause of the abnormality, and displays it by reusing the indicator light of port 80, thereby reducing the occupation of CPLD pins and the use of mainboard area. The abnormal information is sent to the BMC for users and support personnel to view, so that the cause of the problem can be quickly located, and an indication is made on the server mainboard body. When the BMC is not connected or a failure occurs in the BMC during development and production, the cause of the problem can be intuitively viewed, so that the problem can be quickly checked.

[0118] The method for indicating abnormal power supply timing during server startup provided by the present invention is a module and algorithm step of each example described in combination with the embodiments disclosed herein, and can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0119] Those skilled in the art will appreciate that the various aspects of the method for indicating abnormal power supply timing during server startup provided by the present invention can be implemented as a system, method or program product. Therefore, various aspects of the present disclosure can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which can be collectively referred to as "circuits", "modules" or "systems" herein.

[0120] In the non-transitory computer-readable storage medium storing the method for indicating abnormal power supply timing during the server startup process, it can be, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0121] As an extension of the present application, other sub-boards that use CPLD to control the power-on timing, such as the midplane, PCIE switch board, hard disk backplane, etc., can add LEDs and then use CPLD to judge the power-on timing abnormalities to indicate the power-on timing problem points, thereby improving the efficiency of problem analysis.

[0122] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person of ordinary skill in the art may easily think of changes or substitutions within the technical scope disclosed by the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A method for indicating abnormal power supply timing during server startup, characterized in that: The steps include: After the complex programmable logic device detects the power-on instruction, it executes the pre-set power-on power-on timing control and changes the indication module function to abnormal timing indication; The complex programmable logic device detects whether the power-on sequence is completed normally, and when the power-on sequence is not completed normally, the abnormal position of the power-on sequence is displayed through the indication module, and when the power-on sequence is completed normally, the function of the indication module is restored to indicate the startup status of the basic input and output system.

2. The method for indicating abnormal power supply timing during server startup as claimed in claim 1, characterized in that: After the complex programmable logic device detects the power-on instruction, it executes the preset power-on power-on timing control, and before the step of changing the indication module function to the abnormal timing indication, it also includes the following steps: Pre-connect the power-on timing-related control signal lines of the central processing unit, each power supply control module and each logic device to the corresponding pins of the complex programmable logic device; Preset the specific timing of the timing-related control signal lines of the central processor, each power supply control module, and each logic device during the server startup process, and define the corresponding operation of each control signal line failure; Each state of the port 80 indicator light is encoded, and each control signal line fault is bound to a state code of the port 80 indicator light of the indication module and the corresponding operation of the fault, and then the binding relationship is generated into a table and stored in the complex programmable logic device.

3. The method for indicating abnormal power supply timing during server startup as claimed in claim 2, characterized in that: The specific steps for executing the preset power-on sequence control and changing the indication module function to abnormal sequence indication are as follows: Execute the specific timing of the timing-related control signal lines of the central processor, each power supply control module, and each logic device during the pre-set server startup process; Change the indicator light function of port 80 of the indicator module from basic input and output system startup status indication to abnormal timing indication.

4. The method for indicating abnormal power supply timing during server startup as claimed in claim 2, characterized in that: The complex programmable logic device detects whether the power-on sequence is completed normally, and when the power-on sequence is not completed normally, displays the abnormal position of the power-on sequence through the indication module, and when the power-on sequence is completed normally, restores the indication module function to indicate the startup state of the basic input and output system. The specific steps are: The complex programmable logic device detects whether a completion signal of the last control signal of a specific timing in the service startup process is received; If the completion signal of the last control signal is received, the function of the port 80 indicator light of the indicator module is changed from the abnormal timing indication to the basic input and output system startup status indication, and the process ends; If the completion signal of the last signal is not received, determining whether the currently executed control signal receives the completion signal within a preset time; If a completion signal is received within the preset time, the next control signal is executed and the signal detection step of the last control signal is returned to complete; If the completion signal is not received within the preset design, the currently executed control signal is taken as an abnormal signal, and the control signal line where the abnormal signal is located is taken as the abnormal position. The abnormal position is indicated by the indicator light of port 80 of the indication module, and an alarm message containing the name of the abnormal signal is generated and sent to the baseboard management controller.

5. The method for indicating abnormal power supply timing during server startup as claimed in claim 4, characterized in that: The specific steps of taking the control signal line where the abnormal signal is located as the abnormal position and indicating the abnormal position through the port 80 indicator of the indicator module are as follows: Obtain the binding relationship table, find out the port 80 indicator light status code corresponding to the abnormal signal and the control signal fault and the operation corresponding to the fault; The complex programmable logic device controls the indicator light of port 80 according to the found status code, indicates the abnormal position, and generates corresponding alarm information according to the operation corresponding to the fault and sends it to the baseboard management controller.

6. A system for indicating abnormal power supply timing during server startup, characterized in that: It includes a server mainboard, on which a complex programmable logic device, a central processing unit, a basic input and output system, an indication module, a plurality of power supply control modules and a plurality of logic devices are arranged; The complex programmable logic device is connected to the central processing unit, the indication module, each power supply control module and each logic device; The indication module is also connected to the basic input and output system; The complex programmable logic device controls the power-on sequence of the central processing unit, each power supply control module and each logic device, changes the function of the indication module, indicates the abnormal position during the execution of the power-on sequence according to the preset logic, and restores the function of the indication module after the power-on sequence is completed to indicate the startup status of the basic input and output system.

7. The system for indicating abnormal power supply timing during server startup as claimed in claim 6, characterized in that: The complex programmable logic device is also connected to a baseboard management controller; The complex programmable logic device generates alarm information according to the abnormal position of the power-on sequence execution process, and sends and displays the alarm information to the baseboard management controller.

8. The system for indicating abnormal power supply timing during server startup as claimed in claim 6, characterized in that: The indicator module uses port 80 indicator light; The complex programmable logic device is connected to the central processing unit through a first reset signal line, a first reset completion signal line, a first clock enable signal line, and a first clock completion signal line. The complex programmable logic device is connected to each power supply control module through a power supply enable signal line and a power supply completion signal line, and the complex programmable logic device is connected to each logic device through a second reset signal line, a second reset completion signal line, a second clock enable signal line, and a second clock completion signal line.

9. An electronic device, characterized in that: including a processor and a memory; The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the electronic device executes the method described in any one of claims 1 to 5.

10. A storage medium, characterized in that: The storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in any one of claims 1 to 5.

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