High-integration-level passive phase shifter based on 1-bit time sequence control of single-sideband time modulation

Abstract

The invention discloses a high-integration-level passive phase shifter based on 1-bit time sequence control of single side band time modulation. The high-integration-level passive phase shifter is provided with a differential orthogonal signal generation unit, an I-path input buffer unit, a Q-path input buffer unit, an I-path vector synthesis unit, a Q-path vector synthesis unit, an output amplification unit and a digital time sequence control unit. Radio frequency input differential signals RFin + and RFin-are connected with the differential orthogonal generation unit, the differential orthogonal generation unit is connected with the input buffer unit, vector synthesis is carried out through the I-path vector synthesis unit and the Q-path vector synthesis unit, the output end of the output amplification unit is the output end of the passive phase shifter, radio frequency output differential signals RFout + and RFout-are connected with the output end of the output amplification unit, and the output end of the output amplification unit is connected with the output end of the passive phase shifter. And the digital time sequence control unit controls insertion loss of the I-path vector synthesis unit and the Q-path vector synthesis unit, so that a digital control phase shift function is realized.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency microwave integrated circuit design, and in particular is a highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation. Background Art

[0002] The phase shifter is a key module of the phased array system. Its performance directly determines the performance of the phased array system. It realizes beam scanning by controlling the phase of the receiving or transmitting signal of each unit in the antenna array. The key indicators of the phase shifter include: phase shift range, phase shift number, phase shift accuracy, amplitude error, insertion loss, power consumption and area. In order to meet the application requirements of microwave on-chip integrated phase shifters and microwave on-chip phased array transceiver components in China, it is necessary to design and study high-performance on-chip integrated phase shifters.

[0003] Currently, common passive phase shifters usually include reflective, loaded line and switch line types. These structures have advantages in power consumption and bandwidth, but they often have disadvantages such as large insertion loss, large chip area and large phase error. Passive vector synthesis phase shifters have the advantages of small chip area, digital control and high phase control accuracy. Figure 1 The circuit architecture of the traditional passive phase shifter based on vector synthesis is given. Figure 1 In the process, the RF input signal is converted into a differential signal by a balun, and then converted into four differential orthogonal signals by an orthogonal phase shift network. Then, the I-channel and Q-channel signals are respectively vector synthesized after passing through an X-type attenuator. Finally, the RF synthesized signal is output after passing through a power synthesizer. Figure 1 In the example, the I-channel control sequence and the Q-channel control sequence control the equivalent impedance value of the X-type attenuator by switching the control sequence, thereby controlling the insertion loss of the I-channel and Q-channel attenuators respectively to control the output synthetic phase value. Assuming G I and G Q are the I and Q path insertion losses, G0 is the insertion loss of the X-type attenuator, θ is the vector synthesis phase, then G I and G Q It can be expressed as

[0004]

[0005] It can be seen from formula (1) that the phase shift accuracy of the passive vector synthesis structure is mainly limited by the insertion loss error value of the attenuator. If higher accuracy is to be achieved, more phase shift states need to be obtained to approach the ideal value, resulting in more complex digital control circuits and attenuator array circuits. The current passive vector synthesis scheme usually needs to obtain as many phase shift states as possible and select specific phase shift states from them to achieve high-precision phase shift, which can barely reach 7-bit phase shift number. If higher phase shift accuracy and phase shift number requirements need to be met, the time complexity of circuit simulation and testing will increase exponentially, and will result in a larger chip area. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the traditional passive vector synthesis phase shifter based on the X-type attenuator, and to provide a design scheme of a highly integrated passive phase shifter based on 1-bit timing control of single-sideband time modulation, which can achieve 1-bit timing control, high integration, 360° phase shift range, more than 10 bits of phase shift number, high phase shift accuracy, low amplitude deviation and high sideband suppression under low power consumption.

[0007] The technical solution to achieve the purpose of the present invention is: a highly integrated passive phase shifter with 1-bit timing control based on single-sideband time modulation, comprising: a differential orthogonal signal generating unit 1, an I-way input buffer unit 2, a Q-way input buffer unit 3, an I-way vector synthesis unit 4, a Q-way vector synthesis unit 5, an output amplification unit 6 and a digital timing control unit 7, wherein the RF input differential signal RF in + and RF in - connected to the differential orthogonal generating unit 1, the four output ends of the differential orthogonal generating unit 1 are respectively connected to the two input ports of the I-way input buffer unit 2 and the two input ports of the Q-way input buffer unit 3, the output end of the I-way input buffer unit 2 is connected to the input port of the I-way vector synthesizing unit 4, the output end of the Q-way input buffer unit 3 is connected to the input port of the Q-way vector synthesizing unit 5, the positive output of the I-way vector synthesizing unit 4 is connected to the positive output of the Q-way vector synthesizing unit 5 and then connected to the positive pole of the output amplifying unit 6 after being superimposed, the negative output of the I-way vector synthesizing unit 4 is connected to the negative output of the Q-way vector synthesizing unit 5 and then connected to the negative pole of the output amplifying unit 6, the output end of the output amplifying unit 6 is used as the output end of the passive phase shifter, and the RF output differential signal RF out + and RF out -, the output of the digital timing control unit 7 is connected to the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5, thereby realizing the digital control phase shift function.

[0008] Preferably, the I-path vector synthesis unit and the Q-path vector synthesis unit have the same switch tube gate width and fork index, but different control bits.

[0009] Preferably, the control timing of the I-path vector synthesis unit and the control timing of the Q-path vector synthesis unit are multiplexed.

[0010] Preferably, the I-path vector synthesis unit and the Q-path vector synthesis unit each have four MOS tube arrays, each array having two N-2 MOS tube with a gate width of 2, where N is the order of the time modulation technology used, and 2 N-2 The gate width ratio of the MOS tube is 1-cos(θ1):cos(θ1)-cos(θ2):cos(θ2)-cos(θ3):…:cos(θ N-1 )-cos(θ N ):cos(θ N ), where θ k =k×360 / 2 N , k=1,2,3,…,2 N-2 -1.

[0011] Preferably, the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5 respectively have 4 MOS tube arrays, using 4th-order time modulation technology, each array has MOS tubes with 4 gate widths, and the gate width ratio is 1-cos(θ1):cos(θ1)-cos(θ2):cos(θ2)-cos(θ3):cos(θ3), where θ k =k×360 / 2 4 , k=1,2,3.

[0012] Preferably, the I-channel input buffer unit 2 and the I-channel vector synthesis unit constitute an I-channel channel, the Q-channel input buffer unit 3 and the Q-channel vector synthesis unit constitute a Q-channel channel, the normalized insertion loss values ​​of the I / Q-channel channels are sin[πN / (2N)], sin[π(N-1) / (2N)], ..., sin[π / (2N)], respectively, and the control signal output by the digital timing control unit makes the I-channel channel insertion loss timing present an N-level step-type timing of a sine curve, and makes the Q-channel channel insertion loss timing present an N-level step-type timing approximating a cosine curve, so that the time t2, t1, t'2 and t'1 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, where t1 and t'1 represent the moments when the relative insertion loss of the I and Q paths is positive, t2 and t'2 represent the moments when the relative insertion loss of the I and Q paths is negative, T P is the period of the modulation function, and the pulse width τ1 with normalized insertion loss sin[π / (2N)] satisfies: τ1=(2N-1)T P / (4N), the normalized insertion loss is sin[π(N-1) / (2N)] of the pulse width τ N-1 Satisfy: τN-1 =3T P / (4N), the normalized insertion loss is sin[πN / (2N)] of the pulse width τ N Satisfy: τ N =T P / (4N).

[0013] Preferably, each MOS tube array in the I-way vector synthesis unit includes 8 MOS tubes, and the gate control signals of the MOS tube array M1 and the MOS tube array M4 are 8-bit control signals P I <7:0>, the gate control signal of MOS tube array M2 and MOS tube array M3 is the 8-bit inverted control signal P IB <7:0>, each MOS tube array is divided into 4 groups, P I <7:6> The gate width of the MOS tube controlled by is W1, P I <5:4> The gate width of the MOS tube controlled by is W2, P I <3:2> The gate width of the MOS tube controlled by is W3, P I The gate width of the MOS tube controlled by <1:0> is W4.

[0014] Preferably, each MOS tube array in the Q-path vector synthesis unit 5 includes 8 MOS tubes, and the gate control signals of the MOS tube array M1 and the MOS tube array M4 are 8-bit control signals P Q <7:0>, the gate control signal of MOS tube array M2 and MOS tube array M3 is the 8-bit inverted control signal P QB <7:0>, each MOS tube array is divided into 4 groups, P Q <7:6> The gate width of the MOS tube controlled by is W1, P Q <5:4> The gate width of the MOS tube controlled by is W2, P Q <3:2> The gate width of the MOS tube controlled by is W3, P Q The gate width of the MOS tube controlled by <1:0> is W4.

[0015] Compared with the prior art, the present invention has the following significant advantages:

[0016] (1) 1-bit timing control. The digital control circuit of the present invention only needs to input a square wave signal with a duty cycle of 50% to drive the phase shifter to realize the phase shift function, and by designing a specific X-type attenuator control timing, the I-channel control timing signal and the Q-channel control timing signal can be multiplexed or multiplexed after passing through an inverter, thereby simplifying the control signal of the X-type attenuator from a sixteen-bit control signal to an eight-bit square wave control signal with a duty cycle of 50%. The eight-bit control signal is output by a sixteen-bit frequency divider and an inverter based on a TSPC (true single-phase clock) structure, so the phase shifter proposed by the present invention can be controlled by 1-bit timing.

[0017] (2) High integration. The circuit of the present invention simplifies the complex and cumbersome digital insertion loss control circuit by designing a sixteen-frequency divider based on the TSPC structure. The phase shift function adopts a vector synthesis unit. Compared with the traditional passive phase shifter, the layout area is extremely small, and no inductor is used in the circuit, which makes the chip layout compact and greatly saves the chip area. Therefore, the present invention has the characteristics of high integration.

[0018] (3) High phase shift number. The present invention introduces time variables by changing the initial timing of the FPGA, and realizes the linear phase shift function of the passive vector synthesis structure through single-sideband time modulation technology, which effectively solves the problem of complex phase and insertion loss control operations of traditional passive vector synthesis phase shifters, greatly improves the phase shift number, and can achieve 360° phase coverage. The phase shift number of the present invention in the 1-4.5GHz frequency band can reach more than 10 bits and cover a 360° phase shift range.

[0019] (4) High phase shift accuracy. The phase shift function of the present invention is to set the transistor gate width of the MOS tube array in the vector synthesis unit to a specific proportional value, so that each time the phase shift is performed, the I path and the Q path can accurately meet the square sum condition of the vector synthesis, and the higher precision phase shift is achieved by changing the starting timing of the FPGA input timing signal. Therefore, the phase shift accuracy is also determined by the timing control accuracy of the FPGA. Compared with the traditional passive vector synthesis phase shifter, the present invention can achieve extremely high phase shift accuracy. The RMS phase shift error of the present invention in the 1-4.5GHz frequency band is 0.05-0.2° (see Fig.12 ), while the RMS phase shift error of traditional passive phase shifters based on vector synthesis is generally greater than 1°.

[0020] (5) Low amplitude deviation. The phase shift function of the present invention is achieved by FPGA providing a timing control signal to the digital control circuit. First, the overall equivalent gate width of the transistors that turn on and off each branch in each phase shift state is guaranteed to remain unchanged. At this time, as the state switches, the input and output impedances on the branch remain unchanged, thereby achieving a lower amplitude deviation. Then, the high-precision 10-bit phase shift function is achieved by changing the initial moment of the FPGA timing control signal. In each timing cycle, the circuit state of the phase shifter is completely consistent, and the amplitude does not change with the phase shift state. Therefore, the present invention has an extremely low amplitude deviation. The RMS amplitude deviation of the present invention in the 1-4.5 GHz frequency band is less than 0.02dB (see Fig.13 ), while the RMS amplitude deviation of traditional passive vector synthesis phase shifters is generally greater than 0.5dB.

[0021] (6) High sideband suppression. The present invention adopts single-sideband time modulation technology, which can suppress useless sidebands other than the 161-1 sideband by using a 4-step ladder signal equivalent to a sine / cosine signal, and can achieve a sideband suppression of 23.5dBc. Therefore, compared with the traditional time modulation device based on a 2-step ladder signal, the present invention can achieve high sideband suppression.

[0022] (7) Low power consumption. The present invention adopts a passive X-type attenuator structure as a vector synthesis unit, which has the characteristic of zero power consumption. The power consumption only exists in the input buffer stage circuit and the output amplifier, thereby effectively reducing the circuit power consumption. Therefore, the present invention has lower power consumption.

[0023] (8) The present invention can achieve 1-bit timing control, high integration, 360° phase shift range, more than 10 bits of phase shift number, high phase shift accuracy, low amplitude deviation and high sideband suppression under low power consumption, and has advantages in application in phased array systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the circuit architecture of the traditional passive phase shifter based on vector synthesis;

[0025] Figure 2 It is a circuit block diagram of a highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation of the present invention;

[0026] Figure 3 It is a circuit principle diagram of an I-way vector synthesis unit of the present invention;

[0027] Figure 4 It is a circuit principle diagram of the Q-path vector synthesis unit of the present invention;

[0028] Figure 5 The I / Q path insertion loss control timing implemented by the present invention under the standardized control timing

[0029] Figure 6 It is a circuit schematic diagram of a digital timing control unit of the present invention;

[0030] Figure 7 It is the circuit principle diagram of the TSPC basic unit of the present invention;

[0031] Figure 8 is an output logic diagram of the digital timing control unit of the present invention;

[0032] Fig. 9 It is an eight-way control timing output by the digital timing control unit of the present invention;

[0033] Fig.10 In the present invention, Fig. 9The I / Q gain timing (period is T P );

[0034] Fig.11 The phase shift curve and phase shift accuracy of the typical phase shift value of the present invention in the 1-4.5 GHz frequency band;

[0035] Fig.12 It is a partial phase shift curve and phase shift accuracy of the 10-bit phase shift in the 1-4.5 GHz frequency band of the present invention;

[0036] Fig.13 It is the amplitude curve and amplitude deviation of the present invention in the 1-4.5 GHz frequency band. DETAILED DESCRIPTION

[0037] like Figure 2 As shown, a highly integrated passive phase shifter with 1-bit timing control based on single-sideband time modulation includes: a differential orthogonal signal generating unit 1, an I-channel input buffer unit 2, a Q-channel input buffer unit 3, an I-channel vector synthesis unit 4, a Q-channel vector synthesis unit 5, an output amplification unit 6 and a digital timing control unit 7, wherein the RF input differential signal RF in + and RF in - connected to the differential orthogonal generating unit 1, the four output ends of the differential orthogonal generating unit 1 are respectively connected to the two input ports of the I-way input buffer unit 2 and the two input ports of the Q-way input buffer unit 3, the output end of the I-way input buffer unit 2 is connected to the input port of the I-way vector synthesizing unit 4, the output end of the Q-way input buffer unit 3 is connected to the input port of the Q-way vector synthesizing unit 5, the positive output of the I-way vector synthesizing unit 4 is connected to the positive output of the Q-way vector synthesizing unit 5 and then connected to the positive pole of the output amplifying unit 6 after being superimposed, the negative output of the I-way vector synthesizing unit 4 is connected to the negative output of the Q-way vector synthesizing unit 5 and then connected to the negative pole of the output amplifying unit 6, the output end of the output amplifying unit 6 is used as the output end of the passive phase shifter, and the RF output differential signal RF out + and RF out -, the output of the digital timing control unit 7 is connected to the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5, thereby realizing the digital control phase shift function.

[0038] Preferably, the I-path vector synthesis unit and the Q-path vector synthesis unit adopt an X-type attenuator structure.

[0039] Preferably, the X-type attenuator structure is achieved by making the MOS tube work in the deep triode region, and the drain and source are equivalent to a variable resistor controlled by the gate voltage, so as to realize the attenuator characteristics; and then the X-type attenuator is realized by connecting the MOS tubes in groups in an X-shaped cross-coupling manner.

[0040] The 10-bit or higher high-precision phase shifting of the present invention is achieved by changing the delay of the 1-bit square wave signal input by the digital timing control unit. Assuming that the frequency f of the square wave signal is P If you need to achieve 10-bit precision phase shift, that is, to achieve 1024 (2 10 ) phase shift state, the corresponding unit delay of the square wave signal needs to be set to 1 / (f P ×2 10 )=0.098ns, the phase changes by 360 / 2 10 =0.35°, at this time, by changing the multiple of the input unit delay, a 10-bit phase shift within 360° can be achieved.

[0041] The description of the core circuit module is as follows:

[0042] The MOS tubes in the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5 work in the deep triode region. At this time, when the gate voltage of the MOS tube changes, the drain and source of the MOS tube are equivalent to a resistor that changes with the gate voltage, and then connected in a cross-coupling manner, thereby realizing the X-type attenuator characteristics. From the MOS tube equivalent resistance formula (2), it can be seen that when other variables are controlled unchanged and only the gate width W is changed, the equivalent resistance decreases as the gate width W increases. Therefore, if the X-type attenuator needs to reduce the insertion loss, the gate width needs to be increased.

[0043]

[0044] I-way vector synthesis unit 4 Figure 3 As shown, it includes four MOS tube arrays M1, M2, M3 and M4, each MOS tube array includes 8 MOS tubes, and the gate control signals of the MOS tube array M1 and the MOS tube array M4 are 8-bit control signals P I <7:0>, the gate control signal of MOS tube array M2 and MOS tube array M3 is the 8-bit inverted control signal P IB <7:0>. Each MOS tube array is divided into 4 groups, P I <7:6> The gate width of the MOS tube controlled by is W1, P I <5:4> The gate width of the MOS tube controlled by is W2, P I <3:2> The gate width of the MOS tube controlled by is W3, P I The gate width of the MOS tube controlled by <1:0> is W4. At this time, in any phase shift state, the number of MOS tubes connected to the IN+ / IN- branch in the open state and the closed state is the same.

[0045] Q path vector synthesis unit 5 Figure 4As shown, it includes four MOS tube arrays M1, M2, M3 and M4, each MOS tube array includes 8 MOS tubes, and the gate control signals of the MOS tube array M1 and the MOS tube array M4 are 8-bit control signals P Q <7:0>, the gate control signal of MOS tube array M2 and MOS tube array M3 is the 8-bit inverted control signal P QB <7:0>. Each MOS tube array is divided into 4 groups, P Q <7:6> The gate width of the MOS tube controlled by is W1, P Q <5:4> The gate width of the MOS tube controlled by is W2, P Q <3:2> The gate width of the MOS tube controlled by is W3, P Q The gate width of the MOS tube controlled by <1:0> is W4. At this time, in any phase shift state, the number of MOS tubes connected to the IN+ / IN- branch in the open state and the closed state is the same.

[0046] The MOS tube arrays in the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5 use four different gate widths W1, W2, W3, and W4, and the gate width ratio is W1:W2:W3:W4=1-cos(θ1):cos(θ1)-cos(θ2):cos(θ2)-cos(θ3):cos(θ3)=1:2.8:4.3:5, where θ k =k×360 / 2 4 (k=1,2,3).

[0047] See also Figure 5 Here is the I / Q path insertion loss control timing (period is T P , frequency is f P ), assuming the normalized insertion loss of the 4-step ladder of time modulation is a n = sin(nπ / 8), n = 0, 1, 2, 3, 4. Taking the I-path vector synthesis unit 4 as an example, each pair of MOS transistors of the MOS array M1 and M4 on the I path will be affected by the timing control signal P I <2(4-n)+1> and P I <2(4-n)> control, the sum of the equivalent gate widths W of all turned-on MOS tubes in the M1 and M4 arrays can be calculated by formula (3) I,eff .

[0048]

[0049] Assuming that W1 is 1 at this time, Table 1 shows the I-way control signal P I <7:0> is implemented Figure 5 Table 2 shows the level state of the I-channel insertion loss control timing, and Table 2 shows the Q-channel control signal P Q<7:0> is implemented Figure 5 The level state of the Q-path insertion loss control timing is given. From Tables 1 and 2, it can be seen that through special design, the control signals can be square wave signals with a duty cycle of 50%, and the control signals can be further multiplexed: P I <0> and P Q <7> Merge, P I <1> and P Q <6> The anti-phase merger, P I <2> and P Q <5> The anti-phase merger, P I <3> and P Q <4> Merge, P I <4> and P Q <2> The anti-phase merger, P I <5> and P Q <3> Merge, P I <6> and P Q <0> The anti-phase merger, P I <7> and P Q <1> The control signals of the I-way vector synthesis unit 4 and the Q-way vector synthesis unit 5 can be simplified to an I-way 8-bit control signal. IB <7:0> and P QB <7:0> is merged and multiplexed.

[0050] Table 1

[0051]

[0052] Table 2

[0053]

[0054] Reference Figure 6 The digital timing control unit 7 is provided with TSPC trigger 1, TSPC trigger 2, TSPC trigger 3, TSPC trigger 4, TSPC trigger 5, TSPC trigger 6, TSPC trigger 7, TSPC trigger 8, inverter inv1, inverter inv2, inverter inv3, inverter inv4, inverter inv5, inverter inv6, inverter inv7 and inverter inv8. The TSPC trigger structure refers to Figure 7 When the input period is T P When the clock signal CLK is / 16, the TSPC output timing refers to Figure 8 shown.

[0055] Reference Figure 8As shown in Table 1, the 16 output terminals Bit1, Bit1N, Bit2, Bit2N, ..., Bit8, Bit8N of the digital timing control unit 7 can be directly connected to the control signal terminal P multiplexed by the I-way vector synthesis unit 4 and the Q-way vector synthesis unit 5. I <7:0>, inverted P IB <7:0>(P Q <7:0> and inverted P QB <7:0> multiplexing), specific connection method: Bit1 connects to P IB <0> , Bit1N connects to P I <0> ; Bit2 connects to P IB <1> , Bit2N connects to P I <1> ; Bit3 connects to P IB <2> , Bit3N connects to P I <2> ; Bit4 connects to P IB <4> , Bit4N connects to P I <4> ; Bit5 connects to P IB <6> , Bit5N connects to P I <6> ; Bit6 connects to P I <7> , Bit6N connects to P IB <7> ; Bit7 connects to P I <5> , Bit6N connects to P IB <5> ; Bit8 connects to P I <3> , Bit8N connects to P IB <3> .

[0056] See also Fig. 9 Here is the timing of the eight-way control signal multiplexed by the I-way vector synthesis unit 4 and the Q-way vector synthesis unit 5 (the inverted signal is not given). Fig.10 , given here in Fig. 9 The I / Q path insertion loss control timing (period is T P , frequency is f P ), the design principle of the output control timing is: make the I-channel insertion loss timing present a four-level step timing that is approximately a sine curve, make the Q-channel insertion loss timing present a four-level step timing that is approximately a cosine curve, and make the times t1, t2, t'1 and t'2 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, t1 and t'1 represent the moments when the relative insertion loss of the I and Q paths is positive, t2 and t'2 represent the moments when the relative insertion loss of the I and Q paths is negative, and make the normalized insertion loss be sin(π / 2) pulse width τ4, the normalized insertion loss be sin(3π / 8) pulse width τ3, the normalized insertion loss be sin(π / 4) pulse width τ2 and the normalized insertion loss be sin(π / 8) pulse width τ1, τ3=3τ4=3T P / 16,τ2=5τ4=5T P / 16, τ1=7τ4=7T P / 16. When the I / Q path insertion loss timing is Fig.10 As shown, the total insertion loss of the passive phase shifter can be expressed as: G I (t)+jG Q (t), after Fourier series expansion, we can get:

[0057]

[0058] In formula (4), A k is the kth sideband (kf P ) (k=0,±1,…,±∞), under the above timing conditions, its formula is derived as follows:

[0059]

[0060]

[0061] From equation (5), we can see that in the required -1 sideband, the complex amplitude A k The modulus value is constant, The time-varying vector synthesis phase term of the present invention changes the value of time t1, when t1∈[-7T P / 32,25T P / 32], a full 360° phase coverage can be achieved linearly. In addition, the useless sidebands other than the 161-1 sideband are effectively suppressed, and the power suppression ratio of the largest useless sideband (+15 sideband) reaches -23.5dBc.

[0062] See also Fig.11 It can be seen that the phase shift curve of the present invention in the 1-4.5 GHz frequency band does not change with frequency. Fig.11 The 16 curves in the figure are typical values ​​of phase shift.

[0063] Reference Fig.12It can be seen that this is the phase shift curve when the 1-bit square wave signal input by FPGA to the digital timing control unit is shifted by 0.098*kns (the square wave signal frequency is 10MHz). The error between it and the ideal value of 0.35*k° is less than 0.2° in the 1-4.5GHz frequency band, where k=0,1,2,3,…,15. This result shows that the phase shift number of the present invention reaches more than 10bit. At the same time, the phase shift accuracy of the present invention in the 1-4.5GHz frequency band is extremely high, and the RMS phase shift error is 0.05-0.2°, while the RMS phase shift error of the traditional passive phase shifter based on vector synthesis is generally greater than 1°.

[0064] See also Fig.13 It can be seen that the amplitude curves of different phase shift states in the 1-4.5 GHz frequency band of the present invention are basically overlapped, and the RMS amplitude deviation is less than 0.02 dB, while the RMS amplitude deviation of the traditional passive phase shifter based on vector synthesis is generally greater than 0.5 dB.

[0065] Furthermore, in order to suppress more useless sidebands, an N-order time modulation control sequence (period is T P , frequency is f P ), in the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5, MOS tubes satisfying a specific ratio gate width ratio can be added, and the normalized insertion loss values ​​of the I / Q-path channels are respectively sin[πN / (2N)], sin[π(N-1) / (2N)] and sin[π / (2N)], and then the digital timing control unit 7 is used to output a specific control signal, so that the I-path insertion loss timing presents an N-level step-type timing that is approximately a sine curve, and the Q-path insertion loss timing presents an N-level step-type timing that is approximately a cosine curve, and reference is made to Fig. 9 So that the time t2, t1, t'2 and t'1 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, where t1 and t'1 represent the moments when the relative insertion loss of the I and Q paths is positive, t2 and t'2 represent the moments when the relative insertion loss of the I and Q paths is negative, T P is the period of the modulation function, and the pulse width τ1 with normalized insertion loss sin[π / (2N)] satisfies: τ1=(2N-1)T P / (4N), the normalized insertion loss is sin[π(N-1) / (2N)] of the pulse width τ N-1 Satisfy: τ N-1 =3T P / (4N), the normalized insertion loss is sin[πN / (2N)] of the pulse width τ N Satisfy: τ N =T P / (4N).

[0066] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A highly integrated passive phase shifter based on 1-bit timing control of single-sideband time modulation, characterized in that: include: Differential orthogonal signal generating unit 1, I-way input buffer unit 2, Q-way input buffer unit 3, I-way vector synthesis unit 4, Q-way vector synthesis unit 5, output amplification unit 6 and digital timing control unit 7, RF input differential signal RF in + and RF in - connected to the differential orthogonal generating unit 1, the four output ends of the differential orthogonal generating unit 1 are respectively connected to the two input ports of the I-way input buffer unit 2 and the two input ports of the Q-way input buffer unit 3, the output end of the I-way input buffer unit 2 is connected to the input port of the I-way vector synthesizing unit 4, the output end of the Q-way input buffer unit 3 is connected to the input port of the Q-way vector synthesizing unit 5, the positive output of the I-way vector synthesizing unit 4 is connected to the positive output of the Q-way vector synthesizing unit 5 and then connected to the positive pole of the output amplifying unit 6 after being superimposed, the negative output of the I-way vector synthesizing unit 4 is connected to the negative output of the Q-way vector synthesizing unit 5 and then connected to the negative pole of the output amplifying unit 6, the output end of the output amplifying unit 6 is used as the output end of the passive phase shifter, and the RF output differential signal RF out + and RF out -, the output of the digital timing control unit 7 is connected to the I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5, thereby realizing the digital control phase shift function.

2. The highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation according to claim 1, characterized in that: The I-path vector synthesis unit and the Q-path vector synthesis unit have the same switch tube gate width and fork index, but different control bits.

3. The highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation according to claim 1, characterized in that: The control timing of the I-path vector synthesis unit and the control timing of the Q-path vector synthesis unit are multiplexed.

4. The highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation according to claim 1, characterized in that: The I-path vector synthesis unit and the Q-path vector synthesis unit each have four MOS tube arrays, each array having two N-2 MOS tube with a gate width of 2, where N is the order of the time modulation technology used, and 2 N-2 The gate width ratio of the MOS tube is 1-cos(θ1):cos(θ1)-cos(θ2):cos(θ2)-cos(θ3):…:cos(θ N-1 )-cos(θ N ):cos(θ N ), where θ k =k×360 / 2 N , k=1,2,3,…,2 N-2 -1.

5. The highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation according to claim 1, characterized in that: The I-path vector synthesis unit 4 and the Q-path vector synthesis unit 5 respectively have 4 MOS tube arrays, using 4-order time modulation technology, each array has MOS tubes with 4 gate widths, and the gate width ratio is 1-cos(θ1):cos(θ1)-cos(θ2):cos(θ2)-cos(θ3):cos(θ3), where θ k =k×360 / 2 4 , k=1,2,3.

6. The highly integrated passive phase shifter with 1-bit timing control based on single sideband time modulation according to claim 4 or 5, characterized in that: The I-channel input buffer unit 2 and the I-channel vector synthesis unit constitute an I-channel channel, the Q-channel input buffer unit 3 and the Q-channel vector synthesis unit constitute a Q-channel channel, the normalized insertion loss values ​​of the I / Q-channel channels are sin[πN / (2N)], sin[π(N-1) / (2N)], ..., sin[π / (2N)], respectively, and the control signal output by the digital timing control unit makes the I-channel channel insertion loss timing present an N-level step-type timing of a sine curve, and makes the Q-channel channel insertion loss timing present an N-level step-type timing approximating a cosine curve, so that the time t2, t1, t'2 and t'1 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, where t1 and t'1 represent the moments when the relative insertion loss of the I and Q paths is positive, t2 and t'2 represent the moments when the relative insertion loss of the I and Q paths is negative, T P is the period of the modulation function, and the pulse width τ1 with normalized insertion loss sin[π / (2N)] satisfies: τ1=(2N-1)T P / (4N), the normalized insertion loss is sin[π(N-1) / (2N)] of the pulse width τ N-1 Satisfy: τ N-1 =3T P / (4N), the normalized insertion loss is sin[πN / (2N)] of the pulse width τ N Satisfy: τ N =T P / (4N).

7. The highly integrated passive phase shifter with 1-bit timing control based on single sideband time modulation according to claim 4 or 5, characterized in that: Each MOS tube array in the I-way vector synthesis unit includes 8 MOS tubes, and the gate control signals of the MOS tube array M1 and the MOS tube array M4 are 8-bit control signals P I <7:0>, the gate control signal of MOS tube array M2 and MOS tube array M3 is 8-bit inverted control signal P IB <7:0>, each MOS tube array is divided into 4 groups, P I <7:6> The gate width of the MOS tube controlled by is W1, P I <5:4> The gate width of the MOS tube controlled by is W2, P I <3:2> The gate width of the MOS tube controlled by is W3, P I The gate width of the MOS tube controlled by <1:0> is W4.

8. The highly integrated passive phase shifter with 1-bit timing control based on single sideband time modulation according to claim 4 or 5, characterized in that: Each MOS tube array in the Q-path vector synthesis unit 5 includes 8 MOS tubes, and the gate control signals of the MOS tube array M1 and the MOS tube array M4 are 8-bit control signals P Q <7:0>, the gate control signal of MOS tube array M2 and MOS tube array M3 is the 8-bit inverted control signal P QB <7:0>, each MOS tube array is divided into 4 groups, P Q <7:6> The gate width of the MOS tube controlled by is W1, P Q <5:4> The gate width of the MOS tube controlled by is W2, P Q <3:2> The gate width of the MOS tube controlled by is W3, P Q The gate width of the MOS tube controlled by <1:0> is W4.

9. The highly integrated passive phase shifter based on 1-bit timing control of single sideband time modulation according to claim 1, characterized in that: The I-path vector synthesis unit and the Q-path vector synthesis unit both adopt an X-type attenuator structure.

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