Single-core hit rate extraction method for simulating permutation instruction

Abstract

The invention discloses a mononuclear hit rate extraction method for simulating a permutation instruction, which belongs to the technical field of real-time embedded system application, and is characterized by comprising the following steps: S1, modeling a processor cache to obtain a cache model; s2, performing stream analysis on a to-be-analyzed program to determine an instruction stream, classifying each instruction according to the type, and predicting the position of each instruction in the cache model; and S3, determining a core memory access frequency for LRU replacement simulation, and simulating interference when other cores access the shared cache through a preset frequency insertion null instruction to obtain a single-core hit rate simulation result. By simulating cache interference in a processor and simulating LRU replacement, the instruction hit rate of the shared cache level is accurately analyzed, and therefore accurate and reliable performance evaluation can be provided for a real-time system.

Description

Technical Field

[0001] The invention relates to the technical field of real-time embedded system applications, and in particular to a single-core hit rate extraction method for simulating a replacement instruction. Background Art

[0002] WCET, or the worst-case execution time, is one of the key parameters for evaluating system performance and reliability. It indicates the longest time required for the target program to execute on a specific hardware platform after considering all possible situations. The use of a multi-core hierarchical CPU architecture in today's embedded systems can greatly improve computing performance. However, while performance is improved, the difficulty of analyzing WCET is also greatly increased. For real-time systems, the response time of the system is of particular concern. For example, both airborne and vehicle-mounted situations require the program to respond in a timely manner within the specified time. If the task does not respond within the specified time, serious consequences may result. Therefore, the analysis of WCET needs to be reliable and close to the true value.

[0003] There are two methods for calculating WCET: static analysis and dynamic analysis.

[0004] Static analysis is a technology based on program code. It calculates the execution time of a program under the most unfavorable conditions by analyzing the instructions, loops, conditional branches and other elements in the program. Some common static analysis methods include flow analysis, low-level analysis, valuation and calculation.

[0005] In contrast, dynamic analysis methods analyze the program while it is actually running, and calculate the worst-case execution time (WCET) of the program by monitoring the program's execution and performance indicators. Common examples of dynamic analysis methods include time slice timing, hardware performance counters, and simulators.

[0006] These two methods provide different perspectives to evaluate the performance characteristics of a program. Static analysis is mainly based on the structure and properties of the program code, while dynamic analysis focuses on the actual running behavior and performance indicators of the program.

[0007] The following problems exist in the current multi-core WCET analysis method: Hit rate analysis of shared cache is difficult: In a multi-core system, there may be a shared cache, usually a L2 cache or L3 cache, shared by multiple cores. In WCET analysis, the instruction hit rate in the shared cache needs to be considered because it affects the performance of multiple cores. If multiple cores compete for the same cache resources at the same time, performance may be degraded.

[0008] It is difficult to obtain the memory access flow of each core in a multi-core system: In a multi-core system, the memory access process of each core is complicated because it is necessary to consider multiple factors such as parallelism, hierarchical cache structure, shared resources, cache consistency, and performance optimization. When calculating WCET in static analysis, timing information analysis is crucial for multi-core processor cores. In particular, in the cache modeling process of the processor, it is key to model the cache access behavior in the program in detail to determine cache hits and cache misses, as well as to estimate the additional delays associated with cache access. The impact of cache on program execution time is particularly significant in modern computer systems, so the task at this stage is to ensure accurate determination of the cache hits of instructions.

[0009] However, in reality, some programs may run on a single core, while the specific running conditions on other cores are unknown. In this case, it becomes very complicated to analyze the instruction hits in the shared cache area in the multi-core hierarchical architecture, which increases the uncertainty and difficulty of the analysis, and sometimes even makes it impossible to carry out the WCET analysis of the program.

[0010] A Chinese patent document with publication number CN115658344A and publication date January 31, 2023 discloses a CPU shared cache partitioning method for real-time tasks of embedded systems, characterized in that the CPU shared cache partitioning method is applied to multi-core multi-threaded real-time task cache behavior prediction to formulate a dynamic partitioning strategy for shared cache of embedded real-time systems, specifically including the following steps: For multi-core and multi-threaded real-time cache tasks, a cache behavior prediction model is built to perform the cache behavior prediction process; Determine the input parameters of the cache behavior prediction model, the input parameters include a cache service state migration matrix and an initial cache state parameter; wherein the cache service state migration matrix is ​​composed of MN×MN migration probability elements; the initial cache state parameter is a shared cache state parameter when the embedded system is in an initial state and performs tasks normally; Determine the model output parameters, the model output parameters include cache usage rate, cache loss rate, process conflict probability; wherein the cache usage rate is the percentage of cache capacity occupied by each real-time task on average; the cache loss rate is the probability of average cache access failure each time; the process conflict probability includes the probability of shared cache access conflict between task processes due to the failure of the real-time task itself during the execution of the real-time task process, and the probability of task conflict caused by process access to shared cache during the execution of the system task; A dynamic partitioning strategy for shared cache of an embedded real-time system is formulated based on the output parameters of the model.

[0011] The patent document discloses a CPU shared cache partitioning method for real-time tasks in embedded systems, and proposes a cache behavior prediction model to predict cache miss rate, usage rate, cache conflicts between processes, and other cache behaviors. The shared cache partitioning method that introduces real-time task thread weight vectors can improve the CPU cache resource utilization of embedded systems in multi-core and multi-threaded environments. However, it cannot simulate cache interference in multi-core processors, and cannot analyze the instruction hit rate of the shared cache level, so it cannot provide accurate and reliable performance evaluation for real-time systems. Summary of the invention

[0012] In order to overcome the defects of the above-mentioned prior art, the present invention provides a single-core hit rate extraction method for simulating replacement instructions. The present invention simulates cache interference in the processor and simulates LRU replacement to accurately analyze the instruction hit rate of the shared cache level, thereby providing accurate and reliable performance evaluation for real-time systems.

[0013] The present invention is achieved through the following technical solutions: A single-core hit rate extraction method for simulating a replacement instruction, characterized by comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0014] In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

[0015] In the step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

[0016] The data structure specifically refers to a graph or a tree.

[0017] In step S12, full associativity specifically means that an address in the main memory is mapped into any cache line.

[0018] In step S12, group associativity specifically means that both the main memory and the cache are grouped, the number of blocks in a group in the main memory is the same as the number of groups in the cache, direct mapping is used between groups, and full associative mapping is used within a group.

[0019] In step S12, direct mapping specifically means that the cache line to which the memory address is mapped is fixed.

[0020] In the step S13, determining the size of each level of cache means obtaining it through the technical manual of the processor or a hardware feature query tool.

[0021] In the step S2, determining the instruction stream specifically refers to obtaining the instruction stream through a performance analysis tool.

[0022] In step S3, inserting empty instructions specifically refers to adding empty instructions simulating other cores accessing the shared cache to simulate interference in the instruction stream according to a preset frequency.

[0023] In step S3, the mode and frequency of other cores accessing the shared cache are determined by application scenarios or workload characteristics.

[0024] The LRU described in the present invention refers to a cache replacement strategy, which is used to determine which data blocks are replaced when the cache is full to make room for new data blocks; the data blocks that have been least recently accessed are considered the most likely candidates to be replaced.

[0025] The shared cache described in the present invention refers to a cache type in computer architecture design, which is used in a multi-core processor system. In this architecture, multiple processor cores share the same level of cache, usually a second-level cache or a third-level cache.

[0026] The control flow graph described in the present invention refers to a graph representing the program control flow, wherein each node represents a basic block, that is, a group of continuous instructions without entering or leaving branches, and each edge represents a possible process transfer.

[0027] The hardware characteristic query tool described in the present invention refers to CPU detection software.

[0028] The performance analysis tool described in the present invention refers to a dynamic memory detection tool.

[0029] The basic principles of the present invention are as follows: Processor cache hierarchical modeling: Determine the cache hierarchy and cache size of the processor. In traditional multi-core processors, it is usually a multi-level structure, that is, each core has its own private cache, and all cores have a shared cache. The private cache can only be accessed by the core bound to it, while the shared cache can be accessed by all cores as a shared resource. After obtaining the above information, an abstract cache model can be established to simulate the life activities of each instruction in the cache.

[0030] Modeling of cached data storage: Determine the data storage method. After the subsequent program flow analysis obtains the instruction stream, each instruction can be mapped to the corresponding cache entry through the address mapping rules, which is used to perform operations such as storing in the cache, replacing the cache, or determining whether the new instruction exists in the cache when it arrives.

[0031] Program flow analysis to be analyzed Determine the instruction flow of the program to be analyzed and obtain the order of instructions arriving at the cache for subsequent instruction hit rate analysis.

[0032] Instruction decoding, decoding the code into the corresponding instruction sequence; Build a control flow graph. Build the control flow graph of the program through static code analysis. The control flow graph represents the various control flows, conditional statements, and loop structures in the program.

[0033] Determine the memory access frequency of other cores for LRU replacement simulation Assuming that other cores access the shared cache at a stable and continuous frequency, the memory access frequency of other cores is assumed through the task type, and the interference of other cores to the core to be analyzed when accessing the shared cache is simulated by inserting empty instructions in the instruction stream according to the frequency to preempt the shared cache.

[0034] Using the LRU algorithm at the L2 cache level, when the running status of other cores is unknown, by maintaining an abstract L2 cache table, it is assumed that the access behavior of other cores to the L2 cache is uniform and stable during the program running time, and the instructions they run are mutually exclusive for the core being analyzed, and are continuously output in the form of clock pulses to simulate the access to the L2 cache. Such empty instructions can be replaced by the instructions stored in the original cache through the LRU algorithm to achieve the influence of other cores on the core being analyzed. By executing the LRU algorithm on the abstract L2 cache table, the hit status of the instructions running on the core being analyzed is obtained, thereby completing the hit classification of the instructions.

[0035] The beneficial effects of the present invention are mainly manifested in the following aspects: 1. The present invention, S1, models the processor cache to obtain a cache model; S2, performs flow analysis on the program to be analyzed to determine the instruction flow, classifies each instruction by type, and predicts the position of each instruction in the cache model; S3, determines the core memory access frequency for LRU replacement simulation, inserts empty instructions at a preset frequency to simulate the interference when other cores access the shared cache, and obtains a single-core hit rate simulation result. Compared with the prior art, by simulating cache interference in the processor and simulating LRU replacement, the instruction hit rate of the shared cache level is accurately analyzed, thereby providing accurate and reliable performance evaluation for real-time systems.

[0036] 2. The present invention, by abstracting the core of a multi-core processor, simulates the interference of other cores on the core to be analyzed, and uses a pulse simulation LRU replacement algorithm to operate on the shared cache level, and can accurately analyze the instruction hit rate of the shared cache level.

[0037] 3. The present invention is suitable for extracting the hit rate of pulse simulation replacement instructions of the LRU strategy under a multi-core hierarchical cache architecture, and can solve the problem of difficulty in analyzing the hit rate of a single core under a multi-core architecture.

[0038] 4. The present invention can effectively analyze the execution of a single core in a multi-core environment by simulating cache interference in the processor and simulating LRU replacement, thereby providing more accurate performance evaluation for real-time systems.

[0039] 5. The present invention provides more accurate data support for WCET analysis by deeply understanding and analyzing the execution status of a single core in a multi-core environment.

[0040] 6. The present invention can accurately capture the single-core hit rate in a multi-core environment and simulate the interference between different cores, providing strong support for performance optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 It is a flowchart of the present invention. DETAILED DESCRIPTION

[0042] Example 1 See also Figure 1 , a single-core hit rate extraction method for simulating a replacement instruction, comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0043] This embodiment is the most basic implementation method. Compared with the prior art, it simulates cache interference in the processor and simulates LRU replacement to accurately analyze the instruction hit rate of the shared cache level, thereby providing accurate and reliable performance evaluation for real-time systems.

[0044] Example 2 See also Figure 1 , a single-core hit rate extraction method for simulating a replacement instruction, comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0045] In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

[0046] Preferably, in step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

[0047] The data structure specifically refers to a graph.

[0048] This embodiment is a preferred implementation method. It abstracts the multi-core processor core, simulates the interference of other cores on the core to be analyzed, and uses a pulse simulation LRU replacement algorithm to operate on the shared cache level. It can accurately analyze the instruction hit rate of the shared cache level.

[0049] Example 3 See also Figure 1 , a single-core hit rate extraction method for simulating a replacement instruction, comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0050] In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

[0051] In the step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

[0052] The data structure specifically refers to a tree.

[0053] In step S12, full associativity specifically means that an address in the main memory is mapped into any cache line.

[0054] In step S12, group associativity specifically means that both the main memory and the cache are grouped, the number of blocks in a group in the main memory is the same as the number of groups in the cache, direct mapping is used between groups, and full associative mapping is used within a group.

[0055] This embodiment is another preferred implementation method, which is suitable for extracting the hit rate of pulse simulation replacement instructions of the LRU strategy under a multi-core hierarchical cache architecture, and can solve the problem of difficulty in analyzing the hit rate of a single core under a multi-core architecture.

[0056] Example 4 See also Figure 1 , a single-core hit rate extraction method for simulating a replacement instruction, comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0057] In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

[0058] In the step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

[0059] The data structure specifically refers to a tree.

[0060] Further preferably, in step S12, full associativity specifically means that an address in the main memory is mapped into any cache line.

[0061] In step S12, group associativity specifically means that both the main memory and the cache are grouped, the number of blocks in a group in the main memory is the same as the number of groups in the cache, direct mapping is used between groups, and full associative mapping is used within a group.

[0062] In step S12, direct mapping specifically means that the cache line to which the memory address is mapped is fixed.

[0063] In the step S13, determining the size of each level of cache means obtaining it through the technical manual of the processor or a hardware feature query tool.

[0064] This embodiment is another preferred implementation method. By simulating cache interference in the processor and simulating LRU replacement, it is possible to effectively analyze the execution of a single core in a multi-core environment, thereby providing a more accurate performance evaluation for the real-time system.

[0065] Example 5 See also Figure 1 , a single-core hit rate extraction method for simulating a replacement instruction, comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0066] In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

[0067] In the step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

[0068] The data structure specifically refers to a tree.

[0069] In step S12, full associativity specifically means that an address in the main memory is mapped into any cache line.

[0070] In step S12, group associativity specifically means that both the main memory and the cache are grouped, the number of blocks in a group in the main memory is the same as the number of groups in the cache, direct mapping is used between groups, and full associative mapping is used within a group.

[0071] In step S12, direct mapping specifically means that the cache line to which the memory address is mapped is fixed.

[0072] In the step S13, determining the size of each level of cache means obtaining it through the technical manual of the processor or a hardware feature query tool.

[0073] In the step S2, determining the instruction stream specifically refers to obtaining the instruction stream through a performance analysis tool.

[0074] This embodiment is another preferred implementation method, which provides more accurate data support for WCET analysis by deeply understanding and analyzing the execution status of a single core in a multi-core environment.

[0075] Example 6 See also Figure 1 , a single-core hit rate extraction method for simulating a permutation instruction, comprising the following steps: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

[0076] In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

[0077] In the step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

[0078] The data structure specifically refers to a tree.

[0079] In step S12, full associativity specifically means that an address in the main memory is mapped into any cache line.

[0080] In step S12, group associativity specifically means that both the main memory and the cache are grouped, the number of blocks in a group in the main memory is the same as the number of groups in the cache, direct mapping is used between groups, and full associative mapping is used within a group.

[0081] In step S12, direct mapping specifically means that the cache line to which the memory address is mapped is fixed.

[0082] In the step S13, determining the size of each level of cache means obtaining it through the technical manual of the processor or a hardware feature query tool.

[0083] More preferably, in step S2, determining the instruction stream specifically refers to obtaining the instruction stream through a performance analysis tool.

[0084] In step S3, inserting empty instructions specifically refers to adding empty instructions simulating other cores accessing the shared cache to simulate interference in the instruction stream according to a preset frequency.

[0085] In step S3, the mode and frequency of other cores accessing the shared cache are determined by application scenarios or workload characteristics.

[0086] This embodiment is the best implementation method, which can accurately capture the single-core hit rate in a multi-core environment and simulate the interference between different cores, providing strong support for performance optimization.

[0087] The single-core hit rate extraction of the present invention is specifically described below: Hierarchical modeling of processor cache: Assume that the processor has two levels of cache, where the first level cache is the private cache of each core with a size of 32KB, and the second level cache is the cache shared by all cores with a size of 2MB.

[0088] Modeling of cache data storage: Assume that the first-level cache is direct-mapped and the second-level cache is 4-way set associative.

[0089] In the L1 cache, each memory address has a fixed location; whereas in the L2 cache, a memory address can be mapped to any of 4 possible locations.

[0090] Instruction decoding, decode the code into the corresponding instruction sequence, and build a control flow graph, including loop header, loop body and loop end. The loop is executed 10,000 times, and the overall impact of 10,000 iterations is considered.

[0091] Determine the memory access frequency of other cores for LRU replacement simulation. Assume that other cores access the L2 cache once every two instruction cycles. In the instruction stream, insert an empty instruction after every two instructions to simulate other cores accessing the L2 cache. By simulating the execution of this new instruction stream in the above cache structure, whenever an empty instruction is encountered, simulate a L2 cache access and update the cache status according to the LRU policy, the hit rate of a single core can be calculated.

Claims

1. A single-core hit rate extraction method for simulating a replacement instruction, characterized in that: The following steps are involved: S1. Model the processor cache to obtain a cache model; S2, performing flow analysis on the program to be analyzed to determine the instruction flow, classify each instruction by type, and predict the location of each instruction in the cache model; S3. Determine the core memory access frequency for LRU replacement simulation, insert empty instructions at a preset frequency to simulate the interference of other cores accessing the shared cache, and obtain the single-core hit rate simulation result.

2. The single-core hit rate extraction method of a simulated replacement instruction according to claim 1, characterized in that: In step S1, modeling the processor cache specifically includes: S11, determining a cache hierarchy structure of a processor; S12, determining whether the data storage mode of the cache is fully associative, set associative or direct mapping; S13. Determine the size of cache at each level.

3. The single-core hit rate extraction method of a simulated replacement instruction according to claim 2, characterized in that: In the step S11, determining the cache hierarchy structure of the processor specifically refers to obtaining cache hierarchy data through a hardware feature query tool or a technical manual of the processor, and using a data structure to describe the shared cache and the private cache of each core.

4. The single-core hit rate extraction method of a simulated replacement instruction according to claim 3 is characterized in that: The data structure specifically refers to a graph or a tree.

5. The single-core hit rate extraction method of a simulated replacement instruction according to claim 2, characterized in that: In step S12, full associativity specifically means that an address in the main memory is mapped into any cache line.

6. The single-core hit rate extraction method of a simulated replacement instruction according to claim 2, characterized in that: In step S12, group associativity specifically means that both the main memory and the cache are grouped, the number of blocks in a group in the main memory is the same as the number of groups in the cache, direct mapping is used between groups, and full associative mapping is used within a group.

7. The single-core hit rate extraction method of the simulated replacement instruction according to claim 2 is characterized in that: In step S12, direct mapping specifically means that the cache line to which the memory address is mapped is fixed.

8. The single-core hit rate extraction method of the simulated replacement instruction according to claim 2 is characterized in that: In the step S13, determining the size of each level of cache means obtaining it through the technical manual of the processor or a hardware feature query tool.

9. The single-core hit rate extraction method of the simulated replacement instruction according to claim 1, characterized in that: In the step S2, determining the instruction stream specifically refers to obtaining the instruction stream through a performance analysis tool.

10. The single-core hit rate extraction method of simulating a replacement instruction according to claim 1, characterized in that: In step S3, inserting empty instructions specifically refers to adding empty instructions simulating other cores accessing the shared cache to simulate interference in the instruction stream according to a preset frequency.

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