Cache resource configuration device, memory access control device and chip

Abstract

The invention relates to a Cache resource configuration device, a memory access control device and a chip, and the device comprises a receiving module which is used for receiving an access request transmitted by a peripheral, obtaining a peripheral id and virtual address data according to the access request, obtaining a PARTID according to the peripheral id, and sending the PARTID and the virtual address data to an access monitoring module; the access monitoring module is used for receiving the PARTID and the virtual address data, counting the access flow of the cache partition corresponding to the PARTID in the current period according to the virtual address data, sending the virtual address data to the group association Cache, and sending the access flow to the capacity adjusting module; and the partition capacity adjusting module is used for dynamically adjusting the allocation capacity of the plurality of cache partitions periodically according to the access traffic of the plurality of cache partitions in the current period. According to the method and the device, the effective utilization rate of the group associative Cache resources can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit development, and in particular to a cache resource configuration device, a memory access control device and a chip. Background Art

[0002] In a system that supports an Input / Output Memory Management Unit (IOMMU) or System Memory Management Unit (SMMU), the IOMMU or SMMU will provide address services to each peripheral. When the peripheral accesses memory, it provides a virtual address. After the virtual address is translated into a physical address by the IOMMU or SMMU, the memory is accessed. In this process, the IOMMU or SMMU performs address translation. In order to improve the efficiency of peripheral memory access, a common processing technology is to set up an address translation cache unit (Translation Local Buffer, TLB) inside the IOMMU or SMMU. After the IOMMU or SMMU performs an address translation, the information related to this address translation will be cached in the TLB. The next time the address translation of the same page is performed, if the relevant entry in the TLB is hit, the physical address can be directly obtained and the address translation process can be skipped, reducing the memory access delay introduced by the peripheral due to address translation.

[0003] Since IOMMU or SMMU exists in the domain peripherals, there may be a situation where multiple peripherals share one SMMU. At this time, different peripherals will share the TLB in IOMMU or SMMU. At the same time, in order to speed up the search of peripherals into the cache, the TLB is generally set to a group-associative structure. If all peripherals can use all TLBs, when multiple peripherals access the same virtual address at the same time, the cache lines of the corresponding group will be frequently replaced, while the cache line usage rate of the remaining groups is very low. The common solution is to use the transmitted sideband signal (usually statically configured by software) to carry a small amount of information to determine in which cache line the relevant address translation information of the peripheral will be cached, or to partition the TLB through software so that a specific peripheral can only use the cache line in the TLB of a specific partition. However, once this configuration takes effect, it does not support modification when the IOMMU or SMMU is working, that is, it is a static configuration. When the IOMMU or SMMU is working, the density of the address streams sent by each peripheral to the IOMMU or SMMU is different and not balanced, and there is uncertainty in time and space. Using static configuration may cause a peripheral to have to replace cachelines for a period of time due to the small number of available cachelines, which means that memory access and address translation processes need to be performed all the time. However, other peripherals may not need address translation during this period of time. The cachelines allocated to them cannot be reallocated to other processes or peripherals because they were previously occupied, and are in an idle state, reducing the effective use of the cache. At the same time, when the software configures the partitions twice, it may be necessary to invalidate the content originally cached in the cache. When the peripheral accesses memory later, it needs to re-access the memory, which has low access efficiency. Summary of the invention

[0004] The purpose of this application is to provide a cache resource configuration device, a memory access control device and a chip to improve the effective utilization rate of set-associative cache resources.

[0005] To achieve the above-mentioned purpose, according to a first aspect of the present application, a Cache resource configuration device is provided, comprising: A receiving module, used for receiving an access request transmitted by a peripheral device, obtaining a peripheral device ID and virtual address data according to the access request, obtaining a PARTID according to the peripheral device ID, and sending the PARTID and virtual address data to an access monitoring module; An access monitoring module, used for receiving the PARTID and virtual address data, counting the access traffic of the cache partition corresponding to the PARTID in the current cycle according to the virtual address data, sending the virtual address data to the set associative Cache, and sending the access traffic to the capacity adjustment module; wherein the set associative Cache includes a plurality of cache partitions; The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of the multiple cache partitions in the current cycle.

[0006] According to a second aspect of the present application, a memory access control device is provided, comprising an address translation unit, a set associative cache, and a cache resource configuration device according to the first aspect of the present application; The address translation unit is used to receive the access request transmitted by the peripheral device and forward the access request to the Cache resource configuration device; The group-associative cache includes a cache controller and a cache memory, wherein the cache memory includes a plurality of groups, and each group includes a plurality of cache lines; The cache controller is used to determine the group corresponding to the virtual address data in the group-associative cache according to the virtual address data, and determine whether there is physical address data corresponding to the virtual address data in the corresponding group, if so, take out the hit physical address data from the cacheline of the corresponding group and send it to the memory controller to access the memory, if not, return a miss result to the address translation unit; The address translation unit is further used to obtain virtual address data according to the access request based on the miss result, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller; The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it.

[0007] According to the third aspect of the present application, a chip is provided, comprising the cache resource configuration device according to the first aspect of the present application, or comprising the memory access control device according to the second aspect of the present application.

[0008] Implementing the above-mentioned cache resource configuration device, memory access control device and chip has the following beneficial effects: (1) The access monitoring module counts the access traffic of each cache partition and dynamically adjusts the allocated capacity of the cache partition according to the access traffic. This allows the set-associative cache resources to be dynamically adjusted according to the actual access requirements of multiple peripherals, so that the set-associative cache resources can be more reasonably allocated to each peripheral. This can adapt to the situation where multiple peripherals share one IOMMU or SMMU, solving the problem of low utilization of set-associative cache resources caused by static configuration. (2) Multiple peripherals (physical devices or virtual devices) may access the same storage partition. Therefore, by introducing PARTID to classify multiple peripherals, the monitoring of peripheral access behavior can be simplified, thereby reducing the hardware design resources required for the access monitoring module and reducing the difficulty of hardware design. (3) Since the set-associative cache resource configuration is dynamic, the invalidation operation of the set-associative cache content is reduced when the software performs the previous and subsequent partition configurations, thereby improving the access efficiency of the set-associative cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A schematic diagram of the framework structure of a Cache resource configuration device in an embodiment of the present application.

[0011] Figure 2 This is a flowchart of the first step of adjusting the cache partition allocation capacity in one embodiment of the present application.

[0012] Figure 3 This is a flowchart of the second step of adjusting the cache partition allocation capacity in one embodiment of the present application.

[0013] Figure 4 A schematic diagram of the framework structure of a memory access control device in one embodiment of the present application.

[0014] Figure 5 A schematic diagram of the circuit structure of a memory access control device in one embodiment of the present application.

[0015] Figure 6 A schematic diagram of the structure of a cache memory in one embodiment of the present application. DETAILED DESCRIPTION

[0016] The detailed description of the drawings is intended as an illustration of some embodiments of the present application, and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.

[0017] See also Figure 1 , an embodiment of the present application provides a Cache resource configuration device, including a receiving module, an access monitoring module and a partition capacity adjustment module; The receiving module is used to receive an access request transmitted by a peripheral device, obtain a peripheral device ID and virtual address data according to the access request, obtain a PARTID according to the peripheral device ID, and send the PARTID and virtual address data to an access monitoring module.

[0018] Specifically, in hardware description languages ​​(such as Verilog, VHDL) and circuit design, using English names is also an industry standard to ensure code readability and maintainability. Therefore, in this embodiment, the peripheral id is represented by DeviceID for ease of description. DeviceID is used to uniquely identify a peripheral (external device), and PARTID is used to uniquely identify a storage partition of a group-associative cache.

[0019] For example, the receiving module obtains the PARTID according to the peripheral id by searching a mapping table of DeviceID to PARTID according to the DeviceID sent by each peripheral, and after obtaining the corresponding PARTID, routing the virtual address data of the peripheral to the access monitoring module. The design of a mapping from DeviceID to PARTID here mainly takes into account that there may be virtual devices in the peripherals, or two physical devices will only access the same memory space during design. At this time, different DeviceIDs should be mapped to the same PARTID to facilitate unified management of memory; of course, in actual design, DeviceID can also be used directly, that is, DeviceID=PARTID, and this method should also be understood as within the scope of protection of this application.

[0020] The access monitoring module is used to receive the PARTID and virtual address data, count the access traffic of the cache partition corresponding to the PARTID in the current cycle according to the virtual address data, send the virtual address data to the set-associative Cache, and send the access traffic to the capacity adjustment module; wherein, the set-associative Cache includes multiple cache partitions, each cache partition includes multiple cachelines; from another aspect, the set-associative Cache includes multiple sets, each set includes multiple cachelines, and the set and cache partition are independent concepts.

[0021] Specifically, the number of cache partitions in the set-associative cache is 2 n , correspondingly, the number of PARTIDs is also 2 n The access monitoring module is used to monitor the virtual address data of each peripheral device sent by the receiving module and perform periodic access traffic statistics. It includes multiple counters, each PARTID corresponds to a counter, and each counter is used to count the access traffic of the cache partition corresponding to the PARTID in the current cycle, and then the statistical results (access traffic) of each counter are sent to the partition capacity adjustment module.

[0022] The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of the multiple cache partitions in the current cycle.

[0023] Specifically, the partition capacity adjustment module may have a built-in timer, and when the count of the timer is greater than a time threshold ADJUST_TIME_TH configured by software, it triggers dynamic adjustment of the allocated capacity of the multiple cache partitions according to the statistical results of each counter.

[0024] For example, if the access traffic of a cache partition is very high, it indicates that the peripherals associated with it need more cache resources to improve access efficiency. Therefore, the partition capacity adjustment module may increase the number of cachelines of the partition. On the contrary, if the access traffic of a cache partition is very low, it indicates that the currently allocated cache resources may be too many. The number of cachelines of the partition can be reduced to allocate the excess resources to other partitions that need them more. This dynamic adjustment can be implemented based on various strategies, including but not limited to most frequently used first (MRU), least recently used (LRU) or other custom algorithms.

[0025] In some specific embodiments, the partition capacity adjustment module is further used to: Acquire access traffic rates of the multiple cache partitions in the current cycle according to the access traffic of the multiple cache partitions in the current cycle; If the access flow rate of any cache partition in the current cycle is greater than its access flow rate in the previous cycle, then obtain the flow rate increment of any cache partition V, if V> V max , then any cache partition needs to be increased in capacity and its capacity increment is determined; if V< V min, then any cache partition needs to be reduced in capacity, and its capacity reduction is determined; where, V max and V min is the preset threshold; If the access traffic rate of any cache partition in the current cycle is less than the access traffic rate in the previous cycle, the capacity of any cache partition needs to be reduced, and the capacity reduction is determined; The allocated capacities of the plurality of cache partitions are adjusted according to the capacity increment and the capacity decrement.

[0026] Specifically, when the dynamic adjustment of the allocated capacity of the multiple cache partitions is triggered according to the statistical results of each counter, the partition capacity adjustment module calculates the real-time rate corresponding to each PARTID, and the rate calculation method is: divide the real-time access traffic value of the current cycle by the time threshold ADJUST_TIME_TH to obtain the real-time traffic rate; ADJUST_TIME_TH can be understood as the adjustment cycle time.

[0027] Based on the calculated flow rate, for the i-th PARTID, use V n Indicates the real-time calculation rate of the current cycle corresponding to PARTID, expressed as V f Indicates the traffic rate calculated in the last cycle corresponding to PARTID, using V i Represents V of the i-th PARTID n -V f Value, use V max Indicates the threshold of the rate difference before and after the capacity needs to be increased. V min Indicates the threshold of the rate difference before and after the capacity needs to be reduced, which is: When V f <V n When V i = V n -V f ;when V i > V max When , it means that the allocated capacity of the cache partition corresponding to the i-th PARTID should be increased; when V min <= V<= V max , it means no adjustment is needed. When V f >V n Or (V f <Vn )&&( V i < V min ), it means that the allocated capacity of the cache partition corresponding to the i-th PARTID should be reduced.

[0028] It should be noted that the increment and decrement of the allocated capacity can be customized, for example, increasing or decreasing the capacity by a fixed value each time, or obtaining the increment or decrement based on multiplying the current allocated capacity by a preset coefficient. The above is only an example and this embodiment is not limited to this.

[0029] In some specific embodiments, the partition capacity adjustment module is further used to: Obtaining the unallocated capacity of the current cycle, determining the allocatable capacity according to the sum of the unallocated capacity and the capacity reduction of the cache partition that needs to be reduced, and determining the sum of the capacity increment according to the capacity increment of the cache partition that needs to be increased; When the allocatable capacity is greater than or equal to the sum of the capacity increments, the allocated capacity of the corresponding cache partition is increased according to the capacity increment of the cache partition to be increased, and the allocated capacity of the corresponding cache partition is decreased according to the capacity reduction of the cache partition to be reduced, and the unallocated capacity is updated; When the allocatable capacity is less than the sum of the capacity increments, the allocated capacity of the corresponding cache partition is reduced according to the capacity reduction of the cache partition to be reduced, the allocated capacity of the cache partition to be increased remains unchanged, and the unallocated capacity is updated.

[0030] Specifically, at the beginning of each adjustment cycle, the partition capacity adjustment module first determines how much cache capacity is currently not allocated to any cache partition, that is, unallocated capacity. In this embodiment, PAR_REV is used to represent unallocated capacity. The partition capacity adjustment module calculates the allocatable capacity, which is obtained by adding PAR_REV to the sum of the capacity reductions of all cache partitions that need to be reduced. The cache partitions that need to be reduced are those with low access traffic and need to reduce the number of allocated cachelines. At the same time, the partition capacity adjustment module also calculates the sum of the capacity increments of all cache partitions that need to be increased. The cache partitions that need to be increased are those with high access traffic and need to increase the number of allocated cachelines.

[0031] The partition capacity adjustment module compares the allocatable capacity with the sum of the capacity increments of the cache partitions to be increased. There are two possible situations: Case 1: The allocatable capacity is greater than or equal to the sum of the capacity increments. If the allocatable capacity is sufficient, the capacity adjustment can be performed normally. The partition capacity adjustment module will increase the allocated capacity according to the capacity increment of each cache partition that needs to be increased. At the same time, the partition capacity adjustment module will also reduce the allocated capacity according to the capacity reduction of each cache partition that needs to be reduced. After these adjustments, the partition capacity adjustment module will update the value of the unallocated capacity to reflect the new allocation.

[0032] Case 2: The allocatable capacity is less than the sum of the capacity increments. If the allocatable capacity is insufficient to meet the needs of all cache partitions that need to be increased, the partition capacity adjustment module will not increase the allocated capacity of any cache partition that needs to be increased, but the partition capacity adjustment module will still reduce the allocated capacity of the cache partition that needs to be reduced according to the capacity reduction of the cache partition that needs to be reduced, thereby releasing some capacity. After these adjustments, the partition capacity adjustment module will also update the value of the unallocated capacity.

[0033] In this way, the partition capacity adjustment module can ensure that the allocation of cache resources is balanced, and during the operation of the entire system, cache resources can be dynamically adjusted according to actual needs. This mechanism helps to maximize the utilization efficiency of the cache while avoiding resource waste.

[0034] In some specific embodiments, the capacity increment and capacity decrement of any cache partition in each cycle are P; among them, P is a preset integer value, indicating the number of cachelines increased or decreased, the unallocated capacity (PAR_REV) indicates the number of unallocated cachelines, and the allocated capacity of the cache partition indicates the number of cachelines included in the cache partition.

[0035] Specifically, in order to facilitate fast calculation, two parameters ADD_NUM and DEC_NUM are defined in this embodiment. ADD_NUM * P means that after adjustment, the number of cachelines that have not been allocated in the next time period can be increased; DEC_NUM* P means that after the adjustment, the number of cachelines in the cache that has not been allocated in the next time period will be reduced; in each adjustment, the initial values ​​of ADD_NUM and DEC_NUM are 0; based on the above parameter definitions, the function of the partition capacity adjustment module is described in detail below. When performing capacity adjustment, it can be performed in two beats (one beat is one clock cycle).

[0036] The first step is to preliminarily determine whether the cache partition corresponding to each PARTID is increased, unchanged, or reduced. The determination process of increasing, unchanged, or reducing the cache partition corresponding to each PARTID can be found in Figure 2 ,include: Step 1.1, determine V n and V f If V f >V n， This means that the capacity of the corresponding PARTID needs to be reduced. P, and ADD_NUM increases by 1, PAR_NUM_MAX_N_t = PAR_NUM_MAX_N - P; otherwise proceed to step 1.2; step1.2, get the corresponding V i = V n -V f and judge V i Is it less than V min If so, the capacity of the corresponding PARTID is reduced P, and ADD_NUM increases by 1, PAR_NUM_MAX_N_t = PAR_NUM_MAX_N- P; otherwise proceed to step 1.3; step1.3 When V min <= V i <= V max When , the capacity of the corresponding PARTID remains unchanged, and ADD_NUM remains unchanged; when V i > V max When , it indicates that the capacity of the corresponding PARTID increases P, and at the same time increase DEC_NUM by 1, PAR_NUM_MAX_N_t = PAR_NUM_MAX_N + P; PAR_NUM_MAX_N represents the current allocated capacity of the cache partition with PARTID N, and PAR_NUM_MAX_N_t represents the allocated capacity of the cache partition with PARTID N after adjustment.

[0037] The second beat is to further determine whether the cache partitions corresponding to each PARTID need to be expanded, remain unchanged, or reduced. The determination process can refer to Figure 3 , including: step2.1, determine whether PAR_REV + ADD_NUM is greater than DEC_NUM; step2.2, when PAR_REV + ADD_NUM >= DEC_NUM, it means that there are enough unallocated cachelines for the PARTs that need to be added. When configuring software parameters using registers, the value of PAR_NUM_MAX_N_t can be updated to the corresponding register PAR_NUM_MAX_N at this time. At the same time, the value of PAR_REV is updated to PAR_REV + ADD_NUM - DEC_NUM, and this round of adjustment ends; step2.3, when PAR_REV + ADD_NUM < DEC_NUM, it means that there are not enough remaining cachelines for the cache partitions that need to be added. At this time, the value of PAR_NUM_MAX_N_t < PAR_NUM_MAX_N is updated to the corresponding register PAR_NUM_MAX_N, that is, the reduction adjustment of the cache partition is normally executed. At the same time, the value of PAR_REV is updated to PAR_REV + ADD_NUM; the number of cachelines corresponding to the cache partitions that need to be expanded remains unchanged, and this round of adjustment ends.

[0038] Based on the description of the above embodiments, the cache resource configuration device of this embodiment counts the access traffic of each cache partition through the access monitoring module, and dynamically adjusts the allocation capacity of the cache partition according to the access traffic, realizing the dynamic adjustment of the set-associative cache resources according to the actual access requirements of multiple peripherals, so that the set-associative cache resources can be more reasonably allocated to each peripheral, and can adapt to the situation where multiple peripherals share one IOMMU or SMMU, solving the problem of low utilization rate of set-associative cache resources caused by static configuration; multiple peripherals (physical devices or virtual devices) may access the same storage partition. Therefore, by introducing PARTID to classify multiple peripherals, the monitoring of peripheral access behavior can be simplified, thereby reducing the hardware design resources required by the access monitoring module and also reducing the hardware design difficulty; since the configuration of set-associative cache resources is dynamic, the invalidation operation of the set-associative cache content during the two partition configurations before and after in software is reduced, improving the access efficiency of the set-associative cache.

[0039] Refer to Figure 4, another embodiment of the present application further provides a memory access control device, including an address translation unit, a set associative cache, and a cache resource configuration device according to the above embodiment; The address translation unit is used to receive the access request transmitted by the peripheral device and forward the access request to the Cache resource configuration device; it should be noted that the processing flow of the access request of each peripheral device by the Cache resource configuration device has been explained in detail in the content of the Cache resource configuration device described in the aforementioned embodiment, and therefore, it will not be repeated here, and you can refer to the content of the aforementioned embodiment for understanding.

[0040] The group-associative cache includes a cache controller and a cache memory, the cache memory includes multiple groups (sets), each group includes multiple cache lines; the group-associative cache is the adjustment object targeted by the cache resource configuration device of the above embodiment, which includes multiple cache partitions, each cache partition includes multiple cache lines, and each cache partition corresponds to a PARTID.

[0041] The cache controller is used to determine the group corresponding to the virtual address data in the set-associative cache according to the virtual address data, and determine whether there is physical address data corresponding to the virtual address data in the corresponding group. If so, the hit physical address data is taken out from the cacheline of the corresponding group and sent to the memory controller to access the memory. If not, a miss result is returned to the address translation unit. Specifically, when the cache controller receives the virtual address data, its primary task is to determine the group corresponding to the virtual address data in the set-associative cache. The set-associative cache is composed of multiple groups, each group contains multiple cachelines, and each cacheline can store a certain range of virtual address to physical address mapping. After determining the corresponding group, the cache controller then checks whether there is physical address data corresponding to the virtual address data in the group. This process is called cache hit check. If the physical address data corresponding to the virtual address data is found in the corresponding group (i.e., cache hit), the cache controller will take out the hit physical address data from the cacheline of the group. Then, the cache controller sends this physical address data to the memory controller, and the memory controller uses this physical address data to access the data in the memory. If the physical address data corresponding to the virtual address data is not found in the corresponding group (i.e., a cache miss), the cache controller will return a miss result to the address translation unit. This miss result tells the address translation unit that the mapping of the requested virtual address to the physical address is not stored in the cache, so the access request needs to be further processed, that is, translated into physical address data, which is the address translation function performed by, for example, IOMMU or SMMU in the background technology.

[0042] The address translation unit is further used to obtain virtual address data according to the access request based on the miss result, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller; specifically, when the cache controller notifies the address translation unit of a cache miss, the address translation unit will take action to process the missed access request. The address translation unit first obtains virtual address data according to the missed access request, and this virtual address data is the address that the peripheral originally requested to access. Next, the address translation unit translates this virtual address data into physical address data. Address translation is an important function of memory management, which converts virtual addresses (addresses used by peripherals) into physical addresses (addresses in actual memory). The address translation unit sends the translated physical address data to the memory controller, which is the component responsible for actually accessing the physical memory hardware, and it uses this physical address to read or write data in the memory. At the same time, the address translation unit also sends the translated physical address data to the cache controller. This is so that after the memory access is completed, the cache controller can store this address mapping in the cache, so that the same virtual address request in the future can directly find the corresponding physical address in the cache, thereby improving access efficiency. The cache controller is further used to store the currently translated physical address data in a cacheline of the corresponding group or discard it; specifically, when the address translation unit completes the translation of the virtual address to the physical address and sends the physical address data to the cache controller, the cache controller needs to decide whether to store (or fill) this physical address data in a cacheline of the corresponding group in the group-associative cache. If it is decided to store, this cacheline will record the mapping relationship between the virtual address and the physical address, so that when the peripheral accesses the same virtual address again in the future, the cache can provide fast access. In some cases, the cache controller may decide not to store the physical address data, for example, because the cache space is limited and the current cache policy (such as Least Recently Used (LRU) or random replacement) indicates that the existing data should be replaced; for example, the access pattern of the data indicates that it is unlikely to be accessed again, so storing it in the cache may not bring performance benefits; for example, in order to maintain cache consistency, it may be necessary to discard certain data according to specific cache policies or system requirements.

[0043] It should be noted that the memory access control device described in this embodiment can be regarded as a device similar to an input / output address translation unit (IOMMU) or a system address translation unit (SMMU). Both IOMMU and SMMU are hardware components for performing address translation and access control between a device (such as a peripheral) and a system memory. However, the memory access control device of this embodiment has the following improvements compared to a traditional IOMMU or SMMU: (1) The memory access control device in this embodiment includes a cache resource configuration device, which allows the allocation of cache resources to be adjusted dynamically. This means that the size and allocation of the cache can be optimized based on the actual usage of the peripherals, rather than statically configured. This dynamism can improve the utilization of the cache and the overall performance of the system.

[0044] (2) By introducing PARTID and the access monitoring module, this embodiment provides more sophisticated access control, which can allocate different sizes of cache resources to different peripherals according to their access patterns and requirements, thereby improving efficiency. Using PARTID to classify peripherals can reduce the hardware resources required by the monitoring module, because there is no need to design monitoring logic for each peripheral separately, but the access patterns of multiple peripherals can be aggregated and monitored.

[0045] (3) By dynamically adjusting cache resources, the cache hit rate can be optimized according to the actual access traffic of the peripherals, reducing cache misses, thereby reducing the number of memory accesses and latency. Dynamic cache resource configuration allows the system to better adapt to different workloads and access patterns, and also facilitates expansion in the future when more peripherals or more complex access patterns need to be supported.

[0046] The above improvements make the memory access control device more efficient and flexible in processing memory access requests of peripherals, especially in scenarios with multiple peripherals and high concurrent access, which can significantly improve the performance and scalability of the system.

[0047] In some specific embodiments, see Figure 5 , the memory access control device may also include a scheduling control module.

[0048] The cache controller is further used to determine whether there is at least one free cacheline in the corresponding group. If so, the currently translated physical address data is stored in any free cacheline. If not, the PARTID corresponding to the access request and the PARTID corresponding to each cacheline in the corresponding group are obtained, and the priority corresponding to the PARTID corresponding to the access request and the priority corresponding to the PARTID corresponding to each cacheline are further obtained, and output to the scheduling control module; wherein the PARTID corresponding to the cacheline is the PARTID corresponding to the storage data of the cacheline.

[0049] Specifically, Figure 5 A 4-way set-associative cache is shown, where each Cacheline represents a way, and every 4 Cachelines form a set. When performing cache indexing, the corresponding set will be indexed first. The cache controller first checks whether there is at least one free Cacheline (i.e., an unoccupied Cacheline) in the corresponding group. If there is a free Cacheline, it means that this Cacheline currently does not store any valid data and can be used to store new physical address data. If there is a free Cacheline, the cache controller will store the currently translated physical address data in any free Cacheline. In this way, when the same virtual address is requested again, the cache can quickly provide the physical address data, reducing the number of memory accesses.

[0050] If there is no free cacheline in the corresponding group, the cache controller needs to obtain the PARTID corresponding to the access request (i.e. the PARTID corresponding to the peripheral id) and the PARTID corresponding to each cacheline in the corresponding group (i.e. the PARTID corresponding to the stored data of the cacheline). Next, the cache controller further obtains the priority corresponding to the PARTID corresponding to the access request and the priority corresponding to the PARTID corresponding to each cacheline. This priority information is used to determine which data should be stored in the cache and which data should be replaced when the cache space is insufficient. After obtaining the above information, the cache controller outputs this information to the scheduling control module, and the scheduling control module decides whether to store the physical address data in the cache based on this information.

[0051] The scheduling control module is used to determine whether to store the currently translated physical address data in a cacheline of the corresponding group according to the priority corresponding to the PARTID corresponding to the access request and the priority corresponding to the PARTID corresponding to each cacheline, and return the determination result to the cache controller; Specifically, the scheduling control module decides whether to store the physical address data in the cache according to the priority of the PARTID corresponding to the access request and the priority of the PARTID corresponding to each cacheline. This decision is made based on the storage strategy of the cache, such as but not limited to the least frequently used (LFU), most frequently used (LFU) or partition priority strategy, etc., according to the determination result of the scheduling control module.

[0052] The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it according to the determination result.

[0053] Specifically, the cache controller decides whether to store the currently translated physical address data in a cacheline of the corresponding group or discard the data.

[0054] In summary, in this embodiment, when the cache controller decides to store new data in the cache, it determines how to handle the acquisition of free cachelines and priority information, and how to collaborate with the scheduling control module to determine the data storage strategy. This strategy can optimize the use efficiency of the cache and reduce the latency of memory access.

[0055] In some specific embodiments, the scheduling control module is further used to determine to discard the currently translated physical address data when the priority corresponding to the PARTID corresponding to the access request is lower than the priority corresponding to the PARTID corresponding to any cacheline in the corresponding group.

[0056] Specifically, when the scheduling control module receives the PARTID and its priority corresponding to the access request provided by the Cache controller, as well as the PARTID and its priority corresponding to each Cacheline in the corresponding group, it will compare these priorities. If the priority of the PARTID corresponding to the access request is lower than the priority of the PARTID corresponding to any Cacheline in the corresponding group, this means that the physical address data of the access request has a lower priority and is not the data that is most needed to be retained in the Cache at present. In this case, the scheduling control module will decide to discard the currently translated physical address data, which means that this data will not be stored in the Cache. This decision can avoid storing low-priority data in the Cache, thereby keeping the data in the Cache as the most needed high-priority data at present, which can ensure that the Cache resources are used most efficiently, while reducing cache misses caused by storing low-priority data. Through this strategy, the system can process access requests more efficiently, because the data in the Cache is the data that is most likely to be accessed, which helps to improve the overall performance and response speed of the system.

[0057] In some specific embodiments, the scheduling control module is further used to select at least one cacheline with the lowest priority from the at least one cacheline when the priority corresponding to the PARTID corresponding to the access request is higher than or equal to the priority corresponding to the PARTID corresponding to at least one cacheline in the corresponding group, and select a cacheline with the least number of uses within a recent preset time from the at least one cacheline with the lowest priority to store the currently translated physical address data.

[0058] Specifically, when the scheduling control module receives the PARTID and its priority corresponding to the access request provided by the Cache controller, as well as the PARTID and its priority corresponding to each Cacheline in the corresponding group, it will compare these priorities. If the priority of the PARTID corresponding to the access request is higher than or equal to the priority of the PARTID corresponding to at least one Cacheline in the corresponding group, this means that the data priority of the access request is higher and needs to be retained in the Cache first. In this case, the scheduling control module will select the Cacheline with the lowest priority from the at least one Cacheline. The Cacheline with the lowest priority means that the data stored in it is not the data that most needs to be retained in the Cache. At this time, there may be one or at least two Cachelines with the lowest priority. If there is only one Cacheline with the lowest priority, this Cacheline with the lowest priority is determined to be used to store the currently translated physical address data. If there are at least two Cachelines with the lowest priority, the scheduling control module will select the Cacheline with the least number of uses in the recent preset time from the at least two Cachelines with the lowest priority, that is, determine the Cacheline to be replaced based on the least used (LRU) strategy. Finally, the scheduling control module returns the information of the selected Cacheline to the Cache controller to tell the Cache controller to store the currently translated physical address data in this Cacheline with the least number of uses. In the above manner, it can be ensured that the data in the Cache is the data that is most likely to be accessed, while following the cache replacement strategy to maintain the efficiency and performance of the Cache.

[0059] In some specific embodiments, the cache memory further includes a priority data module and an LRU module, wherein the priority data module is used to store priority information corresponding to each PARTID, and the LRU module is used to store the number of times each cacheline is used within a recent preset time.

[0060] Specifically, if Figure 6The figure shows a 4-way group-associative cache, in which each Cacheline includes Tag, Data and PARTID. The Tag is used to store all information that can uniquely identify each peripheral transmission stream, for example, it can be set to {Device ID, Process ID, Address, Privilege}. Each Cacheline will correspond to a Tag, Data is used to store valid data in the data stream, that is, the translated physical address data, and PARTID is used to store the PARTID (partition id) corresponding to the cache data of each Cacheline. The LRU module is used to record the number of times each Cacheline has been used recently M. When the Cacheline needs to be replaced, the Cacheline with the least number of recent uses M will be replaced first according to the records in the LRU; the priority data module (PARTPRIRAM) is used to store the priority information corresponding to each PARTID. The priority data module can be formed by a RAM, and the depth of the RAM is the maximum number of supported PARTIDs. The cache controller can read the priority information of the corresponding PARTID from the priority data module and the number of cacheline usage records from the LRU module, and then send them to the scheduling control module for cacheline replacement storage decision.

[0061] In some specific embodiments, the scheduling control module is further used to determine the priority corresponding to each PARTID according to the allocated capacity and the actually used capacity of the storage partition corresponding to each PARTID, and the unallocated capacity.

[0062] Specifically, in this embodiment, parameters PAR_NUM_N and PAR_NUM_S are further set, PAR_NUM_N represents the number of cachelines actually occupied by the cache partition with PARTID N, and PAR_NUM_S represents the part of cachelines occupied by all PARTIDs that exceeds the maximum number of cachelines allocated by its register PAR_NUM_MAX_N; it is assumed here that there are only two IDs with PARTIDs of 1 and 2, the numbers they occupy are 10 and 15 respectively, and the numbers allocated by their corresponding registers PAR_NUM_MAX_N are both 8, then PAR_NUM_S = 10 – 8 + 15 – 8 = 9.

[0063] The scheduling control module counts the values ​​of PAR_NUM_N and PAR_NUM_S in real time, and sets the priority PART_PRI_N corresponding to each PARTID according to the size relationship between the value in PAR_NUM_MAX_N and PAR_NUM_N. The value of this priority will be cached with the data in the priority data module (PARTPRIRAM) of the corresponding cacheline during cache allocation. The priority setting method is shown in Table 1 below: Table 1

[0064] In order to configure the parameters of the hardware circuit, the device of this embodiment also includes a status register module (CSR) for storing the status values ​​of various parameters of the hardware circuit, including multiple status registers such as PAR_NUM_MAX_(N), PAR_REV, ADJUST_TIME_TH, PAR_NUM_(N), and PART_PRI_(N), as shown in Table 2 below: Table 2

[0065] Based on the priorities defined in Table 2 and the status registers defined in Table 1, the workflow of the scheduling control module of this embodiment is further described, which specifically includes the following steps: Step 3.1: Based on the incoming transmission, the cacheline is indexed in the traditional group-associative cache indexing method. After indexing the corresponding group, the status of each cacheline in the corresponding group is read, and then step 3.2 is performed; Step 3.2, when there is an unoccupied cacheline in the indexed group, directly assign the transaction to the cacheline, and increase the corresponding PAR_NUM_N value by 1. When PAR_NUM_N>PAR_NUM_MAX_N, increase the PAR_NUM_S value by 1, and the transfer assignment ends; otherwise, proceed to step 3.3; The step 3.3 includes: When all cachelines in the indexed group are occupied, read the PARTID_i corresponding to the data stored in each cacheline of the group to obtain the priority PART_PRI_i of each cacheline. At the same time, the PART_PRI_N of each cacheline can also be obtained from the CSR through the PARTID of the newly transmitted data, and then make the following judgment: (a) When PART_PRI_N = 1, and there is a transfer with the same PARTID in the indexed group, read the statistical count M of the LRU module corresponding to the cacheline with the same PARTID in the group, and replace the transfer into the cacheline with the smallest M value according to the LRU algorithm. All status registers do not need to be changed; (b) When PART_PRI_N = 1, and the indexed group does not contain the same PARTID, the transmission will not be allocated to the cache and will be discarded directly, and all status registers do not need to be changed; (c) When PART_PRI_N = 2, and a cacheline with PART_PRI_i = 1 in the group is indexed, the statistical count M of the LRU module corresponding to the cacheline with PART_PRI_i = 1 in the group is read out, and the transfer is replaced into the cacheline with the smallest M value according to the LRU algorithm. The PAR_NUM_N value corresponding to the transfer is increased by 1, and the PAR_NUM_i value corresponding to the replaced cacheline is decreased by 1. (d) When PART_PRI_N = 2, and a cacheline with PART_PRI_i = 1 is indexed in the group, determine whether there is a cacheline in the group with the same PARTID as the transfer. If so, read the statistical count M of the LRU module corresponding to the cacheline with the same PARTID as the transfer in the group, and replace the transfer into the cacheline with the smallest M value according to the LRU algorithm, and all status registers do not need to be changed; otherwise, the transfer will not be allocated to the cache and will be directly discarded, and all status registers do not need to be changed; (e) When PART_PRI_N=3, cachelines must be cached, with priority 1 replaced first, followed by priority 2. When there are multiple cachelines with the same priority, they are replaced according to the LRU algorithm (read the statistical count M in the LUR module, and then select the cacheline with the smallest M). After the replacement is successful, the PAR_NUM_N value corresponding to the transfer is increased by 1, the PAR_NUM_i value corresponding to the replaced cacheline is decreased by 1, the PAR_NUM_S value is decreased by 1, and the values ​​of the other status registers remain unchanged.

[0066] Another embodiment of the present application further provides a chip, comprising the cache resource configuration device according to the above embodiment.

[0067] Another embodiment of the present application further provides a chip, comprising the memory access control device according to the above embodiment.

[0068] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A Cache resource configuration device, characterized in that: include: A receiving module, used for receiving an access request transmitted by a peripheral device, obtaining a peripheral device ID and virtual address data according to the access request, obtaining a PARTID according to the peripheral device ID, and sending the PARTID and virtual address data to an access monitoring module; An access monitoring module, used for receiving the PARTID and virtual address data, counting the access traffic of the cache partition corresponding to the PARTID in the current cycle according to the virtual address data, sending the virtual address data to the set-associative Cache, and sending the access traffic to the capacity adjustment module; wherein the set-associative Cache includes a plurality of cache partitions; The partition capacity adjustment module is used to periodically and dynamically adjust the allocated capacity of the multiple cache partitions according to the access traffic of the multiple cache partitions in the current cycle.

2. The Cache resource configuration device according to claim 1, characterized in that: The partition capacity adjustment module is further used to: Acquire access traffic rates of the multiple cache partitions in the current cycle according to the access traffic of the multiple cache partitions in the current cycle; If the access flow rate of any cache partition in the current cycle is greater than its access flow rate in the previous cycle, then obtain the flow rate increment of any cache partition V, if V> V max , then any cache partition needs to be increased in capacity and its capacity increment is determined; if V< V min , then any cache partition needs to be reduced in capacity, and its capacity reduction is determined; where, V max and V min is the preset threshold; If the access traffic rate of any cache partition in the current cycle is less than the access traffic rate in the previous cycle, the capacity of any cache partition needs to be reduced, and the capacity reduction is determined; The allocated capacities of the plurality of cache partitions are adjusted according to the capacity increment and the capacity decrement.

3. The Cache resource configuration device according to claim 2, characterized in that: The partition capacity adjustment module is further used to: Obtaining the unallocated capacity of the current cycle, determining the allocatable capacity according to the sum of the unallocated capacity and the capacity reduction of the cache partition that needs to be reduced, and determining the sum of the capacity increment according to the capacity increment of the cache partition that needs to be increased; When the allocatable capacity is greater than or equal to the sum of the capacity increments, the allocated capacity of the corresponding cache partition is increased according to the capacity increment of the cache partition to be increased, and the allocated capacity of the corresponding cache partition is decreased according to the capacity reduction of the cache partition to be reduced, and the unallocated capacity is updated; When the allocatable capacity is less than the sum of the capacity increments, the allocated capacity of the corresponding cache partition is reduced according to the capacity reduction of the cache partition to be reduced, the allocated capacity of the cache partition to be increased remains unchanged, and the unallocated capacity is updated.

4. The Cache resource configuration device according to claim 3, characterized in that: The capacity increment and decrement of any cache partition in each cycle are P; among them, P is a preset integer value, indicating the number of cachelines increased or decreased, the unallocated capacity indicates the number of unallocated cachelines, and the allocated capacity of the cache partition indicates the number of cachelines included in the cache partition.

5. A memory access control device, characterized in that: It comprises an address translation unit, a set associative cache and a cache resource configuration device according to any one of claims 1 to 4; The address translation unit is used to receive the access request transmitted by the peripheral device and forward the access request to the Cache resource configuration device; The group-associative cache includes a cache controller and a cache memory, wherein the cache memory includes a plurality of groups, and each group includes a plurality of cache lines; The cache controller is used to determine the group corresponding to the virtual address data in the group-associative cache according to the virtual address data, and determine whether there is physical address data corresponding to the virtual address data in the corresponding group, if so, take out the hit physical address data from the cacheline of the corresponding group and send it to the memory controller to access the memory, if not, return a miss result to the address translation unit; The address translation unit is further used to obtain virtual address data according to the access request based on the miss result, translate the virtual address data into physical address data, send the currently translated physical address data to the memory controller to access the memory, and send the currently translated physical address data to the cache controller; The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it.

6. The memory access control device according to claim 5, characterized in that: The memory access control device also includes a scheduling control module; The cache controller is further used to determine whether there is at least one free cacheline in the corresponding group. If so, the currently translated physical address data is stored in any free cacheline. If not, the PARTID corresponding to the access request and the PARTID corresponding to each cacheline in the corresponding group are obtained, and the priority corresponding to the PARTID corresponding to the access request and the priority corresponding to the PARTID corresponding to each cacheline are further obtained, and output to the scheduling control module; wherein the PARTID corresponding to the cacheline is the PARTID corresponding to the storage data of the cacheline; The scheduling control module is used to determine whether to store the currently translated physical address data in a cacheline of the corresponding group according to the priority corresponding to the PARTID corresponding to the access request and the priority corresponding to the PARTID corresponding to each cacheline, and return the determination result to the cache controller; The cache controller is further configured to store the currently translated physical address data in a cacheline of the corresponding group or discard it according to the determination result.

7. The memory access control device according to claim 6, characterized in that: The scheduling control module is further used to determine to discard the currently translated physical address data when the priority corresponding to the PARTID corresponding to the access request is lower than the priority corresponding to the PARTID corresponding to any cacheline in the corresponding group.

8. The memory access control device according to claim 6, characterized in that: The scheduling control module is further used to select at least one cacheline with the lowest priority from the at least one cacheline when the priority corresponding to the PARTID corresponding to the access request is higher than or equal to the priority corresponding to the PARTID corresponding to at least one cacheline in the corresponding group, and select a cacheline with the least number of uses within a recent preset time from the at least one cacheline with the lowest priority to store the currently translated physical address data.

9. The memory access control device according to claim 8, characterized in that: The cache memory further includes a priority data module and an LRU module. The priority data module is used to store priority information corresponding to each PARTID, and the LRU module is used to store the number of times each cacheline is used within a recent preset time.

10. The memory access control device according to any one of claims 6 to 9, characterized in that: The scheduling control module is further used to determine the priority corresponding to each PARTID according to the allocated capacity and the actually used capacity of the storage partition corresponding to each PARTID, and the unallocated capacity of the current cycle.

11. A chip, comprising the cache resource configuration device according to any one of claims 1 to 4, or comprising the memory access control device according to any one of claims 5 to 10.

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