Data receiving method and system and FPGA (Field Programmable Gate Array) equipment

Abstract

The invention provides a data receiving method and system and FPGA equipment, and the method comprises the steps: setting the assertion state of a TREADY signal according to the numerical value of a first counter and the assertion state of a TVALID signal, executing a data transmission task when the TVALID signal and the TREADY signal are both asserted to be effective, and transmitting the data to the FPGA equipment when the TREADY signal and the TVALID signal are asserted to be effective. Controlling a first counter to perform corresponding counting operation according to the execution state of the data transmission task; receiving a data packet in the data transmission task, temporarily storing the data packet in a register, reading the data packet from the register in the next clock period, performing data processing, not establishing a buffer pool, occupying a small memory space, and adding one to the numerical value of a second counter; and when the numerical values of the first counter and the second counter are equal to the total number of the data groups, ending the data transmission task, resetting the numerical values of the first counter and the second counter, ensuring the correctness of data receiving by utilizing a double-counting mode, and managing the inflow and outflow of the data.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data receiving method, system and FPGA device. Background Art

[0002] With the advent of the digital and information age, the amount of data processing has shown explosive growth. FPGA (Field Programmable Gate Array) is widely used in communication and data processing in various fields due to its high-speed data processing capabilities. In FPGA applications, the AXI4-Stream (AXI4StreamProtocol) bus protocol is usually used for high-speed serial communication. The AXI4-Stream protocol is a simple, easy-to-use, high-speed and reliable communication protocol that can effectively improve the efficiency and reliability of FPGA data transmission, and realize the efficient transmission, processing and analysis of large amounts of data by FPGA, thereby meeting the needs of various complex applications.

[0003] In the actual scenario where FPGA uses the AXI4-Stream protocol for data transmission, the two parties of data transmission carry out the data transmission in a division of labor and cooperation manner. The commonly used transmission method is that the sending end is responsible for controlling the data transmission, and the receiving end FPGA uses internal storage resources to create a buffer in advance to wait for receiving data; moreover, in order to enable the buffer to continuously receive data, the FPGA usually starts to read data from the buffer pool immediately after at least one transmission task is completed, and performs data processing synchronously during the data reception process to ensure the continuity and rate of data reception.

[0004] Although the above-mentioned method of FPGA receiving data is continuous and efficient, it requires pre-planning of memory space to create a buffer pool. On the one hand, this receiving method occupies a large amount of memory space resources, which may limit the transmission rate and processing rate of the FPGA; on the other hand, this buffer pool receiving method is mainly suitable for situations where the input data flow speed is slow and the output processing speed is fast. It may not be fully effective for other transmission methods and has certain limitations. In addition, the buffer pool needs to accurately manage the inflow and outflow of data, and its flow control is relatively complex.

[0005] Therefore, how to provide a data receiving method with strong universality, small memory space occupation and easy flow control under the premise of ensuring the data transmission rate is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0006] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0007] To this end, a first object of the present invention is to provide a data receiving method.

[0008] The second objective of the present invention is to provide an FPGA device.

[0009] The third objective of the present invention is to provide a data receiving system.

[0010] To achieve the above-mentioned purpose, the first aspect of the present invention proposes a data receiving method, comprising the following steps: creating a first counter and a second counter, and setting the initial values ​​of the first counter and the second counter to zero; determining the total length of data and the total number of data packets of a single data transmission task; setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal of the transmitting end, executing the data transmission task when the TVALID signal and the TREADY signal are both asserted, and controlling the first counter to perform corresponding counting operations according to the execution state of the data transmission task; wherein the counting operation includes adding one to a value and subtracting one from a value; receiving the data packet in the data transmission task and temporarily storing it in a register, reading the data packet from the register in the next clock cycle for data processing, and adding one to the value of the second counter while performing data processing; wherein receiving the data packet and performing data processing on the data packet are both single-cycle operations; until the value of the first counter and the value of the second counter are both equal to the total number of data packets, the data transmission task is terminated, and the values ​​of the first counter and the second counter are cleared to zero.

[0011] In a specific embodiment of the first aspect, determining the total data length and the total number of data packets of a single data transmission task includes: determining the total data length of the data transmission task through bilateral negotiation between the sending end and the receiving end; determining the data bit width of a single transmission through bilateral negotiation between the sending end and the receiving end, wherein the data bit width of a single transmission is determined based on the AXI4-Stream protocol; determining the total number of data packets based on the total data length of the data transmission task and the data bit width of the single transmission.

[0012] In a specific embodiment of the first aspect, the assertion state of the TREADY signal is set according to the value of the first counter and the assertion state of the TVALID signal of the transmitting end, including: when the value of the first counter is less than the total number of data packets, if the TVALID signal is asserted valid, the TREADY signal is set to be asserted valid; if the TVALID signal is asserted invalid, the TREADY signal is set to be asserted invalid.

[0013] In a specific embodiment of the first aspect, before controlling the first counter to perform a corresponding counting operation according to the execution status of the data transmission task, it also includes: at the starting time of each clock cycle, based on the value of the first counter, the assertion status of the TVALID signal and the TREADY signal, combined with the total number of data packets, the execution status of the data transmission task is collaboratively determined; if the value of the first counter is less than the total number of data packets and the TVALID signal is asserted valid, it is predicted that the execution status of the data transmission task in the next clock cycle is normal transmission; if the value of the first counter is less than or equal to the total number of data packets, the TVALID signal is asserted invalid and the TREADY signal is asserted valid, the execution status of the data transmission task is determined to be transmission interruption.

[0014] In a specific embodiment of the first aspect, the first counter is controlled to perform a corresponding counting operation according to the execution status of the data transmission task, including: if the execution status of the data transmission task in the next clock cycle is predicted to be normal transmission, the first counter is controlled to perform a value addition operation in the next clock cycle.

[0015] In a specific embodiment of the first aspect, controlling the first counter to perform a corresponding counting operation according to the execution status of the data transmission task includes: if the execution status of the data transmission task is a transmission interruption, controlling the first counter to perform a value subtraction operation in the next clock cycle.

[0016] In a specific embodiment of the first aspect, setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal of the transmitting end includes: when the value of the first counter is equal to the total number of data packets, judging whether the TVALID signal is invalid and the TREADY signal is valid; if so, waiting for the value of the first counter to be reduced by one, and then setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal; otherwise, setting the TREADY signal to be invalid until the data transmission task is completed.

[0017] In a specific embodiment of the first aspect, the step of adding one to the value of the second counter while performing data processing comprises: at the start of each clock cycle, determining the data processing state of the next clock cycle by detecting the assertion state of the TVALID signal and the TREADY signal; wherein the data processing state includes not performing data processing and performing data processing on the received data packets; if the data processing state of the next clock cycle is to perform data processing on the received data packets, then adding one to the value of the second counter in the next clock cycle.

[0018] To achieve the above-mentioned purpose, the second aspect of the present invention proposes an FPGA device, including a creation module, a determination module, a data operation module and a closing module; wherein the data operation module includes a data transmission unit and a data processing unit; the creation module is used to create a first counter and a second counter, and set the initial values ​​of the first counter and the second counter to zero; the determination module is used to negotiate with the sending end to determine the total length of data for a single data transmission task, and to determine the total number of data packets for a single data transmission task; the data transmission unit is used to set the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal, and receive data packets when both the TVALID signal and the TREADY signal are asserted. To execute the data transmission task, and control the first counter to perform corresponding counting operations according to the execution status of the data transmission task; wherein, the counting operations include adding one to the value and subtracting one from the value; the data processing unit is used to receive the data packets in the data transmission task and temporarily store them in a register, read the data packets from the register in the next clock cycle for data processing, and increase the value of the second counter by one while performing data processing; wherein, receiving the data packets and processing the data packets are both single-cycle operations; the ending module is used to end the data transmission task and clear the values ​​of the first counter and the second counter until the values ​​of the first counter and the second counter are equal to the total number of data packets.

[0019] To achieve the above-mentioned purpose, the third aspect embodiment of the present invention proposes a data receiving system, including the FPGA device and the transmitting end described in the second aspect embodiment; the transmitting end is used to negotiate with the FPGA device to determine the total data length of a single data transmission task; it is also used to set the assertion state of the TVALID signal; and it is also used to send data packets to execute the data transmission task when both the TVALID signal and the TREADY signal are asserted.

[0020] Beneficial effects of the present invention: The assertion state of the TREADY signal is set according to the value of the first counter and the assertion state of the TVALID signal of the transmitting end, and the data transmission task is executed when the TVALID signal and the TREADY signal are both asserted to be valid. When the data transmission task is executed, the received data packet is temporarily stored in the register, and the data packet is read out from the register for data processing before the next data packet is received, and the next data packet is received and the data processing of the previous data packet is synchronously performed within one clock cycle to ensure the high efficiency and continuity of data transmission, and only one register is occupied to temporarily store one data packet, and there is no need to establish a buffer pool, which occupies less memory space; A first counter is created in advance and used to synchronously count the number of received data packets when receiving data packets. A second counter is created in advance and used to synchronously count the number of processed data packets when processing data packets, until the values ​​of the first counter and the second counter reach the total number of data packets, the assertion state of the TREADY signal is set to end the data transmission task. A double counting method is used to ensure the correctness of data reception, and the assertion mode and assertion state of the TREADY signal are set to enable the receiving end to control the start and stop of the data transmission task, manage the inflow and outflow of data, and make flow control more simple and convenient. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flow chart of a data receiving method provided by an embodiment of the present invention; Figure 2 A block diagram of an FPGA device provided by an embodiment of the present invention; Figure 3 A block diagram of a data receiving system provided by an embodiment of the present invention; Figure 4 A schematic diagram of transmission of a single data packet provided by an embodiment of the present invention; Figure 5 Another schematic diagram of transmission of a single data packet provided by an embodiment of the present invention; Figure 6 A transmission schematic diagram of continuous transmission of multiple data packets provided by an embodiment of the present invention; Figure 7 Another transmission schematic diagram of continuous transmission of multiple data packets provided by an embodiment of the present invention; Figure 8 A transmission schematic diagram of multiple data packets interrupted transmission provided by an embodiment of the present invention; Fig. 9 Another transmission schematic diagram of multiple data packets interrupted transmission provided by an embodiment of the present invention; Fig.10 It is a transmission schematic diagram of the traditional transmission method; Figure 4-Figure 10 middle: CLK—clock signal; TVALID—TVALID signal; TREADY—TREADY signal; TLAST—TLAST signal; TDATA—received data packet; cnt1—the value of the first counter; WR_EN—data processing signal; cnt2—the value of the second counter; WR_DATA—Data packet for data processing. DETAILED DESCRIPTION

[0022] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0023] For ease of understanding, the terms, custom words and application scenarios involved in the present invention are first explained in combination with the technical solution of the present invention: AXI4-Stream protocol: is a stream-oriented transmission protocol used to transmit data streams between a transmitter and a receiver, suitable for high-speed data streams, and allows unlimited data burst transmission. When the present invention uses the AXI4-Stream protocol for data transmission, the receiving end involved is an FPGA device.

[0024] Sender: In the AXI4-Stream protocol, the sender refers to the device or module that generates data and sends it to the transmission line, such as a host, FPGA device, etc. The sender prepares the data to be transmitted and then sends it to the receiver through the AXI4-Stream interface.

[0025] CLK (Clock, clock signal): The clock signal in the electronic circuit is used to control the time rhythm in the circuit.

[0026] TVALID signal: One of the interface signals of AXI4-Stream, whose assertion state is set by the sender, including assertion valid (TVALID signal is high level 1) and assertion invalid (TVALID signal is low level 0); when the sender sets the TVALID signal to be asserted (TVALID signal is high level), it indicates that the sender is driving a valid transmission; when both TVALID signal and TREADY signal are asserted, a data packet transmission occurs.

[0027] TREADY signal: one of the interface signals of AXI4-Stream. The receiving end can set the assertion mode and assertion state of the TREADY signal. In actual application of the present invention, the assertion state of the TREADY signal is set according to the value of the first counter and the assertion state of the TVALID signal. The assertion state of the TREADY signal includes assertion valid (TREADY signal is high level 1) and assertion invalid (TREADY signal is low level 0); when the TREADY signal is asserted valid, it indicates that the receiving end can receive a data packet in the current clock cycle; when both the TREADY signal and the TVALID signal are asserted valid, a data packet transmission occurs.

[0028] TLAST signal: One of the interface signals of AXI4-Stream, controlled by the sender, used to indicate the last data packet of a data transmission task.

[0029] TDATA (Transferred Data Stream): represents data packets transmitted through the AXI4-Stream protocol, that is, data packets received by the receiving FPGA device using the AXI4-Stream protocol and controlled by the receiving end.

[0030] cnt1: The value of the first counter, controlled by the receiving end.

[0031] WR_EN: Data processing signal. In the AXI4-Stream protocol, it is controlled by the receiving end and is usually used to indicate a write operation enable signal. When the WR_EN signal is high, it indicates that the write operation is enabled and data can be written to the target device.

[0032] cnt2: The value of the second counter, controlled by the receiving end.

[0033] WR_DATA: During data transmission using the AXI4-Stream protocol between the sender and receiver, WR_DATA is a data packet for data processing and is controlled by the receiver.

[0034] Register: A small storage area inside the FPGA (Field-Programmable Gate Array) used to store data. It is a high-speed storage component with limited storage capacity and is used to temporarily store data involved in the operation and the results of the operation. In the actual application of the present invention, the register is used to temporarily store a data packet when performing a data transmission task. Therefore, the register capacity only needs to be greater than the data length of a data packet, and less memory resources are occupied. First counter: a logic circuit pre-created by the receiving end to implement counting operations, used to count the number of received data packets in a data transmission task, with the counting range from zero to the total number of data packets (0-total number of data packets).

[0035] Second counter: A logic circuit pre-created by the receiving end to implement counting operations, used to count the number of processed data packets in the data transmission task, with a counting range from zero to the total number of data packets (0-total number of data packets) Single data transmission task: A data transmission operation in which the sender uses the AXI4-Stream protocol to transmit a data packet of a certain length to the receiver. When performing a single data transmission task, the data packet of the certain length will be split into one or more data packets and transmitted in groups. The last data packet of each data transmission task is indicated by the TLAST signal, one of the AXI4-Stream interface signals.

[0036] The total data length of a single data transmission task: the data length of the data packet to be transmitted in a single data transmission task. The data length unit includes but is not limited to bits, bytes, and double words. In actual applications, the total data length of a single data transmission task is usually determined by the sender and the receiver after negotiation based on actual business needs, that is, the total data length of a single data transmission task can be customized; or, the total data length of a single data transmission task can also be a fixed length.

[0037] Data bit width of a single transmission: When the sender and receiver use the AXI4-Stream protocol for data transmission, the amount of data / bits that can be transmitted in one clock cycle, that is, the data length of a data packet.

[0038] Total number of data packets in a single data transmission task: the total number of data packets into which the data packets to be transmitted are split in a data transmission task; due to the data bit width limitation of a single transmission, when performing a single data transmission task, the data packets to be transmitted need to be split into one or more data packets before group transmission.

[0039] Execution status of data transmission task: At the start of each clock cycle, based on the data transmission task related information, such as the value of the first counter, the total number of data packets, the assertion status of the TVALID signal and the TREADY signal, the transmission status of the data packets in the clock cycle is determined, or the estimated transmission status of the data packets in the next clock cycle, including normal transmission and transmission interruption, as well as transmission start and transmission end, which is mainly used to control the first counter to perform corresponding counting operations.

[0040] Single-cycle operation: One instruction is executed in one clock cycle, and the next instruction starts to be executed after one instruction is completed.

[0041] The starting moment of each clock cycle: usually refers to each rising edge of the clock signal, that is, the moment when the clock signal jumps from a low level to a high level. Each rising edge marks the beginning of a new clock cycle.

[0042] In the present invention, the AXI4-Stream protocol is applied between the sending end and the receiving end for data transmission, and an FPGA device is used as the receiving end. The sending end is a hardware device or system that can generate and send AXI4-Stream protocol data. For example, the sending end is an FPGA device or a host, etc. The sending end sends the AXI4-Stream protocol data to the FPGA device receiving end through the AXI4-Stream interface.

[0043] When the AXI4-Stream protocol is applied at the sending and receiving ends to perform a single data transmission task, it is divided into the following stages: In the preparation stage, the FPGA device creates a first counter for counting received data packets and a second counter for counting processed data packets; the sending end and the FPGA device jointly negotiate to determine the total length of data transmitted in this data transmission task, and the FPGA device determines the total number of data packets based on the total length of the data.

[0044] At the beginning of the data transmission task, such as Figures 4 to 9 As shown in the first three clock cycles (CLK), the transmitter first pulls up the TVALID signal (sets the TVALID signal to be asserted valid). After the FPGA device detects that the transmitter has pulled up the TVALID signal, it pulls up the TREADY signal (sets the TREADY signal to be asserted valid), indicating that the FPGA device is ready to receive data. After the transmitter detects that the FPGA device has pulled up the TREADY signal, it starts to execute the data transmission task. A data packet is transmitted during the clock cycle in which both the TVALID signal and the TREADY signal are asserted valid. The first counter cnt1 in the FPGA device performs a counting operation (value increment operation) while the data packet is transmitted. After receiving a data packet, the FPGA device stores it in a register, and takes out the data packet from the register in the next clock cycle and processes the data. While the data packet is being processed, the value of the second counter cnt2 in the FPGA device is incremented by one.

[0045] If the total number of data packets is 1, the data transmission task enters the final stage, such as Figure 4 and Figure 5 As shown, the first counter cnt1 pulls down the TREADY signal after reaching the total number of data packets, and ends the data transmission task after the value of the second counter cnt2 also reaches the total number of data packets. The values ​​of the first counter cnt1 and the second counter cnt2 are both cleared to prepare for the next data transmission task.

[0046] If the total number of data packets is greater than 1, the TVALID signal may be invalid in the execution of the data transmission task because the sending end may not be ready for the data packets to be transmitted or the sending end has not set the transmission status. Therefore, there are the following three situations in the continuation stage of the data transmission task: the first is that if the TVALID signal remains valid in the process of executing the data transmission task, it means that data packets are continuously transmitted in the execution of the data transmission task; the second is that if the TVALID signal is invalid before the transmission of the (total number of data packets - 1)th data packet, it means that a transmission interruption occurs in the execution of the data transmission task, and the transmission interruption occurs before the transmission of the (total number of data packets - 1)th data packet; the third is that if the TVALID signal is invalid after the transmission of the (total number of data packets - 1)th data packet and before the transmission of the (total number of data packets)th data packet, it means that a transmission interruption occurs in the execution of the data transmission task, and the transmission interruption occurs after the transmission of the (total number of data packets - 1)th data packet is completed; Specifically, after completing the transmission of the first data packet, continue to set the assertion state of the TREADY signal according to the assertion state of the TVALID signal, and continue to transmit data packets when the TVALID signal and the TREADY signal are both at high levels. At the same time, the first counter cnt1 performs a counting operation (the value is increased by one), and the received data packet is processed in the next clock cycle. At the same time, the value of the second counter cnt2 is increased by one until the last data packet is transmitted. The data transmission task enters the final stage. After the first counter cnt1 reaches the total number of data packets, the TREADY signal is pulled low. After the value of the second counter cnt2 also reaches the total number of data packets, the data transmission task is terminated, and the values ​​of the first counter cnt1 and the second counter cnt2 are both cleared to zero for use in the next transmission task.

[0047] It should be noted that in the traditional transmission mode, the receiving end FPGA device uses internal storage resources to create a buffer in advance to wait for receiving data, and uses the sending end to control data transmission, so there will be two or more consecutive data transmission tasks; Fig.10 As shown, the TREADY signal is continuously asserted, and the assertion state of the TVALID signal determines the transmission of the data packet and the execution state of the data transmission task. It can be seen from the TLAST signal that the data packet D a0 Belongs to the first data transmission task, data packet D b0 and D b1 Belongs to the second data transmission task, D c0 , D c1 This is the third data transmission task. The first data transmission task is completed between the sending and receiving FPGA devices (FPGA device receives data packet Da0 ), pull the TVALID signal low, pull the TVALID signal high again after a period, and perform two data transmission tasks (the second data transmission task and the third data transmission task) in succession, that is, the FPGA device completes receiving the data packet D b0 , D b1 , D c0 and D c1 After that, the TVALID signal is pulled low; The present invention adopts a transmission mode in which the receiving end controls the data transmission, and uses a double counting method to ensure the correctness of data reception in a single data transmission task. When both the first counter and the second counter reach the total number of data packets, the data transmission task is terminated, so there will be no situation where two or more data transmission tasks are performed consecutively. Figure 4 As shown, when the value of the first counter is less than the total number of data packets, the assertion state of the TREADY signal is set according to the assertion state of the TVALID signal until all data packets in a single data transmission task are transmitted. After the value of the first counter reaches the total number of data packets, the TREADY signal is set to assert invalid until all data packets in a single data transmission task are processed. The value of the second counter reaches the total number of data packets, and the data transmission task is completed. The values ​​of the first counter and the second counter are cleared to zero before the next data transmission task can be continued.

[0048] The data receiving method according to the embodiment of the present invention is described below with reference to the accompanying drawings.

[0049] like Figure 1 As shown, a data receiving method according to an embodiment of the present invention is applied to an FPGA device, comprising the following steps: Create a first counter and a second counter, and set initial values ​​of the first counter and the second counter to zero; Determine the total length of data for a single data transmission task and the total number of corresponding data packets; It should be noted that the total data length of a single data transmission task is usually determined by negotiation between the sending end and the receiving end, and the total number of data packets is calculated by the receiving end based on the total data length of the single data transmission task and the data length of a single data packet; In some embodiments, the data length of a single data packet is the data bit width of a single transmission determined by the transmitting end and the receiving end through negotiation based on the AXI4-Stream protocol, so the data length of a single data packet is one of the data bit widths required by the AXI4-Stream protocol. For example, the data bit width required by the AXI4-Stream protocol may be 8, 16, 32, or 64 bits. The transmitting end and the receiving end negotiate to determine that the data bit width of a single transmission is 8 bits, 16 bits, 32 bits, or 64 bits. The total number of data packets is calculated by the receiving end based on the total data length of a single data transmission task and the data bit width of a single transmission. In other embodiments, the data length of a single data packet is a fixed length, and the fixed length is one of the data bit widths required by the AXI4-Stream protocol. For example, the data bit width required by the AXI4-Stream protocol can be 8, 16, 32, or 64 bits, and the fixed length is 8 bits, 16 bits, 32 bits, or 64 bits. The total number of data packets is calculated by the receiving end based on the total data length and the fixed length of a single data transmission task.

[0050] The assertion state of the TREADY signal is set according to the value of the first counter and the assertion state of the TVALID signal of the transmitting end, and the data transmission task is executed when both the TVALID signal and the TREADY signal are asserted (both the TVALID signal and the TREADY signal are at a high level), and the first counter is controlled to perform a corresponding counting operation according to the execution state of the data transmission task; wherein the counting operation includes adding one to the value and subtracting one from the value; It should be noted that the assertion state of the TREADY signal at the receiving end is jointly controlled by the assertion state of the TVALID signal at the sending end and the value of the first counter at the receiving end; specifically, at the beginning stage of the data transmission task and during the data transmission task, the assertion state of the TREADY signal is controlled by the assertion state of the TVALID signal; when the data transmission task enters the final stage, the assertion state of the TREADY signal is controlled by the value of the first counter.

[0051] It should also be noted that the data transmission task is performed when the TVALID signal and the TREADY signal are both asserted, specifically, a data packet is transmitted within a clock cycle in which the TVALID signal and the TREADY signal are both asserted, and the first counter performs a value increment operation when the FPGA device receives a data packet, and the value increment operation of the first counter and the operation of the FPGA device receiving a data packet are performed synchronously. In other words, during the clock cycle in which the FPGA device receives the nth data packet, the first counter synchronously performs a value increment operation.

[0052] receiving a data packet in the data transmission task and temporarily storing the data packet in a register, reading the data packet from the register in the next clock cycle for data processing, and increasing the value of the second counter by one while performing data processing; wherein both receiving the data packet and performing data processing on the data packet are single-cycle operations; It should be noted that storing the received data packets in the register specifically assigns the value of the received valid data packets to the pre-edited register of the FPGA device, with the purpose of stably storing the received valid data packets for data processing operations.

[0053] It should also be noted that the duration for the receiving end FPGA device to read a data packet from the register and process the data packet is less than or equal to one clock cycle; moreover, the FPGA device receives the nth data packet, the first counter performs a value increment operation based on the reception of the nth data packet, takes out the (n-1)th data packet from the register for data processing, and the second counter performs a value increment operation based on the processing of the (n-1)th data packet. These four operations are synchronously performed within the same clock cycle, and the process of receiving data packets and the process of processing data packets are a complete state machine; The purpose of data processing is, on the one hand, to take out the data packets stored in the register while receiving new data packets, so that the new data packets can be stored in the register. The inflow and outflow of data packets in the register ensure that the receiving end FPGA device can continuously receive data. At the same time, the parallel processing of data reception and data processing also makes the data receiving method provided by the present invention have no limitations on the input data stream, and is suitable for sending ends of various input data stream speeds, with strong universality. On the other hand, in the actual data stream, in addition to receiving data packets, the receiving end FPGA device often needs to process the data packets and transmit them to the back end for use by the user logic. Integrating data processing into the process of data reception can realize the synchronization of data transmission and data processing, and effectively improve the data transmission rate and data processing efficiency. Among them, data processing includes but is not limited to writing to Fifo, judgment, verification, and shifting.

[0054] When the values ​​of the first counter and the second counter are both equal to the total number of data packets, it means that all data packets of this data transmission task have been transmitted and processed, and this data transmission task is ended, and the values ​​of the first counter and the second counter are cleared to prepare for the next data transmission task.

[0055] It should be noted that the embodiment of the present invention sets the assertion state of the TREADY signal at the receiving end according to the value of the first counter and the assertion state of the TVALID signal at the sending end, and sets the operation of adding one to the value of the first counter and the operation of the FPGA device receiving data packets to be performed synchronously, so as to set the assertion state of the TREADY signal according to the real-time value of the first counter and the real-time assertion state of the TVALID signal, avoid the counting delay of the first counter, and cause the assertion state of the TREADY signal to be wrong, thereby ensuring the correct execution of the data transmission task.

[0056] When the FPGA device takes out the data packet from the register and processes the data, the data increment operation of the second counter is performed synchronously. On the one hand, the real-time and accuracy of the statistics of the processed data packets can be guaranteed. On the other hand, when the values ​​of the first counter and the second counter are equal to the total number of data packets, the data transmission task will be ended. The value increment operation of the first counter is synchronized with the operation of the FPGA device receiving the data packet, and the value increment operation of the second counter is synchronized with the operation of the FPGA device processing the data packet. This can save the waiting time for the next data transmission task. In other words, it can shorten the execution interval between two adjacent data transmission tasks, so that the FPGA device can quickly enter the next data transmission task, thereby further improving the speed at which the FPGA device receives data.

[0057] A data receiving method according to an embodiment of the present invention sets the assertion state of a TREADY signal according to the value of a first counter and the assertion state of a TVALID signal of a transmitting end, executes a data transmission task when both the TVALID signal and the TREADY signal are asserted, temporarily stores a received data packet in a register when the data transmission task is executed, and reads the data packet from the register for data processing before receiving the next data packet, synchronously performs the reception of the next data packet and the data processing of the previous data packet within one clock cycle, so as to ensure the high efficiency and continuity of data transmission, occupies only one register to temporarily store one data packet, does not need to establish a buffer pool, and occupies less memory space; A first counter is created in advance and used to synchronously count the number of received data packets when receiving data packets. A second counter is created in advance and used to synchronously count the number of processed data packets when processing data packets, until the values ​​of the first counter and the second counter reach the total number of data packets, the assertion state of the TREADY signal is set to end the data transmission task. A double counting method is used to ensure the correctness of data reception, and the assertion mode and assertion state of the TREADY signal are set to enable the receiving end to control the start and stop of the data transmission task, manage the inflow and outflow of data, and make flow control more simple and convenient.

[0058] In some embodiments, determining the total data length and the total number of data packets of a single data transmission task includes: The total length of the data for the data transmission task is determined through negotiation between the sending end and the receiving end; Determine the data bit width of a single transmission through a double-end negotiation between a transmitting end and a receiving end, wherein the data bit width of a single transmission is determined based on an AXI4-Stream protocol; The total number of data packets is determined based on the total data length of the data transmission task and the data bit width of a single transmission.

[0059] It should be noted that in order to apply to various scenarios in which the sending and receiving FPGA devices use the AXI4-Stream protocol for data transmission, the sending and receiving ends usually negotiate based on the AXI4-Stream protocol to determine the total data length of the data transmission task and the data bit width of a single transmission, and the receiving FPGA device determines the total number of data packets based on the total data length of the data transmission task and the data bit width of a single transmission.

[0060] Specifically, the total number of data packets of a single data transmission task can be calculated based on the total data length of the single data transmission task and the data bit width of the single transmission. For example, the total data length of a single data transmission task (the data length of the data packet to be transmitted) is 1024 bits, and the data bit width required by the AXI4-Stream protocol can be 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits, 512 bits and 1024 bits. The sending and receiving ends negotiate and determine that the data bit width of a single transmission (the data length of a data packet) is 128 bits. Then the total number of data packets of a single data transmission task is 1024 bits / 128 bits=8.

[0061] In some embodiments, setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal at the transmitting end includes: When the value of the first counter is less than the total number of data packets, if the TVALID signal is asserted, the TREADY signal is set to be asserted; if the TVALID signal is asserted, the TREADY signal is set to be invalid.

[0062] It should be noted that the assertion state of the TVALID signal at the transmitting end is detected at the beginning of each clock cycle to set the assertion state of the TREADY signal at the receiving end in the next clock cycle; Specifically, the value of the first counter is less than the total number of data packets, which is divided into two stages, namely, the data transmission task starts to proceed stage, and the data transmission task continues to proceed stage; At the beginning of the data transmission task, if the TVALID signal is detected to be valid (TVALID signal is high level) at the beginning of the clock cycle, the TREADY signal in the next clock cycle is set to be valid (TREADY signal is pulled high), so that the TVALID signal and TREADY signal are both asserted valid (both are high level) in the next clock cycle, and the receiving end receives a data packet; if the TVALID signal is detected to be invalid (TVALID signal is low level) at the beginning of the clock cycle, the TREADY signal is kept invalid in the next clock cycle; In the data transmission task continuing stage, if the TVALID signal is detected to be valid (TVALID signal is high level) at the beginning of the clock cycle, the TREADY signal in the next clock cycle is set to be valid (TREADY signal is pulled high), so that the TVALID signal and the TREADY signal are both asserted valid (both are high level) in the next clock cycle, and the receiving end receives a data packet; specifically, if Figure 6 and Figure 7 As shown in FIG. 1 , the TVALID signal assertion is detected to be valid at the rising edge of the second clock cycle, and the TREADY signal assertion is set to be valid in the third clock cycle, so that the TVALID signal and the TREADY signal are both asserted valid in the third clock cycle, and the receiving end FPGA device receives the data packet D in the third clock cycle. a1 , the TVALID signal is detected to be valid at the rising edge of the third clock cycle, and the TREADY signal is set to be valid in the fourth clock cycle, so that both the TVALID signal and the TREADY signal are asserted in the fourth clock cycle, and the receiving end FPGA device receives the data packet D in the fourth clock cycle a2 ; During the data transmission task continuation stage, if the TVALID signal is detected to be invalid (TVALID signal is low level) at the start of the clock cycle, it means that the transmission interruption occurs before the transmission of the (total number of data packets - 1)th data packet, then the TREADY signal in the next clock cycle is set to be invalid (pull down the TREADY signal), so that the TREADY signal starts to be invalid (low level) at the start of the next clock cycle; specifically, if Figure 8 As shown, the total number of data packets is 3. At the beginning of the third clock cycle, the TVALID signal is detected to be invalid, indicating that the second data packet D is transmitted. a1 If a transmission interruption occurs before the 4th clock cycle, the TREADY signal assertion set in the 4th clock cycle is invalid.

[0063] In some embodiments, before controlling the first counter to perform a corresponding counting operation according to the execution state of the data transmission task, the method further includes: At the start of each clock cycle, based on the value of the first counter, the assertion state of the TVALID signal and the TREADY signal, and in combination with the total number of data packets, collaboratively determine the execution state of the data transmission task; If the value of the first counter is less than the total number of data packets and the TVALID signal is asserted valid, it is predicted that the execution state of the data transmission task in the next clock cycle is in normal transmission; If the value of the first counter is less than or equal to the total number of data packets, and the TVALID signal is not asserted and the TREADY signal is asserted, then it is determined that the execution state of the data transmission task is transmission interruption.

[0064] It should be noted that if the value of the first counter is less than the total number of data packets, and the TVALID signal is asserted invalid and the TREADY signal is asserted valid, the transmission interruption occurs before the transmission of the (total number of data packets - 1)th data packet (for example, as shown in the attached Figure 8 As shown); if the value of the first counter is equal to the total number of data packets, and the TVALID signal is asserted invalid and the TREADY signal is asserted valid, the transmission interruption occurs after the transmission of the (total number of data packets-1)th data packet and before the transmission of the (total number of data packets)th data packet (for example, as shown in the attached Fig. 9 as shown).

[0065] Further, controlling the first counter to perform a corresponding counting operation according to the execution state of the data transmission task includes: If the execution status of the data transmission task in the next clock cycle is predicted to be normal transmission, the first counter is controlled to perform a value increment operation in the next clock cycle.

[0066] Furthermore, controlling the first counter to perform a corresponding counting operation according to the execution state of the data transmission task includes: If the execution status of the data transmission task is transmission interruption, the first counter is controlled to perform a value reduction operation in the next clock cycle.

[0067] It should be noted that, at the start of each clock cycle, based on the fact that the value of the first counter is less than the total number of data packets and the TVALID signal is asserted to be valid, it can only be predicted that the execution status of the data transmission task in the next clock cycle is normal transmission. This prediction result is only an estimated transmission status of the data packet in the next clock cycle, which is used to control the first counter to perform data addition operation in the next clock cycle. Whether the data packet is actually transmitted in the next clock cycle must be comprehensively determined in combination with the values ​​of the first counter and the second counter in the next clock cycle, the total number of data packets, and the assertion status of the TVALID signal and the TREADY signal.

[0068] Specifically, it is divided into the following application scenarios: The first application scenario is that the data transmission task transmits only one data packet, that is, the total number of data packets is 1, and the initial values ​​of the first counter and the second counter are both zero. The assertion state of the TVALID signal is detected at the beginning of each clock cycle. If the TVALID signal is asserted to be valid, the TREADY signal is set to be asserted to be valid in the next clock cycle. When both the TVALID signal and the TREADY signal are asserted to be valid in the next clock cycle, a data packet is received and stored in the register. While receiving the data packet, the value of the first counter is increased by one. When the value of the first counter reaches the total number of data packets, the TREADY signal is set to be invalid. The data packet is taken out from the register in the next clock cycle and data processing is performed on the data packet. While processing the data packet, the value of the second counter is increased by one. When the value of the second counter reaches the total number of data packets, the data transmission task is terminated, and the values ​​of the first counter and the second counter are cleared to prepare for the next data transmission task.

[0069] In a specific embodiment, Figure 4 and Figure 5 As shown, the total number of data packets is 1, the initial values ​​of the first counter and the second counter are both zero, and at the rising edge of the first clock cycle, the TVALID signal is detected to be pulled high, and then the TREADY signal is pulled high at the rising edge of the second clock cycle. In the second clock cycle, since both the TVALID signal and the TREADY signal are high, the FPGA device receives the data packet D a0 At the same time, in the second clock cycle, the value of the first counter is increased by one, and the value of the first counter reaches the total number of data packets 1. After the second clock cycle ends, the TREADY signal is pulled low, and the data packet D is reset in the third clock cycle. a0 Perform data processing, and at the same time increase the value of the second counter by one in the third clock cycle. When the value of the second counter reaches the total number of data packets 1, the data transmission task is terminated. In the fourth clock cycle, the values ​​of the first counter and the second counter are cleared to zero in preparation for the next data transmission task.

[0070] It should be noted that, since the present invention adopts a transmission mode in which the receiving end controls the data transmission, after all the data packets in a single data transmission task are transmitted, that is, after the value of the first counter reaches the total number of data packets, the TREADY signal is set to be invalid, and waits for the value of the second counter to reach the total number of data packets. The data transmission task is completed, so Figure 4 and Figure 5As shown, no matter whether the TVALID signal is still kept at a high level or pulled down after the second clock cycle ends, the TREADY signal needs to be pulled down after the second clock cycle ends.

[0071] The second application scenario is that the data transmission task needs to transmit multiple data packets and transmit the data packets continuously. The initial values ​​of the first counter and the second counter are both zero. The assertion state of the TVALID signal is detected at the beginning of each clock cycle. In this application scenario, the TVALID signal remains asserted from the beginning of the assertion detection to the end of the data transmission task. In the process of the next cycle in which the TVALID signal is detected to be asserted to the end of the data transmission task, the TREADY signal is set to be asserted; the data transmission task is received within the clock cycle in which both the TVALID signal and the TREADY signal begin to be asserted. The first data packet is stored in the register, and the value of the first counter is increased by one while receiving the data packet, and the data packet is taken out from the register in the next clock cycle, and data processing is performed on the data packet. The value of the second counter is increased by one while processing the data packet, and the above single-cycle operation of receiving data packets and processing data packets is repeated until the value of the first counter reaches the total number of data packets, and the TREADY signal is set to assert invalid. When the value of the second counter reaches the total number of data packets, the data transmission task is terminated, and the values ​​of the first counter and the second counter are cleared to zero in preparation for the next data transmission task.

[0072] In a specific embodiment, Figure 6 and Figure 7 As shown in FIG. 1 , the total number of data packets is 3, the initial values ​​of the first counter and the second counter are both zero, and at the rising edge of the first clock cycle, the TVALID signal is detected to be pulled high, and the TVALID signal keeps a high level from the rising edge of the first clock cycle to the end of the fourth clock cycle, and then the TREADY signal is pulled high at the rising edge of the second clock cycle, and the TREADY signal keeps a high level from the rising edge of the second clock cycle to the end of the fourth clock cycle. In the second clock cycle, the FPGA device receives the data packet D a0 At the same time, in the second clock cycle, the value of the first counter is increased by one, changing from 0 to 1; in the third clock cycle, the FPGA device receives the data packet D a1 , the value of the first counter is increased by one, from 1 to 2, and at the same time, in the third clock cycle, the FPGA device groups the data into D a0 After data processing, the value of the second counter is increased by one, changing from 0 to 1; in the fourth clock cycle, the FPGA device receives the data packet D a2, the value of the first counter is increased by 1, from 2 to 3, reaching the total number of data packets 3, and the TREADY signal is pulled low after the fourth clock cycle. At the same time, the FPGA device registers data packet D in the fourth clock cycle. a1 After data processing, the value of the second counter is increased by one, from 1 to 2; in the fifth clock cycle, the FPGA device processes the data group D a2 After data processing, the value of the second counter is increased by one, changing from 2 to 3, reaching the total number of data packets 3, ending this data transmission task. Within the 6th clock cycle, the values ​​of the first counter and the second counter are cleared to zero in preparation for the next data transmission task.

[0073] It should be noted that, since the present invention adopts a transmission mode in which the receiving end controls the data transmission, after all the data packets in a single data transmission task are transmitted, that is, after the value of the first counter reaches the total number of data packets, the TREADY signal is set to be invalid, and waits for the value of the second counter to reach the total number of data packets. The data transmission task is completed, so Figure 6 and Figure 7 As shown, no matter whether the TVALID signal is still kept at a high level or pulled down after the fourth clock cycle, the TREADY signal needs to be pulled down after the fourth clock cycle.

[0074] The third application scenario is that the data transmission task needs to transmit multiple data packets, and a transmission interruption occurs before the transmission of the (total number of data packets - 1)th data packet. The initial values ​​of the first counter and the second counter are both zero. According to the assertion of the TVALID signal, the TREADY signal is set to be asserted in the next clock cycle. When both the TVALID signal and the TREADY signal are asserted, the reception of the first data packet is completed. When the data packet is received, the value of the first counter is increased by one, and the data packet is processed in the next clock cycle. While processing the data packet, the value of the second counter is increased by one. Subsequently, at the start of each clock cycle, if the TVALID signal is asserted, the above data reception and data processing operations are repeated until it is detected that the TVALID signal is asserted invalid. Since the TVALID signal is asserted valid at the start of the previous clock cycle and the value of the first counter in the previous clock cycle does not reach the total number of data packets, the TREADY signal will be set to be asserted valid in this clock cycle, and the value of the first counter will be increased by one in this clock cycle, but the actual In the above clock cycle, data transmission interruption has begun to occur, and the execution status of the data transmission task is transmission interruption. The FPGA device has not received any data packets in this clock cycle, so the value of the first counter is reduced by one in the next clock cycle; subsequently, whenever the execution status of the data transmission task is transmission interruption, the value of the first counter is reduced by one in the next clock cycle when the execution status of the data transmission task is transmission interruption, until the value of the first counter reaches the total number of data packets, the TREADY signal is set to assert invalid, and when the value of the second counter reaches the total number of data packets, the data transmission task is terminated, and the values ​​of the first counter and the second counter are cleared to zero in preparation for the next data transmission task.

[0075] In a specific embodiment, Figure 8 As shown, the total number of data packets is 3, the initial values ​​of the first counter and the second counter are both zero, and at the rising edge of the first clock cycle, the TVALID signal is detected to be pulled high, so the TREADY signal is pulled high at the rising edge of the second clock cycle, and in the second clock cycle, the TVALID signal and the TREADY signal are both high, and the data packet D is received. a0, and at the same time, the value of the first counter is increased by one in the second clock cycle, changing from 0 to 1; at the rising edge of the third clock cycle, it is detected that the TVALID signal is pulled low, but because the TVALID signal is at a high level at the rising edge of the second clock cycle, and the value 1 of the first counter is less than the total number of data packets 3, the TREADY signal is kept at a high level in the third clock cycle and the value of the first counter is increased by one, changing from 1 to 2. According to the fact that the value 2 of the first counter is less than the total number of data packets 3, and the TVALID signal is invalid and the TREADY signal is valid, it is determined that the execution state of the data transmission task in the third clock cycle is a transmission interruption (the data transmission task is interrupted before the second data packet is transmitted), and the first counter is controlled to perform a value reduction operation in the fourth clock cycle, and at the same time, the data packet D is incremented in the third clock cycle. a0 Data processing is performed and the value of the second counter is increased by one, changing from 0 to 1; since the TVALID signal is detected to be low at the rising edge of the third clock cycle, the TREADY signal is pulled low at the rising edge of the fourth clock cycle, and according to the execution state of the data transmission task in the third clock cycle is transmission interruption, the value of the first counter is reduced by one in the fourth clock cycle, changing from 2 to 1; since the TVALID signal is detected to be high at the rising edge of the fourth clock cycle, the TREADY signal is pulled high at the rising edge of the fifth clock cycle, and the data packet D is received in the fifth clock cycle because both the TVALID signal and the TREADY signal are high. a1 At the same time, in the fifth clock cycle, the value of the first counter is increased by one, from 1 to 2; in the sixth clock cycle, since the TVALID signal and the TREADY signal are both high, the data packet D is received. a2 , and in the sixth clock cycle, the value of the first counter is increased by one, from 2 to 3, reaching the total number of data packets 3, and after the sixth clock cycle, the TREADY signal is pulled low, and at the same time, the data packet D is received in the sixth clock cycle. a1 Perform data processing and increase the value of the second counter by one, from 1 to 2; in the 7th clock cycle, group the data D a2 Perform data processing and increase the value of the second counter by one, from 2 to 3, reaching the total number of data packets 3, ending this data transmission task, and clearing the values ​​of the first counter and the second counter to zero within the 8th clock cycle in preparation for the next data transmission task.

[0076] The fourth type is that the data transmission task needs to transmit multiple data packets, and a transmission interruption occurs after the transmission of the (total number of data packets - 1)th data packet and before the transmission of the (total number of data packets)th data packet. The initial values ​​of the first counter and the second counter are both zero. According to the assertion of the TVALID signal, the TREADY signal is set to be asserted in the next clock cycle. When both the TVALID signal and the TREADY signal are asserted, the reception of the first data packet is completed. When the data packet is received, the value of the first counter is increased by one, and the data packet is processed in the next clock cycle. While the data packet is processed, the value of the second counter is increased by one. Subsequently, at the start of each clock cycle, if the TVALID signal is asserted, the above steps of data reception and data processing are repeated until it is detected that the TVALID signal is asserted invalid. Since the TVALID signal is asserted valid at the start of the previous clock cycle and the value of the first counter in the previous clock cycle is less than the total number of data packets, the TREADY signal will be set to be asserted valid in the clock cycle. In this clock cycle, the value of the first counter is increased by one to reach the total number of data packets, but in fact in this clock cycle Data transmission interruption has begun to occur, and the execution status of the data transmission task is transmission interruption. The FPGA device has not received the last data packet, so the value of the first counter is reduced by one in the next clock cycle to make the value of the first counter less than the total number of data packets; after the TVALID signal is detected to be asserted again, the TREADY signal is pulled high, and the last data packet is received when both the TVALID signal and the TREADY signal are asserted. When the value of the first counter reaches the total number of data packets, the TREADY signal is set to be invalid, and when the value of the second counter reaches the total number of data packets, the data transmission task is terminated, and the values ​​of the first counter and the second counter are cleared to zero in preparation for the next data transmission task.

[0077] In a specific embodiment, Fig. 9 As shown, the total number of data packets is 3, the initial values ​​of the first counter and the second counter are both zero, and at the rising edge of the first clock cycle, the TVALID signal is detected to be pulled high, so the TREADY signal is pulled high at the rising edge of the second clock cycle, and the data packet D is received in the second clock cycle because the TVALID signal and the TREADY signal are both high. a0 At the same time, in the second clock cycle, the value of the first counter is increased by one, changing from 0 to 1; in the third clock cycle, since the TVALID signal and the TREADY signal are both high, the data packet D is received. a1 , and increase the value of the first counter by one, from 1 to 2, and at the same time, in the third clock cycle, the data packet D a0Data processing is performed and the value of the second counter is increased by one, changing from 0 to 1; at the rising edge of the 4th clock cycle, it is detected that the TVALID signal is pulled low, but because the TVALID signal is at a high level at the rising edge of the 3rd clock cycle, and the value 2 of the first counter in the 3rd clock cycle is less than the total number of data packets 3, the TREADY signal is kept at a high level in the 4th clock cycle and the value of the first counter is also increased by one, changing from 2 to 3, reaching the total number of data packets 3. According to the fact that the value 3 of the first counter is equal to the total number of data packets 3, and the TVALID signal is asserted invalid and the TREADY signal is asserted valid, it is determined that the execution state of the data transmission task in the 4th clock cycle is a transmission interruption (the data transmission task is interrupted after the transmission of the 2nd data packet and before the transmission of the 3rd data packet), the first counter is controlled to perform a value reduction operation in the 5th clock cycle, and at the same time, the data packet D is incremented in the 4th clock cycle. a1 Data processing is performed and the value of the second counter is also increased by one, changing from 1 to 2; since the TVALID signal is detected to be low at the rising edge of the fourth clock cycle, the TREADY signal is pulled low at the rising edge of the fifth clock cycle, and according to the execution state of the data transmission task in the fourth clock cycle is transmission interruption, the value of the first counter is reduced by one in the fifth clock cycle, changing from 3 to 2, and the value 2 of the first counter is less than data packet 3; since the TVALID signal is detected to be pulled high at the rising edge of the fifth clock cycle, the TREADY signal is pulled high at the rising edge of the sixth clock cycle, and data packet D is received in the sixth clock cycle because both the TVALID signal and the TREADY signal are high. a2 At the same time, in the sixth clock cycle, the value of the first counter is increased by one, from 2 to 3, reaching the total number of data packets 3, and the TREADY signal is pulled low after the sixth clock cycle ends; in the seventh clock cycle, the data packet D a2 Perform data processing and increase the value of the second counter by one, from 2 to 3, reaching the total number of data packets 3, ending this data transmission task, and clearing the values ​​of the first counter and the second counter to zero within the 8th clock cycle in preparation for the next data transmission task.

[0078] It should also be noted that, since the data transmission task transmits multiple data packets, and when a transmission interruption occurs after transmitting the (total number of data packets - 1)th data packet and before transmitting the (total number of data packets)th data packet, even if the first counter reaches the total number of data packets, the FPGA device has not received the last data packet in this data transmission task, and the second counter reaches the total number of data packets, indicating that the FPGA device has received and processed the last data packet in this data transmission task. Therefore, an embodiment of the present invention is configured to end the data transmission task when the values ​​of the first counter and the second counter both reach the total number of data packets, so as to ensure the correctness of data reception and data processing by the FPGA device in a double counting manner.

[0079] In some embodiments, setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal at the transmitting end includes: When the value of the first counter is equal to the total number of data packets, determining whether the TVALID signal is asserted invalid and the TREADY signal is asserted valid; If yes, wait until the value of the first counter is reduced by one, and then set the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal; It should be noted that the receiving end detects the assertion state of the TVALID signal and the value of the first counter at the start of each clock cycle, and sets the assertion state of the TREADY signal in the next clock cycle according to the value of the first counter and the assertion state of the TVALID signal at the transmitting end; if, when the value of the first counter is equal to the total number of data packets, it is detected that the TVALID signal assertion is invalid and the TREADY signal assertion is valid, it means that the data transmission task needs to transmit multiple data packets, and a transmission interruption occurs after the transmission of the (total number of data packets - 1)th data packet and before the transmission of the (total number of data packets)th data packet, and no data transmission occurs for the last data packet in this data transmission task; but the value of the first counter has reached the data packet Total number, therefore, the value of the first counter must be reduced by one in the next clock cycle, and after the value of the first counter is updated to (total number of data packets - 1), the assertion state of the TREADY signal is set according to the detected value of the first counter and the assertion state of the TVALID signal. Specifically, if it is detected at the start of the clock cycle that the value of the first counter is less than the total number of data packets and the TVALID signal is invalid, the TREADY signal assertion is kept invalid in the next clock cycle until it is detected that the value of the first counter is less than the total number of data packets and the TVALID signal is valid. Then, the TREADY signal assertion is set valid in the next clock cycle, and the last data packet is transmitted. At the same time, the value of the first counter reaches the total number of data packets.

[0080] Otherwise, the TREADY signal is set to be deasserted until the data transfer task is completed.

[0081] It should be noted that, when the value of the first counter is equal to the total number of data packets, the TVALID signal is not detected to be invalid and the TREADY signal is valid, indicating that the transmission of the last data packet of this data transmission task has been completed. Therefore, the TREADY signal is set to be invalid (the TREADY signal is pulled low) until the current data transmission task is officially completed, the value of the first counter is cleared, and the next data transmission task is waited for, and the assertion state of the TREADY signal is set again according to the value of the first counter and the assertion state of the TVALID signal at the sending end.

[0082] In some embodiments, increasing the value of the second counter by one while performing data processing comprises: At the start of each clock cycle, the data processing state of the next clock cycle is determined by detecting the assertion states of the TVALID signal and the TREADY signal; wherein the data processing state includes not performing data processing and performing data processing on the received data packets; Specifically, at the start of each clock cycle, if it is detected that both the TVALID signal and the TREADY signal are asserted, the data processing state of the next clock cycle is determined to be data processing for the received data packet; otherwise, the data processing state of the next clock cycle is determined to be no data processing.

[0083] If the data processing state of the next clock cycle is to perform data processing on the received data packet, the value of the second counter is increased by one in the next clock cycle.

[0084] It should be noted that, after receiving the data packet, the received data packet will not be processed until the next clock cycle, and the value of the second counter will be increased by one while the received data packet is processed, that is to say, the operation of increasing the value of the second counter by one must occur in the next clock cycle after receiving the corresponding data packet; and the condition for receiving the data packet is that both the TVALID signal and the TREADY signal are asserted valid. Therefore, by detecting the assertion status of the TVALID signal and the TREADY signal, the data processing status of the next clock cycle can be determined, thereby determining whether the value of the second counter needs to be increased by one in the next clock cycle.

[0085] An FPGA device according to an embodiment of the present invention is described below with reference to the accompanying drawings.

[0086] like Figure 2As shown, an FPGA device according to an embodiment of the present invention includes a creation module, a determination module, a data operation module and a closing module; wherein the data operation module includes a data transmission unit and a data processing unit; The creation module is used to create a first counter and a second counter, and set the initial values ​​of the first counter and the second counter to zero; The determination module is used to negotiate with the sending end to determine the total length of data for a single data transmission task, and to determine the total number of data packets for a single data transmission task; The data transmission unit is used to set the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal, receive data packets to execute the data transmission task when both the TVALID signal and the TREADY signal are asserted, and control the first counter to perform corresponding counting operations according to the execution state of the data transmission task; wherein the counting operations include adding one to the value and subtracting one from the value; The data processing unit is used to receive the data packets in the data transmission task and temporarily store them in the register, read the data packets from the register in the next clock cycle for data processing, and increase the value of the second counter by one while performing data processing; wherein receiving the data packets and performing data processing on the data packets are both single-cycle operations; The finishing module is used to end the data transmission task and clear the values ​​of the first counter and the second counter to zero when the values ​​of the first counter and the second counter are both equal to the total number of data packets.

[0087] An FPGA device according to an embodiment of the present invention sets the assertion state of a TREADY signal according to the value of a first counter and the assertion state of a TVALID signal of a transmitting end through a data transmission unit, executes a data transmission task when both the TVALID signal and the TREADY signal are asserted, temporarily stores a received data packet in a register through a data operation module when executing the data transmission task, reads the data packet from the register for data processing before receiving the next data packet, synchronously receives the next data packet and processes the data of the previous data packet within one clock cycle, so as to ensure the high efficiency and continuity of data transmission, occupies only one register to temporarily store one data packet, does not need to establish a buffer pool, and occupies less memory space; The first counter and the second counter are pre-created by the creation module, and the first counter is controlled by the data operation module to synchronously count the number of received data packets when receiving data packets, and the second counter is controlled to synchronously count the number of processed data packets when processing data packets. When the values ​​of the first counter and the second counter reach the total number of data packets, the assertion state of the TREADY signal is set to end the data transmission task by the end module; the embodiment of the present invention adopts a double counting method to ensure the correctness of data reception, and participates in setting the assertion mode and assertion state of the TREADY signal, so as to realize the receiving end to control the start and stop of the data transmission task, manage the inflow and outflow of data, and make the flow control more simple and convenient.

[0088] A data receiving system according to an embodiment of the present invention is described below with reference to the accompanying drawings.

[0089] like Figure 3 As shown, a data receiving system according to an embodiment of the present invention comprises the FPGA device and the transmitting end according to the above embodiment; The transmitting end is used to negotiate with the FPGA device to determine the total data length of a single data transmission task; is also used to set the assertion state of the TVALID signal; and is also used to send a data packet to execute the data transmission task when both the TVALID signal and the TREADY signal are asserted.

[0090] A data receiving system according to an embodiment of the present invention determines the total data length of a single data transmission task through negotiation between a transmitting end and an FPGA device, sets the assertion state of a TVALID signal by the transmitting end, and uses the FPGA device to set the assertion state of a TREADY signal according to the value of a first counter and the assertion state of the TVALID signal of the transmitting end, and executes the data transmission task between the transmitting end and the receiving end when both the TVALID signal and the TREADY signal are asserted to be valid. When the FPGA device executes the data transmission task, it temporarily stores the received data packet in a register, and reads the data packet from the register for data processing before receiving the next data packet, and synchronously performs the reception of the next data packet and the data processing of the previous data packet within one clock cycle, so as to ensure the high efficiency and continuity of data transmission, and only occupies one register to temporarily store one data packet, without the need to establish a buffer pool, and occupies less memory space. The FPGA device pre-creates a first counter and is used to synchronously count the number of received data packets when receiving data packets. It pre-creates a second counter and is used to synchronously count the number of processed data packets when processing data packets. When the values ​​of the first counter and the second counter reach the total number of data packets, the assertion state of the TREADY signal is set to end the data transmission task. A dual counting method is used to ensure the correctness of data reception, and the assertion mode and assertion state of the TREADY signal are set to enable the receiving end to control the start and stop of the data transmission task, manage the inflow and outflow of data, and make flow control simpler and more convenient.

Claims

1. A data receiving method, characterized in that: The method comprises: Creating a first counter and a second counter, and setting initial values ​​of the first counter and the second counter to zero; Determine the total data length and total number of data packets for a single data transmission task; The assertion state of the TREADY signal is set according to the value of the first counter and the assertion state of the TVALID signal of the transmitting end, and the data transmission task is executed when the TVALID signal and the TREADY signal are both asserted and valid, and the first counter is controlled to perform a corresponding counting operation according to the execution state of the data transmission task; wherein the counting operation includes adding one to the value and subtracting one from the value; receiving a data packet in the data transmission task and temporarily storing the data packet in a register, reading the data packet from the register in the next clock cycle for data processing, and increasing the value of the second counter by one while performing data processing; wherein both receiving the data packet and performing data processing on the data packet are single-cycle operations; When the value of the first counter and the value of the second counter are both equal to the total number of data packets, the data transmission task is terminated and the values ​​of the first counter and the second counter are cleared.

2. The data receiving method according to claim 1, wherein: Determining the total data length and the total number of data packets for a single data transmission task includes: Determine the total length of the data of the data transmission task through negotiation between the sending end and the receiving end; Determine the data bit width of a single transmission through a double-end negotiation between a transmitting end and a receiving end, wherein the data bit width of a single transmission is determined based on an AXI4-Stream protocol; The total number of data packets is determined based on the total data length of the data transmission task and the data bit width of the single transmission.

3. The data receiving method according to claim 1, wherein: The step of setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal at the transmitting end includes: When the value of the first counter is less than the total number of data packets, if the TVALID signal is asserted, the TREADY signal is set to be asserted; if the TVALID signal is asserted, the TREADY signal is set to be invalid.

4. The data receiving method according to claim 1, wherein: Before controlling the first counter to perform a corresponding counting operation according to the execution state of the data transmission task, the method further includes: At the start of each clock cycle, based on the value of the first counter, the assertion status of the TVALID signal and the TREADY signal, and in combination with the total number of data packets, collaboratively determine the execution status of the data transmission task; If the value of the first counter is less than the total number of data packets and the TVALID signal is asserted valid, it is predicted that the execution state of the data transmission task in the next clock cycle is in normal transmission; If the value of the first counter is less than or equal to the total number of data packets, and the TVALID signal is asserted invalid and the TREADY signal is asserted valid, it is determined that the execution state of the data transmission task is transmission interruption.

5. The data receiving method according to claim 4, characterized in that: The controlling the first counter to perform a corresponding counting operation according to the execution state of the data transmission task includes: If the execution status of the data transmission task in the next clock cycle is predicted to be normal transmission, the first counter is controlled to perform a value increment operation in the next clock cycle.

6. The data receiving method according to claim 4, characterized in that: The controlling the first counter to perform a corresponding counting operation according to the execution state of the data transmission task includes: If the execution status of the data transmission task is transmission interruption, the first counter is controlled to perform a value reduction operation in the next clock cycle.

7. The data receiving method according to claim 6, characterized in that: The step of setting the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal at the transmitting end includes: When the value of the first counter is equal to the total number of data packets, determining whether the TVALID signal is invalid and the TREADY signal is valid; If yes, wait until the value of the first counter is reduced by one, and then set the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal; Otherwise, the TREADY signal is set to be deasserted until the data transfer task is completed.

8. The data receiving method according to claim 1, wherein: The step of increasing the value of the second counter by one while performing data processing comprises: At the start of each clock cycle, the data processing state of the next clock cycle is determined by detecting the assertion states of the TVALID signal and the TREADY signal; wherein the data processing state includes not performing data processing and performing data processing on the received data packets; If the data processing state of the next clock cycle is to process the received data packet, the value of the second counter is increased by one in the next clock cycle.

9. An FPGA device, characterized in that: It includes a creation module, a determination module, a data operation module and a closing module; wherein the data operation module includes a data transmission unit and a data processing unit; The creation module is used to create a first counter and a second counter, and set the initial values ​​of the first counter and the second counter to zero; The determination module is used to negotiate with the sending end to determine the total length of data for a single data transmission task, and to determine the total number of data packets for a single data transmission task; The data transmission unit is used to set the assertion state of the TREADY signal according to the value of the first counter and the assertion state of the TVALID signal, receive data packets to execute the data transmission task when both the TVALID signal and the TREADY signal are asserted, and control the first counter to perform corresponding counting operations according to the execution state of the data transmission task; wherein the counting operations include adding one to the value and subtracting one from the value; The data processing unit is used to receive the data packets in the data transmission task and temporarily store them in a register, read the data packets from the register in the next clock cycle for data processing, and increase the value of the second counter by one while performing data processing; wherein receiving the data packets and performing data processing on the data packets are both single-cycle operations; The finishing module is used to end the data transmission task and clear the values ​​of the first counter and the second counter to zero when the values ​​of the first counter and the second counter are both equal to the total number of data packets.

10. A data receiving system, characterized in that: Comprising the FPGA device and the transmitting end as claimed in claim 9; The transmitting end is used to negotiate with the FPGA device to determine the total data length of a single data transmission task; is also used to set the assertion state of the TVALID signal; and is also used to send a data packet to execute the data transmission task when both the TVALID signal and the TREADY signal are asserted.

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