Multi-chip synchronous signal transmission system and control method thereof

Abstract

The invention discloses a multi-chip synchronization signal transmission system and a control method thereof, and the system comprises a multi-chip signal transmission module, a signal input module, a synchronization mechanism setting module, a timing synchronization transmission module, a subordinate chip synchronization module, and a time synchronization check module. According to the invention, timing synchronous transmission processing is carried out on each signal data, timing transmission time is set, automatic transmission processing is carried out when the signal transmission time is reached, the transmission efficiency is improved, and the synchronous fault real-time monitoring module is arranged, so that the synchronous time point of each chip transmission signal is checked, and the detection accuracy is improved. According to the multi-chip synchronous signal transmission system, the accuracy of multi-chip synchronous signal transmission is guaranteed, encryption processing during signal transmission is achieved through the arrangement of the signal transmission inspection module, identity verification processing is conducted on the master chip, the slave chip and transmission target position equipment, and the accuracy of signal data transmission is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of signal transmission, and in particular to a multi-chip synchronous signal transmission system and a control method thereof. Background Art

[0002] Chip, also known as integrated circuit (IC) or microcircuit (Microcircuit), microchip, refers to a silicon wafer containing integrated circuits. It is very small and is often part of a computer or other electronic device. Chip is a general term for semiconductor component products. It is the carrier of integrated circuits and is divided from wafers. The chip production process includes many complex steps, such as design, manufacturing, packaging and testing. Multi-chip synchronous signal transmission refers to the use of synchronization signals to ensure that the data transmission between each chip is synchronized when multiple chips are used for data transmission. This synchronization is crucial to the stability of the system and the accuracy of the data. The synchronization signal is a signal that provides the same time reference to machines and equipment that need to process information synchronously. In a multi-chip system, each chip needs to receive and send data according to a unified time reference to ensure the consistency and integrity of the data. The synchronization signal can be a switch signal or a continuous pulse. The specific form depends on the needs and design of the system. In multi-chip synchronous signal transmission, there is usually a master chip (or synchronization source) responsible for generating the synchronization signal and transmitting the signal to other slave chips. After receiving the synchronization signal, the slave chip will synchronize its data transmission operation according to the signal's instructions. In this way, it can ensure that all chips start and end data transmission at the same time, thereby avoiding data conflicts and losses. However, the existing multi-chip synchronization signal transmission system does not fully confirm the synchronization of signal transmission. When deviations occur, they cannot be discovered and handled in time. Manual regular inspections are inefficient, and the security of signal transmission is low, which is prone to external tampering and theft. Summary of the invention

[0003] The object of the present invention is to provide a multi-chip synchronous signal transmission system and a control method thereof, so as to solve the problems proposed in the above-mentioned background technology that the synchronization confirmation of signal transmission in the existing multi-chip synchronous signal transmission system is not comprehensive enough, deviations cannot be discovered and handled in time, manual regular inspections are inefficient, and the security of signal transmission is low, which is prone to external tampering and theft.

[0004] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a multi-chip synchronous signal transmission system, comprising: a multi-chip signal transmission module, a signal entry module, a synchronization mechanism setting module, a timing synchronization transmission module, a slave chip synchronization module, a time synchronization verification module, a data concentration module, a signal positioning transmission module, a data synchronization transmission module, a synchronization fault real-time monitoring module and a signal transmission verification module, wherein the output end of the multi-chip signal transmission module is communicatively connected to the input end of the signal entry module, the output end of the signal entry module is communicatively connected to the input end of the synchronization mechanism setting module, the output end of the synchronization mechanism setting module is communicatively connected to the input end of the timing synchronization transmission module, the timing synchronization transmission module is bidirectionally connected to the slave chip synchronization module, the output end of the timing synchronization transmission module is communicatively connected to the input end of the time synchronization verification module, the time synchronization verification module is bidirectionally connected to the data concentration module, the output end of the data concentration module is communicatively connected to the input end of the signal positioning transmission module, the signal positioning transmission module is bidirectionally connected to the data synchronization transmission module, the output end of the signal positioning transmission module is communicatively connected to the input end of the synchronization fault real-time monitoring module, and the synchronization fault real-time monitoring module is bidirectionally connected to the signal transmission verification module;

[0005] The multi-chip signal transmission module is used to associate the signal transmission of the master chip and the slave chip;

[0006] The signal input module is used to input and process the transmission signals of the master chip and the slave chip;

[0007] The synchronization mechanism setting module is used to set and process the synchronization mechanism used for the transmission signals of the master chip and the slave chip;

[0008] The timing synchronization transmission module is used to perform timing transmission processing according to the signal transmitted by the synchronization mechanism;

[0009] The slave chip synchronization module is used to synchronize signal transmission between the slave chips;

[0010] The time synchronization checking module is used to check the time of signal synchronous transmission;

[0011] The data concentration module is used to aggregate the data in the synchronous transmission signal;

[0012] The signal positioning transmission module is used to perform positioning processing on the target position of the transmission signal;

[0013] The data synchronous transmission module is used to perform synchronous transmission processing on each signal data after locating the target position of the transmission signal;

[0014] The synchronization fault real-time monitoring module is used to detect the synchronization state of signal data transmission and perform real-time monitoring and processing when a synchronization fault occurs;

[0015] The signal transmission verification module is used to encrypt the signal transmission and perform integrity verification on the signal arriving at the target location.

[0016] Preferably, the multi-chip signal transmission module comprises: a master chip unit, a slave chip unit and a chip security identity association unit, and the master chip unit and the slave chip unit are both bidirectionally connected to the chip security identity association unit;

[0017] The main chip unit is used to process the signal data received and sent by each main chip;

[0018] The slave chip unit is used to process the signal data received and sent by each slave chip;

[0019] The chip security identity association unit is used to verify the identity security of the master chip and the slave chip.

[0020] Preferably, the synchronization mechanism setting module includes: a synchronization clock signal unit, a synchronization algorithm unit and a synchronization circuit unit;

[0021] The synchronous clock signal unit is used for the master chip to generate a synchronous clock signal according to an internal clock source or an externally input clock signal, and the master chip transmits the synchronous clock signal or the synchronous control signal to the slave chip through data, thereby completing the synchronous clock signal operation;

[0022] The synchronization algorithm unit is used to synchronize the data transmission between the master chip and the slave chip using a synchronization algorithm;

[0023] The synchronization circuit unit is used to complete data synchronization between the master chip and the slave chip through a synchronization circuit mechanism.

[0024] Preferably, the timing synchronization transmission module comprises a transmission time setting unit, a transmission time detection unit and a timing transmission unit, the output end of the transmission time setting unit is communicatively connected to the input end of the transmission time detection unit, and the output end of the transmission time detection unit is communicatively connected to the input end of the timing transmission unit;

[0025] The transmission time setting unit is used to set the signal transmission time;

[0026] The transmission time detection unit is used to detect the current transmission time of the signal;

[0027] The timing transmission unit is used to perform timing synchronous transmission processing on the signal when the set time is reached.

[0028] Preferably, the time synchronization verification module includes a timestamp acquisition unit, a self-time verification unit and a time synchronization verification unit, the output end of the timestamp acquisition unit is communicatively connected to the input end of the self-time verification unit, and the output end of the self-time verification unit is communicatively connected to the input end of the time synchronization verification unit;

[0029] The timestamp acquisition unit is used to acquire the timestamp of the current signal transmission;

[0030] The self-time checking unit is used to obtain the self-signal transmission time of the master chip and the slave chip;

[0031] The time synchronization verification unit is used to perform synchronization verification processing on the signal transmission time of the master chip and the slave chip according to the timestamp.

[0032] Preferably, the data concentration module includes a synchronization signal unit, a control instruction unit and a service data unit;

[0033] The synchronization signal unit is used to centrally process the synchronously transmitted signals;

[0034] The control instruction unit is used to centrally process the sent control instructions;

[0035] The service data unit is used to centrally process the content of the sent service data.

[0036] Preferably, the signal positioning transmission module comprises a signal transmission position selection unit, a signal transmission IP acquisition unit, a signal transmission IP verification unit and a terminal receiving unit, wherein the output end of the signal transmission position selection unit is communicatively connected to the input end of the signal transmission IP acquisition unit, the output end of the signal transmission IP acquisition unit is communicatively connected to the input end of the signal transmission IP verification unit, and the output end of the signal transmission IP verification unit is communicatively connected to the input end of the terminal receiving unit;

[0037] The signal transmission position selection unit is used to determine the target position of signal transmission;

[0038] The signal transmission IP acquisition unit is used to acquire the IP information of the signal transmission target location;

[0039] The signal transmission IP verification unit is used to verify the IP information and confirm the accuracy of the signal transmission target location;

[0040] The terminal receiving unit is used to perform signal transmission and reception work through the terminal at the target location.

[0041] Preferably, the synchronization fault real-time monitoring module includes a synchronization time point storage unit, a synchronization time point verification unit, a time point reset unit, a synchronization state recovery unit, a data encryption unit and a transmission protocol encryption unit, the synchronization time point storage unit is bidirectionally connected to the synchronization time point verification unit, the output end of the synchronization time point verification unit is communicatively connected to the input end of the time point reset unit, the output end of the time point reset unit is communicatively connected to the input end of the synchronization state recovery unit, the synchronization state recovery unit is bidirectionally connected to the data encryption unit, and the data encryption unit is bidirectionally connected to the transmission protocol encryption unit;

[0042] The synchronization time point storage unit is used to record and store the time points in real time;

[0043] The synchronization time point checking unit is used to check the synchronization time point of the current transmission signal;

[0044] The time point resetting unit is used to perform time point resetting processing through the synchronization time point storage unit when the synchronization time point deviates or is lost;

[0045] The synchronization state recovery unit is used to perform time point recovery processing on the signal synchronization transmission state;

[0046] The data encryption unit is used to use encryption technology in the multi-chip synchronization signal transmission process, the encryption technology includes symmetric encryption and asymmetric encryption, and encrypts the multi-chip synchronization signal to ensure that even if the signal is intercepted, it cannot be decrypted by unauthorized personnel;

[0047] The transmission protocol encryption unit is used to ensure the security and integrity of data during transmission by supporting encrypted transmission protocols, including TLS (Transport Layer Security) and SSL (Secure Sockets Layer).

[0048] Preferably, the signal transmission verification module includes a signal transmission encryption unit, an identity authentication unit, a synchronization signal integrity verification unit, a real-time monitoring unit, a log audit unit, a firmware update unit and a vulnerability management unit, the signal transmission encryption unit is bidirectionally connected to the identity authentication unit, the identity authentication unit is bidirectionally connected to the synchronization signal integrity verification unit, the synchronization signal integrity verification unit is bidirectionally connected to the real-time monitoring unit, the real-time monitoring unit is bidirectionally connected to the log audit unit, the log audit unit is bidirectionally connected to the firmware update unit, and the firmware update unit is bidirectionally connected to the vulnerability management unit;

[0049] The signal transmission encryption unit is used to encrypt sensitive data or control instructions when transmitting the synchronization signal;

[0050] The identity authentication unit is used to perform identity authentication before establishing communication between the master chip and the slave chip and the device at the target location;

[0051] The synchronization signal integrity check unit is used to split the integrity of the synchronization signal and perform integrity check processing on each split part;

[0052] The real-time monitoring unit is used to deploy a monitoring system to monitor the signal transmission process in real time, and promptly detect and handle abnormal situations;

[0053] The log audit unit is used to establish a complete log audit mechanism to record all operations and behaviors during the signal transmission process and to trace and investigate when a security incident occurs;

[0054] The firmware update unit is used to regularly release firmware updates and vulnerability repair patches to address emerging security threats and vulnerabilities;

[0055] The vulnerability management unit is used to establish a vulnerability management mechanism to promptly evaluate, repair and report discovered vulnerabilities to ensure that the security of the chip system is continuously maintained.

[0056] A control method for a multi-chip synchronous signal transmission system comprises the following steps:

[0057] S1. Set the reference clock source as the synchronization reference for all chips and distribute it to each chip through the circuit for time synchronization;

[0058] S2. Setting a timing mechanism to trigger the signal transmission between the master chip and the slave chip at a specific time point, so that the chips can perform synchronous operations at the same time;

[0059] S3, after the timing signal is transmitted, the chip is reset and the next signal transmission is performed;

[0060] S4, recording the transmission time of the signals from the master chip and the slave chip to the target device;

[0061] S5. Optimize the transmission speed according to the transmission time, adjust the delay of the chip clock and data signals, and perform precise synchronization control;

[0062] S6. When the transmission signal verification fails, the current transmission signal is isolated, the type of the current transmission signal is learned, and the dangerous signal type is stored;

[0063] S7, perform synchronization calibration and verification processing on the signal, send the synchronization signal after setting the synchronization parameters, measure the synchronization deviation after sending the synchronization signal, and perform precision adjustment processing on the synchronization deviation.

[0064] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

[0065] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting up a timed synchronous transmission module, the timed synchronous transmission processing of each signal data is realized, the timed transmission time is set, and automatic transmission processing is performed when the transmission signal time is reached, thereby improving the transmission efficiency; by setting up a synchronous fault real-time monitoring module, the synchronization time point of each chip transmission signal can be checked, and the accuracy of multi-chip synchronous signal transmission is guaranteed; by setting up a signal transmission verification module, encryption processing is realized during signal transmission, and identity authentication processing is performed on the master chip, the slave chip and the transmission target location device, thereby ensuring the accuracy of signal data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the drawings required for the implementation methods or the prior art descriptions are briefly introduced below. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0067] Figure 1 This is a block diagram of the overall system of the present invention. DETAILED DESCRIPTION

[0068] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0069] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] See also Figure 1As shown, the multi-chip synchronous signal transmission system of the embodiment of the present invention includes: a multi-chip signal transmission module, a signal entry module, a synchronization mechanism setting module, a timing synchronization transmission module, a slave chip synchronization module, a time synchronization verification module, a data concentration module, a signal positioning transmission module, a data synchronization transmission module, a synchronization fault real-time monitoring module and a signal transmission verification module, the output end of the multi-chip signal transmission module is communicatively connected to the input end of the signal entry module, the output end of the signal entry module is communicatively connected to the input end of the synchronization mechanism setting module, the output end of the synchronization mechanism setting module is communicatively connected to the input end of the timing synchronization transmission module, the timing synchronization transmission module is bidirectionally connected to the slave chip synchronization module, the output end of the timing synchronization transmission module is communicatively connected to the input end of the time synchronization verification module, the time synchronization verification module is bidirectionally connected to the data concentration module, the output end of the data concentration module is communicatively connected to the input end of the signal positioning transmission module, the signal positioning transmission module is bidirectionally connected to the data synchronization transmission module, the output end of the signal positioning transmission module is communicatively connected to the input end of the synchronization fault real-time monitoring module, and the synchronization fault real-time monitoring module is bidirectionally connected to the signal transmission verification module;

[0071] The multi-chip signal transmission module is used to associate the signal transmission of the master chip and the slave chip;

[0072] The signal input module is used to input and process the transmission signals of the master chip and the slave chip, ensuring that the signal sent by the master chip can be accurately received, stored, and processed or responded to by the slave chip;

[0073] The synchronization mechanism setting module is used to set and process the synchronization mechanism used for the transmission signals of the master chip and the slave chip;

[0074] The timing synchronization transmission module is used to perform timing transmission processing according to the signal transmitted by the synchronization mechanism;

[0075] The slave chip synchronization module is used to synchronize the signal transmission between the slave chips;

[0076] The time synchronization verification module is used to verify the time of signal synchronization transmission;

[0077] The data collection module is used to collect and process the data in the synchronous transmission signal;

[0078] The signal positioning transmission module is used to position the target position of the transmission signal;

[0079] The data synchronization transmission module is used to perform synchronization transmission processing on each signal data after locating the target position of the transmission signal;

[0080] The synchronization fault real-time monitoring module is used to detect the synchronization state of signal data transmission and perform real-time monitoring and processing when a synchronization fault occurs;

[0081] The signal transmission verification module is used to encrypt signal transmission and perform integrity verification on the signal reaching the target location.

[0082] The multi-chip signal transmission module includes: a master chip unit, a slave chip unit and a chip security identity association unit, and the master chip unit and the slave chip unit are both bidirectionally connected to the chip security identity association unit;

[0083] The main chip unit is used to process the signal data received and sent by each main chip;

[0084] The slave chip unit is used to process the signal data received and sent by each slave chip;

[0085] The chip security identity association unit is used to verify the identity security of the master chip and the slave chip;

[0086] Multi-chip signals mainly refer to signals exchanged between chips in electronic devices that adopt multi-chip design (such as multi-chip modules MCM) in order to achieve functional collaboration, data sharing or transmission of control commands. Multi-chip signals are characterized by diversity, complexity and high speed. Since there are multiple chips in the system and each chip may be responsible for different functions, the types and quantities of signals will be relatively large.

[0087] Among them, the synchronization mechanism setting module includes: a synchronization clock signal unit, a synchronization algorithm unit and a synchronization circuit unit;

[0088] The synchronous clock signal unit is used for the master chip to generate a synchronous clock signal according to the internal clock source or the external input clock signal. The master chip transmits the synchronous clock signal or the synchronous control signal to the slave chip through data, thereby completing the synchronous clock signal operation;

[0089] The synchronization algorithm unit is used to synchronize the data transmission between the master chip and the slave chip using the synchronization algorithm;

[0090] The synchronization circuit unit is used to complete data synchronization between the master chip and the slave chip through a synchronization circuit mechanism;

[0091] In a multi-chip system, since each chip may run in a different clock domain or have a different processing speed, timing mismatch or data conflict may occur during signal transmission and processing. Therefore, it is essential to establish an effective multi-chip signal synchronization mechanism to ensure the stability and reliability of the system.

[0092] The timing synchronous transmission module includes a transmission time setting unit, a transmission time detection unit and a timing transmission unit, the output end of the transmission time setting unit is communicatively connected to the input end of the transmission time detection unit, and the output end of the transmission time detection unit is communicatively connected to the input end of the timing transmission unit;

[0093] The transmission time setting unit is used to set the signal transmission time;

[0094] The transmission time detection unit is used to detect the current transmission time of the signal;

[0095] The timing transmission unit is used to perform timing synchronous transmission processing on the signal when the set time is reached. When timing transmission is required, the signal transmission time is set, the current transmission time of the signal is detected, and synchronous transmission processing is performed when the time for signal transmission is reached.

[0096] The time synchronization verification module includes a timestamp acquisition unit, a self-time verification unit and a time synchronization verification unit, the output end of the timestamp acquisition unit is communicatively connected to the input end of the self-time verification unit, and the output end of the self-time verification unit is communicatively connected to the input end of the time synchronization verification unit;

[0097] The timestamp acquisition unit is used to acquire the timestamp of the current signal transmission;

[0098] The self-time checking unit is used to obtain the self-signal transmission time of the master chip and the slave chip;

[0099] The time synchronization verification unit is used to perform synchronization verification processing on the signal transmission time of the master chip and the slave chip according to the timestamp.

[0100] Among them, the data concentration module includes a synchronization signal unit, a control instruction unit and a business data unit;

[0101] The synchronization signal unit is used to centrally process the synchronously transmitted signals;

[0102] The control instruction unit is used to centrally process the sent control instructions;

[0103] The service data unit is used to centrally process the content of the sent service data.

[0104] Among them, the signal positioning transmission module includes a signal transmission position selection unit, a signal transmission IP acquisition unit, a signal transmission IP verification unit and a terminal receiving unit, the output end of the signal transmission position selection unit is communicatively connected to the input end of the signal transmission IP acquisition unit, the output end of the signal transmission IP acquisition unit is communicatively connected to the input end of the signal transmission IP verification unit, and the output end of the signal transmission IP verification unit is communicatively connected to the input end of the terminal receiving unit;

[0105] The signal transmission position selection unit is used to determine the target position of the signal transmission;

[0106] The signal transmission IP acquisition unit is used to acquire the IP information of the signal transmission target location;

[0107] The signal transmission IP verification unit is used to verify the IP information and confirm the accuracy of the signal transmission target location;

[0108] The terminal receiving unit is used to perform signal transmission and reception work through the terminal at the target location.

[0109] Among them, the synchronization fault real-time monitoring module includes a synchronization time point storage unit, a synchronization time point verification unit, a time point reset unit, a synchronization state recovery unit, a data encryption unit and a transmission protocol encryption unit. The synchronization time point storage unit is bidirectionally connected to the synchronization time point verification unit, the output end of the synchronization time point verification unit is communicatively connected to the input end of the time point reset unit, the output end of the time point reset unit is communicatively connected to the input end of the synchronization state recovery unit, the synchronization state recovery unit is bidirectionally connected to the data encryption unit, and the data encryption unit is bidirectionally connected to the transmission protocol encryption unit;

[0110] The synchronous time point storage unit is used to record and store the time points in real time;

[0111] The synchronization time point checking unit is used to check the synchronization time point of the current transmission signal;

[0112] The time point resetting unit is used to perform time point resetting processing through the synchronization time point storage unit when the synchronization time point deviates or is lost;

[0113] The synchronization state recovery unit is used to perform time point recovery processing on the signal synchronization transmission state;

[0114] The data encryption unit is used to use encryption technology in the transmission process of multi-chip synchronization signals. The encryption technology includes symmetric encryption and asymmetric encryption. The multi-chip synchronization signals are encrypted to ensure that even if the signal is intercepted, it cannot be decrypted by unauthorized personnel;

[0115] The transport protocol encryption unit is used to ensure the security and integrity of data during transmission by supporting encrypted transport protocols, including TLS (Transport Layer Security) and SSL (Secure Sockets Layer).

[0116] Among them, the signal transmission inspection module includes a signal transmission encryption unit, an identity authentication unit, a synchronization signal integrity verification unit, a real-time monitoring unit, a log audit unit, a firmware update unit and a vulnerability management unit. The signal transmission encryption unit is bidirectionally connected to the identity authentication unit, the identity authentication unit is bidirectionally connected to the synchronization signal integrity verification unit, the synchronization signal integrity verification unit is bidirectionally connected to the real-time monitoring unit, the real-time monitoring unit is bidirectionally connected to the log audit unit, the log audit unit is bidirectionally connected to the firmware update unit, and the firmware update unit is bidirectionally connected to the vulnerability management unit;

[0117] The signal transmission encryption unit is used to encrypt sensitive data or control instructions when transmitting synchronization signals;

[0118] The identity authentication unit is used to perform identity authentication before establishing communication between the master chip and the slave chip and the device at the target location;

[0119] The synchronization signal integrity check unit is used to split the integrity of the synchronization signal and perform integrity check processing on each split part;

[0120] The real-time monitoring unit is used to deploy a monitoring system to monitor the signal transmission process in real time, and promptly detect and handle abnormal situations;

[0121] The log audit unit is used to establish a complete log audit mechanism to record all operations and behaviors during signal transmission and conduct tracing and investigation when security incidents occur;

[0122] The firmware update unit is used to regularly release firmware updates and vulnerability fixes to address emerging security threats and vulnerabilities;

[0123] The vulnerability management unit is used to establish a vulnerability management mechanism to promptly evaluate, repair and report discovered vulnerabilities to ensure that the security of the chip system is continuously maintained.

[0124] A control method for a multi-chip synchronous signal transmission system comprises the following steps:

[0125] S1. Set the reference clock source as the synchronization reference for all chips and distribute it to each chip through the circuit for time synchronization;

[0126] S2. Setting a timing mechanism to trigger the signal transmission between the master chip and the slave chip at a specific time point, so that the chips can perform synchronous operations at the same time;

[0127] S3, after the timing signal is transmitted, the chip is reset and the next signal transmission is performed;

[0128] S4, recording the transmission time of the signals from the master chip and the slave chip to the target device;

[0129] S5. Optimize the transmission speed according to the transmission time, adjust the delay of the chip clock and data signals, and perform precise synchronization control;

[0130] S6. When the transmission signal verification fails, the current transmission signal is isolated, the type of the current transmission signal is learned, and the dangerous signal type is stored;

[0131] S7, perform synchronization calibration and verification processing on the signal, send the synchronization signal after setting the synchronization parameters, measure the synchronization deviation after sending the synchronization signal, and perform precision adjustment processing on the synchronization deviation.

[0132] Specifically, when in use, each master chip and slave chip are associated to complete signal transmission, and the identity security of the master chip and the slave chip is verified before signal transmission. By recording and processing the transmission signals of the master chip and the slave chip, it is ensured that the signal sent by the master chip can be accurately received and stored by the slave chip, and corresponding processing or response is performed. The synchronization mechanism is set through a clock source or an externally input clock signal, a synchronization algorithm, and a synchronization circuit. The signal is synchronized for data transmission through different synchronization mechanisms. When timed transmission is required, the signal transmission time is set, the current signal transmission time is detected, and synchronous transmission processing is performed when the time when the signal needs to be transmitted is reached. The signal transmission between each slave chip is synchronized, and the time is synchronized during signal synchronous transmission. The time stamp of the current signal transmission is obtained, the signal transmission time of the master chip and the slave chip itself is obtained, and then the transmission time can be synchronized and verified through the timestamp, and the transmission data of each chip is centrally processed. Before the signal data is sent, the target position of the signal transmission is determined, the IP information of the target position of the signal transmission is obtained, and then the device of the sending target is verified through the IP address information to ensure the accuracy of the signal transmission. During the signal transmission, the signal transmission synchronization failure is monitored in real time, the time point is recorded and stored in real time, and the time point when the signal is transmitted is verified with the current time point. When the synchronization time point deviates or is lost, the time point is reset through the synchronization time point storage unit, and the transmission signal time point is reset and restored.

[0133] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0134] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope of the present disclosure is indicated by the following claims.

Claims

1. A multi-chip synchronous signal transmission system, characterized in that: include: A multi-chip signal transmission module, a signal entry module, a synchronization mechanism setting module, a timing synchronization transmission module, a slave chip synchronization module, a time synchronization verification module, a data concentration module, a signal positioning transmission module, a data synchronization transmission module, a synchronization fault real-time monitoring module and a signal transmission verification module, wherein the output end of the multi-chip signal transmission module is communicatively connected to the input end of the signal entry module, the output end of the signal entry module is communicatively connected to the input end of the synchronization mechanism setting module, the output end of the synchronization mechanism setting module is communicatively connected to the input end of the timing synchronization transmission module, the timing synchronization transmission module is bidirectionally connected to the slave chip synchronization module, the output end of the timing synchronization transmission module is communicatively connected to the input end of the time synchronization verification module, the time synchronization verification module is bidirectionally connected to the data concentration module, the output end of the data concentration module is communicatively connected to the input end of the signal positioning transmission module, the signal positioning transmission module is bidirectionally connected to the data synchronization transmission module, the output end of the signal positioning transmission module is communicatively connected to the input end of the synchronization fault real-time monitoring module, and the synchronization fault real-time monitoring module is bidirectionally connected to the signal transmission verification module; The multi-chip signal transmission module is used to associate the signal transmission of the master chip and the slave chip; The signal input module is used to input and process the transmission signals of the master chip and the slave chip; The synchronization mechanism setting module is used to set and process the synchronization mechanism used for the transmission signals of the master chip and the slave chip; The timing synchronization transmission module is used to perform timing transmission processing according to the signal transmitted by the synchronization mechanism; The slave chip synchronization module is used to synchronize signal transmission between the slave chips; The time synchronization checking module is used to check the time of signal synchronous transmission; The data concentration module is used to aggregate the data in the synchronous transmission signal; The signal positioning transmission module is used to perform positioning processing on the target position of the transmission signal; The data synchronous transmission module is used to perform synchronous transmission processing on each signal data after locating the target position of the transmission signal; The synchronization fault real-time monitoring module is used to detect the synchronization state of signal data transmission and perform real-time monitoring and processing when a synchronization fault occurs; The signal transmission verification module is used to encrypt the signal transmission and perform integrity verification on the signal arriving at the target location.

2. The multi-chip synchronous signal transmission system according to claim 1, characterized in that: The multi-chip signal transmission module comprises: a master chip unit, a slave chip unit and a chip security identity association unit, wherein the master chip unit and the slave chip unit are both bidirectionally connected to the chip security identity association unit; The main chip unit is used to process the signal data received and sent by each main chip; The slave chip unit is used to process the signal data received and sent by each slave chip; The chip security identity association unit is used to verify the identity security of the master chip and the slave chip.

3. The multi-chip synchronous signal transmission system according to claim 2, characterized in that: The synchronization mechanism setting module includes: a synchronization clock signal unit, a synchronization algorithm unit and a synchronization circuit unit; The synchronous clock signal unit is used for the master chip to generate a synchronous clock signal according to an internal clock source or an externally input clock signal, and the master chip transmits the synchronous clock signal or the synchronous control signal to the slave chip through data, thereby completing the synchronous clock signal operation; The synchronization algorithm unit is used to synchronize the data transmission between the master chip and the slave chip using a synchronization algorithm; The synchronization circuit unit is used to complete data synchronization between the master chip and the slave chip through a synchronization circuit mechanism.

4. The multi-chip synchronous signal transmission system according to claim 3, characterized in that: The timing synchronization transmission module includes a transmission time setting unit, a transmission time detection unit and a timing transmission unit, wherein the output end of the transmission time setting unit is communicatively connected to the input end of the transmission time detection unit, and the output end of the transmission time detection unit is communicatively connected to the input end of the timing transmission unit; The transmission time setting unit is used to set the signal transmission time; The transmission time detection unit is used to detect the current transmission time of the signal; The timing transmission unit is used to perform timing synchronous transmission processing on the signal when the set time is reached.

5. The multi-chip synchronous signal transmission system according to claim 4, characterized in that: The time synchronization verification module includes a timestamp acquisition unit, a self-time verification unit and a time synchronization verification unit, wherein the output end of the timestamp acquisition unit is communicatively connected to the input end of the self-time verification unit, and the output end of the self-time verification unit is communicatively connected to the input end of the time synchronization verification unit; The timestamp acquisition unit is used to acquire the timestamp of the current signal transmission; The self-time checking unit is used to obtain the self-signal transmission time of the master chip and the slave chip; The time synchronization verification unit is used to perform synchronization verification processing on the signal transmission time of the master chip and the slave chip according to the timestamp.

6. The multi-chip synchronous signal transmission system according to claim 5, characterized in that: The data concentration module includes a synchronization signal unit, a control instruction unit and a service data unit; The synchronization signal unit is used to centrally process the synchronously transmitted signals; The control instruction unit is used to centrally process the sent control instructions; The service data unit is used to centrally process the content of the sent service data.

7. The multi-chip synchronous signal transmission system according to claim 6, characterized in that: The signal positioning transmission module includes a signal transmission position selection unit, a signal transmission IP acquisition unit, a signal transmission IP verification unit and a terminal receiving unit, wherein the output end of the signal transmission position selection unit is communicatively connected to the input end of the signal transmission IP acquisition unit, the output end of the signal transmission IP acquisition unit is communicatively connected to the input end of the signal transmission IP verification unit, and the output end of the signal transmission IP verification unit is communicatively connected to the input end of the terminal receiving unit; The signal transmission position selection unit is used to determine the target position of signal transmission; The signal transmission IP acquisition unit is used to acquire the IP information of the signal transmission target location; The signal transmission IP verification unit is used to verify the IP information and confirm the accuracy of the signal transmission target location; The terminal receiving unit is used to perform signal transmission and reception work through the terminal at the target location.

8. The multi-chip synchronous signal transmission system according to claim 7, characterized in that: The synchronization fault real-time monitoring module includes a synchronization time point storage unit, a synchronization time point verification unit, a time point reset unit, a synchronization state recovery unit, a data encryption unit and a transmission protocol encryption unit, the synchronization time point storage unit is bidirectionally connected to the synchronization time point verification unit, the output end of the synchronization time point verification unit is communicatively connected to the input end of the time point reset unit, the output end of the time point reset unit is communicatively connected to the input end of the synchronization state recovery unit, the synchronization state recovery unit is bidirectionally connected to the data encryption unit, and the data encryption unit is bidirectionally connected to the transmission protocol encryption unit; The synchronization time point storage unit is used to record and store the time points in real time; The synchronization time point checking unit is used to check the synchronization time point of the current transmission signal; The time point resetting unit is used to perform time point resetting processing through the synchronization time point storage unit when the synchronization time point deviates or is lost; The synchronization state recovery unit is used to perform time point recovery processing on the signal synchronization transmission state; The data encryption unit is used to use encryption technology in the multi-chip synchronization signal transmission process, the encryption technology includes symmetric encryption and asymmetric encryption, and encrypts the multi-chip synchronization signal to ensure that even if the signal is intercepted, it cannot be decrypted by unauthorized personnel; The transmission protocol encryption unit is used to ensure the security and integrity of data during transmission by supporting encrypted transmission protocols, including TLS (Transport Layer Security) and SSL (Secure Sockets Layer).

9. The multi-chip synchronous signal transmission system according to claim 8, characterized in that: The signal transmission verification module includes a signal transmission encryption unit, an identity authentication unit, a synchronization signal integrity verification unit, a real-time monitoring unit, a log audit unit, a firmware update unit and a vulnerability management unit, wherein the signal transmission encryption unit is bidirectionally connected to the identity authentication unit, the identity authentication unit is bidirectionally connected to the synchronization signal integrity verification unit, the synchronization signal integrity verification unit is bidirectionally connected to the real-time monitoring unit, the real-time monitoring unit is bidirectionally connected to the log audit unit, the log audit unit is bidirectionally connected to the firmware update unit, and the firmware update unit is bidirectionally connected to the vulnerability management unit; The signal transmission encryption unit is used to encrypt sensitive data or control instructions when transmitting the synchronization signal; The identity authentication unit is used to perform identity authentication before establishing communication between the master chip and the slave chip and the device at the target location; The synchronization signal integrity check unit is used to split the integrity of the synchronization signal and perform integrity check processing on each split part; The real-time monitoring unit is used to deploy a monitoring system to monitor the signal transmission process in real time, and promptly detect and handle abnormal situations; The log audit unit is used to establish a complete log audit mechanism to record all operations and behaviors during the signal transmission process and to trace and investigate when a security incident occurs; The firmware update unit is used to regularly release firmware updates and vulnerability repair patches to address emerging security threats and vulnerabilities; The vulnerability management unit is used to establish a vulnerability management mechanism to promptly evaluate, repair and report discovered vulnerabilities to ensure that the security of the chip system is continuously maintained.

10. The control method of a multi-chip synchronous signal transmission system according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1. Set the reference clock source as the synchronization reference for all chips and distribute it to each chip through the circuit for time synchronization; S2. Setting a timing mechanism to trigger the signal transmission between the master chip and the slave chip at a specific time point, so that the chips can perform synchronous operations at the same time; S3, after the timing signal is transmitted, the chip is reset and the next signal transmission is performed; S4, recording the transmission time of the signals from the master chip and the slave chip to the target device; S5. Optimize the transmission speed according to the transmission time, adjust the delay of the chip clock and data signals, and perform precise synchronization control; S6. When the transmission signal verification fails, the current transmission signal is isolated, the type of the current transmission signal is learned, and the dangerous signal type is stored; S7, perform synchronization calibration and verification processing on the signal, send the synchronization signal after setting the synchronization parameters, measure the synchronization deviation after sending the synchronization signal, and perform precision adjustment processing on the synchronization deviation.

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