Distribution method of time division multiplexing coefficients, electronic equipment and storage medium

Abstract

The invention relates to the technical field of EDA, in particular to a time division multiplexing coefficient distribution method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a key information table, for a driving chip and a driven chip which are directly connected, calculating the delay optimization ratio TDR between chip pairs according to the target delay in the key information table; for a driving chip and a driven chip which are not directly connected, reference time delay between each chip pair on a key path from drvFPGAh to toFPGAh is obtained, and TDR between each chip pair is calculated through the reference time delay, target time delay and a time delay function. Compared with the prior art, the method provided by the invention balances delay distribution.

Description

Technical Field

[0001] The present invention relates to the technical field of EDA, and in particular to a method for allocating time division multiplexing coefficients, electronic equipment and storage medium. Background Art

[0002] In the localization process, when the chip assigned to each circuit unit is given, the timing of the system is estimated. In addition to the fixed hardware delays in the timing diagram, such as memory delays and port delays, the delay between two connected pin pairs will change with the change of channel usage between the corresponding chip pairs. Among them, each circuit unit has multiple pins, each pin is configured with a signal, and only pins with the same signal can be connected by wires. The topological structure formed by the same signal is a network net. After the wiring of each net is determined, it is possible to assign an accurate time-division multiplexing coefficient (TDM ratio) to each wiring segment to accurately estimate the system timing. However, the probabilistic router (ProbeRoute) assumes that all networks have the same timing criticality, assigns the same time-division multiplexing coefficient to the signals between each chip pair, and then estimates the delay between chip pairs. This method may overestimate the delay on the critical path and tend to be pessimistic about the critical path; it may underestimate the delay on the non-critical path and tend to be optimistic about the non-critical path. Summary of the invention

[0003] In order to solve the technical problem of delay imbalance caused by allocating the same time division multiplexing coefficient to the signals between each chip pair, the technical solution adopted by the present invention is: a method for allocating time division multiplexing coefficients, the method comprising the following steps:

[0004] B100, obtain a key information table, wherein the key information table includes associated entries of N driving pins, wherein each associated entry includes a driving pin drvPin, a driving chip drvFPGA, and multiple fan-out sub-entries, and each fan-out sub-entry includes a driven chip toFPGA, a target delay TargetDelay, and a delay optimization ratio ScaleRatio.

[0005] B200, assign the hth drive pin drvPin according to the key information table h drvFPGA h and toFPGA h The time division multiplexing coefficient of each chip pair includes:

[0006] B210, when drvFPGA h and toFPGA h When connected directly, according to TargetDelay h and delay function calculation drvFPGAh and toFPGA h The time division multiplexing coefficient TDR between them.

[0007] B220, when drvFPGA h and toFPGA h When it is not a direct connection, according to the wiring results, get the h toFPGA h The reference delay ref_delay between each chip pair on all paths is calculated according to ref_delay, TargetDelay h and delay function calculation net h TDR between each chip pair.

[0008] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0009] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0010] The present invention has at least the following beneficial effects:

[0011] The present invention provides a method for allocating time division multiplexing coefficients, an electronic device and a storage medium. For a directly connected driver chip and a driven chip, the delay optimization ratio TDR between the chip pairs is directly obtained according to the target delay in the key information table; for a non-directly connected driver chip and a driven chip, the delay optimization ratio TDR obtained from the drvFPGA is obtained. h toFPGA h The reference delay ref_delay between each chip pair on the critical path is used to calculate the TDR between each chip pair through the reference delay, the target delay and the delay function. Compared with the prior art in which the delay between chip pairs is estimated by directly allocating the same time division multiplexing coefficient to all networks in each chip pair, the method provided in the second embodiment of the present invention balances the distribution of delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1A flow chart of a wiring method provided in Embodiment 1 of the present invention;

[0014] Figure 2 A flow chart of a delay estimation method based on timing drive provided in Embodiment 2 of the present invention;

[0015] Figure 3 A schematic diagram for comparing the chip topology structure and the minimum trees of different networks is provided for the second embodiment of the present invention;

[0016] Figure 4 A flow chart of a method for obtaining path delay provided in Embodiment 3 of the present invention;

[0017] Figure 5 A schematic diagram of a method for obtaining a delay reservation ratio provided in a fourth embodiment of the present invention;

[0018] Figure 6 A schematic diagram of a method for obtaining a delay reservation ratio in a target relaxation area provided in Embodiment 5 of the present invention;

[0019] Figure 7 A schematic diagram of a method for obtaining a variable delay reservation ratio provided in Embodiment 6 of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0021] When the user design is placed in the FPGA for verification, the user design is generally large, and the user design needs to be divided into different modules and placed in different FPGAs. This process is called partitioning. After the partitioning is completed, it is necessary to optimize the path delay by copying and moving the circuit unit to ensure that the timing requirements are met. This process is called localization. In the partitioning and localization stages, wiring must be performed every time the system timing needs to be estimated, which will be too time-consuming. In order to solve this problem, the present invention provides embodiment 1.

[0022] Embodiment 1

[0023] See also Figure 1 , which shows a wiring method, the method comprising the following steps:

[0024] A100, obtain a key information table, wherein the key information table includes associated entries of N driving pins, wherein each associated entry includes a driving pin drvPin, a driving chip drvFPGA, and multiple fan-out sub-entries, and each fan-out sub-entry includes a driven chip toFPGA. Wherein toFPGA is directly or indirectly connected to drvFPGA.

[0025] Optionally, the chip is an FPGA chip, and other chips used for chip verification in the prior art all fall within the protection scope of the present invention.

[0026] Among them, each circuit unit has multiple pins, each pin is configured with a corresponding signal, and the pins of the same signal have a physical connectivity relationship, that is, a topological structure is formed between the pins of the same signal, and this topological structure is called a network.

[0027] It should be noted that when a user design is large, it needs to be placed in multiple FPGA chips for verification. Since the same user design is placed in multiple FPGAs, there are corresponding connections between the multiple FPGAs. Since the wire distance between the chips is long, the delay on the wire will be long. The timing path with the largest delay is the critical path. The greater the delay on the critical path, the worse the chip performance. Therefore, it is necessary to plan the wiring length and optimize the delay on the wire during the wiring process.

[0028] The driving pin drvPin is an active node to be optimized. The definition of the active node is the same as that in the fifth embodiment and will not be described in detail.

[0029] Among them, the driver chip drvFPGA is the chip where drvPin is located.

[0030] The driven chip toFPGA is the chip where the fan-out of drvPin is located. A drvPin may have multiple fan-outs, each of which may be located in a different chip or in the same chip. It should be noted that the path formed by the critical network between drvFPGA and toFPGA is the critical path.

[0031] A300, get the set of all networks to be routed net = {net1, net2, ..., net i ,…net N}, where net i is the i-th network, and the value of i ranges from 1 to N.

[0032] Among them, the i-th network net i The topology includes multiple pins with the same signal.

[0033] A500, for each network in net, traverse the key information table to obtain the key network set and the non-key network set; i The traversal steps include: net i The driving pin drvPin i Matches the drvPin of each associated entry. If a match is successful, net i Mark as a critical network and put it into the critical network set; if the match fails, the net i Mark the network as non-critical and put it into the non-critical network set.

[0034] It should be noted that the drvPin of all key networks is saved in the key information table, that is, if the network to be routed has been saved in the key information table, it means that the current network to be routed is a key network. In order to route the key network in a targeted manner, the key network is identified through A500.

[0035] A700, separately wire the networks in the critical network set and the networks in the non-critical network set.

[0036] It should be noted that, from the definition of a network, a network is a network topology formed by all pins with the same signal. Due to the different transmission delays between different pins, some pins of a critical network are located on the critical path, while others are not. Therefore, in a critical network, pins on the critical path are critical pins, and pins not on the critical path are non-critical pins. The steps given below are the steps for routing chip pairs that the critical path passes through and chip pairs that the non-critical path passes through.

[0037] Further, when net i When it is an element in the key network concentration, net i The wiring steps include:

[0038] A710, get net i The target chip where all the pins are located, the chip where the driving pins are located, and the chip where each fan-out pin is located form a chip pair.

[0039] A730, according to each chip pair, traverses the key chip pair composed of drvFPGA and toFPGA of each entry in the key information table. When a match is successful, the network between the matched chip pairs is i The pins passed through are marked as key pins, and the key pins between the chip pairs are directly wired; otherwise, the toFPGA is marked as a non-key chip, and a non-key chip set is obtained. The connection obtained by direct wiring is the key connection.

[0040] As an example, when the neti The connected chip pair is {F A ,F B}, where F A For the Ath chip, F B For the Bth chip, then F A and F B Chinese i The wiring steps include: according to the chip {F A ,F B} Traverse and search for the key chip pair {drvFPGA, toFPGA} composed of drvFPGA and toFPGA in each entry in the key information table. When the search is successful, it is F A and F B net i Directly route the key pins that pass through; otherwise, A ,F B}Marked as net i Non-critical chip pairs.

[0041] Since the key pin is the pin that affects the critical path delay, drvPin i The physical distance between the drvPin and the key pin determines the delay on the critical path, and the delay increases with the increase of physical distance. i The delay between the key pin and the drvPin is connected through the intermediate node. i The delay of direct connection will be smaller, which can directly reduce the delay on key pins, thereby effectively reducing the delay of critical paths and improving system performance.

[0042] A750, generate all connection net i The minimum tree of the chips in the non-critical chipset and the driver chip drvPart is obtained, and the wiring between drvPart and all the chips in the non-critical chipset is formed according to the minimum tree. The connection obtained by the minimum tree of this step is marked as a non-critical connection.

[0043] Steps A710-A750 complete the routing of the critical network, and by directly routing the critical pins on the critical path in the critical network, the delay on the critical path is reduced and the chip performance is improved.

[0044] Among them, the smallest tree is from net i Select some links from all the endpoints in so that these links connect all the endpoints and the total weight of the formed tree is the smallest.

[0045] Optionally, the minimum tree is a Steiner minimum tree SMT (Steiner minimum tree) or a minimum spanning tree (MST).

[0046] Preferably, the minimum tree is a Steiner minimum tree SMT. In the prior art, other wiring methods with the same function as obtaining the minimum tree all fall within the protection scope of the present invention.

[0047] In summary, the present invention provides a wiring method, which divides all networks to be wired into critical networks according to the driving pins in the key information table, and then divides the critical pins and non-critical pins in the critical network according to the driving chip and driven chip of each driving pin recorded in the key information table, and then performs different wiring methods for the critical pins and non-critical pins. Under the premise of ensuring the wiring efficiency, the results of the probabilistic router are more in line with the actual timing drive router.

[0048] Embodiment 1 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0049] Embodiment 1 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0050] Since the number of signals between chips is much larger than the number of physical connections, time-division multiplexing is usually required to complete the allocation between signals and physical connections. The probabilistic router (ProbeRoute) assumes that all networks have the same timing criticality, assigns the same time-division multiplexing coefficient to the signals between each chip pair, and then estimates the delay between chip pairs. This method may overestimate the delay on the critical path and tend to be pessimistic about the critical path; it may underestimate the delay on the non-critical path and tend to be optimistic about the non-critical path. In order to solve this technical problem, the present invention provides embodiment 2.

[0051] Embodiment 2

[0052] See also Figure 2 , which shows a flow chart of a method for allocating time division multiplexing coefficients, the method comprising the following steps:

[0053] B100, obtain a key information table, wherein the key information table includes associated entries of N driving pins, wherein each associated entry includes a driving pin drvPin, a driving chip drvFPGA, and multiple fan-out sub-entries, and each fan-out sub-entry includes a driven chip toFPGA, a target delay TargetDelay, and a delay optimization ratio ScaleRatio.

[0054] The key information table is the same as that in the first embodiment, and drvPin, drvFPGA and toFPGA are not described in detail. Compared with the key information table of A100 in the first embodiment, the key information table in the second embodiment also includes the target delay TargetDelay and the delay optimization ratio ScaleRatio of each fan-out.

[0055] Among them, TargetDelay is the target delay that needs to be achieved between drvFPGA and each fan-out toFPGA.

[0056] Among them, the delay optimization ratio ScaleRatio is the ratio that needs to be optimized between drvFPGA and toFPGA.

[0057] B200, assign the hth drive pin drvPin according to the key information table h drvFPGA h and toFPGA h The time division multiplexing coefficient of each chip pair between them;

[0058] Among them, in the key information table, drvPin h For key pins, in drvFPGA h and toFPGA h The two chips may be directly connected, or may need to be indirectly connected via one or more chips, and the wiring method provided in the first embodiment is used for wiring.

[0059] Further, B200 includes:

[0060] B210, when drvFPGA h and toFPGA h When connected directly, according to TargetDelay h and delay function calculation drvFPGA h and toFPGA h The time division multiplexing coefficient TDR between them.

[0061] In the delay function, the estimated delay is the dependent variable, TDR is the independent variable, and the estimated delay is positively correlated with TDR. Optionally, the delay function is a user-given function, and other methods for obtaining the delay function fall within the protection scope of the present invention.

[0062] Among them, when drvFPGA h and toFPGA h When connected directly, TargetDelay h To estimate the delay.

[0063] B220, when drvFPGA h and toFPGA h When it is not a direct connection, according to the wiring results, get the h toFPGA h The reference delay ref_delay between each chip pair on all paths is calculated according to ref_delay, TargetDelay h and delay function calculation net h TDR between each chip pair. net h For the drive pin drvPin h Driven network.

[0064] It should be noted that when drvFPGA h and toFPGA h When it is a non-direct connection, the key information table saves the drvFPGA h toFPGA h TargetDelay h , which is generated by drvFPGA h toFPGA h The delay of all chip pairs that the shortest paths pass through is composed of, but how to allocate the corresponding routing usage to each chip pair is unknown, so it is necessary to estimate the reference delay between each chip pair. The steps for obtaining the reference delay ref_delay of each chip pair also include:

[0065] B221, get net h All minimal trees of all chips where all pins are located.

[0066] Optionally, the minimum tree is a minimum spanning tree. Methods for calculating the optimal path using other minimum trees in the prior art also fall within the protection scope of the present invention.

[0067] Preferably, the minimum tree is net iThe Steiner minimum tree SMT (Steiner minimum tree). The Steiner minimum tree SMT is used to minimize the total number of hops in the network. Among them, SMT means starting from a set of specific pins in a weighted undirected graph of a net, looking for a tree that contains all these pins and possible other non-specified additional pins, so that the sum of the weights of all the edges of the tree is as small as possible.

[0068] B222, get from drvFPGA h toFPGA h The sum of the network routing shares Pro of all networks between each chip pair. Among them, Pro is called the channel routing share. It should be noted that there may be multiple networks between each chip pair, and each network occupies a corresponding part of the routing share.

[0069] As a preferred embodiment, B222 also includes obtaining chip pair {F A ,F B} between the rth network net r Route Share Pro r,AB Steps:

[0070] B2221, when drvPin h for net r Pin in, get net r The set T of N(r) smallest trees r ; T r ={t r1 ,t r2 ,…,t rj ,…t rN(r)}, t rj T r The jth smallest tree in t rj Including K connections E rj ={e AB |e AB ∈t rj , where e AB For the Ath chip F A To the Bth chip F B The connection line between them}. Among them, E rj t rj The connection set.

[0071] B2222, chip pair {F A ,F B The rth network net between} r Route Share Pro r,AB Meet: Pro r,AB =∑ r (1 / |T r|), where r is |T r | is the size of the set. That is, net r In the chip pair {F A ,F B The routing share between} is the cumulative sum of the routing shares of all minimum trees.

[0072] As an example, see Figure 3 , which shows a schematic diagram of the comparison of the chip topology and the minimum trees of different networks. The schematic diagram includes the minimum trees of two networks: two minimum trees of net1 and one minimum tree of net2. The two minimum trees of net1 include the first minimum tree from A through B, F to G, and the second minimum tree from A through E, F to G. The minimum tree of net2 is the third minimum tree from A through E to D. Figure 3 It can be seen that net1 obtains two minimum trees, and |T1| = 2. Then, the routing share of the connection between each chip pair in the first minimum tree is 0.5, and the routing share of the connection between each chip pair in the second minimum tree is also 0.5; and e FG That is, the connection of the first smallest tree and the connection of the second smallest tree. According to Pro r,AB From the formula, we can see that e FG The routing share is 0.5+0.5=1. The usage of the corresponding channels is shown in Table 1:

[0073] Table 1 Channel usage examples

[0074] Channel Net1 Net2 Total A→B 0.5 0 0.5 A→E 0.5 1 1.5 E→D 0 1 1 B→F 0.5 0 0.5 E→F 0.5 0 0.5 F→G 1 0 1

[0075] From Table 1, we can see that net1 has A and F B The routing share between them is 0.5, and net2 is in F A and F B The routing share between F A and F B The channel routing share between them is 0.5. It should be noted that the network routing share is the routing share of a certain network between chip pairs, while the channel routing share is the sum of the routing shares of all networks between chip pairs.

[0076] Other methods for obtaining the network routing share of each network between each chip pair also fall within the protection scope of the present invention.

[0077] B223, obtain the reference delay ref_delay between each chip pair according to Pro, wire resource supply and delay function between each chip pair.

[0078] Among them, the product of Pro and the wire bandwidth is equal to the routing usage. Since the bandwidth of each wire is 1, the channel routing share between each chip pair is equal to the routing usage. Among them, ref_delay is positively correlated with Pro and negatively correlated with supply.

[0079] Optionally, ref_delay satisfies: ref_delay=f(TDR), TDR=usage / supply, usage=Pro, where f(TDR) is a delay function. Other methods for calculating ref_delay based on Pro, supply and delay function also fall within the protection scope of the present invention.

[0080] Optional, for each associated entry in drvPin h For each fan-out sub-entry, the step of calculating its TDR between each chip pair according to ref_delay and the delay function also includes:

[0081] B224, according to ref_delay, chip from drvFPGA h toFPGA h The shortest path set and TargetDelay h Calculate the delay optimization ratio ScaleRatio h , where ScaleRatio h Negatively correlated with ref_delay and negatively correlated with TargetDelay h Positive correlation.

[0082] Optional, ScaleRatio h =TargetDelay h / ref_delay. Others depend on ref_delay and TargetDelay h Calculating ScaleRatio h All of the methods fall within the protection scope of the present invention.

[0083] B225, according to ScaleRatio h and ref_delay to estimate the target channel delay pair_delay between each chip pair.

[0084] Where pair_delay and ScaleRatio h , ref_delay are both positively correlated.

[0085] Optional, pair_delay = ScaleRatio h ×ref_delay. Others depend on ScaleRatioh The method of calculating pair_delay using ref_delay falls within the protection scope of the present invention.

[0086] B226, calculate the TDR between each chip pair based on pair_delay and delay function.

[0087] As a preferred embodiment, the method further includes:

[0088] B300, based on TDR and wire resource supply, calculate the usage of the critical path between chip pairs. TDR is positively correlated with usage and negatively correlated with wire resource supply between chip pairs. Supply is the total number of wires allocated for routing between chip pairs.

[0089] Optionally, TDR satisfies: TDR=usage / supply. Other methods in the prior art for calculating the time-division reuse coefficient based on the usage of wire resources and wire resources all fall within the protection scope of the present invention.

[0090] Prioritize allocating wire resources to signals in critical networks. The more wire resources allocated, the lower the delay of the critical path, thus achieving the goal of optimizing the critical path.

[0091] As a preferred embodiment, the method further includes:

[0092] B400, obtains TDR of non-critical paths between chip pairs, including:

[0093] B410, calculate the wire resource supply′ of the non-critical path according to the usage of the critical path between the chip pairs and the wire resource supply.

[0094] Among them, supply′ satisfies: supply′=supply-usage.

[0095] B420, calculate the time-division reuse coefficient TDR' according to the routing usage' and supply' of the non-critical path. The calculation method of TDR' is the same as that of TDR, which will not be repeated here.

[0096] The step of obtaining usage' is to obtain the channel routing share Pro' between each chip pair according to steps B221-B222, and obtain usage' according to Pro'. When the bandwidth of each wire is 1, Pro' is equal to usage'.

[0097] After allocating signal wire resources to key networks first, the time-sharing multiplexing coefficient of non-key networks between chip pairs is obtained through B400, thereby achieving the purpose of optimizing key networks.

[0098] In summary, the method provided in the second embodiment of the present invention directly obtains the delay optimization ratio TDR between the chip pairs according to the target delay in the key information table for the directly connected driver chip and the driven chip; and obtains the delay optimization ratio TDR from the drvFPGA for the indirectly connected driver chip and the driven chip. h toFPGA h The reference delay ref_delay between each chip pair on the critical path is used to calculate the TDR between each chip pair through the reference delay, the target delay and the delay function. Compared with the prior art in which the delay between chip pairs is estimated by directly allocating the same time division multiplexing coefficient to all networks in each chip pair, the method provided in the second embodiment of the present invention balances the distribution of delay.

[0099] Embodiment 2 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0100] Embodiment 2 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0101] After the network routing share is evenly distributed to each chip pair through the probabilistic router, because there are unidirectional and bidirectional channel wires between each chip pair, and the number and delay function of the two are different, if the routing share in the chip pair is not reasonably distributed to the two, the delay estimation will have a large deviation from the reality. In order to solve this technical problem, the present invention provides embodiment three.

[0102] Embodiment 3

[0103] See also Figure 4 , which shows a flow chart of a method for obtaining path delay, the method comprising the following steps:

[0104] C100, obtaining the wiring resource attributes between each chip pair, wherein the wiring resource attributes include routing usage and wire resource supply.

[0105] The wire resource supply is the total number of wires in the channel of the chip pair, which is divided into bidirectional wires and unidirectional wires. In particular, unidirectional wires can only accommodate signals in the same direction.

[0106] Among them, the routing usage is the number of signals between two chips, distinguishing the transmission direction.

[0107] C200,reconfigures the delay on each wire between chip pairs according to the routing resource attributes between,each chip pair.

[0108] Further, reconfigure the Ath chip F A and the Bth chip F B The wires between the chip pairs AB The delay steps include:

[0109] C210, when F A and F B When all the communication channels formed by the connections between them are single channel type, according to F A and F B Usage of wiring between AB and wire resourcesSupply AB Calculate e AB The delay on.

[0110] Among them, the channel type is divided into two types. The first type is a single channel type. The single channel type is divided into a unidirectional communication channel and a bidirectional communication channel. Among them, the unidirectional communication channel also includes a communication channel composed of F A to F B The communication channel and F B to F A communication channel. A and F B When all the communication channels formed by the connections between the two are one-way communication channels or two-way communication channels, it is called F A and F B There is only a single channel type. For example, F A and F B All the communication channels formed by the connections between them are A to F B One-way communication channel; or, both are from F A and F B The second type is a composite channel type, which includes two or more channels among a unidirectional communication channel in a specified direction, a unidirectional channel opposite to the specified direction, and a bidirectional communication channel. For example, F A and F B The communication channel formed by all the connections between F A to F B One-way communication channel and F A and F B or, including a combination of bidirectional channels between F B to F A One-way communication channel and F A and F Bor, including a combination of bidirectional channels between F A to F B One-way communication channel, F B to F A One-way communication channel and F A and F B A combination of two-way channels between.

[0111] As a preferred embodiment, when e AB Only by F A to F B When the transmission channel is one-way, net i The usage of the wiring in a unidirectional transmission channel is Usage i,AB , F A and F B The wire resources of all unidirectional transmission channels u between them are Supply u AB , then F A to F B Delay between AB satisfy:

[0112] delay AB =f u (TDR u AB ). Among them, F A and F B Time division multiplexing coefficient TDR u AB satisfy:

[0113] TDR u AB =∑ i (Usage i,AB ) / Supply u AB .

[0114] Among them, ∑ i (Usage i,AB ) is used to calculate F A and F B The cumulative sum of the routing usage of all networks in the unidirectional transmission channel between delay AB With TDR u AB Positive correlation, TDR u AB The larger the delay, AB The bigger.

[0115] Optional, f u (x) is a given function, where x is the time division multiplexing coefficient.

[0116] Furthermore, when F A and F B When there is only a two-way transmission channel between i,AB Because F A to F B In the bidirectional transmission channel of net i Usage of routing i,BA Because F B to F A In the bidirectional transmission channel of net i The wiring usage of Supply b AB For F A and F B The wire resources of all bidirectional transmission channels b between A and F B Delay between AB satisfy:

[0117] delay AB =f b (TDR b AB ). Among them, F A and F B Time division multiplexing coefficient TDR b AB satisfy:

[0118] TDR b AB =∑ i (Usage i,AB +Usage i,BA ) / Supply b AB .

[0119] Among them, ∑ i (Usage i,AB +Usage i,BA ) is used to calculate F A and F B The cumulative sum of the routing usage of all networks between them. AB With TDR b AB Positive correlation, TDR b AB The larger the delay, AB The bigger.

[0120] Optional, f b (x) is a given function.

[0121] The core idea is to use F A and F B The routing usage of the transmission channel and the wire resource calculation delay of the transmission channel AB All formulas fall within the protection scope of the present invention.

[0122] C220, otherwise, the time-division multiplexing coefficient is reallocated so that F A and F B The delays in all channel types are equal, and the redistributed delays are obtained.

[0123] Among them, when e AB When there are at least two types of channels formed by all the connections in the , it is necessary to balance the wire time-division multiplexing coefficients so that the delays generated by the wires of each channel type are equal or approximately equal.

[0124] As a preferred embodiment, when the delays generated by the wires of each channel type are equal, the delay after the wire resources are reallocated satisfies the following conditions:

[0125] f u (TDR u AB ) = f u (TDR u BA ) = f b (TDR AB ); (1)

[0126] Among them, f u (x) and f b (x) are given functions, respectively, and f in C210 u (x) and f b (x) are the same.

[0127] Among them, TDR u AB =Usage u AB / Supply u AB , TDR u AB Because F A to F B The time-division multiplexing coefficient of all unidirectional channels u, Usage u AB Because F A to F B The routing usage of all unidirectional channels u, Supply u AB Because F A to F BThe wire resources of all unidirectional channels u. TDR u BA =Usage u BA / Supply u BA , TDR u BA Because F B to F A The time-division multiplexing coefficient of all unidirectional channels, Usage u BA Because F B to F A The routing usage of all unidirectional channels, Supply u BA Because F B to F A The wire resources for all unidirectional channels of TDR AB =((∑ i Usage i,AB +∑ i Usage i,BA )-Usage u AB -Usage u BA ) / Supply b AB , TDR AB F A and F B The wire time-division multiplexing coefficient of all bidirectional channels in , ∑ i Usage i,AB +∑ i Usage i,BA F B and F A The routing usage of all networks in (∑ i Usage i,AB +∑ i Usage i,BA )-Usage u AB -Usage u BA F B and F A The routing usage of all bidirectional channels in Supply b AB Because F B to F A Wire resources for all channel types.

[0128] As an example, if F A and FB The channel type formed by all the connections between them is a bidirectional channel type and the F A to F B If the channel type is one-way, then according to f u (TDR u AB ) = f b (TDR AB ) calculates the delay, where TDR AB Usage u BA is 0.

[0129] Algorithms in the prior art that make the delays generated by wires of each channel type equal or approximately equal all fall within the protection scope of the present invention.

[0130] In summary, the third embodiment of the present invention determines whether the transmission channel between the chip pairs is a single channel type. If so, the delay is calculated using the delay calculation formula corresponding to the single channel type. If not, the time division multiplexing coefficient is reallocated so that F A and F B The delays in all channel types are equal, and the redistributed delay is obtained. The redistribution method can reduce the delay on the transmission channel with high delay, thereby reducing the delay on the critical path, breaking through the optimization bottleneck, and obtaining the optimized delay.

[0131] Embodiment three of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0132] Embodiment 3 of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0133] ProbeRoute is usually used to preliminarily estimate the delay of the signal path to speed up the design process. This method estimates the delay of the signal from one point to another through statistical analysis and prediction, and the delay between two nodes needs to meet the timing constraints. In order to ensure the correctness of the timing and accurately estimate the delay, the present invention provides embodiments 4, 5 and 6. At the same time, embodiments 4, 5 and 6 also provide a method for obtaining the key information table in the above embodiment 2.

[0134] Embodiment 4

[0135] See also Figure 5 , which shows a schematic diagram of a method for obtaining a delay reservation ratio, the method comprising the following steps:

[0136] D100, obtain the ideal slack ideal_slack and target slack target slack of each endpoint, where the endpoint is a pin or circuit port of the circuit unit.

[0137] Among them, the circuit unit is the circuit unit of the chip that is re-divided during the dynamic planning process. Specifically, when a user design is large, it needs to be placed in multiple FPGA chips for verification. The purpose of dynamic planning is to improve the overall performance after being placed in the FPGA chip. Without changing the connection relationship between the circuit units in the critical timing path, by reconfiguring the chip where each circuit unit in the critical path is placed, the arrival time of each circuit unit in the critical path to different chips is evaluated, so that the propagation time on the critical timing path is optimized.

[0138] Among them, slack is equal to the required time minus the arrival time. When the system does not reach the required time, the slack is negative. Therefore, when the slack is smaller, the gap from the expected system timing is greater, and the system performance is worse.

[0139] Among them, the ideal relaxation ideal_slack is obtained after completing the dynamic planning in the localization process. The ideal relaxation is the optimal timing that the system can achieve when assuming that the delay between chips remains unchanged.

[0140] The target slack target slack is positively correlated with the input slack input_slack, and the target slack is greater than the input_slack. The input_slack is a given value. The methods for calculating the target slack by the input slack in the prior art all fall within the protection scope of the present invention.

[0141] Preferably, target slack = input_slack × L. L is a preset value. Optionally, L = 0.9. The value of L can also be changed according to user settings. L is an optimization target set in advance, and it is expected to be optimized by 10 percentage points each time. If the ideal slack obtained is not better than the set target slack, that is, it is not optimized to 10 percentage points after optimization, it is considered necessary to use the method provided in Example 2 of the present invention to estimate the delay and retry the optimization.

[0142] D200, determine the end point of the timing diagram where ideal_slack is less than target slack as the target end point to be optimized;

[0143] Among them, the target end point refers to the key end point with no improvement compared to the input slack, and the target end point satisfies the following condition: ideal_slack < input_slack × L, where L is a preset value.

[0144] D300, determine the end point with ideal_slack less than the target slack as the key end point, otherwise determine it as a non - key end point.

[0145] As an example, the input slack input_slack is - 100, the target slack is - 90, and the current slack has been optimized to - 95. Then the end points with slack between - 95 and - 90 are key end points, and the end points with absolute value less than 90 are non - key end points.

[0146] D400, sort the ideal_slack of all end points. When there are non - key end points, obtain the worst slack of the non - key end points according to the sorting, and obtain the target slack margin Budget_target_slack based on the worst slack; when there are no non - key end points, obtain the target slack margin Budget_target_slack according to the best slack of the key end points;

[0147] Among them, if there are non - key end points, Budget_target_slack is K times the worst slack of the non - key end points. Optionally, K is 0.8, and other values specified by the user all fall within the protection scope of the present invention. In the prior art, other calculation methods for setting the target slack margin all fall within the protection scope of the present invention.

[0148] As an example, the input slack is - 100, the target slack is - 90, the best slack is - 70, and the current slack has been optimized to - 95. Then the end points covered between - 95 and - 90 are key end points, and the end points covered between - 90 and - 70 are non - key end points. The worst slack of the non - key end points is - 90, then - 90 multiplied by 0.8 gives - 72, and - 72 is used as Budget_target_slack.

[0149] Among them, if there are no non - key end points, Budget_target_slack is K times the best slack of the key end points.

[0150] As an example, the input slack is - 100, the target slack is - 90, and the best slack among all ideal_slack is - 93, that is, all ideal_slack are worse than the target slack. Then K times of - 93 is used as Budget_target_slack.

[0151] D500, obtain the ideal arrival time target_arr based on ideal_arr, Budget_target_slack and ideal_slack.

[0152] The target reaching time satisfies: target_arr=ideal_arr+ideal_slack-buget_target_slack.

[0153] Wherein, ideal_arr=require_arr-ideal_slack; require_arr is the arrival time required for data transmission between the chip pair.

[0154] After transforming the above formula, the ideal arrival time ideal_arr satisfies:

[0155] ideal_arr=target_arr-ideal_slack+buget_target_slack.

[0156] It should be noted that any solution for calculating ideal_arr using the same or equivalent formula as that provided by the present invention falls within the protection scope of the present invention.

[0157] D600, obtain the delay reservation ratio budget_ratio on each line segment between chips according to target_arr and ideal_arr.

[0158] Wherein, budget_ratio satisfies: budget_ratio=target_arr / ideal_arr. It should be noted that solutions for calculating budget_ratio using the same or equivalent formula as that provided by the present invention all fall within the protection scope of the present invention.

[0159] If target_arr is less than 0, it means that it is not achievable and the budget ratio needs to be set to 0, indicating that the TDR of the relevant path is required to be minimum.

[0160] In summary, embodiment 4 of the present invention provides a method for obtaining a delay reservation ratio, which first determines the end point where the optimization bottleneck occurs according to the ideal relaxation and the target relaxation to obtain the target end point to be optimized; obtains the target relaxation margin according to whether there is a key point, and then obtains the target arrival time according to the target relaxation margin, the target arrival time and the ideal relaxation; finally, obtains an accurate delay reservation ratio according to the target arrival time and the ideal arrival time.

[0161] Embodiment 4 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0162] Embodiment 4 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0163] In the fourth embodiment, the delay reservation ratio of each endpoint is obtained, and the delay reservation ratio needs to be transferred to the key timing node that needs to be optimized. Among all the circuits designed by the user, not all circuits are key timing nodes, and not all endpoints are endpoints that need to be further relaxed. Therefore, the delay ratio obtained in the fourth embodiment needs to be propagated to the key timing nodes in a targeted manner. In order to solve this problem, the present invention provides a fifth embodiment.

[0164] Embodiment 5

[0165] See also Figure 6 , which shows a schematic diagram of a method for obtaining a delay reservation ratio in a target relaxation area, the method comprising the following steps:

[0166] E100, obtain the arrival time thresholds of H endpoints arrBnd={arrBnd1,arrBnd2,…,arrBnd h ,…,arrBnd H}, where arrBnd h is the hth endpoint h The arrival time threshold of h ranges from 1 to H.

[0167] The end point is a terminal node for signal propagation, each node is a pin of a circuit unit, and the end point is the same as the end point in the fourth embodiment, which will not be described in detail.

[0168] Wherein, arrBnd is a threshold. When the arrival time of an endpoint is later than this threshold, it is considered to be related to the circuit achieving the target performance.

[0169] As an example, when the target_arr of the signal arriving at the node is 10ns, if its arrival time is greater than arrBnd=target_arr*G=9ns, it is considered to be related to the circuit achieving the target performance.

[0170] As a preferred embodiment, the initial value of arrBnd is set to G times the target arrival time target_arr. Optionally, the value of G is 0.9. Other methods of setting the initial value of arrBnd through target_arr in the prior art all fall within the protection scope of the present invention.

[0171] The target arrival time target_arr is also called the path arrival time. The target_arr has been introduced in detail in the fourth embodiment and will not be described again.

[0172] E200, obtain the target relaxation area of ​​each endpoint according to arrBnd, where endpoint is obtained h The steps to target relaxation areas include:

[0173] E210, arrBnd h From the endpoint h Start backpropagation in the input netlist to obtain all timing nodes on the propagation path.

[0174] The input netlist stores all logic gates, registers, wires and other elements that constitute the circuit topology in the user design and their interconnections, forming the circuit topology. The circuit topology is the basis for executing the back propagation algorithm and determines how the timing information is traced back from the output end point to the input end point.

[0175] In the process of backpropagation, the signal path can be traced by inputting the netlist, and the arrival time threshold arrBnd and the delay reserve ratio budget_ratio of the relevant timing nodes can be calculated and updated. Backpropagation is only performed on the target relaxation area to reduce unnecessary calculations and focus on the critical path that affects the final timing performance.

[0176] E220, obtain the input arrival time of each timing node on the propagation path in the timing diagram as in_arr.

[0177] Among them, the timing graph describes the timing relationship and signal propagation delay between various components (such as registers, combinational logic gates, etc.) in digital circuit design. The timing graph includes nodes and edges, where nodes represent pins in the circuit. Among them, the edge connects the nodes, representing the path of signal propagation between two nodes, namely Timing Arcs. TimingArc defines the causal relationship between the two pins in timing. Each edge or node is accompanied by detailed information about the timing, such as delay, setup time, hold time, clock skew, etc. By traversing the Timing Graph, the STA tool can identify all possible timing paths and calculate the arrival time of each timing node.

[0178] E230, obtain active nodes based on the in_arr and arrival time threshold of each timing node on the propagation path.

[0179] Further, E230, determining whether each timing node is an active node includes: E231, when the nu-th timing node node on the propagation path nu The input arrival time in_arr nu Less than node nu Arrival time threshold arrBnd nu When the node nu Mark the node as active.

[0180] Among them, arrBnd nu =min nv (arrBnd nv )-delay nu->nv . nv is node nu The total number of all fan-outs, min nv (arrBnd nv ) is the minimum value of all fan-out arrival time thresholds; delay nu->nv For node nu The delay between the nvth fan-out node.

[0181] Among them, when in_arr n Less than arrBnd nu , it indicates that the timing node is a key node that needs to be optimized.

[0182] E240, endpoint h Constitute the target relaxation region for all active nodes at the end point.

[0183] E300 performs back propagation in the target relaxation region starting from the end point of the user design according to the input netlist and arrBnd, and updates the delay reservation ratio budget_ratio of each timing node in the user design.

[0184] As a preferred embodiment, E300 further includes:

[0185] E310, when the t-th active node belongs to L different propagation paths, respectively obtain L delay reservation ratios budget_ratio of reverse propagation on the t-th active node.

[0186] E320, update the final delay reservation ratio budget_ratio of the t-th active node to the minimum value of the L delay reservation ratios budget_ratio.

[0187] As an example, the tth active node belongs to two propagation paths: path1 and path2. The budget_ratio of the back propagation from the propagation path path1 is 0.6, and the budget_ratio of the back propagation from the propagation path path2 is 0.8. At this time, 0.6 is taken as the final budget_ratio of the tth active node. Because when the budget_ratio is 0.6, the optimization of these two key paths can be met. If the budget_ratio is 0.8, only the optimization goal of path2 can be met, and the optimization goal of path1 cannot be met.

[0188] In summary, the present invention provides a method for obtaining a delay reservation ratio in a target relaxation area, which obtains the delay threshold of each end point and the input arrival time of each path, and marks the nodes in the path whose input arrival time is greater than the arrival time threshold as active nodes; the area formed by all active nodes of each terminal node is the target relaxation area, and the delay reservation ratio of each timing node is reversely propagated from the end point in the target relaxation area according to the input netlist and the arrival time threshold, so as to achieve the purpose of targetedly propagating the delay reservation ratio to the key timing nodes.

[0189] Embodiment five of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0190] Embodiment 5 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0191] The delay reservation ratio provided in Example 5 is for the overall path delay between chip pairs. However, the overall path delay between chip pairs also includes fixed delay and variable delay. The fixed delay cannot be adjusted and reduced by allocating time-division multiplexing coefficients. Therefore, the present invention provides Example 6 to convert the overall path delay reservation ratio into a variable delay reservation ratio for variable delay.

[0192] Embodiment 6

[0193] See also Figure 7 , which shows a schematic diagram of a method for obtaining a variable delay reservation ratio, the method comprising the following steps:

[0194] F100, obtain the path delay arc_delay, fixed delay base_delay and delay reservation ratio budget_ratio of each active node between chips.

[0195] Among them, the active node is the timing node to be optimized, and the definition of the active node is the same as that in the fourth embodiment and will not be repeated here.

[0196] The budget_ratio is the same as that in the fifth embodiment, and will not be described again. The budget_ratio is the ratio by which the entire path delay needs to be reduced, that is, the budget_ratio is an indicator for the path delay.

[0197] The path delay arc_delay is the same as the target delay in the fourth embodiment and will not be described in detail.

[0198] The path delay arc_delay includes variable delay and fixed delay. The fixed delay is determined by the physical distance between the two transmission nodes and is a fixed and unchangeable basic delay. The variable delay can be changed through optimization and is affected by the number of transmission signals and the number of allocated transmission wires, that is, by TDR. Since the fixed delay cannot be optimized, the delay reservation ratio budget_ratio on the entire path needs to be converted into a variable delay reservation ratio of the variable delay.

[0199] F200, obtain a variable delay reservation ratio var_budget_ratio between each active node and a fan-out node on another chip according to arc_delay, base_delay and budget_ratio, wherein the fan-out node is an active node.

[0200] Further, the Ath chip F A The tth active node is the drive pin drvPin t When drvPin t To the Bth chip F B Variable latency reserve ratio var_budget_ratio between fan-out nodes t,FA，FB The steps to obtain include:

[0201] F210, get drvPin t In F B The W fan-out nodes fanout={fanout1, fanout2,…, fanout w ,…,fanout W}, fanout w for drvPin t In F B The w-th fan-out node, where w ranges from 1 to W.

[0202] Each chip includes multiple active nodes, and when an active node is a driving pin, it may include multiple fan-out nodes, each of which may be an active node. There is a corresponding transmission wire between the driving pin and each fan-out node, and each transmission wire has a path delay, a fixed delay, and a delay reservation ratio.

[0203] F220, according to drvPin t to F B Calculate the arc_delay, base_delay and budget_ratio between each fan-out node of drvPin t to F B Variable delay reservation ratio before and after optimization between each fan-out node.

[0204] It should be noted that the variable delay reservation ratio before and after optimization refers to the ratio of the variable delay after optimization to the variable delay before optimization, and the optimized ratio on the transmission line between the two active nodes is obtained.

[0205] As a preferred embodiment, F220 also includes obtaining drvPin t to fanout w Variable delay reserve ratio var_budget_ratio before and after optimization t,FA，FB,w Steps:

[0206] F221, get drvPin t to fanout w Path delay between arc_delay t,w , Fixed delay base_delay t,w , delay reservation ratio budget_ratio t,w and minimum path delay min_delay t,w .

[0207] It should be noted that min_delay t,w Indicates the minimum delay that can be achieved by the wires of the chip pair, and its value is determined by the system.

[0208] F222, according to arc_delay t,w and base_delay t,w Calculate drvPin t to fanout w The original variable delay Svar_delay t,w .

[0209] Among them, Svar_delay t,w Satisfies: Svar_delayt,w =arc_delay t,w -base_delay t,w .

[0210] F223, according to Svar_delay t,w 、arc_delay t,w and budget_ratio t,w Calculate candidate variable delay Tvar_delay t,w .

[0211] Among them, Tvar_delay t,w Satisfies: Tvar_delay t,w =Svar_delay t,w -(1-budget_ratio t,w )×arc_delay t,w It should be noted that, because the budget_ratio in the fifth embodiment is for nodes, and for each path, the delay reservation ratio of the path is equal to the delay reservation ratio of the path to the node, that is, drvPin t to fanout w The delay reserve ratio budget_ratio between the paths t,w Equal to fanout w Delay reservation ratio budget_ratio w .

[0212] This step converts the delay that needs to be reduced on the entire path into the original variable delay to be reduced, and obtains the reduced candidate variable delay.

[0213] Other prior art methods for the same or similar deformation according to Svar_delay t,w 、arc_delay t,w and budget_ratio t,w Calculate Tvar_delay t,w All of the methods fall within the protection scope of the present invention.

[0214] F224, according to Tvar_delay t,w and min_delay t,w The maximum value between them is the optimized variable delay var_delay t,w .

[0215] It should be noted that when optimizing the variable delay, the lower limit of the variable delay cannot be exceeded, so the maximum value between the two is taken to achieve the purpose of obtaining the variable delay without exceeding the lower limit of the variable delay.

[0216] F225, according to var_delay t,w and Svar_delay t,w Get var_budget_ratio t,FA，FB,w .

[0217] Optional, var_budget_ratio t,FA，FB,w satisfy:

[0218] var_budget_ratio t,FA，FB,w =var_delay t,w / Svar_delay t,w .

[0219] Other methods for obtaining drvPin in the prior art for the same or similar deformation t to fanout w Variable delay reserve ratio var_budget_ratio before and after optimization t,FA，FB,w All of the methods fall within the protection scope of the present invention.

[0220] F230, get drvPin t To F B The minimum value of the variable delay reservation ratio between the W fan-out nodes is var_budget_ratio t,FA，FB .

[0221] As an example, F A There is a drive pin drvPin t , F B There are fanout nodes fanout1 and fanout2 on it. If drvPin t The variable delay reservation ratio between fanout1 and drvPin is 0.6. t The variable delay reservation ratio between fanout2 and fanout2 is 0.4. At this time, the variable delay reservation ratio of 0.4 is taken as drvPin t to F B Variable delay reservation ratio between all fan-out nodes to make the optimized drvPin t variable delay between fanout1 and drvPin t The variable delay between fanout1 and fanout2 can meet the optimization requirements.

[0222] As a preferred embodiment, the current delay budget result is based on the delay budget result of the previous iteration. t,FA，FBAfterwards, the step of updating the key information table is further included: the updates of the target delay TargetDelay and the delay optimization ratio ScaleRatio between the driving chip and the driven chip in the key information table respectively meet the following conditions:

[0223] TargetDelay=var_budget_ratio×Svar_delay t,w ;

[0224] Among them, Svar_delay t,w is the variable delay between the tth active node and its wth fan-out node on another chip.

[0225] ScaleRatio=TargetDelay / ∑ lim (Pro h,AB ×ref_delay AB ), where lim is chip AB ∈CHIP h , where CHIP h drvFPGA is the slave driver pin h To driven pin toFPGA h The set of all chip pairs between AB For chip F A and the Bth chip F B A chip pair consisting of Pro h,AB To drive the pin drvFPGA h In F A and F B The share of routing used between the chip pairs, ref_delay AB F A and F B The reference delay between the chip pairs. h,AB and ref_delay AB The definitions are the same as those in the second embodiment and will not be repeated here.

[0226] In summary, embodiment 6 of the present invention provides a method for obtaining a variable delay reservation ratio, which obtains multiple fan-out nodes of each driving pin, calculates the variable delay reservation ratio between each driving pin and each fan-out node before and after optimization, and the minimum value of the variable delay reservation ratio of all fan-out nodes is the variable delay reservation ratio. The variable delay reservation ratio can make the delay optimization more accurate.

[0227] Embodiment six of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0228] Embodiment 6 of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0229] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0230] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for allocating time division multiplexing coefficients, characterized in that: The method comprises the following steps: B100, obtaining a key information table, wherein the key information table includes associated entries of N driving pins, wherein each associated entry includes a driving pin drvPin, a driving chip drvFPGA, and multiple fan-out sub-entries, and each fan-out sub-entry includes a driven chip toFPGA, a target delay TargetDelay, and a delay optimization ratio ScaleRatio; B200, assign the hth drive pin drvPin according to the key information table h drvFPGA h and toFPGA h The time division multiplexing coefficient of each chip pair includes: B210, when drvFPGA h and toFPGA h When connected directly, according to TargetDelay h and delay function calculation drvFPGA h and toFPGA h The time division multiplexing coefficient TDR between them; B220, when drvFPGA h and toFPGA h When it is not a direct connection, according to the wiring results, get the h toFPGA h The reference delay ref_delay between each chip pair on all paths is calculated according to ref_delay, TargetDelay h and delay function calculation net h TDR between each chip pair.

2. The method according to claim 1, characterized in that B220 also includes: a step of obtaining a reference delay ref_delay between each chip pair: B221, get net h All the minimum trees of the chips where all the pins are located; B222, get from drvFPGA h toFPGA h The sum of the network routing shares of all networks between each chip pair in Pro; B223, obtain the reference delay ref_delay between each chip pair according to Pro, wire resource supply and delay function between each chip pair.

3. The method according to claim 2, characterized in that B222 also includes obtaining chip pairs {F A ,F B } between the rth network net r Route Share Pro r,AB Steps: B2221, when drvPin h for net r Pin in, get net r The set T of N(r) smallest trees r ; T r ={t r1 ,t r2 ,…,t rj ,…t rN(r) }, t rj T r The jth smallest tree in t rj Including K connections E rj ={e AB |e AB ∈t rj , where e AB For the Ath chip F A To the Bth chip F B The connection between them}; B2222, chip pair {F A ,F B The rth network net between} r Route Share Pro r,AB Meet: Pro r,AB =∑ r (1 / |T r |), where r is |T r | is the size of the collection.

4. The method according to claim 2, characterized in that: The ref_delay in B223 satisfies: ref_delay = f(TDR), TDR = usage / supply, usage is the routing usage, and f(TDR) is the delay function.

5. The method according to claim 1, characterized in that The method further comprises: B300, calculates the routing usage of the critical path between chip pairs based on TDR and wire resource supply.

6. The method according to claim 5, characterized in that The TDR is positively correlated with usage, and negatively correlated with supply of wire resources between chip pairs.

7. The method according to claim 1, characterized in that The method further comprises: B400, obtains TDR of non-critical paths between chip pairs, including: B410, calculate the wire resource supply′ of the non-critical path according to the usage of the critical path between the chip pairs and the wire resource supply; B420, the time-division reuse coefficient TDR′ is calculated based on the routing usage′ and supply′ of the non-critical path.

8. The method according to claim 7, characterized in that In B410, supply′ satisfies: supply′=supply-usage.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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