Image sensor and readout circuit thereof

Abstract

The invention provides an image sensor and a readout circuit thereof, the readout circuit of the image sensor comprises a ramp voltage circuit, a comparison circuit, a counter circuit, a storage circuit and a negation control circuit, the image sensor circuit quantizes a reset signal into a first digital code value in a reset sampling period and stores the first digital code value; in the first exposure sampling period, the first pixel pulse signal is quantized on the basis of the second digital code value to realize correlated double sampling, and in the second exposure sampling period, the second pixel pulse signal is quantized on the basis of the fourth digital code value to realize correlated double sampling. The second digital code value and the fourth digital code value are negation values corresponding to the first digital code value, in the whole quantization process, quantization of two pixel pulse signals can be completed only by quantizing the reset signal once, the pixel signal time division multiplexing counter circuit read out twice and one set of reading circuit, and the quantization efficiency is improved. The structure of the image sensor is simplified, and power consumption is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensors, and in particular relates to an image sensor and a readout circuit thereof. Background Art

[0002] CMOS image sensors have the advantages of low voltage, low power consumption, low cost and high integration, and have important application value in machine vision, consumer electronics, high-definition monitoring and medical imaging.

[0003] First of all, ALL Direction Auto Focus (ADAF) plays an important role in image sensors, such as Figure 1 In the pixel array shown, 4 pixels are arranged in 2×2, sharing a floating diffusion node and source follower transistor. When reading out, TXA and TXC are turned on first, and the two pixel signals on the right are read out to obtain the right phase information; then TXB and TXD are turned on, and the two pixel signals on the left are read out to obtain the left phase information. Through these two phase information, the phase difference can be calculated for autofocus.

[0004] Secondly, dynamic range is a key factor in the imaging quality of image sensors. DCG (Dual Conversion Gain) is applied to the pixel circuit of image sensors. Under low illumination conditions, a smaller integral capacitor is used to increase the conversion gain to improve sensitivity. Under high illumination conditions, a larger integral capacitor is used to increase the stored charge and reduce the conversion gain to improve the dynamic range.

[0005] The correlated double sampling technology (CDS) can eliminate the thermal noise and some fixed pattern noise caused by pixel reset, which can greatly improve the noise performance of the image sensor. CDS technology needs to read out the reset signal Vrst and exposure signal Vsig of the pixel separately, and then make the difference between the two. Therefore, when using CDS technology in a four-phase pixel structure or dual conversion gain technology, two sets of readout circuits are required for one column of pixels, one set is used to quantize the reset signal and the right pixel signal or the high-gain pulse signal, and the other set is used to quantize the reset signal and the left pixel signal or the low-gain pulse signal. This method increases the structural complexity and power consumption of the image sensor. Summary of the invention

[0006] The object of the present invention is to provide a readout circuit of an image sensor, aiming to solve the problems of complex structure and high power consumption in a traditional four-phase pixel structure or in a dual conversion gain technology using CDS technology.

[0007] A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, the readout circuit comprising:

[0008] A ramp voltage circuit configured to output a ramp voltage signal;

[0009] A comparison circuit, wherein a first input terminal is connected to the pixel unit, and a second input terminal is connected to the ramp voltage circuit, and is configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal, and output at least one reset pulse signal and two pixel pulse signals at intervals;

[0010] a counter circuit connected to the comparison circuit, configured to count at least one reset pulse signal in at least one reset sampling period and store it as at least one first digital code value, count the first pixel pulse signal based on the second digital code value in the first exposure sampling period and store it as a third digital code value, and count the second pixel pulse signal based on the fourth digital code value in the second exposure sampling period and store it as a fifth digital code value;

[0011] a storage circuit connected to the counter circuit and configured to store at least one first digital code value and, before the second exposure sampling period, to write back one of the at least one first digital code value to the counter circuit when triggered by a write-back control signal;

[0012] The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, it is triggered by the mode selection signal to output the inversion control signal to the counter circuit to trigger the counter circuit to invert the first digital code value of the memory to generate a second digital code value or a fourth digital code value.

[0013] A second aspect of an embodiment of the present invention provides an image sensor, comprising a pixel array, a control circuit, and a plurality of readout circuits of the above image sensors, wherein the pixel array comprises a plurality of pixel units arranged in an array;

[0014] The readout circuit of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit of each image sensor is also respectively connected to the control circuit.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned image sensor circuit quantizes the reset signal into a first digital code value and stores it during the reset sampling period, quantizes the first pixel pulse signal based on the second digital code value during the first exposure sampling period to achieve correlated double sampling, and quantizes the second pixel pulse signal based on the fourth digital code value during the second exposure sampling period to achieve correlated double sampling, the second digital code value and the fourth digital code value are the inverse values ​​of the corresponding first digital code value, and in the entire quantization process, the reset signal only needs to be quantized once, and the pixel signals read out twice use a set of counter circuits in time-sharing, so only one set of readout circuits is needed to complete the quantization of the two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption, and determines image information based on the quantization results of the two pixel pulse signals to achieve automatic focus or high dynamic range, thereby improving imaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A first circuit diagram of a pixel unit provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of a module of a readout circuit provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a junction circuit of a pixel unit or a sub-pixel provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of a module of a readout circuit provided by an embodiment of the present invention;

[0021] Figure 5 A schematic diagram of a first signal timing sequence of a readout circuit provided by an embodiment of the present invention;

[0022] Figure 6 A second signal timing diagram of a readout circuit provided by an embodiment of the present invention;

[0023] Figure 7 A first circuit diagram of a readout circuit provided by an embodiment of the present invention;

[0024] Figure 8 A third signal timing diagram of the readout circuit provided by an embodiment of the present invention;

[0025] Fig. 9 A fourth signal timing diagram of the readout circuit provided by an embodiment of the present invention;

[0026] Fig.10 A second circuit diagram of a readout circuit provided by an embodiment of the present invention;

[0027] Fig.11 A third circuit diagram of a readout circuit provided by an embodiment of the present invention;

[0028] Fig.12 A circuit diagram of a D flip-flop in a readout circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] Embodiment 1

[0032] A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, such as Figure 2 As shown, the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may also include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array, and a plurality of pixel units arranged in columns are connected in common. The control circuit 3 selects the pixel units in each row through a row selection signal, and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information according to the digital code value.

[0033] Among them, a pixel unit usually has at least one sub-pixel, such as Figure 1 The pixel unit shown includes at least four sub-pixels arranged in 2×2, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal Vrst or a pixel signal. The sub-pixels in the pixel unit can be grouped in pairs or in other combinations, and the specific grouping method is not limited.

[0034] Each sub-pixel generally includes a photoelectric conversion element, a transmission transistor TX, a reset transistor RST, a source follower transistor SF and a row selection transistor SEL, wherein the photoelectric conversion element includes but is not limited to a photodiode PD, such as a Pin-type photodiode PD, and the number of the photoelectric conversion element, the transmission transistor TX, the reset transistor RST, the source follower transistor SF and the row selection transistor SEL can be one or more, that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited, such as Figure 3 As shown, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, wherein the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, the second end of the transfer transistor TX, the first end of the reset transistor RST, and the controlled end of the source follower transistor SF are all coupled to the floating diffusion node, the anode of the photodiode PD is grounded, the second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD, the second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL, and the second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output the corresponding pixel signal.

[0035] When the pixel unit includes at least four sub-pixels arranged in 2×2, the four sub-pixels share a floating diffusion node FD and a source follower transistor. When reading out, first txa and txc are turned on, the two pixel signals on the right are read out, and the right phase information is obtained; then txb and txd are turned on, and the two pixel signals on the left are read out to obtain the left phase information. (Or: first txa and txb are turned on, the two pixel signals on the top are read out, and the upper phase information is obtained; then txc and txd are turned on, and the two pixel signals on the bottom are read out to obtain the lower phase information.) Through these two phase information, the phase difference can be calculated, so as to perform autofocus.

[0036] In order to simplify the structure of the image sensor and its readout circuit 1 and reduce power consumption, in this embodiment, Figure 4 As shown, the readout circuit 1 includes:

[0037] The ramp voltage circuit 10 is configured to output a ramp voltage signal;

[0038] A comparison circuit 20, a first input terminal of which is connected to the pixel unit, and a second input terminal of which is connected to the ramp voltage circuit 10, configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal, and output at least one reset pulse signal and two pixel pulse signals at intervals;

[0039] The counter circuit 30 is connected to the comparison circuit 20 and is configured to count at least one reset pulse signal in at least one reset sampling period and store it as at least one first digital code value, count the first pixel pulse signal based on the second digital code value in the first exposure sampling period and store it as a third digital code value, and count the second pixel pulse signal based on the fourth digital code value in the second exposure sampling period and store it as a fifth digital code value;

[0040] The storage circuit 50 is connected to the counter circuit 30 and configured to store at least one first digital code value and write back one of the at least one first digital code value to the counter circuit 30 before the second exposure sampling period under the triggering of the write-back control signal rewrite_en;

[0041] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, it is triggered by the mode selection signal mode_sel to output the inversion control signal trig_pulse to the counter circuit 30 to trigger the counter circuit 30 to invert the first digital code value in the memory to generate a second digital code value or a fourth digital code value.

[0042] In this embodiment, the ramp voltage signals output by the ramp voltage circuit 10 during the reset sampling period and the exposure sampling period may be the same or different, and the specific magnitudes are set according to the voltage amplitudes of the reset signal and the pixel signal.

[0043] Among them, the reset signal Vrst may include one or more, and correspondingly, the reset sampling period may be one or more. When it is a reset signal Vrst, in the reset sampling period, the comparison circuit 20 compares the reset signal Vrst with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30, and the counter circuit 30 counts the reset pulse signal up or down. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, and the quantization of the reset signal Vrst ends. The counter circuit 30 counts to generate a first digital code value and stores it in itself and writes it into the storage circuit 50.

[0044] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the negation mode and inverts the stored first digital code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal and generates a first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops working, the quantization of the first pixel pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value, wherein the third digital code value is the difference between the first pixel signal and the digital code value corresponding to the reset signal Vrst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0045] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value is used as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the second pixel signal in the second exposure sampling period. The comparison circuit 2 0 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the second pixel pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal Vrst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0046] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50, and read out to the corresponding control circuit 3 under the control of the read control signal. The control circuit 3 determines the image information according to the third digital code value and the fifth digital code value.

[0047] When the reset signal Vrst includes two reset signals Vrst corresponding to two pixel signals, in the first reset sampling period, the comparison circuit 20 compares the first reset signal Vrst1 with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the first reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the first reset signal Vrst1 is completed, and the counter circuit 30 counts to generate the first first digital code value and writes it into the storage circuit 50.

[0048] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the second reset signal Vrst2 with the reset ramp voltage signal and generates a second reset pulse signal. The second reset pulse signal is output to the counter circuit 30, and the counter circuit 30 counts the second reset pulse signal in the same direction, and stops counting when the output of the comparison circuit 20 flips, and the quantization of the second reset signal Vrst is completed. The counter circuit 30 counts to generate a second first digital code value and stores it inside itself.

[0049] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel, and the inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode and inverts the stored second first digital code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal and generates a first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops working, the quantization of the first pixel pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value, wherein the third digital code value is the difference between the first pixel signal and the digital code value corresponding to the second reset signal Vrst2, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0050] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first first digital code value to generate a fourth digital code value. The fourth digital code value is used as the initial state of the second exposure sampling. Then, the counter circuit 30 is restored to the counting mode and quantizes the second pixel signal in the second exposure sampling period. The comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, the quantization of the second pixel pulse signal is completed, and the counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the second reset signal Vrst2, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0051] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50, and read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information according to the third digital code value and the fifth digital code value.

[0052] During the entire quantization process, the reset signal Vrst only needs to be quantized once, and the two read-out pixel signals are time-shared with a set of counter circuits 30. Therefore, only one set of read-out circuits 1 is required to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals to achieve automatic focus or high dynamic range, thereby improving imaging quality.

[0053] Among them, the ramp voltage circuit 10 can adopt a corresponding signal source, a voltage generating circuit, etc., such as a ramp generator, and the comparison circuit 20 can adopt a comparator and other structures. Optionally, the comparison circuit 20 includes a first capacitor, a second capacitor and a comparator. The first end of the first capacitor is connected to the signal end of the ramp generating circuit, and the first end of the second capacitor is used to input the reset signal Vrst or the pixel signal output by the pixel unit. The second end of the first capacitor is connected to the positive input end of the comparator, and the second end of the second capacitor is connected to the inverting input end of the comparator. When the ramp voltage signal is less than the corresponding reset signal Vrst or the pixel signal, the comparator outputs a low level and the counter circuit 30 starts counting. When the ramp voltage signal is greater than the corresponding reset signal Vrst or the pixel signal, the comparator outputs a high level and the counter circuit 30 stops counting. At this time, the counting result is the digital code value after the signal is quantized.

[0054] The counter circuit 30 , the negation control circuit 40 and the storage circuit 50 may be specifically determined according to the corresponding reset signal Vrst, the type of the pixel signal and the input and output logic.

[0055] Furthermore, the write-back path of the storage circuit 50 can be directly output to the counter circuit 30 , or indirectly output to the counter circuit 30 via the negation control circuit 40 , and the specific write-back method is not limited.

[0056] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned image sensor circuit quantizes the reset signal Vrst into a first digital code value and stores it in the reset sampling period, quantizes the first pixel pulse signal based on the second digital code value in the first exposure sampling period to achieve correlated double sampling, and quantizes the second pixel pulse signal based on the fourth digital code value in the second exposure sampling period to achieve correlated double sampling, the second digital code value and the fourth digital code value are the inverse values ​​of the corresponding first digital code value, and in the entire quantization process, the reset signal Vrst only needs to be quantized once, and the pixel signals read out twice use a set of counter circuits 30 in time-sharing, so only one set of readout circuits 1 is needed to complete the quantization of the two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption, and determines the image information based on the quantization results of the two pixel pulse signals, realizes automatic focus or high dynamic range, and improves imaging quality.

[0057] Embodiment 2

[0058] Based on the optimization and specificization of the first embodiment, in an optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the pixel unit includes at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal Vrst or a pixel signal;

[0059] At least one reset signal Vrst is a reset signal Vrst generated when the pixel units are reset simultaneously;

[0060] The first pixel pulse signal and the second pixel pulse signal are respectively one of a pixel group pulse signal corresponding to simultaneous exposure of a pixel group and an image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit.

[0061] In this embodiment, the readout circuit 1 is suitable for ADAF technology. Four sub-pixels share a floating diffusion node and a source follower transistor. During readout, the pixel group is turned on first, and the pixel group signal Vsigl of at least two sub-pixels in the pixel group is read out. For example, the two pixel signals on the right are read out to obtain the right phase information.

[0062] Then all the sub-pixels of the pixel unit are turned on, and the image signal Vsig corresponding to the pixel unit is read out. Correspondingly, the comparison circuit 20 obtains the full phase information.

[0063] Specifically, refer to Figure 5 As shown, during the reset sampling period, the comparison circuit 20 compares the reset signal Vrst with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, and the quantization of the reset signal Vrst is completed. The counter circuit 30 counts to generate a first digital code value and stores it in itself and writes it into the storage circuit 50.

[0064] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the negation mode and inverts the stored first digital code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsigl with the pixel ramp voltage signal and generates a pixel group pulse signal. The pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the pixel group pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops working, the pixel group pulse signal quantization ends, and the counter circuit 30 counts to generate a third digital code value, wherein the third digital code value is the difference between the pixel group signal Vsigl and the digital code value corresponding to the reset signal Vrst, that is, Vsigr-Vrst, to achieve correlated double sampling, reduce noise influence, and improve imaging quality.

[0065] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value is used as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the image signal Vsig in the second exposure sampling period. The comparison circuit 20 converts the image signal Vsig into a digital code. The image signal Vsig is compared with the pixel slope voltage signal to generate an image pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the image pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the image pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal Vrst, that is, Vsigr+Vsigl-Vrst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0066] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 can determine the left and right pixel information or the upper and lower pixel information based on the fifth digital code value and the third digital code value, and obtain the phase difference through the pixel information to perform automatic focus and improve the user experience.

[0067] In the quantization process, only one reset signal Vrst needs to be quantized, and the pixel signals read out twice are time-shared with a set of counter circuits 30, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals, realizing automatic focusing and improving the imaging quality.

[0068] Embodiment 3

[0069] Based on the optimization and specificization on the basis of the first embodiment, in another optional embodiment, the reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0070] The first pixel pulse signal and the second pixel pulse signal are respectively one of a high-gain image pulse signal and a low-gain image pulse signal;

[0071] The counter circuit 30 is configured to: count one of the reset pulse signals in a first reset sampling period to generate a first digital code value;

[0072] In a second reset sampling period, another reset pulse signal is counted to generate another first digital code value;

[0073] In the first exposure sampling period, the first pixel pulse signal is counted based on the second digital code value and stored as a third digital code value;

[0074] In the second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value.

[0075] In this embodiment, the readout circuit 1 is suitable for HDR technology, and the pixel unit or sub-pixel includes different integral capacitors, and different integral capacitors are switched under different illumination conditions, wherein a smaller integral capacitor is used to increase the conversion gain under low illumination conditions to improve the sensitivity; and a larger integral capacitor is used to increase the storage charge under high illumination conditions, and the conversion gain is reduced to improve the dynamic range.

[0076] Correspondingly, the reset signal Vrst includes a low gain reset signal lcg_rst and a high gain reset signal hcg_rst, referring to Figure 6As shown, in the first reset sampling period, the comparison circuit 20 compares the first reset signal Vrst1 with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the first reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the first reset signal Vrst1 is completed, and the counter circuit 30 counts to generate the first first digital code value and writes it into the storage circuit 50.

[0077] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the second reset signal Vrst2 with the reset ramp voltage signal, and generates a second reset pulse signal to output to the counter circuit 30, the counter circuit 30 counts the second reset pulse signal in the same direction, and stops counting when the output of the comparison circuit 20 flips, the quantization of the second reset signal Vrst2 is completed, and the counter circuit 30 counts to generate the second first digital code value and stores it inside itself.

[0078] Among them, the second reset signal Vrst2 and the first reset signal Vrst1 are either a high gain reset signal hcg_rst or a low gain reset signal lcg_rst. Correspondingly, the second reset pulse signal and the first reset pulse signal are either a high gain reset pulse signal or a low gain reset pulse signal.

[0079] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30, and the counter circuit 30 switches to the negation mode, and inverts the stored second first digital code value to the second digital code value as the initial state of the first exposure sampling period, and then, the counter circuit 30 returns to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal, wherein the first pixel signal and the second reset signal Vrst2 are the image signal and the reset signal Vrs under the same gain. t, for example, they are respectively a high gain image signal hcg_sig and a high gain reset signal hcg_rst, and are compared to generate a first pixel pulse signal, which is output to a counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops working, the quantization of the first pixel pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value, wherein the third digital code value is the difference between the digital code values ​​corresponding to the first pixel signal and the second reset signal Vrst2, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0080] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored first first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back first first digital code value to generate a fourth digital code value. The fourth digital code value is used as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the second pixel signal in the second exposure sampling period. The second pixel signal and the first reset signal Vrst1 are the image signal and reset signal Vrst under the same gain, for example, respectively a low gain image signal and a reset signal. The comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the second pixel pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the first reset signal Vrst1, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0081] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50, and read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information according to the third digital code value and the fifth digital code value.

[0082] During the entire quantization process, the reset signal Vrst only needs to be quantized once, and the two read-out pixel signals use a set of counter circuits 30 for time-sharing multiplexing. Therefore, only one set of read-out circuits 1 is needed to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals, achieving a high dynamic range and improving the imaging quality.

[0083] Corresponding to the signal input and output logic of the above-mentioned embodiment 2 and embodiment 3, optionally, as Figure 7 As shown, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0084] The storage circuit 50 includes n storage units, such as a first storage unit 51, a second storage unit 52, etc., and one storage unit is respectively connected to a counter unit and an inversion control circuit 40;

[0085] Each storage unit includes a first memory Mem1, a second memory Mem2 and a NAND gate NOR1;

[0086] The input ends of the first memory Mem1 and the second memory Mem2 are respectively connected to a counter unit, the output end of the first memory Mem1 is connected to the first input end of the NAND gate NOR1, the second input end of the NAND gate NOR1 is used to input the write-back control signal rewrite_en, and the NAND gate NOR1 constitutes the output end of the storage unit;

[0087] A first memory Mem1, configured to store a corresponding one-bit count value of at least one first digital code value;

[0088] The first memory Mem1 and the second memory Mem2 respectively store a corresponding one-bit count value of one of the third digital code value and the fifth digital code value.

[0089] When applied to the readout circuit 1 of the second embodiment, refer to Figure 4 , Figure 5 and Figure 7As shown, during the reset sampling period, the comparison circuit 20 compares the reset signal Vrst with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30, and the reset pulse signal is output to the first counter unit 31 to the nth counter unit through the inversion control circuit 40. The n counter units count the reset pulse signal up or down, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the reset signal Vrst is quantized, the n counter units count to generate and store each bit count value of the first digital code value, and store each bit count value of the first digital code value in the first memory Mem1 respectively.

[0090] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30, and the n counter units are switched to the negation mode, and the stored first digital code value is inverted to the second digital code value as the initial state of the first exposure sampling period, and then, the n counter units are restored to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsigl with the pixel ramp voltage signal, and generates a pixel group pulse signal, and the pixel group pulse signal is transmitted through the negation control circuit 20. The circuit 40 outputs to n counter units, and the n counter units count the pixel group pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, and the quantization of the pixel group pulse signal ends. The n counter units count to generate a third digital code value, wherein the third digital code value is the difference between the digital code values ​​corresponding to the pixel group signal Vsigl and the reset signal Vrst, i.e., Vsigr-Vrst, to realize correlated double sampling, reduce noise influence, and improve imaging quality, and the n-bit count value in the third digital code value is respectively stored in n second memories Mem2.

[0091] Afterwards, the n counter units are reset. Before the second exposure sampling period, the first memory Mem1 receives the write-back control signal rewrite_en, and writes the stored first digital code value back to the counter circuit 30 through the NAND gate NOR1 and the inversion control circuit 40. At the same time, the n counter units receive the inversion control signal trig_pulse, and invert the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value, and the fourth digital code value is used as the initial state of the second exposure sampling. Then, the n counter units are restored to the counting mode, and the image signal Vsig is quantized in the second exposure sampling period. The comparison circuit 20 quantizes the image signal Vsig. The signal Vsig is compared with the pixel slope voltage signal, and an image pulse signal is generated. The image pulse signal is output to n counter units. The n counter units count the image pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the image pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, and the n-bit count value of the fifth digital code value is stored in the first memory Mem1, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal Vrst, that is, Vsigr+Vsigl-Vrst, to achieve correlated double sampling, reduce noise influence, and improve imaging quality.

[0092] When applied to the readout circuit 1 of the third embodiment, refer to Figure 4 , Figure 6 and Figure 7 As shown, in the first reset sampling period, the comparison circuit 20 compares the first reset signal Vrst1 with the reset ramp voltage signal and generates a first reset pulse signal, the first reset pulse signal corresponds to the pulse signal of the high gain reset signal hcg_rst or the low gain reset signal lcg_rst, the first reset pulse signal is input to the n counter units through the inversion control circuit 40, the n counter units count up or down the first reset pulse signal, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the quantization of the first reset signal Vrst1 is completed, the n counter units count to generate count values, the n count values ​​are combined to generate the first first digital code value and written into the n first memories Mem1.

[0093] Before the second reset sampling period, the n counter units are reset, and during the second reset sampling period, the comparison circuit 20 compares the second reset signal Vrst2 with the reset ramp voltage signal, the second reset signal Vrst2 and the first reset signal Vrst1, one is a high-gain reset signal hcg_rst, and the other is a low-gain reset signal lcg_rst, and a second reset pulse signal is generated, the second reset pulse signal and the first reset pulse signal, one is a high-gain reset pulse signal, and the other is a low-gain reset pulse signal, the second reset pulse signal is output to the n counter units through the inversion control circuit 40, the n counter units count the second reset pulse signal in the same direction, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the second reset signal Vrst2 is quantized, the n counter units count to generate n count values, the n count values ​​are combined to generate the second first digital code value and stored in the n counter units themselves.

[0094] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the n counter units, and the n counter units switch to the negation mode, and negate the count values ​​stored in each of them, and the count values ​​after negation are combined to generate a second digital code value as the initial state of the first exposure sampling period, and then, the n counter units are restored to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal, and the comparison generates a first pixel pulse signal, and the first pixel The pixel pulse signal is output to n counter units through the inversion control circuit 40. The n counter units count the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the n counter units stop working, the quantization of the first pixel pulse signal ends, and the n counter units count to generate a third digital code value. The count values ​​of each bit of the third digital code value are respectively stored in each second memory Mem2, wherein the third digital code value is the difference between the first pixel signal and the digital code value corresponding to the second reset signal Vrst2, thereby realizing correlated double sampling, reducing the influence of noise, and improving imaging quality.

[0095] Afterwards, the n counter units are reset, and before the second exposure sampling period, each first memory Mem1 receives a write-back control signal rewrite_en, and writes back the first stored first digital code value to the n counter units. At the same time, the n counter units receive a negation control signal trig_pulse, and negate the written-back first first digital code value to generate a fourth digital code value, which is used as the initial state of the second exposure sampling. Then, the n counter units are restored to the counting mode, and the second pixel signal is quantized in the second exposure sampling period, and the comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal , and generate a second pixel pulse signal, the second pixel pulse signal is output to n counter units, the n counter units count the second pixel pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the quantization of the second pixel pulse signal is completed, and the n counter units count to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the first reset signal Vrst1, and the n-bit count values ​​of the fifth digital code value are respectively stored in the n first memories Mem1, to realize correlated double sampling, reduce noise influence, and improve imaging quality.

[0096] Embodiment 4

[0097] Based on the optimization and specificization on the basis of the first embodiment, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the pixel unit includes at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal Vrst or a pixel signal;

[0098] The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0099] The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to simultaneous exposure of a pixel group in a low-gain mode and a low-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit;

[0100] The second exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive;

[0101] The first digital code value includes a first sub-digital code value and a second sub-digital code value;

[0102] The counter circuit 30 is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value;

[0103] In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value;

[0104] In the first exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a third digital code value;

[0105] The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value;

[0106] In the third exposure sampling period, the low gain pixel group pulse signal is counted based on the fourth digital code value and stored as a fifth sub-digital code value;

[0107] In a fourth exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as a sixth sub-digital code value;

[0108] The storage circuit 50 is connected to the counter circuit 30 and configured to store the first sub-digital code value and write the first sub-digital code value back to the counter circuit 30 when triggered by the write-back control signal rewrite_en before the third exposure sampling period and the fourth exposure sampling period;

[0109] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control signal trig_pulse triggers the counter circuit 30 to invert the first sub-digital code value of the memory to generate a fourth digital code value, and invert the second sub-digital code value to generate a second digital code value.

[0110] In this embodiment, the readout circuit 1 is suitable for realizing automatic focusing under low conversion gain, the reset pulse signal includes a high gain reset pulse signal and a low gain reset pulse signal, the first pixel pulse signal includes a high gain image pulse signal, and the second pixel pulse signal includes a low gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low gain mode and a low gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit.

[0111] refer to Figure 8In the first reset sampling period, the comparison circuit 20 compares the low gain reset signal lcg_rst with the reset ramp voltage signal, generates a low gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low gain reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low gain reset signal lcg_rst ends, and the counter circuit 30 counts to generate the first sub-digital code value and writes it into the storage circuit 50.

[0112] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the high gain reset signal hcg_rst with the reset ramp voltage signal and generates a high gain reset pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the high gain reset pulse signal in the same direction, and stops counting when the output of the comparison circuit 20 flips. The quantization of the high gain reset signal hcg_rst is completed, and the counter circuit 30 counts to generate a second sub-digital code value and stores it inside itself.

[0113] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30, and the counter circuit 30 switches to the negation mode, and inverts the stored second sub-digital code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the high-gain image signal hcg_sig with the pixel ramp voltage signal, and generates a high-gain image pulse signal by comparison. The high-gain image pulse signal is output to the counter circuit 30, and the counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops working, the quantization of the high-gain image pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value, wherein the third digital code value is the difference between the digital code values ​​corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, so as to realize correlated double sampling, reduce noise influence, and improve imaging quality.

[0114] Afterwards, the counter circuit 30 is reset. Before the third exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value is used as the initial state of the third exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the low-gain pixel group signal lcg_sigl in the third exposure sampling period. The comparison circuit 20 compares the low-gain pixel group signal lcg_sigl with The pixel slope voltage signal is compared and a low gain pixel group pulse signal is generated. The low gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low gain pixel group pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low gain pixel group pulse signal is completed. The counter circuit 30 counts to generate a fifth sub-digital code value, wherein the fifth sub-digital code value is the difference between the digital code values ​​corresponding to the low gain pixel group signal lcg_sigl and the low gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0115] Then, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored first sub-digital code value back to the counter circuit 30 again. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value is used as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and quantizes the low-gain image signal lcg_sig in the fourth exposure sampling period. The comparison circuit 20 quantizes the low-gain image signal lcg_sig. ig is compared with the pixel ramp voltage signal and a low gain image pulse signal is generated. The low gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low gain image pulse signal ends. The counter circuit 30 counts to generate a sixth sub-digital code value, wherein the sixth sub-digital code value is the difference between the digital code values ​​corresponding to the low gain image signal lcg_sig and the low gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0116] At the same time, the third digital code value, the fifth sub-digital code value and the sixth sub-digital code value obtained by the three quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information according to the third digital code value, the fifth sub-digital code value and the sixth sub-digital code value, and realizes automatic focus in the low conversion gain mode, thereby improving the imaging quality and user experience.

[0117] Embodiment 5

[0118] Based on the optimization and specificization of the first embodiment, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the pixel unit includes four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal Vrst or a pixel signal;

[0119] The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0120] The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to simultaneous exposure of a pixel group in a high-gain mode and a high-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit;

[0121] The second pixel pulse signal includes a low-gain image pulse signal;

[0122] The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive;

[0123] The first digital code value includes a first sub-digital code value and a second sub-digital code value;

[0124] The counter circuit 30 is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value;

[0125] In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value;

[0126] The third digital code value includes a third sub-digital code value and a fourth sub-digital code value;

[0127] In a third exposure sampling period, the high-gain pixel group pulse signal is counted based on the second digital code value and stored as a third sub-digital code value;

[0128] In a fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value;

[0129] In the second exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value;

[0130] The storage circuit 50 is connected to the counter circuit 30 and configured to store the first sub-digital code value and the second sub-digital code value, and before the fourth exposure sampling period and the second exposure sampling period, is triggered by the write-back control signal rewrite_en to write the second sub-digital code value and the first sub-digital code value back to the counter circuit 30;

[0131] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control signal trig_pulse triggers the counter circuit 30 to invert the second sub-digital code value of the memory to generate a second digital code value, and invert the first sub-digital code value to generate a fourth digital code value.

[0132] In this embodiment, the readout circuit 1 is suitable for realizing automatic focus under high conversion gain, the reset pulse signal includes a high gain reset pulse signal and a low gain reset signal lcg_rst, the first pixel pulse signal includes a high gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high gain mode and a high gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit, and the second pixel pulse signal includes a low gain image pulse signal.

[0133] refer to Fig. 9 In the first reset sampling period, the comparison circuit 20 compares the low gain reset signal lcg_rst with the reset ramp voltage signal, generates a low gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low gain reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low gain reset signal lcg_rst ends, and the counter circuit 30 counts to generate the first sub-digital code value and writes it into the storage circuit 50.

[0134] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the high gain reset signal hcg_rst with the reset ramp voltage signal and generates a high gain reset pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the high gain reset pulse signal in the same direction, and stops counting when the output of the comparison circuit 20 flips. The quantization of the high gain reset signal hcg_rst is completed, and the counter circuit 30 counts to generate a second sub-digital code value and stores it inside itself.

[0135] Before the third exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30, and the counter circuit 30 switches to the negation mode, and inverts the stored second sub-digital code value to the second digital code value as the initial state of the third exposure sampling period, and then, the counter circuit 30 returns to the counting mode, and quantizes the high gain pixel group signal hcg_sigl in the third exposure sampling period, and the comparison circuit 20 compares the high gain pixel group signal hcg_sigl with the pixel ramp voltage signal. The comparison circuit 20 compares and generates a high-gain pixel group pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the high-gain pixel group pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain pixel group pulse signal is completed. The counter circuit 30 counts and generates a third sub-digital code value, wherein the third sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0136] Then, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored second sub-digital code value back to the counter circuit 30 again. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back second sub-digital code value to generate a second digital code value. The second digital code value is used as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and quantizes the high-gain image signal hcg_sig in the fourth exposure sampling period. The comparison circuit 20 quantizes the high-gain image signal hcg_sig. ig is compared with the pixel slope voltage signal and a high-gain image pulse signal is generated. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain image pulse signal is completed. The counter circuit 30 counts to generate a fourth sub-digital code value, wherein the fourth sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0137] Then, the counter circuit 30 is reset again, and before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored first sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back first sub-digital code value to generate a fourth digital code value, which is used as the initial state of the second exposure sampling period. Then, the counter circuit 30 is restored to the counting mode, and quantizes the low-gain image signal lcg_sig in the second exposure sampling period. The comparison circuit 20 quantizes the low-gain image signal lcg_ sig is compared with the pixel slope voltage signal, and a low-gain image pulse signal is generated. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain image pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the digital code values ​​corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0138] At the same time, the third sub-digital code value, the fourth sub-digital code value and the fifth sub-digital code value obtained by the three quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information according to the third sub-digital code value, the fourth sub-digital code value and the fifth digital code value, and realizes automatic focus in the high conversion gain mode, thereby improving the imaging quality and user experience.

[0139] Corresponding to the signal input and output logic of the fourth and fifth embodiments above, as shown in FIG. Fig.10 As shown, optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0140] The storage circuit 50 includes n storage units, each storage unit is connected to a counter unit and an inversion control circuit 40;

[0141] Each storage unit includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a NAND gate NOR1 and a first two-to-one data selector MUX1;

[0142] The input end of the first memory Mem1, the input end of the second memory Mem2 and the input end of the third memory Mem3 are connected to a counter unit at the same time, the output end of the first memory Mem1 is connected to the first input end of the first two-to-one data selector MUX1, the output end of the second memory Mem2 is connected to the second input end of the first two-to-one data selector MUX1, the control end of the first two-to-one data selector MUX1 is used to input the write-back selection signal mem_sel, the output end of the first two-to-one data selector MUX1 is connected to the first input end of the NAND gate NOR1, the second input end of the NAND gate NOR1 is used to input the write-back control signal rewrite_en, and the NAND gate NOR1 constitutes the output end of the storage circuit 50;

[0143] The first memory Mem1 is used to store a corresponding one-bit count value in the first sub-digit code value;

[0144] The second memory Mem2 is used to store a corresponding one-bit count value in the second sub-digit code value;

[0145] The first memory Mem1, the second memory Mem2 and the third memory Mem3 also store corresponding one-bit count values ​​of the three digital code values ​​after three exposure samplings respectively.

[0146] In this embodiment, the difference between the circuit structure used in the second embodiment and the third embodiment is that the storage circuit 50 includes three memories and also includes a first two-to-one data selector MUX1, the n first memories Mem1 are used to store the n-bit count value of the first sub-digital code value corresponding to the low gain reset signal lcg_rst during the reset sampling period, and the n second memories Mem2 are used to store the n-bit count value of the second sub-digital code value corresponding to the high gain reset signal hcg_rst during the reset sampling period.

[0147] At the same time, when autofocus is implemented in low gain mode or high gain mode, before the corresponding exposure sampling period, the corresponding write-back selection signal mem_sel is output to the first two-to-one data selector MUX1 according to the first sub-digital code value or the second sub-digital code value to be written back, thereby selecting the first sub-digital code value or the second sub-digital code value to be written back to n counter units through the inversion control circuit 40.

[0148] The n-bit counter unit counts pulse signals input during the reset sampling period and the exposure sampling period and generates corresponding digital code values.

[0149] After each exposure sampling period, the three quantized digital code values ​​are finally stored in the first memory Mem1, the second memory Mem2 and the third memory Mem3 respectively. For example, when the readout circuit 1 is suitable for realizing autofocus under low conversion gain, the third digital code value, the fifth sub-digital code value and the sixth sub-digital code value are obtained by three exposure samplings, wherein the n-bit count value of the third digital code value is stored in n first memories Mem1 respectively, the n-bit count value of the fifth sub-digital code value is stored in n second memories Mem2 respectively, and the n-bit count value of the sixth sub-digital code value is stored in n third memories Mem3 respectively.

[0150] Alternatively, the readout circuit 1 is suitable for obtaining the third sub-digital code value, the fourth sub-digital code value and the fifth sub-digital code value by three exposure samplings when realizing autofocus at a high conversion gain, wherein the n-bit count value of the third sub-digital code value is respectively stored in n first memories Mem1, the n-bit count value of the fourth sub-digital code value is respectively stored in n second memories Mem2, and the n-bit count value of the fifth digital code value is respectively stored in n third memories Mem3, and the three memories are read out to the corresponding control circuit 3 according to the readout control signal, so that the control circuit 3 determines the image information according to the count code value of each storage circuit 50.

[0151] Embodiment 6

[0152] Based on the optimization and specificization of the first embodiment, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the pixel unit includes four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal Vrst or a pixel signal;

[0153] The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0154] The first pixel pulse signal includes a first pixel group pulse signal corresponding to simultaneous exposure of a pixel group in a high gain mode and a first image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit;

[0155] The second pixel pulse signal includes a second pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low gain mode and a second image pulse signal corresponding to simultaneous exposure of the sub-pixels in the pixel unit;

[0156] The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive;

[0157] The second exposure sampling period includes a fifth exposure sampling period and a sixth exposure sampling period that are consecutive;

[0158] The first digital code value includes a first sub-digital code value and a second sub-digital code value;

[0159] The counter circuit 30 is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value;

[0160] In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value;

[0161] The third digital code value includes a third sub-digital code value and a fourth sub-digital code value;

[0162] In a third exposure sampling period, the pulse signal of the first pixel group is counted based on the second digital code value and stored as a third sub-digital code value;

[0163] In a fourth exposure sampling period, the first image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value;

[0164] The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value;

[0165] In the fifth exposure sampling period, the second pixel group pulse signal is counted based on the fourth digital code value and stored as a fifth sub-digital code value;

[0166] In a sixth exposure sampling period, the second image pulse signal is counted based on the fourth digital code value and stored as a sixth sub-digital code value;

[0167] The storage circuit 50 is connected to the counter circuit 30 and configured to store the first sub-digital code value and the second sub-digital code value, and before the fourth exposure sampling period, the second sub-digital code value is triggered by the write-back control signal rewrite_en to be written back to the counter circuit 30, and before the fifth exposure sampling period and the sixth exposure sampling period, the first sub-digital code value is triggered by the write-back control signal rewrite_en to be written back to the counter circuit 30;

[0168] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control signal trig_pulse triggers the counter circuit 30 to invert the second sub-digital code value of the memory to generate a second digital code value, and invert the first sub-digital code value to generate a fourth digital code value.

[0169] In this embodiment, the readout circuit 1 is suitable for realizing autofocus simultaneously under high conversion gain and low conversion gain, the reset pulse signal includes a high gain reset pulse signal and a low gain reset pulse signal, the first pixel pulse signal includes a high gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high gain mode and a high gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit, the second pixel pulse signal includes a low gain image pulse signal, and the second pixel pulse signal includes a low gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low gain mode and a low gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit.

[0170] Combination Figure 8 and Fig. 9 As shown, in the first reset sampling period, the comparison circuit 20 compares the low gain reset signal lcg_rst with the reset ramp voltage signal, generates a low gain reset pulse signal and inputs it to the counter circuit 30, the counter circuit 30 counts the low gain reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate the first sub-digital code value and writes it into the storage circuit 50.

[0171] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the high gain reset signal hcg_rst with the reset ramp voltage signal and generates a high gain reset pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the high gain reset pulse signal in the same direction, and stops counting when the output of the comparison circuit 20 flips. The quantization of the high gain reset signal hcg_rst is completed, and the counter circuit 30 counts to generate a second sub-digital code value and stores it inside itself.

[0172] Before the third exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30, and the counter circuit 30 switches to the negation mode, and inverts the stored second sub-digital code value to the second digital code value as the initial state of the third exposure sampling period, and then, the counter circuit 30 returns to the counting mode, and quantizes the high gain pixel group signal hcg_sigl in the third exposure sampling period, and the comparison circuit 20 compares the high gain pixel group signal hcg_sigl with the pixel ramp voltage signal. The comparison circuit 20 compares and generates a high-gain pixel group pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the high-gain pixel group pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain pixel group pulse signal is completed. The counter circuit 30 counts and generates a third sub-digital code value, wherein the third sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0173] Then, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored second sub-digital code value back to the counter circuit 30 again. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back second sub-digital code value to generate a second digital code value. The second digital code value is used as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and quantizes the high-gain image signal hcg_sig in the fourth exposure sampling period. The comparison circuit 20 quantizes the high-gain image signal hcg_sig. ig is compared with the pixel slope voltage signal and a high-gain image pulse signal is generated. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain image pulse signal is completed. The counter circuit 30 counts to generate a fourth sub-digital code value, wherein the fourth sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0174] Before the fifth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored first sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value is used as the initial state of the fifth exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and quantizes the low-gain pixel group signal lcg_sigl in the fifth exposure sampling period. The comparison circuit 20 compares the low-gain pixel group signal lcg_sigl with the pixel ramp voltage The signals are compared and a low-gain pixel group pulse signal is generated. The low-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain pixel group pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain pixel group pulse signal ends. The counter circuit 30 counts to generate a fifth sub-digital code value, wherein the fifth sub-digital code value is the difference between the digital code values ​​corresponding to the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0175] Then, the counter circuit 30 is reset again. Before the sixth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en, and writes the stored first sub-digital code value back to the counter circuit 30 again. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value is used as the initial state of the sixth exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and quantizes the low-gain image signal lcg_sig in the sixth exposure sampling period. The comparison circuit 20 quantizes the low-gain image signal lcg_sig. ig is compared with the pixel ramp voltage signal and a low gain image pulse signal is generated. The low gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low gain image pulse signal ends. The counter circuit 30 counts to generate a sixth sub-digital code value, wherein the sixth sub-digital code value is the difference between the digital code values ​​corresponding to the low gain image signal lcg_sig and the low gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0176] At the same time, the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value and the sixth sub-digital code value obtained by the four quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information according to the third sub-digital code value, the fourth sub-digital code value and the fifth digital code value, and realizes automatic focus in the high conversion gain mode, thereby improving the imaging quality and user experience.

[0177] Corresponding to the signal input and output logic of the fourth and fifth embodiments above, as shown in FIG. Fig.11 As shown, optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0178] The storage circuit 50 includes n storage units, each storage unit is connected to a counter unit and an inversion control circuit 40;

[0179] Each storage unit includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a fourth memory Mem4, a NAND gate NOR1 and a first two-to-one data selector MUX1;

[0180] The input end of the first memory Mem1, the input end of the second memory Mem2 and the input end of the third memory Mem3 are connected to a counter unit at the same time, the output end of the first memory Mem1 is connected to the first input end of the first two-to-one data selector MUX1, the output end of the second memory Mem2 is connected to the second input end of the first two-to-one data selector MUX1, the control end of the first two-to-one data selector MUX1 is used to input the write-back selection signal mem_sel, the output end of the first two-to-one data selector MUX1 is connected to the first input end of the NAND gate NOR1, the second input end of the NAND gate NOR1 is used to input the write-back control signal rewrite_en, and the NAND gate NOR1 constitutes the output end of the storage circuit 50;

[0181] The first memory Mem1 is used to store a corresponding one-bit count value in the first sub-digit code value;

[0182] The second memory Mem2 is used to store a corresponding one-bit count value in the second sub-digit code value;

[0183] The first memory Mem1, the second memory Mem2, the third memory Mem3 and the fourth memory Mem4 also store corresponding one-bit count values ​​of the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value and the sixth sub-digital code value respectively.

[0184] In this embodiment, the difference between the circuit structure adopted in the fourth embodiment and the fifth embodiment is that the storage circuit 50 includes four memories, n first memories Mem1 are used to store the n-bit count value of the first sub-digital code value corresponding to the low gain reset signal lcg_rst during the reset sampling period, and n second memories Mem2 are used to store the n-bit count value of the second sub-digital code value corresponding to the high gain reset signal hcg_rst during the reset sampling period.

[0185] At the same time, when autofocus is implemented in low gain mode or high gain mode, before the corresponding exposure sampling period, the corresponding write-back selection signal mem_sel is output to the first two-to-one data selector MUX1 according to the first sub-digital code value or the second sub-digital code value to be written back, thereby selecting the first sub-digital code value or the second sub-digital code value to be written back to n counter units through the inversion control circuit 40.

[0186] The n-bit counter unit counts pulse signals input during the reset sampling period and the exposure sampling period and generates corresponding digital code values.

[0187] After each exposure sampling period, the four quantized digital code values ​​are finally stored in the first memory Mem1, the second memory Mem2, the third memory Mem3 and the fourth memory Mem4 respectively. The four memories are read out to the corresponding control circuit 3 according to the read control signal, so that the control circuit 3 determines the image information according to the counting code value of each storage circuit 50.

[0188] Optionally, in some embodiments, the corresponding digital code value may be read out in advance through the memory and then reset, so that the memory read out in advance can be reused as a memory for subsequent digital code values, which can further reduce the number of memories and the occupied area.

[0189] Embodiment 7

[0190] Based on the optimization and specificization of the first embodiment to the embodiment, optionally, as Figure 7 , Fig.10 and Fig.11 As shown, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0191] The negation control circuit 40 includes n selection circuits;

[0192] The first input terminal of the i-th selection circuit is used to input the inversion control signal trig_pulse, the second input terminal of the first selection circuit 41 is used to input the clock signal count_clk, the second input terminals of the second selection circuit 42 to the n-th selection circuit are connected to the output terminal of the i-1-th stage counter unit, the third input terminal of the i-th selection circuit is used to input a low level signal, the fourth input terminal of the first selection circuit 41 is used to input the output signal count_out of the comparison circuit 20, the output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, i is 1, 2, ..n;

[0193] The i-th selection circuit outputs a signal inputted from the first input terminal, the second input terminal or the third input terminal thereof in response to the mode selection signal mode_sel and the reverse writing control signal.

[0194] In this embodiment, the negation control circuit 40 is used to implement the transmission of the negation control signal trig_pulse, the written-back digital code value and the clock signal count_clk.

[0195] Each selection circuit is connected to the front end of a counter unit, and outputs the signal corresponding to the input end to its own output end according to the received mode selection signal mode_sel. Before quantization, each counter unit is reset, and in the reset sampling period, the pixel unit outputs the reset signal Vrst to the comparison circuit 20. The comparison circuit 20 compares the reset signal Vrst with the ramp voltage signal and generates a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the first level mode selection signal mode_sel and triggers the connection of its own second input end and output end. The first selection circuit 41 outputs the clock signal count_clk to the first counter unit 31. The subsequent selection circuit selects the count value of the counter unit of the previous stage and outputs it to the counter unit of the next stage. The counter units of each stage respectively store the first count value of the current stage, and the first count values ​​of the counter units of each stage are combined to generate the first digital code value.

[0196] In the inversion mode of the exposure sampling period, the mode selection signal mode_sel switches to the second level, each selection circuit outputs the inversion control signal trig_pulse of the first input terminal to the counter unit at the back end, each counter unit switches to the inversion mode, and inverts the first count value stored inside itself to the second count value or the fourth digital code value, and then, the mode selection signal mode_sel switches to the first level again, the inversion control signal trig_pulse also switches the level state, and each counter unit switches to the counting mode.

[0197] And in the write-back mode during the exposure sampling period, after receiving the write-back control signal rewrite_en, the storage circuit 50 writes back the stored corresponding first digital code value to the n selection circuits, and the n selection circuits write back the written-back first digital code value to the n counter units.

[0198] Among them, the selection circuit can select a corresponding switch structure, a selector, etc., and the counter unit can select a corresponding trigger, latch, etc. structure.

[0199] Please continue to read Figure 7 , Fig.10 and Fig.11 Optionally, the first selection circuit 41 includes an AND gate AND1, a second two-to-one data selector MUX2, a third two-to-one data selector MUX3 and a first inverter U1;

[0200] The first input terminal of the AND gate AND1 is used to input the clock signal count_clk, the second input terminal of the AND gate AND1 is used to input the output signal count_out of the comparison circuit 20, the first input terminal of the second two-to-one data selector MUX2 is used to input the inversion control signal trig_pulse, the output terminal of the AND gate AND1 is connected to the second input terminal of the two-to-one data selector, the second input terminal of the second two-to-one data selector MUX2 is used to input the low level signal tie_lo, the control terminal of the second two-to-one data selector MUX2 is connected to the output terminal of the storage circuit 50, and the second two-to-one data selector MUX2 is connected to the output terminal of the storage circuit 50. The output end of X2 is connected to the first input end of its third two-select-one data selector MUX3, the second input end of its third two-select-one data selector MUX3 is used to input the clock signal count_clk or the value output by the previous stage counter unit, the control end of its third two-select-one data selector MUX3 is used to input the mode selection signal mode_sel, the output end of its third two-select-one data selector MUX3 is connected to the input end of the first inverter U1, and the output end of its first inverter U1 is used to output a corresponding one of the inverted control signal trig_pulse, the clock signal count_clk and the low level signal tie_lo;

[0201] The second selection circuit 42 to the nth selection circuit respectively include a second two-to-one data selector MUX2, a third two-to-one data selector MUX3 and a first inverter U1;

[0202] The first input end of its second two-to-one data selector MUX2 is used to input the inversion control signal trig_pulse, the second input end of its second two-to-one data selector MUX2 is used to input the low-level signal tie_lo, the control end of its second two-to-one data selector MUX2 is connected to the output end of its storage circuit 50, the output end of its second two-to-one data selector MUX2 is connected to the first input end of its third two-to-one data selector MUX3, the second input end of its third two-to-one data selector MUX3 is used to input the clock signal count_clk or the value output by the previous stage counter unit, the control end of its third two-to-one data selector MUX3 is used to input its mode selection signal mode_sel, the output end of its third two-to-one data selector MUX3 is connected to the input end of its first inverter U1, and the output end of its first inverter U1 is used to output the inversion control signal trig_pulse, its clock signal count_clk, the low-level signal tie_lo and the corresponding one of the value output by the previous stage counter unit.

[0203] The counter unit includes a D flip-flop DFF and a second inverter U2;

[0204] The clock signal count_clk terminal of the D flip-flop DFF of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop DFF of the i-th counter unit is connected to the input terminal of the second inverter U2 and the data input terminal of the D flip-flop DFF, and the output terminal of the second inverter U2 is connected to the second input terminal of the i+1-th selection circuit.

[0205] Alternatively, the counter unit comprises a D flip-flop DFF;

[0206] The clock signal count_clk terminal of the D flip-flop DFF of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop DFF of the i-th counter unit is connected to the data input terminal of the D flip-flop DFF, and the positive output terminal of the D flip-flop DFF is connected to the second input terminal of the i+1-th selection circuit.

[0207] In the present embodiment, when the inverting output terminal of the D flip-flop DFF is connected to the second inverter U2 and the second inverter U2 serves as the output terminal of the counter unit, the counter unit constitutes an up-counter; and when the positive output terminal of the D flip-flop DFF constitutes the output terminal of the counter unit, the counter unit constitutes a down-counter. By performing operations such as inverting and writing back the reset signal Vrst, the counter unit does not need to switch between up-counting and down-counting when continuously quantizing the reset signal Vrst and the pixel signal, and does not need to set up an additional holding circuit. Compared with the traditional counter circuit 30, the number of transistors can be reduced, thereby reducing the layout area and optimizing the routing, thereby achieving the purpose of reducing power consumption.

[0208] refer to Figure 5 and Figure 6 As shown, taking upward counting as an example, when the selection circuit and the counter unit are applied to the ADAF mode, the timing of a complete quantization cycle in the ADAF mode is as follows:

[0209] At time t0-t1, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0210] At time t2, the reset signal Vrst is quantized. At this time, the output signal count_out of the comparison circuit 20 is switched to a high level. After the clock signal count_clk is ANDed with the high level by gate AND1, the clock signal count_clk is output to the second input terminal of the third two-to-one data selector MUX3. At this time, the mode selection signal mode_sel is a high level, and the clock signal count_clk is selected and output to the first inverter U1 and to the first D flip-flop DFF. Each D flip-flop DFF counts upward under the action of the clock signal count_clk.

[0211] At time t3, the output of the comparison circuit 20 flips, the counting stops, the quantization of the reset signal Vrst ends, each D flip-flop DFF stores the count value of each bit of the first digital code value of the quantization result of the reset signal Vrst, and the first count value output by each second inverter U2 is combined to generate the first digital code value.

[0212] At time t4-t5, the read control signal is switched to a high level, and the first quantization result is stored in the first memory Mem1.

[0213] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to the inversion mode.

[0214] At time t6, the inversion control signal trig_pulse is switched to a low level, and a rising edge is generated at the clock input end of each D flip-flop DFF through the second two-to-one data selector MUX2 and the third two-to-one data selector MUX3, and the first quantization result digital code stored in each D flip-flop DFF is inverted as the initial state before the second quantization.

[0215] At time t7, the mode selection signal mode_sel is switched to a high level, and the counter unit returns to the counting mode; at time t8, the negation control circuit 40 is switched to a high level.

[0216] At time t9, the pixel group signal Vsigl is quantized starting from the initial state. At time t10, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the pixel group signal Vsigl is completed, and the D flip-flop DFF stores the third digital code value of the difference between the pixel group signal Vsigl and the reset signal Vrst.

[0217] At time t11-t12, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2, and then read out.

[0218] At time t12-t13, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0219] At time t13, the mode selection signal mode_sel switches to a low level, the write-back control signal rewrite_en switches to a high level, and the counter unit switches to the write-back mode.

[0220] At time t14, the inversion control signal trig_pulse is switched to a low level, and a rising edge is generated at the clock input end of the D flip-flop DFF through the second two-to-one data selector MUX2 and the third two-to-one data selector MUX3, and the first digital code value stored in the first memory Mem1 is written into the n-bit counter unit and inverted as the initial state of the image signal Vsig before quantization.

[0221] At time t15, the mode selection signal mode_sel is switched to a high level, and the counter unit returns to the counting mode. At time t16, the negation control signal trig_pulse is switched to a high level.

[0222] At time t17, the quantization of the image signal Vsig starts from the initial state. At time t18, the output of the comparison circuit 20 is flipped, the counting stops, and the quantization of the image signal Vsig is completed. The D flip-flop DFF stores the difference between the image signal Vsig and the reset signal Vrst, that is, the image quantization value of the correlated double sampling.

[0223] At time t19-t20, the read control signal is enabled, and the final quantization result is stored in the first memory Mem1, and then read out.

[0224] refer to Figure 5 and Figure 7 As shown, when the selection circuit is applied to the PGHDR mode, the timing of a complete quantization cycle in the PGHDR mode is as follows:

[0225] At time t0-t1, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0226] At time t2, the low gain reset signal lcg_rst is quantized. At this time, the output signal count_out of the comparison circuit 20 is switched to a high level. After the clock signal count_clk is ANDed with the high level by gate AND1, the clock signal count_clk is output to the second input terminal of the third two-to-one data selector MUX3. At this time, the mode selection signal mode_sel is a high level, the clock signal count_clk is selected and output to the first inverter U1, and then output to the first D flip-flop DFF. Each D flip-flop DFF counts upward under the action of the clock signal count_clk.

[0227] At time t3, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the low gain reset signal lcg_rst is completed, and the D flip-flop DFF stores the first sub-digital code of the quantization result of the low gain reset signal lcg_rst.

[0228] At time t4-t5, the read control signal is switched to a high level, and the first sub-digital code is stored in each first memory Mem1.

[0229] At time t5-t6, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0230] At time t7, the high gain reset signal hcg_rst is quantized from the initial state. At time t8, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the high gain reset signal hcg_rst is completed, and the second sub-digital code of the high gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0231] At time t9, the mode selection signal mode_sel switches to a low level, and the counter switches to the inversion mode; at time t10, the inversion control signal trig_pulse switches to a low level, and a rising edge is generated at the clock input end of the D flip-flop DFF output through the second two-to-one data selector MUX2 and the third two-to-one data selector MUX3, and the second quantization result digital code stored in each D flip-flop DFF is inverted to the second digital code value as the initial state before the second quantization.

[0232] At time t11, the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode; at time t12, the mode selection signal mode_sel switches to a high level.

[0233] At time t13, the quantization of the high-gain image signal hcg_sig starts from the initial state; at time t14, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the high-gain image signal hcg_sig ends, and the D flip-flop DFF stores the difference between the high-gain image signal hcg_sig and the reset signal Vrst, that is, the image quantization value of the correlated double sampling under high conversion gain. At time t15-t16, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2, and then read out.

[0234] At time t16-t17, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0); at time t17, the mode selection signal mode_sel switches to a low level, the write-back control signal rewrite_en switches to a high level, and the counter unit switches to write-back mode.

[0235] At time t18, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input end of the D flip-flop DFF, and writing the first sub-digital code value corresponding to the low gain reset signal lcg_rst stored in the first memory Mem1 back to the counter unit and inverting it as the initial state of the low gain image signal lcg_sig before quantization.

[0236] At time t19, the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode; at time t20, the negation control signal trig_pulse switches to a high level.

[0237] At time t21, the quantization of the low-gain image signal lcg_sig starts from the initial state; at time t22, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the low-gain image signal lcg_sig is completed, and the D flip-flop DFF stores the difference between the low-gain image signal lcg_sig and the reset signal Vrst, that is, the image quantization value of the correlated double sampling under low conversion gain. At time t23-t24, the readout control signal is enabled, and the final quantization result is stored in the first memory Mem1, and then read out.

[0238] At this point, a complete quantization cycle is completed, and finally the image quantization value of the correlated double sampling under high conversion gain and the image quantization value of the correlated double sampling under low conversion gain are obtained.

[0239] And when the selection circuit is used to implement the ADAF mode at low conversion gain, the timing within a complete quantization cycle is as follows Figure 5 As shown:

[0240] At time t0-t1, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0241] At time t2, the low gain reset signal lcg_rst is quantized, and the counter counts upward under the action of the high-speed clock count_clk. At time t3, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the low gain reset signal lcg_rst is completed, and the D flip-flop DFF stores the first sub-digital code value of the quantization result of the low gain reset signal lcg_rst.

[0242] At time t4-t5, the read control signal is switched to a high level, and the first quantization result is stored in the first memory Mem1.

[0243] At time t5-t6, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0244] At time t7, the high gain reset signal hcg_rst is quantized from the initial state. At time t8, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the high gain reset signal hcg_rst is completed, and the second sub-digital code value of the high gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0245] At time t9, the mode selection signal mode_sel switches to a low level, and the connections between the various stages of the counter are disconnected. At time t10, the inversion control signal trig_pulse switches to a low level, and a rising edge is generated at the clock input of the D flip-flop DFF. The digital code of the second quantization result stored in the D flip-flop DFF is inverted as the initial state before the third quantization.

[0246] At time t11, the mode selection signal mode_sel switches to a high level, and the counter returns to the counting mode; at time t12, the negation control signal trig_pulse switches to a high level.

[0247] At time t13, quantization of the high-gain image signal hcg_sig starts from the initial state; at time t14, the output of the comparison circuit 20 is flipped, the counting stops, and the quantization of the high-gain image signal hcg_sig is completed. The D flip-flop DFF stores the difference between the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, that is, the image quantization value of the correlated double sampling under high conversion gain.

[0248] At time t15, the write-back control signal rewrite_en and the mode selection signal mode_sel are switched to high level, the counter is switched to write-back mode, and the first sub-digital code value stored in the first memory Mem1 is selected to be written back into the counter; at time t15-t16, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2, and then read out.

[0249] At t16-t17, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0); at t17, the mode selection signal mode_sel switches to a low level, and the connections between the various levels of the counter are disconnected; at t18, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D flip-flop DFF, and writing back the first sub-digital code value corresponding to the low-gain reset signal lcg_rst stored in the first memory Mem1 to the counter unit and inverting it as the initial state before the fourth quantization; at t19, the mode selection signal mode_sel switches to a high level, and the counter returns to the counting mode; at t20, the inversion control signal trig_pulse switches to a high level.

[0250] At time t21, the quantization of the low-gain pixel group signal lcg_sigl starts from the initial state; at time t22, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the low-gain pixel group signal lcg_sigl is completed, and the difference between the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst is stored in the D flip-flop DFF, that is, the quantization value of the pixel group signal Vsigl of the correlated double sampling under low conversion gain. At time t23-t24, hcg_wrt is enabled, and the final quantization result is stored in the third memory Mem3, and then read out.

[0251] At t24-t25, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0); at t25, the mode selection signal mode_sel switches to a low level, and the connections between the various levels of the counter units are disconnected; at t26, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D flip-flop DFF, and writing the first digital code value stored in the first memory Mem1 back to the counter and inverting it as the initial state before the fifth sub-quantization; at t27, the mode selection signal mode_sel switches to a high level, and the counter returns to the counting mode; at t28, the inversion control signal trig_pulse switches to a high level.

[0252] At time t29, the quantization of the low-gain image signal lcg_sig starts from the initial state; at time t30, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the low-gain image signal lcg_sig is completed, and the D flip-flop DFF stores the difference between the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, that is, the image quantization value of the correlated double sampling under low conversion gain. At time t31-t32, lcg_wrt is enabled, and the final quantization result is stored in the first memory Mem1, and then read out.

[0253] At this point, a complete quantization cycle is completed, and the image quantization value of the correlated double sampling under high conversion gain, the pixel group quantization value of the correlated double sampling under low conversion gain, and the image quantization value of the correlated double sampling under low conversion gain are obtained in turn.

[0254] By analogy, when the selection circuit is applied to implement the ADAF mode under high conversion gain, or is applied to implement the ADAF mode under high conversion gain and low conversion gain at the same time, the selection circuit selects and outputs the corresponding inversion control signal trig_pulse or the digital code value to the counter unit according to the corresponding mode selection signal mode_sel received or the written-back digital code value, so that the counter unit performs counting, inversion and other operations.

[0255] After each quantization is completed, the corresponding digital code value is stored in the corresponding memory, and each memory reads it to the control circuit 3 according to the received read control signal, so that the control circuit 3 determines the image information according to each digital code value.

[0256] In order to realize the negation function of the D flip-flop DFF in the third and fourth embodiments, as shown in FIG. Fig.12 As shown, optionally, the D flip-flop DFF includes a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transmission gate tran1, a second transmission gate tran2, a third transmission gate tran3 and a fourth transmission gate tran4;

[0257] In this embodiment, the first transmission gate tran1, the fourth inverter U4, the fifth inverter U5 and the second transmission gate tran2 constitute a master latch, the third transmission gate tran3, the sixth inverter U6, the seventh inverter U7 and the fourth transmission gate tran4 constitute a slave latch, the master latch is used to stably latch and output the input value of the D flip-flop DFF, the slave latch is used to stably latch and output the output value of the master latch, the third inverter U3 is used to invert the input data signal and output it to the master latch, the eighth inverter U8 is used to invert the output value of the slave latch and output it, and when the clock signal count_clk end of the D flip-flop DFF receives a rising edge, the third inverter U3, the master latch, the slave latch and the eighth inverter U8 invert and output the latched value.

[0258] Embodiment 8

[0259] The present invention also provides an image sensor, such as Figure 2 As shown, the image sensor includes a pixel array 100, a control circuit 3 and a plurality of image sensor readout circuits 1. The specific structure of the image sensor readout circuit 1 refers to the above embodiment. Since the image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the pixel array 100 includes a plurality of pixel units arranged in an array;

[0260] The readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit 1 of each image sensor is also respectively connected to the control circuit 3 .

[0261] In this embodiment, the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may also include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array, and a plurality of pixel units arranged in columns are connected in common. The control circuit 3 selects the pixel units in each row through a row selection signal, and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information according to the digital code value.

[0262] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A readout circuit for an image sensor, characterized in that: The readout circuit comprises: A ramp voltage circuit configured to output a ramp voltage signal; A comparison circuit, wherein a first input terminal is connected to the pixel unit, and a second input terminal is connected to the ramp voltage circuit, and is configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal, and output at least one reset pulse signal and two pixel pulse signals at intervals; a counter circuit connected to the comparison circuit, configured to count the at least one reset pulse signal in at least one reset sampling period and store it as at least one first digital code value, count the first pixel pulse signal based on the second digital code value in the first exposure sampling period and store it as a third digital code value, and count the second pixel pulse signal based on the fourth digital code value in the second exposure sampling period and store it as a fifth digital code value; a storage circuit connected to the counter circuit and configured to store the at least one first digital code value and, before the second exposure sampling period, to write back one of the at least one first digital code value to the counter circuit when triggered by a write-back control signal; The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, it is triggered by the mode selection signal to output an inversion control signal to the counter circuit to trigger the counter circuit to invert the first digital code value in the memory to generate the second digital code value or the fourth digital code value.

2. The readout circuit of the image sensor according to claim 1, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The at least one reset signal is a reset signal generated when the pixel units are reset simultaneously; The first pixel pulse signal and the second pixel pulse signal are respectively one of a pixel group pulse signal corresponding to simultaneous exposure of the pixel group and an image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit.

3. The readout circuit of the image sensor according to claim 1, wherein: The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal and the second pixel pulse signal are respectively one of a high-gain image pulse signal and a low-gain image pulse signal; The counter circuit is configured to: count one of the reset pulse signals in a first reset sampling period to generate a first digital code value; In a second reset sampling period, another reset pulse signal is counted to generate another first digital code value; In a first exposure sampling period, the first pixel pulse signal is counted based on the second digital code value and stored as a third digital code value; In a second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value.

4. The readout circuit of the image sensor according to claim 2 or 3, characterized in that: The counter circuit includes a first counter unit to an nth counter unit; The storage circuit comprises n storage units, each of which is connected to one of the counter units and the inversion control circuit respectively; Each of the storage units includes a first memory, a second memory and a NAND gate; The input ends of the first memory and the second memory are respectively connected to a counter unit, the output end of the first memory is connected to the first input end of the NAND gate, the second input end of the NAND gate is used to input the write-back control signal, and the NAND gate constitutes the output end of the storage unit; The first memory is configured to store a corresponding one-bit count value of at least one first digital code value; The first memory and the second memory respectively store a corresponding one-bit count value of one of the third digital code value and the fifth digital code value.

5. The readout circuit of the image sensor according to claim 1, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The second exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive; The first digital code value includes a first sub-digital code value and a second sub-digital code value; The counter circuit is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value; In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value; In the first exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a third digital code value; The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value; In a third exposure sampling period, counting the low-gain pixel group pulse signal based on the fourth digital code value and storing it as a fifth sub-digital code value; In a fourth exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as a sixth sub-digital code value; a storage circuit connected to the counter circuit and configured to store the first sub-digital code value and write the first sub-digital code value back to the counter circuit when triggered by a write-back control signal before the third exposure sampling period and the fourth exposure sampling period; The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, the inversion control circuit is triggered by the inversion control signal to control the counter circuit to invert the first sub-digital code value of the memory to generate the fourth digital code value, and to invert the second sub-digital code value to generate the second digital code value.

6. The readout circuit of the image sensor according to claim 1, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The second pixel pulse signal comprises a low-gain image pulse signal; The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive; The first digital code value includes a first sub-digital code value and a second sub-digital code value; The counter circuit is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value; In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value; The third digital code value includes a third sub-digital code value and a fourth sub-digital code value; In a third exposure sampling period, the high-gain pixel group pulse signal is counted based on the second digital code value and stored as a third sub-digital code value; In a fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value; In a second exposure sampling period, counting the low-gain image pulse signal based on the fourth digital code value and storing it as a fifth digital code value; a storage circuit connected to the counter circuit, configured to store the first sub-digital code value and the second sub-digital code value, and before the fourth exposure sampling period and the second exposure sampling period, triggered by a write-back control signal to write the second sub-digital code value and the first sub-digital code value back to the counter circuit; The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, the inversion control circuit is triggered by the inversion control signal to control the counter circuit to invert the second sub-digital code value of the memory to generate the second digital code value, and to invert the first sub-digital code value to generate the fourth digital code value.

7. The readout circuit of the image sensor according to claim 5 or 6, characterized in that: The counter circuit includes a first counter unit to an nth counter unit; The storage circuit comprises n storage units, each of which is connected to one of the counter units and the inversion control circuit respectively; Each of the storage units includes a first memory, a second memory, a third memory, a NAND gate and a first two-to-one data selector; The input end of the first memory, the input end of the second memory and the input end of the third memory are connected to the counter unit at the same time, the output end of the first memory is connected to the first input end of the first two-to-one data selector, the output end of the second memory is connected to the second input end of the first two-to-one data selector, the control end of the first two-to-one data selector is used to input a write-back selection signal, the output end of the first two-to-one data selector is connected to the first input end of the NAND gate, the second input end of the NAND gate is used to input the write-back control signal, and the NAND gate constitutes the output end of the storage circuit; The first memory is used to store a corresponding one-bit count value in the first sub-digit code value; The second memory is used to store a corresponding one-bit count value in the second sub-digit code value; The first memory, the second memory and the third memory also respectively store a corresponding one-bit count value in the three digital code values ​​after three exposure samplings.

8. The readout circuit of the image sensor according to claim 1, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a first pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the high gain mode and a first image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The second pixel pulse signal includes a second pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low gain mode and a second image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive; The second exposure sampling period includes a fifth exposure sampling period and a sixth exposure sampling period that are consecutive; The first digital code value includes a first sub-digital code value and a second sub-digital code value; The counter circuit is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value; In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value; The third digital code value includes a third sub-digital code value and a fourth sub-digital code value; In a third exposure sampling period, counting the first pixel group pulse signal based on the second digital code value and storing it as a third sub-digital code value; In a fourth exposure sampling period, the first image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value; The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value; In a fifth exposure sampling period, the second pixel group pulse signal is counted based on the fourth digital code value and stored as a fifth sub-digital code value; In a sixth exposure sampling period, counting the second image pulse signal based on the fourth digital code value and storing it as a sixth sub-digital code value; a storage circuit connected to the counter circuit, configured to store the first sub-digital code value and the second sub-digital code value, and before a fourth exposure sampling period, triggered by a write-back control signal, write the second sub-digital code value back to the counter circuit, and before a fifth exposure sampling period and a sixth exposure sampling period, triggered by a write-back control signal, write the first sub-digital code value back to the counter circuit; The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, the inversion control circuit is triggered by the inversion control signal to control the counter circuit to invert the second sub-digital code value of the memory to generate the second digital code value, and to invert the first sub-digital code value to generate the fourth digital code value.

9. The readout circuit of the image sensor according to claim 8, characterized in that: The counter circuit includes a first counter unit to an nth counter unit; The storage circuit comprises n storage units, each of which is connected to one of the counter units and the inversion control circuit respectively; Each of the storage units includes a first memory, a second memory, a third memory, a fourth memory, a NAND gate and a first two-to-one data selector; The input end of the first memory, the input end of the second memory and the input end of the third memory are connected to the counter unit at the same time, the output end of the first memory is connected to the first input end of the first two-to-one data selector, the output end of the second memory is connected to the second input end of the first two-to-one data selector, the control end of the first two-to-one data selector is used to input a write-back selection signal, the output end of the first two-to-one data selector is connected to the first input end of the NAND gate, the second input end of the NAND gate is used to input the write-back control signal, and the NAND gate constitutes the output end of the storage circuit; The first memory is used to store a corresponding one-bit count value in the first sub-digit code value; The second memory is used to store a corresponding one-bit count value in the second sub-digit code value; The first memory, the second memory, the third memory and the fourth memory also store corresponding one-bit count values ​​of the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value and the sixth sub-digital code value respectively.

10. The readout circuit of the image sensor according to claim 1, wherein: The counter circuit includes a first counter unit to an nth counter unit; The negation control circuit includes n selection circuits; The first input end of the i-th selection circuit is used to input the negation control signal, the second input end of the first selection circuit is used to input the clock signal, the second input end of the second selection circuit to the n-th selection circuit is connected to the output end of the i-1-th level counter unit, the third input end of the i-th selection circuit is used to input a low level signal, the fourth input end of the first selection circuit is used to input the output signal of the comparison circuit, the output end of the i-th selection circuit is connected to the input end of the i-th level counter unit, i is 1, 2, ..n; The i-th selection circuit outputs the signal inputted from the first input terminal, the second input terminal or the third input terminal thereof in response to the mode selection signal and the reverse write control signal.

11. The readout circuit of the image sensor according to claim 10, characterized in that: The first selection circuit includes an AND gate, a second two-to-one data selector, a third two-to-one data selector and a first inverter; The first input end of the AND gate is used to input the clock signal, the second input end of the AND gate is used to input the output signal of the comparison circuit, the first input end of the second two-to-one data selector is used to input the inversion control signal, the output end of the AND gate is connected to the second input end of the two-to-one data selector, the second input end of the second two-to-one data selector is used to input the low-level signal, the control end of the second two-to-one data selector is connected to the output end of the storage circuit, the output end of the second two-to-one data selector is connected to the first input end of the third two-to-one data selector, the second input end of the third two-to-one data selector is used to input the clock signal or the value output by the previous stage counter unit, the control end of the third two-to-one data selector is used to input the mode selection signal, the output end of the third two-to-one data selector is connected to the input end of the first inverter, and the output end of the first inverter is used to output a corresponding one of the inversion control signal, the clock signal and the low-level signal; The second selection circuit to the nth selection circuit respectively include a second two-to-one data selector, a third two-to-one data selector and a first inverter; The first input end of its second two-to-one data selector is used to input an inversion control signal, the second input end of its second two-to-one data selector is used to input a low-level signal, the control end of its second two-to-one data selector is connected to the output end of its storage circuit, the output end of its second two-to-one data selector is connected to the first input end of its third two-to-one data selector, the second input end of its third two-to-one data selector is used to input a clock signal or a numerical value output by a previous-stage counter unit, the control end of its third two-to-one data selector is used to input its mode selection signal, the output end of its third two-to-one data selector is connected to the input end of its first inverter, and the output end of its first inverter is used to output a corresponding one of the inversion control signal, its clock signal, a low-level signal, and the numerical value output by the previous-stage counter unit.

12. The readout circuit of the image sensor according to claim 10, wherein: The counter unit includes a D flip-flop and a second inverter; The clock signal end of the D flip-flop of the i-th counter unit is connected to the signal output end of the i-th selection circuit, the inverting output end of the D flip-flop of the i-th counter unit is connected to the input end of the second inverter and the data input end of the D flip-flop, and the output end of the second inverter is connected to the second input end of the (i+1)-th selection circuit.

13. The readout circuit of the image sensor according to claim 10, characterized in that: The counter unit comprises a D flip-flop; The clock signal terminal of the D flip-flop of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop of the i-th counter unit is connected to the data input terminal of the D flip-flop, and the positive output terminal of the D flip-flop is connected to the second input terminal of the i+1-th selection circuit.

14. An image sensor, characterized in that: A method of manufacturing an image sensor comprising a pixel array, a control circuit, and a plurality of readout circuits of the image sensor according to any one of claims 1 to 13, wherein the pixel array comprises a plurality of pixel units arranged in an array; The readout circuit of each of the image sensors is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit of each of the image sensors is also respectively connected to the control circuit.

Images