Electrostatic testing method, device, equipment and storage medium for navigation chip packaging

Abstract

The present invention relates to an electrostatic testing method, device, equipment and storage medium for navigation chip packaging, comprising the following steps: identifying whether there is defect information in the three-dimensional packaging model, and if so, identifying and locating the defect type of the three-dimensional packaging model based on the defect information to obtain the defect type and the defect position corresponding to the defect type; simulating the electrostatic electric field distribution corresponding to the defect position through preset electrostatic field simulation software to obtain an electric field strength distribution map; evaluating the degree of impact on the navigation chip based on the electric field strength distribution map to obtain a performance impact assessment level of the navigation chip; if the performance impact assessment level exceeds a preset level threshold, formulating an electrostatic protection design plan based on the electric field strength distribution map of the defect position and the defect type, thereby solving the technical problem that electrostatic discharge phenomenon affects chip performance and life during the packaging process of the navigation chip.

Description

Technical Field

[0001] The present invention relates to the technical field of navigation chips, and in particular to an electrostatic testing method, device, equipment and storage medium for navigation chip packaging. Background Art

[0002] With the rapid development of the global satellite navigation system (GNSS) and its wide application in military, civilian and other fields, the performance and reliability of navigation chips, as the core components for realizing navigation functions, have received unprecedented attention. However, in the packaging process of navigation chips, electrostatic discharge (ESD) has become one of the important factors affecting chip performance and life. ESD may not only cause permanent damage to the internal circuits of the chip, but also cause changes in the physical or chemical properties of the packaging material, thereby indirectly affecting the working stability of the chip. Therefore, how to effectively detect and prevent the impact of ESD on navigation chips has become a key issue in current research.

[0003] Existing ESD testing methods mostly focus on simulation analysis in the chip design stage or functional testing of finished chips, and pay less attention to electrostatic protection during the packaging process. Although these methods can predict the possible impact of ESD on chips to a certain extent, due to the lack of specific analysis of ESD behavior in actual products after packaging, their results are often not accurate enough. In addition, traditional ESD testing methods are difficult to accurately identify and locate internal defects in the packaging structure, resulting in the inability to propose effective electrostatic protection measures in a targeted manner. The existence of these problems limits the application effect of ESD testing technology in improving the reliability of navigation chips and extending their service life.

[0004] In order to solve the above problems, this study proposed an electrostatic testing method for navigation chip packaging, which combines multiple advanced technologies such as surface morphology scanning, defect recognition algorithm, electrostatic field simulation, and performance impact evaluation. Through this method, not only can a comprehensive ESD risk assessment of the navigation chip after packaging be achieved, but also an electrostatic protection scheme can be customized according to the specific defect situation, thereby effectively improving the anti-static ability of the navigation chip. The application of this method will provide navigation chip manufacturers with a more scientific and reasonable ESD protection strategy, which will help promote the technological progress and development of the entire industry. Summary of the invention

[0005] The main purpose of the present invention is to provide an electrostatic testing method, device, equipment and storage medium for navigation chip packaging, which solves the technical problem that electrostatic discharge phenomenon affects chip performance and life during the packaging process of the navigation chip.

[0006] To achieve the above object, the present invention provides an electrostatic testing method for navigation chip packaging, which is applied to a navigation chip packaging device, wherein a navigation chip is arranged in the navigation chip packaging device, and comprises the following steps:

[0007] Scanning the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip;

[0008] Identify whether there is defect information in the three-dimensional packaging model. If so, identify and locate the defect type of the three-dimensional packaging model based on the defect information using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type;

[0009] The electrostatic field distribution corresponding to the defect position is simulated and tested by a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram;

[0010] Based on the electric field strength distribution diagram, the navigation chip is evaluated for its performance impact, to obtain a performance impact evaluation level of the navigation chip;

[0011] If the performance impact assessment level exceeds a preset level threshold, an electrostatic protection design plan is formulated based on the electric field strength distribution diagram of the defect location and the defect type.

[0012] Furthermore, the surface topography scanning of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip includes:

[0013] Scanning the surface of the navigation chip packaging device at multiple angles using a preset non-contact three-dimensional scanner to obtain two-dimensional images at multiple viewing angles;

[0014] Performing coordinate point registration and fusion on the two-dimensional image to obtain preliminary three-dimensional point cloud data;

[0015] Smoothing the preliminary three-dimensional point cloud data to obtain smoothed three-dimensional point cloud data;

[0016] Performing grid processing on the smoothed three-dimensional point cloud data to obtain a preliminary three-dimensional grid model;

[0017] The three-dimensional mesh model is enhanced in detail to obtain a three-dimensional packaging model of the navigation chip.

[0018] Furthermore, the method of identifying and locating the defect type of the three-dimensional packaging model based on the defect information by using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type includes:

[0019] Extracting defect features from the three-dimensional packaging model using a preset defect recognition algorithm to obtain a multi-scale defect feature map;

[0020] Performing preliminary defect recognition on the multi-scale defect feature map through the attention mechanism in the defect recognition algorithm to obtain a preliminary defect candidate region; wherein the preliminary defect candidate region has at least one;

[0021] Performing defect morphology processing on the preliminary defect candidate area to obtain a defect boundary area;

[0022] Selecting a corresponding key defect point in each of the defect boundary regions, and establishing a corresponding polar coordinate system with the key defect point corresponding to each of the defect boundary regions as the center;

[0023] Dividing the space of the polar coordinate system into a plurality of discrete cells, and counting the corresponding numbers of key defect points of the plurality of discrete cells to obtain a statistical result of the key defect points;

[0024] Establishing a local shape context histogram based on the statistical results;

[0025] All the local shape context histograms are connected in series to obtain defect feature vectors corresponding to defect boundary areas in each polar coordinate system;

[0026] Each of the defect feature vectors is input into a pre-trained SVM classifier for defect classification and positioning, so as to obtain a defect type and a defect position corresponding to the defect type; wherein the defect type includes cracks, bubbles and scratches.

[0027] Furthermore, the electrostatic electric field distribution corresponding to the defect position is simulated and tested by a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram, including:

[0028] Setting boundary conditions for the defect boundary region of the defect position on the three-dimensional packaging model to obtain a three-dimensional packaging model with boundary conditions; wherein the three-dimensional packaging model with boundary conditions has charge distribution, grounding conditions and insulation conditions;

[0029] The electric potential distribution of the three-dimensional packaging model with boundary conditions is calculated by solving the Poisson equation to obtain an electric potential distribution diagram of the defect position;

[0030] By using preset electrostatic field simulation software, the electrostatic electric field distribution corresponding to the defect position is solved based on the potential distribution diagram to obtain a preliminary distribution diagram of the electric field intensity at the defect position;

[0031] Performing boundary condition constraint processing on the preliminary distribution map of electric field strength to obtain a boundary constraint distribution map of electric field strength at the defect position;

[0032] Performing a thermal-electric coupling effect simulation on the electric field strength boundary constraint distribution diagram to obtain an electric field strength-thermal effect distribution diagram at the defect position;

[0033] The electric field strength-thermal effect distribution diagram is dynamically simulated to obtain an electric field strength distribution diagram; wherein the electric field strength distribution diagram is an electric field strength distribution diagram of the electric field strength at the defect position changing with time and heat.

[0034] Further, the navigation chip is evaluated for its performance impact based on the electric field strength distribution diagram to obtain a performance impact evaluation level of the navigation chip, including:

[0035] Based on the electric field strength distribution diagram, the impact characteristics of the internal components of the navigation chip are extracted to obtain the corresponding impact characteristic vector; wherein the impact characteristic vector includes the noise gain vector of the processing unit in the navigation chip, the frequency offset vector of the clock circuit, the bit error rate vector of the digital logic circuit and the voltage fluctuation amplitude vector of the power management unit;

[0036] Performing compatibility simulation analysis on the navigation chip based on the impact feature vector to obtain an impact assessment report;

[0037] quantifying the performance degradation risk of the navigation chip based on the impact assessment report to obtain a performance degradation risk assessment value;

[0038] Performing uncertainty analysis on the performance degradation risk assessment value to obtain a probability distribution diagram of the performance assessment level of the navigation chip;

[0039] The evaluation level corresponding to the maximum probability in the probability distribution diagram is used as the performance evaluation level of the navigation chip.

[0040] Furthermore, formulating an electrostatic protection design scheme based on the electric field strength distribution diagram of the defect position and the defect type includes:

[0041] Analyzing the navigation chip material at the defect position based on the electric field strength distribution diagram to obtain navigation chip material performance parameters; wherein the navigation chip material performance parameters include the dielectric constant of the navigation chip material and the conductivity of the navigation chip;

[0042] Based on the navigation chip material performance parameters and the defect type, the electrostatic sensitivity of the defect boundary area is evaluated to obtain an electrostatic sensitivity index, wherein the electrostatic sensitivity index includes a charge accumulation rate, a discharge threshold, and a voltage tolerance;

[0043] By using a topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the electrostatic sensitivity index to obtain an initial shielding structure scheme; wherein the initial shielding structure scheme includes material distribution, geometric shape and thickness gradient;

[0044] Based on the initial shielding structure scheme, an electric field simulation is performed on the defect boundary area of ​​the defect position to obtain an electric field simulation effect; wherein the electric field simulation effect includes an electric field intensity attenuation rate, an electric field suppression degree, and an electric field interference level;

[0045] If the level of the electric field simulation effect is less than a preset electric field simulation effect level, performing defect analysis on the electric field simulation effect to obtain a defect analysis result;

[0046] Based on the defect analysis results, the initial shielding structure scheme is optimized by multiple objectives to obtain an electrostatic protection scheme.

[0047] Furthermore, an electrostatic shielding structure is designed for the defect position based on the electrostatic sensitivity index by using a topology optimization algorithm to obtain an initial shielding structure solution, including:

[0048] Determining a sensitive area of ​​the defect location based on the electrostatic sensitivity index;

[0049] By using a preset topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the sensitive area to obtain a plurality of candidate shielding structure solutions;

[0050] A Pareto optimization analysis is performed on each of the candidate shielding structure solutions to obtain an initial shielding structure solution.

[0051] The present invention also provides an electrostatic test system for navigation chip packaging, which is applied to a navigation chip packaging device, wherein a navigation chip is arranged in the navigation chip packaging device, and comprises:

[0052] A scanning module, used to scan the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip;

[0053] an identification module, used to identify whether there is defect information in the three-dimensional packaging model; if so, a preset defect identification algorithm is used to identify and locate the defect type of the three-dimensional packaging model based on the defect information to obtain the defect type and the defect position corresponding to the defect type;

[0054] A testing module, used to perform a simulation test on the electrostatic electric field distribution corresponding to the defect position through a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram;

[0055] An evaluation module, configured to evaluate the degree of impact on the performance of the navigation chip based on the electric field strength distribution diagram, and obtain a performance impact evaluation level of the navigation chip;

[0056] A formulation module is used to formulate an electrostatic protection design plan based on the electric field strength distribution diagram of the defect position and the defect type if the performance impact assessment level exceeds a preset level threshold.

[0057] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0058] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0059] The electrostatic testing method for navigation chip packaging provided by the present invention comprises the following steps: performing a surface morphology scan on the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip; identifying whether there is defect information in the three-dimensional packaging model, and if so, using a preset defect recognition algorithm, based on the defect information, performing defect type identification and positioning on the three-dimensional packaging model to obtain the defect type and the defect position corresponding to the defect type; performing a simulation test on the electrostatic electric field distribution corresponding to the defect position through a preset electrostatic field simulation software to obtain an electric field strength distribution map; based on the electric field strength distribution map, evaluating the degree of impact on the navigation chip to obtain a performance impact evaluation level of the navigation chip; if the performance impact evaluation level exceeds a preset level threshold, formulating an electrostatic protection design scheme based on the electric field strength distribution map of the defect position and the defect type. Through the above-mentioned technical means, the technical problem that the electrostatic discharge phenomenon affects the chip performance and life during the packaging process of the navigation chip is solved, and it is achieved that an electrostatic protection scheme can be designed in a targeted manner based on the electric field strength distribution map and defect type information. Compared with traditional empirical methods, this design method based on actual test data can more effectively reduce the impact of electrostatic discharge on navigation chips, improve product stability and reliability, and evaluate the performance impact of navigation chips through electric field strength distribution diagrams. It can quantify the impact of different defects on chip performance, provide a scientific basis for product designers, help them make more reasonable design decisions, and avoid technical effects such as product performance degradation or failure due to electrostatic problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a schematic diagram of the steps of an electrostatic testing method for navigation chip packaging in one embodiment of the present invention;

[0061] Figure 2 is a structural block diagram of an electrostatic testing device for navigation chip packaging in one embodiment of the present invention;

[0062] Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0063] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0065] like Figure 1 As shown, Figure 1 It is a schematic diagram of the steps of an electrostatic testing method for a navigation chip package in one embodiment of the present invention;

[0066] In one embodiment of the present invention, a method for electrostatic testing of a navigation chip package is provided, which is applied to a navigation chip packaging device, wherein a navigation chip is disposed in the navigation chip packaging device, and comprises the following steps:

[0067] Step S1, performing a surface topography scan on the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip.

[0068] Specifically, the step of scanning the surface morphology of the navigation chip packaging device to obtain the three-dimensional packaging model of the navigation chip is the basis of the entire electrostatic testing method, which involves the use of high-precision scanning technology to obtain detailed surface information of the navigation chip packaging device. Specifically, the external morphology of the navigation chip packaging device can be comprehensively and carefully scanned by using advanced scanning equipment such as optical microscopes, laser scanning confocal microscopes or three-dimensional scanning electron microscopes. These devices can provide submicron or even nanometer resolution to ensure that complete information of the packaging surface and its fine structure can be captured. During the scanning process, the device scans the packaging device from multiple angles to collect enough data to reconstruct a complete three-dimensional model. For example, in the quality control link of the navigation chip packaging, technicians can use a laser scanning confocal microscope to perform non-contact surface morphology scanning on the packaged chip. This will not only not cause any damage to the chip, but also obtain very detailed surface feature information, including but not limited to the shape and size of each part such as solder joints, lead frames, and plastic packaging materials. This information is crucial for subsequent steps such as defect identification, electric field distribution simulation, and performance impact assessment, because they are directly related to whether the defects that may exist in the packaging process can be accurately determined, and how these defects may affect the electrostatic sensitivity of the chip. The three-dimensional packaging model obtained in this way lays a solid foundation for the entire electrostatic testing process and ensures the accuracy and effectiveness of subsequent steps.

[0069] Step S2, identifying whether there is defect information in the three-dimensional packaging model. If so, a preset defect recognition algorithm is used to identify and locate the defect type of the three-dimensional packaging model based on the defect information to obtain the defect type and the defect position corresponding to the defect type.

[0070] Specifically, after completing the surface morphology scanning of the navigation chip packaging device and obtaining the three-dimensional packaging model, the next step is to conduct an in-depth analysis of the three-dimensional model to identify whether it contains defect information. This process first requires the use of preset defect recognition algorithms, which are usually developed based on image processing and machine learning technologies and can automatically detect various anomalies that may exist in the three-dimensional model. When the algorithm detects suspected defect areas in the model, it will further analyze the characteristics of these areas, such as shape, size, position, etc., to determine whether they actually constitute defects. Once the existence of defects is confirmed, the algorithm will continue to work and identify and locate the defect type of the three-dimensional packaging model based on the defect information, that is, to clarify the specific type of defects (such as cracks, bubbles, impurities, etc.) and the exact location of these defects in the model. For example, in the packaging process of the navigation chip, problems such as internal bubbles or cracks caused by uneven materials or improper processes may occur. When technicians use the above method to inspect the packaged chip, the preset defect recognition algorithm can effectively identify these potential problems from the three-dimensional packaging model. The algorithm can not only point out the location of the defect, but also describe the nature of the defect in detail, such as the diameter of the bubble, the length and direction of the crack, etc. Such information is crucial for evaluating the impact of defects on chip performance, and also provides an important reference for subsequent electrostatic protection design. Through this precise defect identification and positioning, it can ensure that the navigation chip has higher stability and reliability when facing electrostatic discharge, thereby ensuring its normal operation in various application scenarios.

[0071] Step S3, using a preset electrostatic field simulation software to perform a simulation test on the electrostatic electric field distribution corresponding to the defect position to obtain an electric field intensity distribution diagram.

[0072] Specifically, after completing the identification and positioning of the defect type of the navigation chip packaging device, the next step is to simulate the electrostatic electric field distribution corresponding to the defect position through the preset electrostatic field simulation software to obtain the electric field strength distribution map. This process is based on the three-dimensional packaging model obtained in the previous step and the identified defect information. Electrostatic field simulation software usually has powerful computing power and accurate physical models, which can simulate the behavior of the electrostatic field in the real environment, especially in the presence of defects, the change of the electric field distribution is more complicated. The software will calculate the accumulation of static charges in these specific areas according to the location, type and electrical properties of the surrounding materials of the defect, and then generate a detailed electric field strength distribution map. For example, in the process of navigation chip packaging, if the initial detection finds tiny cracks or bubbles inside the packaging material, these defects may become hot spots for static charge accumulation. At this time, the technician can use the electrostatic field simulation software to input the three-dimensional packaging model containing these defect information, and the software will perform simulation tests based on these data. During the test, the software will consider different factors such as static charge amount and environmental humidity, simulate the electric field distribution under different conditions, and finally output one or more electric field strength distribution maps. These distribution maps can intuitively show which areas have higher electric field strength and which areas may be at risk of electrostatic discharge. In this way, R&D personnel can more accurately evaluate the impact of static electricity on chip performance and provide a scientific basis for subsequent electrostatic protection design. For example, during the design stage, the chip layout can be adjusted according to the electric field strength distribution map, the thickness of the protective layer can be increased, or a more suitable packaging material can be selected to reduce the risk of electrostatic discharge and improve the overall reliability and performance of the navigation chip.

[0073] Step S4: evaluating the degree of impact on the performance of the navigation chip based on the electric field strength distribution diagram to obtain a performance impact evaluation level of the navigation chip.

[0074] Specifically, the navigation chip is evaluated for the degree of impact on performance based on the electric field strength distribution map to obtain the performance impact evaluation level of the navigation chip, which is one of the key steps in the electrostatic testing method. In the previous step, the electric field strength distribution map has been obtained through the preset electrostatic field simulation software, which clearly shows the electric field strength of each area inside the packaging device. Next, we need to use these data to evaluate the specific impact of static electricity on the performance of the navigation chip. This evaluation process usually involves comparing and analyzing the electric field strength distribution map with the known electric field-performance impact relationship. The electric field-performance impact relationship is an empirical model established based on a large amount of experimental data, which can reveal the different effects of electric fields of different intensities on chip performance, such as signal transmission delay, increased power consumption, and even permanent damage. For example, in the application scenario of the navigation chip, suppose we find that the electric field strength in a certain area on the electric field strength distribution map is abnormally high, and the area happens to be close to the key circuit part of the chip, such as a signal processor or a storage unit. In this case, we can evaluate the impact of the high electric field strength in the area on the chip performance based on the pre-established electric field-performance impact relationship model. If the evaluation results show that the electric field strength in this area exceeds the safe range that the chip can withstand, it may cause signal transmission delays or significantly increase power consumption, then the performance impact assessment level of the chip will be set at a higher level. On the contrary, if the electric field strength is within the safe range, the assessment level will be set at a lower level. Through this performance impact assessment based on the electric field strength distribution map, R&D personnel can more scientifically judge the actual impact of packaging defects on chip performance, providing an important basis for subsequent electrostatic protection design. For example, if it is found during the evaluation process that the performance impact assessment level of a batch of chips is generally high, this may mean that there are certain common defects in the production process, and it is necessary to adjust the production process or improve the material selection in time to improve the overall reliability and stability of the chip. This evaluation method not only helps to improve the quality of individual chips, but also provides strong support for the optimization of the entire production process.

[0075] Step S5: If the performance impact assessment level exceeds a preset level threshold, an electrostatic protection design plan is formulated based on the electric field strength distribution diagram of the defect position and the defect type.

[0076] Specifically, if the performance impact assessment level exceeds the preset level threshold, an electrostatic protection design scheme is formulated based on the electric field strength distribution map of the defect position and the defect type, which is an important part of the entire electrostatic testing method. In the previous steps, the performance impact of the navigation chip has been evaluated through the electric field strength distribution map, and the performance impact assessment level has been obtained. If the evaluation results show that the electric field strength in certain areas is too high, resulting in chip performance being affected, and this impact exceeds the preset safety threshold, then corresponding electrostatic protection measures need to be taken. Specifically, the process of formulating an electrostatic protection design scheme first requires a careful analysis of the electric field strength distribution map and the defect type. For example, suppose that a large bubble is found in the navigation chip package, and the electric field strength distribution map shows that the electric field strength around the bubble is very high. In this case, we need to comprehensively consider the location and size of the bubble and its specific impact on the electric field distribution. Based on this information, a targeted electrostatic protection scheme can be formulated. Common electrostatic protection measures include but are not limited to: 1. Improve packaging materials: Select packaging materials with higher electrostatic protection performance to reduce the accumulation of static charges. For example, you can choose a plastic packaging material with better conductivity, or add conductive fillers in key areas to disperse the electric field strength. 2. Optimize chip layout: Redesign the circuit layout inside the chip to avoid the key circuit parts being close to the area with high electric field strength. For example, key components such as signal processors or storage units can be placed away from bubbles to reduce the impact of static electricity on these components. 3. Add shielding layer: Add a metal shielding layer to a specific area of ​​the chip package to block the interference of the external electrostatic field. For example, adding a layer of metal shielding around the bubble can effectively reduce the electric field strength in the area and protect the chip from electrostatic damage. 4. Improve production process: Adjust the packaging process parameters to reduce the generation of defects such as bubbles and cracks. For example, the density of the packaging material can be improved and internal defects can be reduced by optimizing parameters such as injection pressure, temperature and time. Through the above measures, the impact of static electricity on the performance of the navigation chip can be effectively reduced, and the reliability and stability of the chip can be improved. For example, in the application scenario of the navigation chip, if it is found through evaluation that a batch of chips has a problem of high electric field strength in a specific area, the above electrostatic protection measures can be taken immediately to ensure that these chips can work normally in actual use and are not affected by electrostatic discharge. This electrostatic protection design based on defect location and electric field strength distribution map can not only solve current problems, but also provide valuable experience and reference for future product design.

[0077] In a specific embodiment, the surface topography scanning of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip includes:

[0078] Scanning the surface of the navigation chip packaging device at multiple angles using a preset non-contact three-dimensional scanner to obtain two-dimensional images at multiple viewing angles;

[0079] Performing coordinate point registration and fusion on the two-dimensional image to obtain preliminary three-dimensional point cloud data;

[0080] Smoothing the preliminary three-dimensional point cloud data to obtain smoothed three-dimensional point cloud data;

[0081] Performing grid processing on the smoothed three-dimensional point cloud data to obtain a preliminary three-dimensional grid model;

[0082] The three-dimensional mesh model is enhanced in detail to obtain a three-dimensional packaging model of the navigation chip.

[0083] Specifically, scanning the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip is a basic step in the entire electrostatic testing method. This process involves multiple key technical links to ensure that the final three-dimensional packaging model can accurately reflect the actual situation of chip packaging. Specifically, first, the surface of the navigation chip packaging device is scanned at multiple angles by a preset non-contact three-dimensional scanner to obtain two-dimensional images under multiple viewing angles. In this process, the non-contact three-dimensional scanner is a high-precision measuring device that can quickly obtain detailed information on its surface without contacting the sample. For example, devices such as laser scanning confocal microscopes or structured light three-dimensional scanners can be used, which can scan the navigation chip packaging device from multiple angles to generate a series of high-resolution two-dimensional images. These images not only contain the macroscopic morphology of the packaging surface, but also capture subtle surface features such as the shape and texture of solder joints, lead frames, and plastic packaging materials. Through multi-angle scanning, it can be ensured that the surface of the packaging device is fully covered from different viewing angles, providing rich data support for subsequent three-dimensional reconstruction. Next, the two-dimensional image is aligned and fused with coordinate points to obtain preliminary three-dimensional point cloud data. This process involves image processing and computer vision technology, the purpose of which is to align two-dimensional images from different perspectives to generate a unified three-dimensional point cloud model. Specifically, feature point matching algorithms such as SIFT (Scale Invariant Feature Transform) or SURF (Speeded Up Robust Features) can be used to find the same feature points in images from different perspectives and calculate the coordinates of these feature points in three-dimensional space. Then, using the principle of multi-view geometry, these coordinate points are registered and fused to generate preliminary three-dimensional point cloud data. Although this preliminary three-dimensional point cloud data contains the basic form of the packaging device, there may be some noise and irregular points that need further processing. In order to improve the quality of the three-dimensional point cloud data, the preliminary three-dimensional point cloud data is then smoothed to obtain smooth three-dimensional point cloud data. The purpose of smoothing is to remove noise and irregular points in the point cloud and make the point cloud data smoother and continuous. Commonly used smoothing algorithms include moving least squares (MLS), Gaussian filters, etc. Through these algorithms, the noise in the point cloud can be effectively reduced and the density and uniformity of the point cloud can be improved. For example, the MLS algorithm can be used to process preliminary three-dimensional point cloud data by fitting a local plane in the neighborhood of each point and projecting the points onto the plane to achieve a smoothing effect. The smoothed three-dimensional point cloud data more accurately reflects the surface morphology of the packaging device, laying the foundation for subsequent meshing processing. After smoothing, the smoothed three-dimensional point cloud data is meshed to obtain a preliminary three-dimensional mesh model. The purpose of meshing is to convert point cloud data into a three-dimensional mesh model composed of triangles or polygons to facilitate subsequent visualization and analysis. Commonly used meshing algorithms include Delaunay triangulation, Poisson reconstruction, etc.The Delaunay triangulation algorithm ensures that the topological structure of the mesh is reasonable by generating triangles that maximize the minimum angle in the point cloud data. The Poisson reconstruction algorithm generates a smooth surface mesh by solving the Poisson equation. These two algorithms have their own advantages, and the appropriate algorithm can be selected according to actual needs. For example, the Poisson reconstruction algorithm can be used to mesh the smooth three-dimensional point cloud data to generate a smooth and continuous three-dimensional mesh model that can accurately reflect the surface characteristics of the packaging device. Finally, the three-dimensional mesh model is enhanced in detail to obtain a three-dimensional packaging model of the navigation chip. The purpose of detail enhancement is to retain and enhance the detailed features of the surface of the packaging device while ensuring the overall smoothness of the model. This step is particularly important for subsequent defect identification and electrostatic field simulation tests, because subtle surface features may have a significant impact on the electric field distribution. Commonly used detail enhancement algorithms include Laplacian smoothing, bilateral filtering, etc. The Laplacian smoothing algorithm achieves detail enhancement by calculating the average position of its neighboring vertices at each vertex, and then moving the vertex a certain distance to the average position. The bilateral filtering algorithm retains edge information while smoothing, which is suitable for enhancing the detailed features of the surface. For example, a bilateral filtering algorithm can be used to enhance the details of the preliminary three-dimensional mesh model to generate a three-dimensional packaging model that is both smooth and retains details. Through the above steps, we can obtain a high-quality three-dimensional packaging model of the navigation chip, which not only accurately reflects the surface morphology of the packaged device, but also retains subtle surface features. For example, in the quality control link of the navigation chip packaging, technicians can use the above method to scan the surface morphology of the packaged chip and generate a three-dimensional packaging model. This model can be used for subsequent defect identification, electric field simulation testing, and performance evaluation steps to ensure that the chip has higher stability and reliability when facing electrostatic discharge phenomena. Through this systematic scanning and modeling method, the quality control level of the navigation chip can be significantly improved, providing a strong guarantee for the reliability and performance of the product.

[0084] In a specific embodiment, the method of identifying and locating the defect type of the three-dimensional packaging model based on the defect information by using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type includes:

[0085] Extracting defect features from the three-dimensional packaging model using a preset defect recognition algorithm to obtain a multi-scale defect feature map;

[0086] Performing preliminary defect recognition on the multi-scale defect feature map through the attention mechanism in the defect recognition algorithm to obtain a preliminary defect candidate region; wherein the preliminary defect candidate region has at least one;

[0087] Performing defect morphology processing on the preliminary defect candidate area to obtain a defect boundary area;

[0088] Selecting a corresponding key defect point in each of the defect boundary regions, and establishing a corresponding polar coordinate system with the key defect point corresponding to each of the defect boundary regions as the center;

[0089] Dividing the space of the polar coordinate system into a plurality of discrete cells, and counting the corresponding numbers of key defect points of the plurality of discrete cells to obtain a statistical result of the key defect points;

[0090] Establishing a local shape context histogram based on the statistical results;

[0091] All the local shape context histograms are connected in series to obtain defect feature vectors corresponding to defect boundary areas in each polar coordinate system;

[0092] Each of the defect feature vectors is input into a pre-trained SVM classifier for defect classification and positioning, so as to obtain a defect type and a defect position corresponding to the defect type; wherein the defect type includes cracks, bubbles and scratches.

[0093] Specifically, the method of identifying and locating the defect type of the three-dimensional packaging model based on the defect information by using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type is one of the core steps in the entire electrostatic testing method. This process involves multiple complex image processing and machine learning technologies to ensure that defects in the packaging model can be accurately identified and located. Specifically, this step includes extracting defect features from the three-dimensional packaging model through a preset defect recognition algorithm to obtain a multi-scale defect feature map; performing preliminary defect recognition on the multi-scale defect feature map through the attention mechanism in the defect recognition algorithm to obtain a preliminary defect candidate area; performing defect morphological processing on the preliminary defect candidate area to obtain a defect boundary area; selecting corresponding key defect points in each of the defect boundary areas, and establishing a corresponding polar coordinate system with the key defect points corresponding to each of the defect boundary areas as the center; dividing the space of the polar coordinate system into a number of discrete cells, and counting the corresponding number of key defect points of a number of the discrete cells to obtain the statistical results of the key defect points; establishing a local shape context histogram based on the statistical results; connecting all the local shape context histograms in series to obtain the defect feature vectors corresponding to the defect boundary area of ​​each polar coordinate system; inputting each of the defect feature vectors into a pre-trained SVM classifier for defect classification and positioning, and obtaining the defect type and the defect position corresponding to the defect type. First, the defect features of the three-dimensional packaging model are extracted through a preset defect recognition algorithm to obtain a multi-scale defect feature map. This process usually involves deep learning techniques such as convolutional neural networks (CNNs) to extract features at different scales through multi-layer convolution operations. For example, a pre-trained CNN model such as ResNet or VGG can be used to perform multi-level feature extraction on a three-dimensional package model. These feature maps not only contain macroscopic features of the package surface, but also capture subtle defect information such as cracks, bubbles, and scratches. Multi-scale feature extraction ensures that the algorithm can identify defects of different sizes and types. Next, the multi-scale defect feature map is used to perform preliminary defect recognition through the attention mechanism within the defect recognition algorithm to obtain preliminary defect candidate regions. The attention mechanism is a technology that can automatically focus on important areas in an image and highlight potential defect areas through weight assignment. For example, a U-Net model with an attention mechanism can be used, which extracts features in the encoder part, restores the image resolution through upsampling in the decoder part, and applies the attention mechanism at each step to highlight possible defect areas. In this way, the algorithm is able to generate a series of preliminary defect candidate regions that may contain defects such as cracks, bubbles, or scratches. The preliminary defect candidate regions are subjected to defect morphological processing to obtain defect boundary regions.Morphological processing is an image processing technology based on set theory. It removes noise and extracts the boundaries of defects through operations such as expansion, corrosion, opening and closing operations. For example, morphological opening operations can be used to first remove small noise points, and then closing operations can be used to fill the holes in the defect area to obtain a clear defect boundary. Through these operations, the boundaries of the preliminary defect candidate area can be ensured to be more accurate and continuous, providing a reliable basis for subsequent feature extraction and classification. Select corresponding key defect points in each of the defect boundary areas, and establish a corresponding polar coordinate system with the key defect points corresponding to each of the defect boundary areas as the center. The selection of key defect points is usually based on feature point detection algorithms, such as Harris corner point detection or SIFT feature point detection. These algorithms can identify key points on the defect boundary, which usually have high gradient changes or unique local features. For example, the Harris corner point detection algorithm can be used to select several key points in each defect boundary area, and then a polar coordinate system is established with these key points as the center. The establishment of the polar coordinate system is helpful for subsequent feature extraction and statistical analysis because it can better describe the local shape and structure of the defect. The space of the polar coordinate system is divided into several discrete cells, and the corresponding numbers of key defect points of several discrete cells are counted to obtain the statistical results of key defect points. This process involves space division and statistical analysis, and the purpose is to generate a feature vector describing the local shape of the defect. For example, the space of the polar coordinate system can be divided into 36 discrete cells, each cell corresponding to an angle range. Then, the number of key defect points in each cell is counted to generate a 36-dimensional statistical vector. This vector can describe the distribution of defects in different directions and provide a basis for subsequent feature extraction. A local shape context histogram is established based on the statistical results. The local shape context histogram is a method for describing the local shape features of an image. By counting the distribution of key points in different directions, a feature vector describing the shape of the defect is generated. For example, the above 36-dimensional statistical vector can be further processed to generate a local shape context histogram. This histogram not only describes the distribution of defects in different directions, but also reflects the shape and structural characteristics of the defects. All the local shape context histograms are connected in series to obtain the defect feature vectors corresponding to the defect boundary area of ​​each polar coordinate system. This process involves the splicing of feature vectors, and the purpose is to generate a complete feature representation for subsequent classification and positioning. For example, the local shape context histograms of each defect boundary area can be connected in series to generate a high-dimensional feature vector. This feature vector can fully describe the shape and structural characteristics of the defect and provide rich input information for the classifier. Each of the defect feature vectors is input into a pre-trained SVM classifier for defect classification and location to obtain the defect type and the defect location corresponding to the defect type.SVM (Support Vector Machine) is a commonly used supervised learning algorithm that achieves efficient classification of different categories by maximizing the classification interval. In the training stage, the SVM classifier can be trained using labeled defect samples to enable it to distinguish different defect types, such as cracks, bubbles, and scratches. In the testing stage, the extracted defect feature vector is input into the trained SVM classifier, and the classifier will output the type of each defect and its corresponding defect location. For example, assuming that some potential defect areas are found in the navigation chip package, through the above feature extraction and classification process, the SVM classifier can accurately identify the types of these defects (cracks, bubbles or scratches) and their specific locations. Through the above steps, we can realize the defect type identification and positioning of the navigation chip packaging model, ensuring that various defects in the package can be accurately identified and located. For example, in the quality control link of the navigation chip package, technicians can use the above method to perform defect detection on the packaged chip and generate a three-dimensional packaging model. Through the defect recognition algorithm, defects such as cracks, bubbles and scratches in the package can be accurately identified, and the specific locations of these defects can be determined. This precise defect identification and location method not only helps improve the quality control level of the chip, but also provides an important reference for the subsequent electrostatic protection design, ensuring that the chip has higher stability and reliability in practical applications. Through this systematic defect identification and location method, the production quality and performance of the navigation chip can be significantly improved, providing a strong guarantee for the reliability and performance of the product.

[0094] In a specific embodiment, the electrostatic electric field distribution corresponding to the defect position is simulated and tested by a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram, including:

[0095] Setting boundary conditions for the defect boundary region of the defect position on the three-dimensional packaging model to obtain a three-dimensional packaging model with boundary conditions; wherein the three-dimensional packaging model with boundary conditions has charge distribution, grounding conditions and insulation conditions;

[0096] The electric potential distribution of the three-dimensional packaging model with boundary conditions is calculated by solving the Poisson equation to obtain an electric potential distribution diagram of the defect position;

[0097] By using preset electrostatic field simulation software, the electrostatic electric field distribution corresponding to the defect position is solved based on the potential distribution diagram to obtain a preliminary distribution diagram of the electric field intensity at the defect position;

[0098] Performing boundary condition constraint processing on the preliminary distribution map of electric field strength to obtain a boundary constraint distribution map of electric field strength at the defect position;

[0099] Performing a thermal-electric coupling effect simulation on the electric field strength boundary constraint distribution diagram to obtain an electric field strength-thermal effect distribution diagram at the defect position;

[0100] The electric field strength-thermal effect distribution diagram is dynamically simulated to obtain an electric field strength distribution diagram; wherein the electric field strength distribution diagram is an electric field strength distribution diagram of the electric field strength at the defect position changing with time and heat.

[0101] Specifically, the process of simulating the electrostatic electric field distribution corresponding to the defect position by the preset electrostatic field simulation software to obtain the electric field strength distribution map is a key step after completing the defect type identification and positioning of the navigation chip packaging model. This process is intended to evaluate the impact of defects on the electrostatic field distribution inside the package to ensure the reliability and safety of the packaging design. Specifically, before starting the simulation test, it is first necessary to set the boundary conditions of the defect boundary area of ​​the defect position on the three-dimensional packaging model, in order to ensure that the simulation environment is as close as possible to the actual situation. In this process, factors such as charge distribution, grounding conditions and insulation conditions in the packaging model need to be considered. For example, in the navigation chip package, there may be some defects, such as cracks, bubbles or scratches, the positions and shapes of these defects have been determined by the previous defect recognition algorithm. For these defects, it is necessary to set the corresponding boundary conditions in the three-dimensional packaging model. For example, if a crack is located in a part of the chip, it is necessary to set the charge density, grounding state and insulation properties of this part of the area to facilitate the subsequent potential distribution calculation. In this way, a three-dimensional packaging model with boundary conditions that matches the actual packaging conditions can be constructed. Once the boundary conditions are set, it is necessary to calculate the potential distribution of the three-dimensional package model with boundary conditions by solving the Poisson equation to obtain the potential distribution map of the defect position. The Poisson equation is a basic equation in electrostatics, which describes the relationship between charge distribution and potential. In this step, the Poisson equation can be solved by the finite element method (FEM) or other numerical solution techniques. For example, using professional electrostatic field simulation software such as ANSYS and COMSOL, the three-dimensional package model with boundary conditions can be imported into the software, and the potential distribution in the entire package model can be calculated by setting appropriate meshing and solution parameters. In particular, for those defective locations that have been identified, the software will focus on calculating the potential changes in these areas to generate a detailed potential distribution map. With the potential distribution map, the next step is to solve the electrostatic electric field distribution corresponding to the defective location based on the potential distribution map through the preset electrostatic field simulation software to obtain a preliminary distribution map of the electric field strength at the defective location. This step is completed based on the relationship between the electric field strength and the potential gradient, that is, the electric field strength is equal to the negative value of the potential gradient. In actual operation, the built-in functions of the electrostatic field simulation software can be used to directly extract the electric field strength information from the potential distribution diagram. For example, in the application scenario of navigation chip packaging, the electric field strength distribution around defects such as cracks, bubbles or scratches can be observed. The electric field strength in these areas may change significantly due to the presence of defects. The preliminary electric field strength distribution diagram can intuitively show these changes and provide a basis for further analysis.However, since the preliminary electric field strength distribution map has not yet taken into account the influence of the actual boundary conditions, it is necessary to perform boundary condition constraint processing on the preliminary electric field strength distribution map to obtain the electric field strength boundary constraint distribution map at the defect location. Boundary condition constraint processing refers to reapplying the previously set boundary conditions on the basis of the preliminary electric field strength distribution to ensure that the simulation results are consistent with the actual situation. For example, if a certain area is set to be grounded, the electric field strength in the area should be zero; if a certain area is set to be insulated, the electric field strength distribution inside it should not be affected by the external electric field. In this way, the unreasonableness in the preliminary electric field strength distribution map can be corrected to make the final result more accurate. On this basis, it is also necessary to simulate the thermal-electric coupling effect of the electric field strength boundary constraint distribution map to obtain the electric field strength-thermal effect distribution map at the defect location. The thermal-electric coupling effect refers to the fact that heat is generated inside the material under the action of the electric field, and this heat will affect the distribution of the electric field. In navigation chip packaging, this coupling effect is particularly important because there is a close relationship between the thermal conductivity and electrical conductivity of the packaging material. Through the simulation of thermal-electric coupling effect, the change of electric field intensity at the defect location can be predicted more accurately. For example, around cracks or bubbles, the change of material properties may cause local temperature rise, which in turn affects the distribution of the electric field. Through the coupling effect simulation, the change trend of the electric field intensity in these areas can be observed, providing a basis for subsequent dynamic simulation. Finally, the electric field intensity-thermal effect distribution diagram is dynamically simulated to obtain an electric field intensity distribution diagram; wherein the electric field intensity distribution diagram is an electric field intensity distribution diagram of the electric field intensity at the defect location with time and heat. Dynamic simulation refers to the continuous monitoring of the change of electric field intensity within a certain time range to understand the long-term impact of defects on the electric field distribution inside the package. For example, a reasonable simulation time range can be set, such as from 0 seconds to 100 seconds, and the change of electric field intensity is recorded every 1 second. In this way, a complete distribution diagram of the electric field intensity with time and heat can be obtained. This is crucial for evaluating the impact of defects on package performance, especially in the case of long-term operation, so that possible problems can be predicted and corresponding preventive measures can be taken. In summary, by simulating the electrostatic electric field distribution at the defect position in the navigation chip packaging model, the impact of defects on packaging performance can be comprehensively evaluated, providing a scientific basis for optimizing packaging design and improving product quality. For example, in the actual navigation chip packaging process, technicians can use the above method to perform detailed electrostatic field simulation tests on the chip before and after packaging. By comparing the test results, problems that may occur in the packaging process, such as cracks, bubbles and other defects, can be discovered in a timely manner, and effective measures can be taken to solve them. In addition, through dynamic simulation, the performance changes of the package under long-term operation can also be predicted, providing a strong guarantee for the reliability and stability of the product.This systematic electrostatic field simulation test method not only helps to improve the production quality of navigation chips, but also provides important technical support for subsequent design optimization and fault diagnosis.

[0102] In a specific embodiment, the performance impact degree of the navigation chip is evaluated based on the electric field strength distribution diagram to obtain the performance impact evaluation level of the navigation chip, including:

[0103] Based on the electric field strength distribution diagram, the impact characteristics of the internal components of the navigation chip are extracted to obtain the corresponding impact characteristic vector; wherein the impact characteristic vector includes the noise gain vector of the processing unit in the navigation chip, the frequency offset vector of the clock circuit, the bit error rate vector of the digital logic circuit and the voltage fluctuation amplitude vector of the power management unit;

[0104] Performing compatibility simulation analysis on the navigation chip based on the impact feature vector to obtain an impact assessment report;

[0105] quantifying the performance degradation risk of the navigation chip based on the impact assessment report to obtain a performance degradation risk assessment value;

[0106] Performing uncertainty analysis on the performance degradation risk assessment value to obtain a probability distribution diagram of the performance assessment level of the navigation chip;

[0107] The evaluation level corresponding to the maximum probability in the probability distribution diagram is used as the performance evaluation level of the navigation chip.

[0108] Specifically, evaluating the degree of impact on the performance of the navigation chip based on the electric field strength distribution map and obtaining the performance impact evaluation level of the navigation chip is one of the key steps in the entire electrostatic testing method. This process aims to fully understand the impact of the electrostatic field on the internal components of the navigation chip through detailed simulation analysis and risk assessment, and ensure the reliability and performance of the chip in practical applications. Specifically, first, based on the electric field strength distribution map, the internal components of the navigation chip are subjected to impact feature extraction to obtain the corresponding impact feature vector. This process requires the use of data in the electric field strength distribution map, combined with the physical and electrical characteristics of each component inside the navigation chip, to extract the response characteristics of each component under the action of the electrostatic field. Specifically, simulation software (such as SPICE) can be used to simulate and analyze the processing unit, clock circuit, digital logic circuit and power management unit inside the navigation chip, respectively, and extract the following feature vectors: Noise gain vector of the processing unit: The noise gain generated by the processing unit under the action of the electrostatic field can reflect the impact of the electrostatic field on the signal processing performance. For example, an increase in noise gain may cause signal distortion and affect the calculation accuracy of the processing unit. Frequency offset vector of clock circuit: The frequency offset generated by clock circuit under the action of electrostatic field can reflect the influence of electrostatic field on clock synchronization. For example, frequency offset may cause timing error and affect the stable operation of the system. Bit error rate vector of digital logic circuit: The bit error rate generated by digital logic circuit under the action of electrostatic field can reflect the influence of electrostatic field on data transmission reliability. For example, the increase of bit error rate may cause data loss or error and affect the normal operation of the system. Voltage fluctuation amplitude vector of power management unit: The voltage fluctuation amplitude generated by power management unit under the action of electrostatic field can reflect the influence of electrostatic field on power supply stability. For example, voltage fluctuation may cause instability of circuit inside chip and affect overall performance. Through these characteristic vectors, the influence of electrostatic field on each component inside navigation chip can be fully described. Next, compatibility simulation analysis is performed on the navigation chip based on the influence characteristic vector to obtain the influence degree evaluation report. Compatibility simulation analysis refers to simulating the actual operation of navigation chip under the action of electrostatic field in simulation environment and evaluating the performance change of each component. For example, simulation tools such as MATLAB or Simulink can be used to input the extracted influence characteristic vector into the simulation model to simulate the performance of chip under different electrostatic field strengths. During the simulation process, the changes in parameters such as the noise gain of the processing unit, the frequency offset of the clock circuit, the bit error rate of the digital logic circuit, and the voltage fluctuation of the power management unit can be observed, and a detailed impact assessment report can be generated. Based on the impact assessment report, the performance degradation risk of the navigation chip is quantified to obtain a performance degradation risk assessment value. The quantification of performance degradation risk refers to converting the simulation results into specific numerical indicators for subsequent analysis and comparison.For example, a calculation formula for a performance degradation risk assessment value can be defined, which comprehensively considers the variation range of parameters such as noise gain, frequency offset, bit error rate and voltage fluctuation. Through this formula, the performance degradation risk assessment value under each simulation scenario can be calculated, thereby quantifying the degree of influence of the electrostatic field on the chip performance. The performance degradation risk assessment value is subjected to uncertainty analysis to obtain a probability distribution diagram of the performance assessment level of the navigation chip. Uncertainty analysis refers to considering uncertain factors in the simulation results, such as fluctuations in simulation parameters, model errors, etc., to evaluate the uncertainty of the performance degradation risk. For example, the Monte Carlo method can be used for multiple simulations, and some parameters are randomly changed during each simulation to generate multiple performance degradation risk assessment values. By statistically analyzing the distribution of these assessment values, a probability distribution diagram of the performance assessment level can be obtained. This probability distribution diagram can intuitively show the possibility of different assessment levels, helping decision makers to understand the performance risk of the chip more comprehensively. The assessment level corresponding to the maximum probability in the probability distribution diagram is used as the performance assessment level of the navigation chip. Finally, the performance assessment level of the navigation chip is determined according to the assessment level corresponding to the maximum probability in the probability distribution diagram. For example, if the probability distribution diagram shows that the probability of the performance evaluation level being "medium risk" is the highest, then "medium risk" can be used as the final performance evaluation level of the navigation chip. This evaluation method based on probability distribution can not only provide a clear evaluation result, but also reflect the credibility and uncertainty of the evaluation result. In summary, through the above steps, the impact of the electrostatic field on the performance of the navigation chip can be comprehensively evaluated to ensure the reliability and performance of the chip in practical applications. For example, in the quality control link of the navigation chip packaging, technicians can use the above method to conduct a detailed performance evaluation of the packaged chip. Through simulation analysis and risk quantification, potential problems such as excessive noise gain, severe frequency offset, increased bit error rate or obvious voltage fluctuation can be discovered in time, and corresponding protective measures can be taken. In addition, through uncertainty analysis and probability distribution diagrams, the performance risk of the chip can be evaluated more scientifically, providing important technical support for product design optimization and fault diagnosis. This systematic performance evaluation method not only helps to improve the production quality of navigation chips, but also provides a strong basis for subsequent electrostatic protection design to ensure the stability and reliability of the chip in various application scenarios.

[0109] In a specific embodiment, formulating an electrostatic protection design scheme based on the electric field strength distribution diagram of the defect position and the defect type includes:

[0110] Analyzing the navigation chip material at the defect position based on the electric field strength distribution diagram to obtain navigation chip material performance parameters; wherein the navigation chip material performance parameters include the dielectric constant of the navigation chip material and the conductivity of the navigation chip;

[0111] Based on the navigation chip material performance parameters and the defect type, the electrostatic sensitivity of the defect boundary area is evaluated to obtain an electrostatic sensitivity index, wherein the electrostatic sensitivity index includes a charge accumulation rate, a discharge threshold, and a voltage tolerance;

[0112] By using a topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the electrostatic sensitivity index to obtain an initial shielding structure scheme; wherein the initial shielding structure scheme includes material distribution, geometric shape and thickness gradient;

[0113] Based on the initial shielding structure scheme, an electric field simulation is performed on the defect boundary area of ​​the defect position to obtain an electric field simulation effect; wherein the electric field simulation effect includes an electric field intensity attenuation rate, an electric field suppression degree, and an electric field interference level;

[0114] If the level of the electric field simulation effect is less than a preset electric field simulation effect level, performing defect analysis on the electric field simulation effect to obtain a defect analysis result;

[0115] Based on the defect analysis results, the initial shielding structure scheme is optimized by multiple objectives to obtain an electrostatic protection scheme.

[0116] Specifically, formulating an electrostatic protection design scheme based on the electric field strength distribution diagram of the defect position and the defect type is one of the key steps in the entire electrostatic testing method. This process aims to ensure that the navigation chip has higher stability and reliability when facing electrostatic discharge phenomena through detailed material analysis, electrostatic sensitivity assessment, shielding structure design and electric field simulation. Specifically, this step includes analyzing the navigation chip material at the defect position based on the electric field strength distribution map to obtain the navigation chip material performance parameters; wherein the navigation chip material performance parameters include the dielectric constant of the navigation chip material and the conductivity of the navigation chip; based on the navigation chip material performance parameters and the defect type, the electrostatic sensitivity of the defect boundary area is evaluated to obtain an electrostatic sensitivity index, wherein the electrostatic sensitivity index includes charge accumulation rate, discharge threshold and voltage tolerance; through a topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the electrostatic sensitivity index to obtain an initial shielding structure scheme; wherein the initial shielding structure scheme includes material distribution, geometric shape and thickness gradient; based on the initial shielding structure scheme, an electric field simulation is performed on the defect boundary area of ​​the defect position to obtain an electric field simulation effect; wherein the electric field simulation effect includes an electric field strength attenuation rate, an electric field suppression degree and an electric field interference level; if the level of the electric field simulation effect is less than a preset electric field simulation effect level, a defect analysis is performed on the electric field simulation effect to obtain a defect analysis result; based on the defect analysis result, a multi-objective optimization is performed on the initial shielding structure scheme to obtain an electrostatic protection scheme. First, the navigation chip material at the defect position is analyzed based on the electric field strength distribution map to obtain the navigation chip material performance parameters. This process requires the use of the data in the electric field strength distribution map, combined with the physical and electrical properties of the navigation chip material, to extract the key material performance parameters. Specifically, the dielectric constant and conductivity of the navigation chip material can be determined through material testing and simulation analysis. The dielectric constant reflects the polarization ability of the material in the electric field, and the conductivity describes the ability of the material to conduct current. For example, in the navigation chip package, if it is found that the electric field strength in a certain area is high, it is necessary to conduct a detailed analysis of the material in the area to determine its dielectric constant and conductivity for subsequent electrostatic sensitivity evaluation. Next, the electrostatic sensitivity of the defect boundary area is evaluated based on the navigation chip material performance parameters and the defect type to obtain an electrostatic sensitivity index. The electrostatic sensitivity evaluation is to quantify the sensitivity of the defect area to the electrostatic field, thereby providing a basis for the design of the shielding structure. The electrostatic sensitivity index includes charge accumulation rate, discharge threshold and voltage tolerance. The charge accumulation rate reflects the speed at which a material accumulates charge in an electrostatic field, the discharge threshold describes the critical electric field strength at which a material discharges in an electrostatic field, and the voltage tolerance reflects the material's tolerance to high electric fields.For example, for a defective area containing a crack, the charge accumulation rate, discharge threshold and voltage tolerance of the area can be determined by simulation analysis, so as to obtain its electrostatic sensitivity index. Based on the electrostatic sensitivity index, the electrostatic shielding structure of the defective position is designed by a topology optimization algorithm to obtain an initial shielding structure scheme. The topology optimization algorithm is a method for optimizing material distribution and geometric shape, aiming to minimize material usage and cost while meeting performance requirements. Specifically, the optimal shielding structure can be designed using a topology optimization algorithm based on the electrostatic sensitivity index of the defective position. The initial shielding structure scheme includes material distribution, geometric shape and thickness gradient. For example, for a cracked area with high electrostatic sensitivity, a shielding layer with a specific material distribution and geometric shape can be designed by a topology optimization algorithm, which can provide effective electrostatic protection in key areas. Based on the initial shielding structure scheme, an electric field simulation is performed on the defect boundary area of ​​the defective position to obtain an electric field simulation effect. The electric field simulation is to verify the effectiveness of the initial shielding structure scheme and ensure that it can achieve the expected electrostatic protection effect. The electric field simulation effect includes the electric field intensity attenuation rate, the electric field suppression degree and the electric field interference level. The electric field strength attenuation rate reflects the degree of attenuation of the electric field strength by the shielding layer, the electric field suppression degree describes the suppression effect of the shielding layer on the electric field, and the electric field interference level reflects the interference degree of the shielding layer on other circuits. For example, the initial shielding structure scheme can be simulated by simulation software to evaluate its electric field strength attenuation rate, electric field suppression degree and electric field interference level under different conditions. If the level of the electric field simulation effect is less than the preset electric field simulation effect level, the electric field simulation effect is subjected to defect analysis to obtain defect analysis results. Defect analysis is to find out the reasons for the poor electric field simulation effect and optimize it. For example, if the electric field simulation results show that the electric field strength attenuation rate is lower than the preset standard, it is necessary to analyze the simulation results in detail to find out the reasons that may lead to insufficient attenuation rate, such as unreasonable material distribution, improper geometric shape design, etc. Based on the defect analysis results, the initial shielding structure scheme is optimized by multi-objective optimization to obtain an electrostatic protection scheme. Multi-objective optimization refers to optimizing the shielding structure scheme under the premise of meeting multiple performance indicators. Specifically, the material distribution, geometric shape and thickness gradient can be adjusted according to the defect analysis results to improve the electric field simulation effect. For example, a multi-objective optimization algorithm can be used to simultaneously optimize the electric field strength attenuation rate, electric field suppression degree, and electric field interference level to ensure that the shielding structure solution can achieve the best results in all aspects. Ultimately, the resulting electrostatic protection solution can effectively reduce the impact of static electricity on the performance of the navigation chip and improve the chip's reliability and stability. In summary, through the above steps, the electrostatic protection design of the navigation chip can be comprehensively evaluated and optimized to ensure the chip's reliability and performance in practical applications.For example, in the quality control link of navigation chip packaging, technicians can use the above method to carry out detailed electrostatic protection design for the packaged chip. Through material analysis, electrostatic sensitivity assessment, shielding structure design and electric field simulation, potential problems such as excessive electric field strength and excessive charge accumulation rate can be discovered in time, and corresponding protective measures can be taken. In addition, through multi-objective optimization, it can be ensured that the shielding structure scheme can achieve the best effect in multiple performance indicators, providing strong guarantee for the reliability and performance of the navigation chip. This systematic electrostatic protection design method not only helps to improve the production quality of navigation chips, but also provides important technical support for subsequent design optimization and fault diagnosis.

[0117] In a specific embodiment, an electrostatic shielding structure design is performed on the defect position based on the electrostatic sensitivity index by using a topology optimization algorithm to obtain an initial shielding structure scheme, including:

[0118] Determining a sensitive area of ​​the defect location based on the electrostatic sensitivity index;

[0119] By using a preset topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the sensitive area to obtain a plurality of candidate shielding structure solutions;

[0120] A Pareto optimization analysis is performed on each of the candidate shielding structure solutions to obtain an initial shielding structure solution.

[0121] Specifically, based on the electrostatic sensitivity index, the sensitive area of ​​the defect position is determined; through a preset topology optimization algorithm, the electrostatic shielding structure of the defect position is designed based on the sensitive area to obtain multiple candidate shielding structure schemes; Pareto optimization analysis is performed on each of the candidate shielding structure schemes to obtain the initial shielding structure scheme, which is one of the key steps in electrostatic protection design. This process aims to ensure that the shielding structure achieves the best effect on multiple performance indicators through detailed sensitive area determination, multi-scheme design and optimization analysis. First, the sensitive area of ​​the defect position is determined based on the electrostatic sensitivity index. The electrostatic sensitivity index includes parameters such as charge accumulation rate, discharge threshold and voltage tolerance, which can reflect the sensitivity of the defect position to the electrostatic field. By analyzing these parameters, it can be determined which areas are most sensitive in the electrostatic field and need to be protected. For example, in the navigation chip package, if the charge accumulation rate of a crack area is very high, the discharge threshold is very low, and the voltage tolerance is also weak, then this area is a highly sensitive area. Through detailed electrostatic sensitivity evaluation, the specific location and range of these sensitive areas can be determined. Next, through the preset topology optimization algorithm, the electrostatic shielding structure design is performed on the defect position based on the sensitive area to obtain multiple candidate shielding structure schemes. The topology optimization algorithm is a method for optimizing material distribution and geometry, aiming to minimize material usage and cost while meeting performance requirements. In this process, it is necessary to focus on the sensitive area as the key protection object and design a variety of different shielding structure schemes. These schemes can have different material distributions, geometries and thickness gradients. For example, a scheme can be designed to add conductive materials around the crack, another scheme can add insulating materials around the crack, and another scheme can add multiple layers of composite materials around the crack. Through these different design schemes, a variety of possible shielding structures can be explored. Finally, Pareto optimization analysis is performed on each of the candidate shielding structure schemes to obtain the initial shielding structure scheme. Pareto optimization analysis is a multi-objective optimization method that aims to find a set of optimal solutions that cannot be surpassed by other solutions at the same time in multiple performance indicators. Specifically, a set of optimal solutions can be screened out from multiple candidate shielding structure schemes through Pareto optimization analysis, and these solutions have excellent performance in terms of electric field intensity attenuation rate, electric field suppression degree and electric field interference level. For example, suppose three different shielding structure solutions are obtained through the topology optimization algorithm, each with a different electric field strength attenuation rate, electric field suppression degree, and electric field interference level. Through Pareto optimization analysis, we can find solutions that are balanced in multiple performance indicators, and these solutions are considered to be Pareto optimal solutions. In the end, the initial shielding structure solution obtained through Pareto optimization analysis not only performs well in terms of electric field strength attenuation rate, electric field suppression degree, and electric field interference level, but also achieves the optimal balance in terms of material usage and cost.For example, in the quality control link of navigation chip packaging, technicians can use the above method to design a detailed electrostatic shielding structure for the packaged chip. By identifying sensitive areas, designing multiple candidate shielding structure schemes, and performing Pareto optimization analysis, a shielding structure scheme can be designed that can effectively reduce the impact of static electricity on chip performance and minimize material usage and cost. This systematic electrostatic shielding design method not only helps to improve the production quality of navigation chips, but also provides important technical support for subsequent design optimization and fault diagnosis, ensuring the stability and reliability of the chip in various application scenarios.

[0122] The electrostatic testing method for the navigation chip package in the embodiment of the present invention is described above. The electrostatic testing device for the navigation chip package in the embodiment of the present invention is described below. Figure 2 , an embodiment of the electrostatic testing device for navigation chip packaging in an embodiment of the present invention includes:

[0123] The scanning module 21 is used to scan the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip;

[0124] An identification module 22 is used to identify whether there is defect information in the three-dimensional packaging model. If there is, a preset defect identification algorithm is used to identify and locate the defect type of the three-dimensional packaging model based on the defect information to obtain the defect type and the defect position corresponding to the defect type.

[0125] The testing module 23 is used to perform a simulation test on the electrostatic electric field distribution corresponding to the defect position through a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram;

[0126] An evaluation module 24, configured to evaluate the degree of impact on the performance of the navigation chip based on the electric field strength distribution diagram, and obtain a performance impact evaluation level of the navigation chip;

[0127] The formulation module 25 is used to formulate an electrostatic protection design plan based on the electric field intensity distribution diagram of the defect position and the defect type if the performance impact assessment level exceeds a preset level threshold.

[0128] In this embodiment, for the specific implementation of each unit in the above system embodiment, please refer to the above method embodiment, which will not be repeated here.

[0129] Reference Figure 3 The present invention also provides a computer device in an embodiment, wherein the internal structure of the computer device can be as follows: Figure 3As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0130] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0131] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0132] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0133] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0134] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An electrostatic testing method for navigation chip packaging, characterized in that: The invention is applied to a navigation chip packaging device, wherein a navigation chip is arranged in the navigation chip packaging device, and comprises the following steps: Scanning the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip; Identify whether there is defect information in the three-dimensional packaging model. If so, identify and locate the defect type of the three-dimensional packaging model based on the defect information using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type; The electrostatic field distribution corresponding to the defect position is simulated and tested by a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram; Based on the electric field strength distribution diagram, the navigation chip is evaluated for its performance impact, to obtain a performance impact evaluation level of the navigation chip; If the performance impact assessment level exceeds a preset level threshold, an electrostatic protection design plan is formulated based on the electric field intensity distribution diagram of the defect location and the defect type; The method of identifying and locating the defect type of the three-dimensional packaging model based on the defect information by using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type includes: Extracting defect features from the three-dimensional packaging model using a preset defect recognition algorithm to obtain a multi-scale defect feature map; Performing preliminary defect recognition on the multi-scale defect feature map through the attention mechanism in the defect recognition algorithm to obtain a preliminary defect candidate region; wherein the preliminary defect candidate region has at least one; Performing defect morphology processing on the preliminary defect candidate area to obtain a defect boundary area; Selecting a corresponding key defect point in each of the defect boundary regions, and establishing a corresponding polar coordinate system with the key defect point corresponding to each of the defect boundary regions as the center; Dividing the space of the polar coordinate system into a plurality of discrete cells, and counting the corresponding numbers of key defect points of the plurality of discrete cells to obtain a statistical result of the key defect points; Establishing a local shape context histogram based on the statistical results; All the local shape context histograms are connected in series to obtain defect feature vectors corresponding to defect boundary areas in each polar coordinate system; Each of the defect feature vectors is input into a pre-trained SVM classifier for defect classification and positioning, so as to obtain a defect type and a defect position corresponding to the defect type; wherein the defect type includes cracks, bubbles and scratches.

2. The electrostatic testing method for navigation chip packaging according to claim 1, characterized in that: The step of scanning the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip includes: Scanning the surface of the navigation chip packaging device at multiple angles using a preset non-contact three-dimensional scanner to obtain two-dimensional images at multiple viewing angles; Performing coordinate point registration and fusion on the two-dimensional image to obtain preliminary three-dimensional point cloud data; Smoothing the preliminary three-dimensional point cloud data to obtain smoothed three-dimensional point cloud data; Performing grid processing on the smoothed three-dimensional point cloud data to obtain a preliminary three-dimensional grid model; The three-dimensional mesh model is enhanced in detail to obtain a three-dimensional packaging model of the navigation chip.

3. The electrostatic testing method for navigation chip packaging according to claim 1, characterized in that: The electrostatic field distribution corresponding to the defect position is simulated and tested by the preset electrostatic field simulation software to obtain an electric field intensity distribution diagram, including: Setting boundary conditions for the defect boundary region of the defect position on the three-dimensional packaging model to obtain a three-dimensional packaging model with boundary conditions; wherein the three-dimensional packaging model with boundary conditions has charge distribution, grounding conditions and insulation conditions; The electric potential distribution of the three-dimensional packaging model with boundary conditions is calculated by solving the Poisson equation to obtain an electric potential distribution diagram of the defect position; By using preset electrostatic field simulation software, the electrostatic electric field distribution corresponding to the defect position is solved based on the potential distribution diagram to obtain a preliminary distribution diagram of the electric field intensity at the defect position; Performing boundary condition constraint processing on the preliminary distribution map of electric field strength to obtain a boundary constraint distribution map of electric field strength at the defect position; Performing a thermal-electric coupling effect simulation on the electric field strength boundary constraint distribution diagram to obtain an electric field strength-thermal effect distribution diagram at the defect position; The electric field strength-thermal effect distribution diagram is dynamically simulated to obtain an electric field strength distribution diagram; wherein the electric field strength distribution diagram is an electric field strength distribution diagram of the electric field strength at the defect position changing with time and heat.

4. The electrostatic testing method for navigation chip packaging according to claim 1, characterized in that: The performance impact degree of the navigation chip is evaluated based on the electric field strength distribution diagram to obtain a performance impact evaluation level of the navigation chip, including: Based on the electric field strength distribution diagram, the impact characteristics of the internal components of the navigation chip are extracted to obtain the corresponding impact characteristic vector; wherein the impact characteristic vector includes the noise gain vector of the processing unit in the navigation chip, the frequency offset vector of the clock circuit, the bit error rate vector of the digital logic circuit and the voltage fluctuation amplitude vector of the power management unit; Performing compatibility simulation analysis on the navigation chip based on the impact feature vector to obtain an impact assessment report; quantifying the performance degradation risk of the navigation chip based on the impact assessment report to obtain a performance degradation risk assessment value; Performing uncertainty analysis on the performance degradation risk assessment value to obtain a probability distribution diagram of the performance assessment level of the navigation chip; The evaluation level corresponding to the maximum probability in the probability distribution diagram is used as the performance evaluation level of the navigation chip.

5. The electrostatic testing method for navigation chip packaging according to claim 4, characterized in that: The formulating of an electrostatic protection design scheme based on the electric field strength distribution diagram of the defect position and the defect type includes: Analyzing the navigation chip material at the defect position based on the electric field strength distribution diagram to obtain navigation chip material performance parameters; wherein the navigation chip material performance parameters include the dielectric constant of the navigation chip material and the conductivity of the navigation chip; Based on the navigation chip material performance parameters and the defect type, the electrostatic sensitivity of the defect boundary area is evaluated to obtain an electrostatic sensitivity index, wherein the electrostatic sensitivity index includes a charge accumulation rate, a discharge threshold, and a voltage tolerance; By using a topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the electrostatic sensitivity index to obtain an initial shielding structure scheme; wherein the initial shielding structure scheme includes material distribution, geometric shape and thickness gradient; Based on the initial shielding structure scheme, an electric field simulation is performed on the defect boundary area of ​​the defect position to obtain an electric field simulation effect; wherein the electric field simulation effect includes an electric field intensity attenuation rate, an electric field suppression degree, and an electric field interference level; If the level of the electric field simulation effect is less than a preset electric field simulation effect level, performing defect analysis on the electric field simulation effect to obtain a defect analysis result; Based on the defect analysis results, the initial shielding structure scheme is optimized by multiple objectives to obtain an electrostatic protection scheme.

6. The electrostatic testing method for navigation chip packaging according to claim 5, characterized in that: By using a topology optimization algorithm, an electrostatic shielding structure is designed for the defect location based on the electrostatic sensitivity index to obtain an initial shielding structure solution, including: Determining a sensitive area of ​​the defect location based on the electrostatic sensitivity index; By using a preset topology optimization algorithm, an electrostatic shielding structure is designed for the defect position based on the sensitive area to obtain a plurality of candidate shielding structure solutions; A Pareto optimization analysis is performed on each of the candidate shielding structure solutions to obtain an initial shielding structure solution.

7. An electrostatic test system for navigation chip packaging, characterized in that: Applicable to a navigation chip packaging device, wherein a navigation chip is arranged in the navigation chip packaging device, including: A scanning module, used to scan the surface morphology of the navigation chip packaging device to obtain a three-dimensional packaging model of the navigation chip; an identification module, used to identify whether there is defect information in the three-dimensional packaging model; if so, a preset defect identification algorithm is used to identify and locate the defect type of the three-dimensional packaging model based on the defect information to obtain the defect type and the defect position corresponding to the defect type; A testing module, used to perform a simulation test on the electrostatic electric field distribution corresponding to the defect position through a preset electrostatic field simulation software to obtain an electric field intensity distribution diagram; An evaluation module, configured to evaluate the degree of impact on the performance of the navigation chip based on the electric field strength distribution diagram, and obtain a performance impact evaluation level of the navigation chip; A formulation module, for formulating an electrostatic protection design scheme based on the electric field intensity distribution diagram of the defect position and the defect type if the performance impact assessment level exceeds a preset level threshold; The method of identifying and locating the defect type of the three-dimensional packaging model based on the defect information by using a preset defect recognition algorithm to obtain the defect type and the defect position corresponding to the defect type includes: Extracting defect features from the three-dimensional packaging model using a preset defect recognition algorithm to obtain a multi-scale defect feature map; Performing preliminary defect recognition on the multi-scale defect feature map through the attention mechanism in the defect recognition algorithm to obtain a preliminary defect candidate region; wherein the preliminary defect candidate region has at least one; Performing defect morphology processing on the preliminary defect candidate area to obtain a defect boundary area; Selecting a corresponding key defect point in each of the defect boundary regions, and establishing a corresponding polar coordinate system with the key defect point corresponding to each of the defect boundary regions as the center; Dividing the space of the polar coordinate system into a plurality of discrete cells, and counting the corresponding numbers of key defect points of the plurality of discrete cells to obtain a statistical result of the key defect points; Establishing a local shape context histogram based on the statistical results; All the local shape context histograms are connected in series to obtain defect feature vectors corresponding to defect boundary areas in each polar coordinate system; Each of the defect feature vectors is input into a pre-trained SVM classifier for defect classification and positioning, so as to obtain a defect type and a defect position corresponding to the defect type; wherein the defect type includes cracks, bubbles and scratches.

8. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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