Characteristic simulation method and simulation system of MOSFET device

Abstract

The invention provides an MOSFET device characteristic simulation method and simulation system, and the method comprises the following steps: carrying out the DC characteristic test of a plurality of devices to be tested in a plurality of temperature environments, and constructing a DC characteristic model of the devices to be tested according to the DC electrical characterization data obtained through the test; according to the direct current electrical representation data, constructing a statistical model, and analyzing and acquiring global change data and local mismatch data of the device to be tested; key electrical parameters of the to-be-tested device are extracted, and a radio frequency characteristic model of the to-be-tested device is constructed; and constructing an intensive model of the to-be-tested device according to the circuit characteristic mathematical model and the radio frequency characteristic model of the to-be-tested device. The invention provides a characteristic simulation method and a simulation system for an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which can accurately describe the characteristics of the MOSFET device in a low-temperature environment.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a characteristic simulation method and a simulation system for a MOSFET device. Background Art

[0002] Low-temperature MOSFET technology has shown great potential in fields such as quantum computing, space exploration, and medical science due to its significantly improved device performance at low temperatures, such as enhanced driving capability, reduced subthreshold swing, and reduced leakage current. In particular, in quantum computing, low-temperature MOSFET technology is essential for realizing the control, amplification, and readout modules of quantum processors, which need to be closely adjacent to the quantum gate array to minimize thermal noise and communication delays. In addition, low-temperature MOSFET technology has also promoted the development of digital / analog integrated circuits such as low-noise amplifiers (LNA), phase-locked loops (PLL), digital to analog converters (DAC), and analog-to-digital converters (ADC), greatly improving the possibility of realizing quantum computing.

[0003] Current electronic design automation (EDA) tools do not support circuit simulation below -40°C, which greatly limits the application of low-temperature MOSFET technology in fields such as quantum computing. Wafer foundries only provide MOSFET models and parameters at room temperature, which cannot fully match the actual working characteristics of MOSFET devices at low temperatures. In EDA simulation, commercial models are limited to a narrow temperature range, which limits the accurate description of MOSFET electrical characteristics in low-temperature environments. Summary of the invention

[0004] The object of the present invention is to provide a method and system for simulating the characteristics of a MOSFET device, which can accurately describe the characteristics of the MOSFET device in a low temperature environment.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a method for simulating the characteristics of a MOSFET device, comprising the following steps:

[0007] Conducting DC characteristic tests on multiple devices under test in multiple temperature environments, and constructing a DC characteristic model of the devices under test based on DC electrical characterization data obtained from the tests;

[0008] Constructing a statistical model based on the DC electrical characterization data, and analyzing and acquiring global change data and local mismatch data of the device under test;

[0009] Extracting key electrical parameters of the device under test and constructing a radio frequency characteristic model of the device under test; and

[0010] A compact model of the device under test is constructed according to the circuit characteristic mathematical model of the device under test and the radio frequency characteristic model.

[0011] In one embodiment of the present invention, the step of constructing the DC characteristic model includes:

[0012] Building a low-temperature test platform, wherein the temperature test range of the low-temperature test platform is 4.2K to 298K, and the frequency test range of the low-temperature test platform is 0.25GHz to 40GHz;

[0013] On a low-temperature test platform, at multiple temperatures, testing the DC characteristics and RF characteristics of the device under test to obtain DC electrical characterization data of the device under test, wherein the DC electrical characterization data is related to temperature; and

[0014] According to the direct current electrical characterization data, key electrical parameters of the device under test are quantitatively expressed, wherein the key electrical parameters include a threshold voltage, a channel mobility, and a subthreshold swing of the device under test.

[0015] In one embodiment of the present invention, in the step of testing the DC characteristics and the RF characteristics of the device under test, the test object is a low-temperature MOSFET device of various sizes and various molding processes.

[0016] In one embodiment of the present invention, the step of obtaining the global change data of the device under test includes:

[0017] Acquire electrical characterization data of all the devices under test involved in the test, and draw a transfer characteristic curve of the device under test according to the relationship between the drain current and the gate voltage of the device under test;

[0018] Comparing the transfer characteristic curves of different devices under test to verify the differences in transfer characteristic curves between different devices under test;

[0019] dividing the plurality of devices under test into small-size transistors and large-size transistors according to device width and device length; and

[0020] According to the difference in transfer characteristic curves of the small-size transistor in a preset low-temperature environment, the trend of the global change data of the device under test changing with temperature is described, wherein the global change data is parameter difference data between transistors of different wafers.

[0021] In one embodiment of the present invention, the step of obtaining the local mismatch data of the device under test includes:

[0022] Obtaining the threshold voltage of the device under test of different sizes; and

[0023] The threshold voltage is compared to obtain local mismatch data of the device under test, wherein the local mismatch data is parameter difference data of different transistors on the same wafer.

[0024] In one embodiment of the present invention, in the step of quantitatively expressing the key electrical parameters of the device under test, an effective temperature parameter is set to quantify the subthreshold swing, and according to the correlation between the threshold voltage and temperature, and the correlation between the channel mobility and temperature, the formula for obtaining the threshold voltage and the channel mobility is adjusted according to the effective temperature parameter, wherein the threshold voltage is calculated according to the following formula:

[0025] V TH (T) = Z * V TH,W (T)+K*V TH,L (T)+△V BS (T);

[0026] Among them, V TH (T) is the threshold voltage of the device under test when the temperature is T, Z*V TH,W (T) is a quantitative description of the narrow channel effect of the device under test at temperature T, K*V TH,L (T) is a quantitative description of the short channel effect of the device under test at temperature T, △V BS (T) is the change in the substrate bias voltage of the device under test when the temperature is T, the fitting parameter Z represents the intensity of the narrow channel effect, and the fitting parameter K represents the intensity of the short channel effect;

[0027] The channel mobility is calculated according to the following formula:

[0028] μ(T)=μ0(T / 298) -1.2 / (f1(λ0,L)*f2(θ1,θ2,T,E eff ));

[0029] Wherein, μ(T) represents the channel mobility of the device under test at temperature T, μ0 represents the long channel low electric field mobility at temperature 298K, T represents temperature, function f1 represents temperature-related scattering, function f1 represents ballistic transport limitation effect, λ0 represents low-field mean free path, L represents channel length, θ1 and θ2 are fitting parameters related to Coulomb scattering, E eff represents the effective vertical electric field considering surface roughness scattering.

[0030] The effective temperature parameter is calculated according to the following formula:

[0031]

[0032] Among them, T eff represents the effective temperature parameter, T0 represents the critical temperature at which the tail effect occurs, and D represents the smoothing parameter.

[0033] In one embodiment of the present invention, the step of constructing the radio frequency characteristic model includes:

[0034] According to the parameter data obtained from the RF test, the scattering parameter set, the admittance parameter set and the impedance parameter set are set, and the conversion relationship between different parameter sets is established;

[0035] Obtaining peripheral input / output impedance, pole-zero position, and resistance-capacitance equivalent circuit model of the device under test;

[0036] The resistance and capacitance values ​​are extracted from the parameter set, excluding the parasitic resistance and capacitance generated by instruments, cables and inter-chip interconnections.

[0037] In one embodiment of the present invention, the step of obtaining the peripheral input / output impedance of the device under test includes extracting the peripheral resistance of the device under test at multiple temperatures, and fitting the temperature variation trend by the following formula:

[0038] T eff，R =A×(T-298) 2 +B×(T-298)+1;

[0039] Among them, T eff,R is the temperature correction dependency of the node resistance, A and B are the correction coefficients related to the device material, and T is the temperature.

[0040] In one embodiment of the present invention, the step of extracting resistance and capacitance values ​​from the parameter set includes:

[0041] Extracting the parasitic resistance of the device under test;

[0042] Converting and acquiring the parasitic capacitance of the device under test through an admittance parameter set;

[0043] Obtain the diffused junction capacitance of the device under test, where the parasitic capacitance of the device under test is based on the following formula:

[0044]

[0045] Among them, C j (T) is the junction capacitance at temperature T, C j0 is the junction capacitance at room temperature, φ biis the built-in potential of the PN junction, ξ is the temperature correction fitting parameter, V pn is the voltage across the PN junction of the device under test.

[0046] The present invention provides a MOSFET device characteristic simulation system, comprising:

[0047] A test module is used to construct a low-temperature test platform, and to perform a DC characteristic test and a radio frequency test on the device under test, and to obtain DC electrical characterization data of the device under test;

[0048] A DC characteristic model building module, used to build a DC characteristic model of the device under test according to the DC electrical characterization data;

[0049] A statistical card construction module, used to construct a statistical model based on the DC electrical characterization data, and analyze and obtain the global change data and local mismatch data of the device under test;

[0050] A radio frequency characteristic model building module, used to extract key electrical parameters of the device under test and build a radio frequency characteristic model of the device under test; and

[0051] The intensive model construction module is used to construct an intensive model of the device under test according to the circuit characteristic mathematical model of the device under test and the radio frequency characteristic model.

[0052] As described above, the present invention provides a method and system for simulating the characteristics of a MOSFET device, and builds a low-temperature test platform for testing DC and RF electrical characteristics. By combining with the physics of semiconductor devices, the changes in key electrical parameters at different temperatures are accurately described. The device performance changes caused by random process fluctuations are analyzed, and global changes and local mismatches are added to the modeling. According to the RF test of the RC network equivalent circuit model of the low-temperature MOSFET device, the external resistance and capacitance that change with temperature and frequency are modeled, realizing an intensive model of low-temperature MOSFET devices covering high frequencies in the entire temperature range.

[0053] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0055] Figure 1Schematic diagram of the process of simulating the characteristics of a low-temperature MOSFET device in one embodiment of the present invention.

[0056] Figure 2 FIG. 4 is a schematic diagram of a low-temperature MOSFET device according to an embodiment of the present invention.

[0057] Figure 3 Schematic diagram of a radio frequency equivalent circuit of a low-temperature MOSFET device in one embodiment of the present invention.

[0058] Figure 4 FIG. 1 is a flow chart of step S100 in an embodiment of the present invention.

[0059] Figure 5 Schematic diagram of a process of obtaining a probability distribution function curve of global change data in step S200 in one embodiment of the present invention.

[0060] Figure 6 FIG. 4 is a flow chart of step S300 in an embodiment of the present invention.

[0061] Figure 7 Schematic diagram of the structure of a low-temperature MOSFET device characteristic simulation system in one embodiment of the present invention.

[0062] In the figure: 10, characteristic simulation system; 11, test module; 12, DC characteristic model building module; 13, statistical card building module; 14, RF characteristic model building module; 15, intensive model building module. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] MOSFET devices are metal oxide semiconductor field effect transistors (MOSFET). In the present invention, the characteristic simulation of low-temperature MOSFET devices is realized by modeling, and the DC and RF characteristics of low-temperature MOSFET devices are described by extracting simulation model parameters. In this article, MOSFET devices are referred to as MOS tubes. At low temperatures, the threshold voltage of MOS tubes increases significantly, so the available overdrive voltage decreases. In addition, the subthreshold swing of MOS tubes will saturate to a constant value when it is lower than a critical temperature, so it is not practical to expect to save current by reducing the temperature. The critical temperature is, for example, 40K. Among them, the parameter extraction work of low-temperature MOSFET devices is mainly carried out in conjunction with the design of infrared readout circuits. The infrared detector works in a low-temperature environment, and the silicon readout circuit coupled to the infrared detector also works in the same low-temperature environment. Therefore, in order to design a circuit that can operate accurately at low temperatures, the RF modeling method of low-temperature MOSFET devices that can be provided by the present invention can work normally even in a low-temperature environment.

[0065] See also Figure 1 As shown, the characteristic simulation method provided by the present invention is based on the radio frequency performance modeling of the low temperature MOSFET device, so as to describe the characteristics of the low temperature MOSFET device. The characteristic simulation method includes steps S100 to S300.

[0066] Step S100: constructing a DC characteristic model of the device under test.

[0067] Step S200: construct a statistical model based on the DC electrical characterization data of the device under test, and analyze and obtain the global change data and local mismatch data of the device under test.

[0068] Step S300: construct a radio frequency characteristic model of the device under test.

[0069] See also Figure 1 and Figure 2 As shown, the present invention provides a device under test 10. The device under test 10 is a low temperature MOSFET device. Figure 2 As shown, the device under test 10 is, for example, a low-temperature intrinsic MOSFET device, wherein the characteristic parameters of the device under test 10 include a threshold voltage V TH (T), channel mobility μ eff (T) and subthreshold swing SS(T). Threshold voltage V TH (T) is the gate (G) voltage when the MOS tube is in the critical conduction state. Channel mobility μ eff(T) is the average drift velocity of carriers under unit electric field strength. The subthreshold swing SS(T) reflects the relationship between the gate voltage and the drain (D) current. Where T represents the temperature. The present invention does not limit the size and process of the MOS tube. Figure 2 The MOS tube structure shown is only one embodiment of the present invention. In step S100, when constructing the DC characteristic model of the device under test 10, the object of sampling data is a plurality of devices under test 10 of different sizes and different processes. In the present invention, before executing step S100, the device under test 10 is tested to obtain the DC electrical characterization data of the device under test 10 related to temperature.

[0070] It should be noted that in the present invention, the size of the device under test 10 is related to the actual application of the device. The gate width of the plurality of devices under test 10 is, for example, 0.12 μm to 1 μm, and the channel length is, for example, 0.04 μm to 1 μm. In this embodiment, the plurality of devices under test 10 in the present invention are divided into a first size group, a second size group, a third size group, and a fourth size group. Among them, the first size group and the second size group are distinguished by the gate width and the channel length. Specifically, the gate width and the channel length of the first size group are greater than the gate width and the channel length of the second size group. Among them, the channel length of the third size group is less than the channel length of the first size group, and the gate width of the third size group is greater than the gate width of the second size group. The gate width of the fourth size group is less than the gate width of the first size group, and the channel length of the fourth size group is greater than the channel length of the second size group. The first size group, the second size group, the third size group, and the fourth size group in the present invention are embodied as a large size group, a small size group, a short channel group, and a narrow gate group. In the large size group, the width of the device and the length of the device are both large. In the small size group, the width of the device and the length of the device are both small. In the short channel group, the width of the device is large and the length of the device is small. In the narrow gate group, the width of the device is small and the length of the device is large. In the preset low temperature environment, the threshold voltage process floating of the device under test 10 of various sizes becomes larger, and is larger than the threshold voltage process floating of the device under test 10 at normal temperature. The preset low temperature environment is, for example, 4.2K to 298K.

[0071] See also Figures 1 to 3 As shown, in one embodiment of the present invention, a low-temperature probe station, a semiconductor device analyzer and a vector network analyzer are used to build a low-temperature test platform suitable for wide temperature and wide frequency, which is used to measure the device under test 10 at multiple temperatures. In this embodiment, the semiconductor device analyzer can be a high-precision Keysight B1500A semiconductor device analyzer. The vector network analyzer can be a Keysight 5227A vector network analyzer.

[0072] See also Figures 1 to 3 As shown, in one embodiment of the present invention, the circuits for DC characteristic test and RF characteristic test are as follows Figure 3 As shown. The device under test 10 has a gate G, a drain D, a source S and a substrate B. The substrate B is electrically connected to the source S. In this embodiment, the characteristic test circuit includes a plurality of resistors, a plurality of capacitors and a plurality of junction capacitors, wherein the resistors are electrically connected to each pole of the device under test 10. Specifically, the characteristic test circuit includes a gate resistor R g,ext , source resistance R s,ext , drain resistance R d,ext and the equivalent substrate resistance R sub The gate resistance R g,ext , source resistance R s,ext , drain resistance R d,ext is the parasitic resistance related to the circuit layout, and the gate resistance R g,ext Related to the gate metallization, the drain resistance R d,ext Related to the drain metallization, the source resistance R s,ext Related to source metallization. Equivalent substrate resistance R sub is the equivalent resistance of the transistor base region, including source and drain diffusion regions and metal connections between adjacent fingers.

[0073] See also Figures 1 to 3 As shown, in one embodiment of the present invention, the characteristic test circuit includes a gate-source capacitor C gs,ext , gate-drain capacitance C gd,ext , source-drain capacitance C ds,ext and gate-base capacitance C gb,ext The gate-source capacitance C gs,ext Electrically connected between the gate G and the source S. Gate-drain capacitance C gd,ext Electrically connected between the gate G and the drain D. Source-drain capacitance C ds,ext Electrically connected between the drain D and the source S. Gate-base capacitance C gb,ext It is electrically connected between the gate G and the substrate B. Among them, the gate-source capacitor C gs,ext , gate-drain capacitance C gd,ext , source-drain capacitance C ds,ext and gate-base capacitance C gb,ext is the parasitic capacitance associated with electrode coupling.

[0074] See also Figures 1 to 3 As shown, in one embodiment of the present invention, the characteristic test circuit includes a first junction capacitor C js and the second junction capacitance C jd The first junction capacitance C js The negative electrode of is electrically connected to the source electrode S of the device under test 10, and the first junction capacitor C js The positive electrode and the second junction capacitor C jd The second junction capacitor C jd The negative electrode of is electrically connected to the drain electrode D of the device under test 10.js is the capacitance from gate to source junction, C js Related to the PN junction in the source region. In the RF equivalent circuit model, C js It affects the parasitic capacitance effect of the source, thus affecting the high-frequency response and speed of the device. At low temperatures, due to the change in carrier concentration, C js The value of C may vary. jd is the capacitance from the gate to the drain junction, associated with the PN junction in the drain region. In the RF equivalent circuit, C jd It is also a key electrical parameter that affects the parasitic capacitance effect of the drain, which in turn affects the high-frequency gain and linearity of the device. jd The value of will also be affected by temperature changes.

[0075] It should be noted that for the design of RF models for low-temperature MOSFET devices, the above-mentioned parameters such as parasitic capacitance, parasitic resistance and junction capacitance affect the high-frequency performance of low-temperature MOSFET devices, such as gain, loss, impedance matching and noise characteristics. By accurately modeling and optimizing parameters such as parasitic capacitance, parasitic resistance and junction capacitance, better performance and higher integration can be achieved in RF circuit design. In the modeling of low-temperature CMOS RF devices, these parameters also need to consider the impact of temperature on device performance to ensure the effectiveness and accuracy of the model in low-temperature environments.

[0076] In the present invention, if Figure 1 and Figure 4 As shown, step S100 includes steps S110 to S130.

[0077] Step S110: obtaining direct current electrical characterization data of the device under test at multiple temperatures.

[0078] Step S120: quantify key electrical parameters of the device under test according to the DC electrical characterization data of the device under test.

[0079] Step S130 : constructing a DC characteristic model of the device under test by combining the device physical principle and the empirical model of the device under test.

[0080] See also Figures 1 to 4As shown, in one embodiment of the present invention, in step S110, under different DC biases and at different temperatures, based on the characteristic test circuit, the voltage data is adjusted to obtain the transfer characteristic curve, output characteristic curve and substrate current curve of the device under test 10. The transfer characteristic curve is the IDS-VGS curve of the device under test 10 to represent the relationship between the drain current and the gate voltage of the device under test 10. In the step of obtaining the transfer characteristic curve, the drain voltage VDS is set to 0.05V / VDD, and the gate voltage VGS and the substrate voltage VBS are set in sequence, so that the gate voltage VGS traverses -0.5V to VDD, and the substrate voltage VBS traverses -V DD ~0V, and record the drain current IDS and gate voltage VGS of the device under test 10 when the voltage is changed. According to the recorded voltage data and current data, the transfer characteristic curve of the device under test 10 is drawn. Among them, the output characteristic curve is the IDS-VDS curve of the device under test 10, which is used to represent the relationship between the drain current and the drain voltage of the device under test 10. In the step of obtaining the output characteristic curve, the gate voltage VGS and the drain voltage VDS are set in sequence, so that the gate voltage VGS traverses 0.5V~VDD, and the drain voltage VDS traverses 0V~VDD, and the drain current IDS and drain voltage VDS of the device under test 10 are recorded when the voltage is changed. According to the recorded voltage data and current data, the output characteristic curve of the device under test 10 is drawn. Among them, the substrate current curve is the Isub-VGS curve of the device under test 10, which is used to represent the relationship between the substrate current and the gate voltage of the device under test 10. In the step of obtaining the substrate current curve, the gate voltage VGS and the drain voltage VDS are set in sequence, so that the gate voltage VGS traverses -0.5V to VDD, and the drain voltage VDS traverses 0V to VDD, and the drain current IDS and the drain voltage VDS of the device under test 10 are recorded when the voltage is changed. Based on the recorded voltage data and current data, the substrate current curve of the device under test 10 is drawn.

[0081] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S120, some key electrical parameters of the device under test 10 are quantified. In this embodiment, the quantified key electrical parameters include the threshold voltage V TH , channel mobility μ eff and effective temperature parameter T eff .

[0082] It should be noted that in a low temperature environment, the change in the body carrier density leads to the movement of the Fermi level, and the expansion of the depletion layer width adjusts the effective width and length of the inversion layer. Such changes lead to a threshold voltage V THIncrease. Due to the reduction of scattering effects, including lattice scattering, impurity and defect scattering, and phonon-electron scattering, as well as the emergence of quantum effects and the reduction of thermal activation energy barriers. These factors work together to make MOSFET devices exhibit better electron transport characteristics at low temperatures, resulting in a channel mobility μ at low temperatures. eff The phenomenon of enhancement. Low temperature changes the distribution and motion characteristics of carriers, reduces thermal excitation and hot carrier effects, enhances the influence of interface states and traps, and reduces possible quantum confinement effects and leakage current. These factors work together to cause the subthreshold swing (SS) of MOSFET devices to become steeper at low temperatures. Therefore, in the present invention, the threshold voltage V TH , channel mobility μ eff and effective temperature parameter T eff Anchor more accurately.

[0083] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S130, the threshold voltage is quantified by the threshold voltage equation. In this embodiment, the threshold voltage is corrected by the temperature-related correction term and the body effect term to obtain a more accurate threshold voltage value in a low temperature environment. In this embodiment, considering the influence of the temperature-driven gate geometry effect, a correction formula for the temperature coefficient and the temperature trend is set to correct the threshold voltage. And in this embodiment, considering that the carrier freeze-out effect will change the substrate resistance, resulting in the redistribution of the body region electric field, thereby generating a corrected body effect term Δ VBS(T). In this embodiment, the corrected V TH (T) accurately describes the relationship between threshold voltage and temperature at low temperature. The threshold voltage equation is as shown in equation (1).

[0084] V TH (T) = Z * V TH,W (T)+K*V TH,L (T)+△V BS (T) (1).

[0085] In formula (1), V TH (T) is the threshold voltage of the device under test 10 when the temperature is T, Z*V TH,W (T) is a quantitative description of the narrow channel effect of the device under test 10 at temperature T, K*V THL (T) is a quantitative description of the short channel effect of the device under test 10 at temperature T, △V BS (T) is the change in the substrate bias voltage of the device under test 10 when the temperature is T, the fitting parameter Z represents the intensity of the narrow channel effect, and the fitting parameter K represents the intensity of the short channel effect.

[0086] See also Figures 1 to 4As shown, in one embodiment of the present invention, in step S130, the drain current IDS and the effective channel mobility μ of the device under test 10 are eff Closely related. When the device under test 10 operates at low temperature, Coulomb scattering and lattice vibration scattering will become dominant factors and limit the channel mobility at low temperature. At the same time, the reduction in channel mobility is related to the ballistic mobility limitation caused by the finite electron acceleration time in the short channel. According to the Matheson rule including Coulomb scattering, lattice vibration scattering and ballistic transport limitation factors, the present invention sets a semi-empirical model to describe the model of the effective mobility caused by the overall channel length changing with temperature. In this embodiment, the calculation formula of the channel mobility is as shown in formula (2). μ(T)=μ0(T / 298) -1.2 / (f1(λ0,L)*f2(θ1,θ2,T,E eff ))(2).

[0087] In formula (2), μ(T) represents the channel mobility of the device under test 10 at temperature T, μ0 represents the long channel low electric field mobility at temperature 298K, and T represents temperature. Function f1 is used to describe temperature-related scattering, such as Coulomb scattering and lattice vibration scattering. Function f2 is used to describe the ballistic transport limitation effect. λ0 represents the low-field mean free path, L represents the channel length, θ1 and θ2 are fitting parameters for Coulomb scattering, and E eff represents the effective vertical electric field considering the scattering of surface roughness.

[0088] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S120, the subthreshold swing (SS) of the device under test 10 is saturated at a deep low temperature. The deep low temperature is T < 40K. In this embodiment, the device under test 10 is, for example, a MOS tube of a 40nm node. The present invention provides a low-temperature subthreshold swing model, setting the effective temperature parameter T eff , to describe the effect of the existence of the band tail on the carrier concentration. It should be noted that the band tail theory states that the physical phenomenon of the subthreshold swing saturating at low temperatures originates from the exponential state tails at the conduction band and the valence band. In semiconductors, a variety of factors can lead to the exponential decay of the energy band state on the band gap, such as the imbalance of doping impurities, defects in the material itself, and the interaction between electrons, holes, and phonons. Due to the defects at the interface of semiconductor materials in the transistor manufacturing process, a band tail of several mega-electron volts is generated on the energy band. In the present invention, the effective temperature coefficient T is defined as eff , thus using the main model framework of BSIM4 for the calculation of parameters such as surface potential and thermal voltage in the BSIM model. Among them, the calculation of the effective temperature parameter is based on formula (3).

[0089]

[0090] In formula (3), T eff represents the effective temperature parameter, T0 represents the critical temperature at which the tail effect occurs, D represents the smoothing parameter, and T represents the current temperature.

[0091] It should be noted that the present invention sets a threshold voltage equation, an effective mobility model and a low-temperature subthreshold swing model to obtain the threshold voltage V TH , channel mobility μ eff and effective temperature parameter T eff In the present invention, the correction formula of temperature trend and body effect term are introduced into the threshold voltage equation. Δ VBS(T) is used to obtain more accurate threshold voltage values ​​at low temperatures. Temperature-dependent scattering and scale-induced ballistic transport effects are introduced into the effective mobility model to obtain more accurate channel mobility values ​​at low temperatures. In the low-temperature subthreshold swing model, the effective temperature parameter is set to describe the phenomenon that the subthreshold swing (SS) saturates at deep low temperatures.

[0092] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S130, according to the transfer characteristic curves, output characteristic curves and substrate current curves of devices of different sizes at different temperatures obtained by DC test, the key electrical parameters such as channel mobility, threshold voltage, subthreshold swing, saturation current of the device at different temperatures are extracted to correct the Cryo-BSIM4 model. The transfer characteristic curve is the IDS-VGS curve. The output characteristic curve is the IDS-VDS curve. The substrate current curve is the Isub-VGS curve. In this embodiment, taking the low electric field mobility Cryo U0 at low temperature as an example, it is demonstrated that by converting the parameter values ​​in the original BSIM model into a combination of formulas related to the device channel width W, the device channel length L, and the test temperature T under the framework of the macro model, the correction terms of the DC characteristic model include equations (4) and (5).

[0093]

[0094] In formula (4), θ cryo represents the temperature-dependent model parameters at low temperatures, L represents the channel length, W represents the channel width, and θ cryol represents the temperature-dependent channel length coefficient, θ cryoll represents the temperature-dependent gate-source or -drain overlap length dependence coefficient, θ cryow represents the temperature-dependent channel width coefficient, θ cryop represents the temperature-dependent channel physical scale dependence coefficient, θ cryopl Represents the temperature-dependent gate-source or -drain physical length dependency coefficient.

[0095]

[0096] In formula (5), UTE cryo represents the strength of the temperature dependence of the low electric field mobility Cryo U0 at low temperatures, UTE cryol represents the strength of the temperature dependence of the channel length, UTE cryoll represents the strength of the temperature dependence of the gate-source or -drain overlap length, UTE cryow represents the intensity of the temperature dependence of the channel width, UTE cryop represents the strength of the temperature dependence of the channel physical scale, UTE cryopl Indicates the strength of the temperature dependence of the gate-source or -drain physical length as it relates to temperature.

[0097] Please refer to equations (1) to (5). Based on the macro model framework, the characteristic parameters of the original device under test 10 are converted into a combination of device channel width W, device channel length L and temperature-related formulas. The characteristic parameters of the original device under test 10 include channel mobility, threshold voltage, interface trap density and on-state current. By using a set of fitting parameters, the modified Cryo-BSIM4 model can reflect the IDS-VGS characteristics of all measured MOSFETs from 298K to 4.2K. The Cryo-BSIM4 model provided by the present invention accurately describes the DC electrical characterization characteristics of the device under test 10 related to temperature changes at low temperatures. In addition, the effective channel mobility and the capacitance-related n factor extracted from the Cryo-BSIM4 model are consistent with the experimental data, which once again verifies the reliability of the model results.

[0098] See also Figure 1 As shown, in one embodiment of the present invention, after obtaining the DC electrical characterization data of the device under test 10 at low temperature in step S100, in step S200, the characteristics of the process float at low temperature are included in the model card range, and a statistical model is obtained. The statistical model is a data set of data changes of the device under test 10 at low temperature. In this embodiment, the parameters of the statistical model are based on formula (6).

[0099] A=A typical +(1+σ)*dA mis +(1+β)*dA var (6).

[0100] In equation (6), A represents the device parameter specified in the statistical model, A typicalrepresents the constant value of device parameter A under the average performance of a process, σ represents the increment of the global process floating random variable of device parameter A under low temperature environment, dA mis represents the random variable of the global process fluctuation of device parameter A, β represents the increment of the local mismatch random variable of device parameter A in a low temperature environment, dA var A random variable representing the local mismatch of device parameter A.

[0101] See also Figures 1 to 5 As shown, it should be noted that under low temperature conditions, the global change is manifested as the standard deviation of the probability density function curve, and the global change increases with decreasing temperature.

[0102] See also Figure 1 and Figure 5 As shown, in one embodiment of the present invention, in step S200, a statistical model is constructed based on the DC electrical characterization data of the device under test 10, and global change data and local mismatch data of the device under test 10 are analyzed and obtained. The analysis and acquisition of the global change data of the device under test 10 in step S200 includes steps S210 to S260.

[0103] Step S210: obtaining measured parameter data of a plurality of devices under test at different temperatures.

[0104] Step S220: pre-processing measured parameter data.

[0105] Step S230: Obtain the distribution type of the measured parameter data.

[0106] Step S240: Obtain estimated parameters of the current data distribution type.

[0107] Step S250: fitting the probability density distribution curve of the measured parameter data.

[0108] Step S260: verify the fitting effect of the probability distribution curve.

[0109] See also Figure 1 and Figure 5 As shown, in one embodiment of the present invention, to obtain the probability density function curve of the global change of the device, first, in step S210, the measured parameter data of multiple devices under test 10 at different temperatures are collected. The collected measured parameter data includes the threshold voltage V TH , electron mobility μ and leakage current I offEtc. Then, in step S220, the collected measured parameter data is preprocessed. Among them, the preprocessing step includes removing outliers and normalizing the measured parameter data to ensure the data quality and the reliability of the analysis results. Then, in step S230, the distribution characteristics of the measured parameter data are analyzed to determine the probability distribution type that the measured parameter data best conforms to, such as normal distribution, lognormal distribution, etc. In this embodiment, a histogram or statistical test method can be used to assist in determining the data distribution type of the measured parameter data. After determining the distribution type of the measured parameter data, in step S240, the parameters of the distribution type are estimated according to the requirements of the distribution type. In this embodiment, the maximum likelihood estimation method is used to estimate the parameters required for the current distribution type to obtain the estimated parameters. For example, in this embodiment, for the normal distribution, the mean and standard deviation of the measured parameter data are estimated. Based on the estimated parameters, in step S250, a probability density distribution curve of the measured parameter data is drawn, wherein the probability density distribution curve can also be referred to as a probability density function curve. The abscissa of the probability density function curve can be a threshold voltage, and the ordinate represents the probability. The probability can be reflected as the proportion of the device under test 10 at the current threshold voltage in all the devices under test 10. Finally, in step S260, the fitting effect is verified by comparing the histogram of the measured parameter data and the fitted probability density function curve. If the fitting effect is not good, it is necessary to re-evaluate the data distribution type or the parameter estimation method, and re-fit the probability density function curve of the measured parameter data. Among them, the error threshold can be set to distinguish whether the fitting effect meets the requirements. For example, if the fitting error exceeds the error threshold, the fitting effect is not good. Through the above steps, a probability density function curve of the global change of MOSFET can be obtained, which is used to simulate and analyze the performance changes of the device under different process fluctuation conditions, so as to evaluate its reliability and performance during the design and manufacturing process. Among them, the global change refers to the data change between different wafers. Moreover, under low temperature conditions, the probability density function statistical curve becomes wider in short channel devices. In this embodiment, after counting all the instances to be tested, it is found that when the substrate temperature drops from 298K to 4.2K, the overall global threshold change ΔV TH Increased by 10%.

[0110] In addition, since the differential pair structure is widely used in analog and RF circuits, any mismatch of paired transistors caused by local random fluctuations will reduce circuit performance. In the present invention, local mismatch refers to the data difference between different transistors on the same wafer. And in this embodiment, the local mismatch is analyzed by extracting the threshold voltage values ​​of transistors of different sizes. When the transistor is cooled from 298K to 4.2K, the characteristic value of the threshold voltage factor depending on the preparation process increases by 78%, indicating that the fluctuation of the doping profile at low temperature is aggravated.

[0111] The present invention provides a statistical model of Cryo-BSIM4 with temperature-dependent random variables at low temperatures based on the quantitative changes shown in equations (1) to (5) and the mismatch results shown in equation (6).

[0112] See also Figure 1 and Figure 6 As shown, in one embodiment of the present invention, in step S300, a radio frequency characteristic model of the device under test 10 is constructed. Step S300 includes steps S310 to S330.

[0113] Step S310: construct a circuit simulation mathematical model of the device under test.

[0114] Step S320: Obtain the parasitic resistance parameters, parasitic capacitance parameters and junction capacitance parameters of the device under test under low temperature conditions, and construct a radio frequency characteristic model of the device under test in combination with the circuit simulation mathematical model of the device under test.

[0115] Step S330: construct an integrated model of the device under test by combining the circuit simulation mathematical model of the device under test and the radio frequency characteristic model of the device under test.

[0116] See also Figure 1 and Figure 6 As shown, in one embodiment of the present invention, in step S310, the small signal equivalent circuit of the RF low-temperature MOSFET device includes a low-temperature intrinsic MOSFET SPICE model and an external RC network equivalent circuit model related to the ground-signal-ground device layout structure.

[0117] See also Figure 1 and Figure 6 As shown, in one embodiment of the present invention, in step S320, a Y parameter set, an S parameter set, and a Z parameter set are set. The S parameter set is a scattering parameter set, the Y parameter set is an admittance parameter set, and the Z parameter set is an impedance parameter set. The parasitic resistance and parasitic capacitance of the device under test 10 are converted into Y parameters and Z parameters. In this embodiment, the parasitic resistance of the device under test 10 includes the gate resistance R g,ext , source resistance R s,ext , drain resistance R d,ext The parasitic capacitance includes the gate-source capacitance C gs,ext , gate-drain capacitance C gd,ext , source-drain capacitance C ds,ext and gate-base capacitance C gb,ext The gate resistance R g,ext and drain resistor R dext As shown in formula (7), the source resistance R sext As shown in formula (8).

[0118] R g,ext ,R d,ext=reZ 22 -reZ 12 (7).

[0119] R g,ext =reZ 12 (8).

[0120] In equations (7) and (8), R g,ext is the parasitic resistance of the gate, R d,ext is the parasitic resistance of the drain, R s,ext is the parasitic resistance of the source. 12 V DS =The real part of the transfer impedance at 0V.

[0121] See also Figure 6 As shown, in this embodiment, in step S320, the gate-source capacitance C gs,ext The calculation method of gate-drain capacitance C is as follows: gd,ext The calculation method of source-drain capacitance C is as follows: ds,ext The calculation method of gate-base capacitance C is as follows: gb,ext The calculation of is based on formula (12).

[0122] C gs,ext =(imY 11 +imY 12 ) / 2πf (9).

[0123] C gd,ext =-imY 12 / 2πf (10).

[0124] C ds,ext =(imY 12 +imY 22 ) / 2πf (11).

[0125] C gb,ext =(imY 11 +2imY 12 ) / 2πf (12).

[0126] In formula (9) to formula (12), C gs,ext is the parasitic capacitance generated by the coupling between the gate and the source, C gd,ext is the parasitic capacitance generated by the coupling between the gate and the drain, C ds,ext is the parasitic capacitance generated by the coupling between the source and drain, C gb,ext is the parasitic capacitance between the gate and the substrate, imY 11 is the imaginary part of the input admittance, Y 12 When port 1 is short-circuited, the transfer admittance between port 2 and port 1, Y 22is the input admittance at port 2 when port 2 is short-circuited, and f is the frequency.

[0127] See also Figure 6 As shown, in this embodiment, in step S320, the parameter Y is set sub , convert the Y parameter and parameter Y sub . Among them, the Y parameter and parameter Y sub The relationship between is as shown in formula (13), the equivalent substrate resistance R sub and Y sub The relationship between the parameters is shown in formula (14).

[0128]

[0129] R sub =reY sub / (imY sub ) 2 (14).

[0130] In formula (13), R ds is the parasitic capacitance between the drain and the source, ω=2πf, f is the operating frequency, C gd is the parasitic capacitance between the gate and the drain. In formula (14), R sub is the equivalent substrate resistance.

[0131] See also Figure 6 As shown, in this embodiment, in step S320, the S parameter set is set, and the conversion between the Y parameter set and the S parameter set is based on equations (15) to (18).

[0132]

[0133]

[0134]

[0135]

[0136] In formula (15) to formula (18), Y 21 It represents the transfer admittance between port 2 and port 1 when port 2 is short-circuited, S 11 Enter the reflection coefficient, S, in the Smith chart 12 is the reverse transmission coefficient, S 21 is the forward transmission coefficient, S 22 is the output reflection coefficient, and Z0 is the characteristic impedance of the device under test 10.

[0137] See also Figure 6As shown, in this embodiment, in step S320, a Z parameter set is set, and the conversion between the Z parameter set and the S parameter set is based on equations (19) to (22).

[0138]

[0139]

[0140]

[0141]

[0142] Combining equations (9) to (22), the calculation method provided by the present invention can realize switching between multiple parameter sets to facilitate analysis and design of radio frequency circuits. Among them, the S parameter set is used to describe the reflection and transmission characteristics of the device, while the Y parameter set and the Z parameter set are suitable for circuit analysis and impedance matching design.

[0143] It should be noted that the equivalent substrate resistance R sub is a model parameter that represents substrate resistance and is not usually directly related to S-parameters, Y-parameters, or Z-parameters. However, R sub It will affect the output conductance and high frequency response of the device. The output conductance and high frequency response of the device may be reflected in the Y parameter or Z parameter, especially when analyzing the input and output impedance of high frequency devices. In the present invention, R sub Together with other parasitic resistances and capacitances, they are integrated into the equivalent circuit model to ensure that the model can accurately predict the performance of the device under actual operating conditions.

[0144] See also Figure 1 and Figure 6 As shown, in one embodiment of the invention, in step S330, the peripheral resistance of the device under test 10 is extracted by the "Cold-FET" method at multiple temperature points. In order to fit the temperature variation trend, the empirical second-order polynomial (23) is used to calculate the peripheral resistance of the device under test 10.

[0145] T eff , R =A×(T-298) 2 +B×(T-298)+1 (23).

[0146] In formula (23), T eff,R Dependence of the temperature correction of the node resistance, A and B are correction factors that depend only on the material, and T is the temperature.

[0147] See also Figure 1 and Figure 6As shown, in one embodiment of the invention, in step S330, the "Cold-FET" method is used to extract the peripheral parasitic capacitance of the device under test 10. It should be noted that the capacitance generated by the metal-to-metal interconnection does not change with temperature. In the present invention, the device under test 10 adopts a single resistor substrate network. In this embodiment, R sub,298K ×T eff The diffusion resistance in the device well and the metal wiring resistance R caused by the gate finger interconnection are fitted by sub In this embodiment, the “Cold-FET” method is used to obtain the parasitic capacitance between the gate and the substrate, that is, the gate-base capacitance C gb In this embodiment, the diffusion junction capacitance formed by the transistor source / drain and the doped silicon body is obtained by using the CV test method, that is, the first junction capacitance C js and the second junction capacitance C jd In this embodiment, the calculation of the diffusion junction capacitance is based on equation (24).

[0148]

[0149] In formula (24), C j (T) is the junction capacitance at temperature T, C j0 is the junction capacitance at room temperature, φ bi is the built-in potential of the PN junction, ξ is the temperature correction fitting parameter, V pn is the voltage across the PN junction of the device under test 10. It should also be noted that in this embodiment, the passive inductor element does not show any temperature dependence, so the inductive reactance of the passive inductor element is regarded as a set of constants in the low-temperature RF device model.

[0150] It should be noted that due to the doped polysilicon gate and the silicided source / drain region, the gate electrode resistance and the source / drain terminal resistance decrease as the temperature decreases. Therefore, in the present invention, a parametric equation that only depends on the material is constructed by modeling and fitting the temperature-dependent resistance. In this embodiment, the temperature-dependent slopes of the capacitive elements related to the RF MOSFET can be divided into two categories. On the one hand, the metal wiring capacitance does not change much with temperature, and the capacitive elements related to the RF MOSFET have the characteristics of a parallel plate capacitor. On the other hand, the diffusion capacitance from the source / drain to the body junction can be modeled as a fitting parameter equation related to the temperature correction term.

[0151] Therefore, after the data fitting process of the low-temperature MOSFET device model is completed in the present invention, the provided RF characteristic model can be used as the RF characteristic model of NMOS and PMOS devices in the range of 0.04μm channel length L1μm, 4.2K temperature T298K and 0.25GHz frequency f40GHz. The simulation method provided by the present invention can cover the characteristic simulation requirements of low-temperature MOSFET devices in a wide temperature, wide frequency and long channel length range, and more accurately realize characteristic modeling at low temperature.

[0152] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for simulating the characteristics of a MOSFET device, characterized in that: The following steps are involved: Conducting DC characteristic tests on multiple devices under test in multiple temperature environments, and constructing a DC characteristic model of the devices under test based on DC electrical characterization data obtained from the tests; Constructing a statistical model based on the DC electrical characterization data, and analyzing and acquiring global change data and local mismatch data of the device under test; Extracting key electrical parameters of the device under test and constructing a radio frequency characteristic model of the device under test; and A compact model of the device under test is constructed according to the circuit characteristic mathematical model of the device under test and the radio frequency characteristic model.

2. A method for simulating the characteristics of a MOSFET device according to claim 1, characterized in that: The steps of constructing the DC characteristic model include: Building a low-temperature test platform, wherein the temperature test range of the low-temperature test platform is 4.2K to 298K, and the frequency test range of the low-temperature test platform is 0.25GHz to 40GHz; On a low-temperature test platform, at multiple temperatures, testing the DC characteristics and RF characteristics of the device under test to obtain DC electrical characterization data of the device under test, wherein the DC electrical characterization data is related to temperature; and According to the direct current electrical characterization data, key electrical parameters of the device under test are quantitatively expressed, wherein the key electrical parameters include a threshold voltage, a channel mobility, and a subthreshold swing of the device under test.

3. A method for simulating the characteristics of a MOSFET device according to claim 2, characterized in that: In the step of testing the DC characteristics and the RF characteristics of the device under test, the test objects are low-temperature MOSFET devices of various sizes and various molding processes.

4. The method for simulating the characteristics of a MOSFET device according to claim 1, characterized in that: The step of obtaining the global change data of the device under test comprises: Acquire electrical characterization data of all the devices under test involved in the test, and draw a transfer characteristic curve of the device under test according to the relationship between the drain current and the gate voltage of the device under test; Comparing the transfer characteristic curves of different devices under test to verify the differences in transfer characteristic curves between different devices under test; dividing the plurality of devices under test into small-size transistors and large-size transistors according to device width and device length; and According to the difference in transfer characteristic curves of the small-size transistor in a preset low-temperature environment, the trend of the global change data of the device under test changing with temperature is described, wherein the global change data is parameter difference data between transistors of different wafers.

5. The method for simulating the characteristics of a MOSFET device according to claim 1, characterized in that: The step of obtaining the local mismatch data of the device under test comprises: Obtaining the threshold voltage of the device under test of different sizes; and The threshold voltage is compared to obtain local mismatch data of the device under test, wherein the local mismatch data is parameter difference data of different transistors on the same wafer.

6. A method for simulating the characteristics of a MOSFET device according to claim 2, characterized in that: In the step of quantitatively expressing the key electrical parameters of the device under test, an effective temperature parameter is set to quantify the subthreshold swing, and according to the correlation between the threshold voltage and temperature, and the correlation between the channel mobility and temperature, the formula for obtaining the threshold voltage and the channel mobility is adjusted according to the effective temperature parameter, wherein the threshold voltage is calculated according to the following formula: V TH (T)=Z*V TH,W (T)+K*V TH,L (T)+△V BS (T); Among them, V TH (T) is the threshold voltage of the device under test when the temperature is T, Z*V TH,W (T) is a quantitative description of the narrow channel effect of the device under test at temperature T, K*V TH,L (T) is a quantitative description of the short channel effect of the device under test at temperature T, △V BS (T) is the change in the substrate bias voltage of the device under test when the temperature is T, the fitting parameter Z represents the intensity of the narrow channel effect, and the fitting parameter K represents the intensity of the short channel effect; The channel mobility is calculated according to the following formula: μ(T)=μ0(T / 298) -1.2 / (f1(λ0,L)*f2(θ1,θ2,T,E eff )); Wherein, μ(T) represents the channel mobility of the device under test at temperature T, μ0 represents the long channel low electric field mobility at temperature 298K, T represents temperature, function f1 represents temperature-related scattering, function f1 represents ballistic transport limitation effect, λ0 represents low-field mean free path, L represents channel length, θ1 and θ2 are fitting parameters related to Coulomb scattering, E eff represents the effective vertical electric field considering the scattering of surface roughness; The effective temperature parameter is calculated according to the following formula: Among them, T eff represents the effective temperature parameter, T0 represents the critical temperature at which the tail effect occurs, and D represents the smoothing parameter.

7. The method for simulating the characteristics of a MOSFET device according to claim 1, characterized in that: The steps of constructing the radio frequency characteristic model include: According to the parameter data obtained from the RF test, the scattering parameter set, the admittance parameter set and the impedance parameter set are set, and the conversion relationship between different parameter sets is established; Obtaining peripheral input / output impedance, pole-zero position, and resistance-capacitance equivalent circuit model of the device under test; The resistance and capacitance values ​​are extracted from the parameter set, excluding the parasitic resistance and capacitance generated by instruments, cables and inter-chip interconnections.

8. The method for simulating the characteristics of a MOSFET device according to claim 1, characterized in that: The step of obtaining the peripheral input / output impedance of the device under test includes extracting the peripheral resistance of the device under test at multiple temperatures, and fitting the temperature variation trend by the following formula: T eff，R =A×(T-298) 2 +B×(T-298)+1; Among them, T eff,R is the temperature correction dependency of the node resistance, A and B are the correction coefficients related to the device material, and T is the temperature.

9. The method for simulating the characteristics of a MOSFET device according to claim 1, characterized in that: The step of extracting resistance and capacitance values ​​from the parameter set comprises: Extracting the parasitic resistance of the device under test; Converting and acquiring the parasitic capacitance of the device under test through an admittance parameter set; Obtain the diffused junction capacitance of the device under test, where the parasitic capacitance of the device under test is based on the following formula: Among them, C j (T) is the junction capacitance at temperature T, C j0 is the junction capacitance at room temperature, φ bi is the built-in potential of the PN junction, ξ is the temperature correction fitting parameter, V pn is the voltage across the PN junction of the device under test.

10. A MOSFET device characteristic simulation system, characterized in that: include: A test module is used to construct a low-temperature test platform, and to perform a DC characteristic test and a radio frequency test on the device under test, and to obtain DC electrical characterization data of the device under test; A DC characteristic model building module, used to build a DC characteristic model of the device under test according to the DC electrical characterization data; A statistical card construction module, used to construct a statistical model based on the DC electrical characterization data, and analyze and obtain the global change data and local mismatch data of the device under test; A radio frequency characteristic model building module, used to extract key electrical parameters of the device under test and build a radio frequency characteristic model of the device under test; as well as The intensive model construction module is used to construct an intensive model of the device under test according to the circuit characteristic mathematical model of the device under test and the radio frequency characteristic model.

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