3D stacked chip global wiring method, device, equipment and medium for thermal analysis optimization

Abstract

The present application provides a 3D stacked chip global wiring method, device, equipment and medium for thermal analysis optimization. The method obtains multiple target bare chips containing network pins from multiple bare chips of a network to be wired, and obtains wiring congestion information of each target bare chip; projects the network pins in each target bare chip to each of the remaining target bare chips to form projection pins corresponding to the network pins of the remaining target bare chips, so as to realize cross-die connection of multiple network pins; obtains first position information corresponding to each network pin and second pin position information corresponding to the projection pin, so as to form bare chip wiring information corresponding to each target bare chip in combination with the wiring congestion information, so as to generate cross-die connection positions and thermal field distribution information corresponding to each target bare chip; obtains through-silicon via distribution information corresponding to each target bare chip according to each thermal field distribution information, so as to optimize the cross-die connection positions, and complete the global wiring of the 3D stacked chip.

Description

Technical Field

[0001] The present invention relates to the field of stacked chip technology, and in particular to a 3D stacked chip global wiring method, device, equipment and medium for thermal analysis optimization. Background Art

[0002] 3D stacked chips are often used in large chips. When wiring, it is necessary to search and match available resources, which consumes a lot of computing resources and storage resources. The existing 3D-IC wiring method uses a 3D Steiner Minimal Tree. The wiring layers, via layers, and through-silicon via layers from different dies are stacked up and down in order according to their corresponding positions as the overall available wiring resources. It is a three-dimensional spatial structure. The 3D Steiner Tree algorithm searches for wiring paths, connects the pins of physical components in dies at different positions in the spatial structure, and completes the wiring task.

[0003] The position of TSV has a huge impact on heat distribution. There are two existing wiring methods: the first is to perform thermal distribution modeling and simulation based on the layout of the device and the placement of TSV during the search for the wiring path, and optimize the heat dissipation efficiency by adjusting the TSV position. TSV position adjustment is a continuous process, and its termination condition is that it exceeds the given execution time or fails to obtain better thermal performance. The second method is to optimize heat dissipation based on the results of thermal distribution modeling and simulation after the wiring is completed, calculate the wiring resource congestion, and tear up the completed wiring network and re-route it when a resource conflict occurs. TSV has good heat dissipation performance, and the wires connected to it can help distribute heat conduction. Inserting specific TSVs and corresponding connections in the wiring can improve the thermal effect.

[0004] The first solution mentioned above adjusts the TSV position during routing, which is computationally complex, time-consuming, and resource-intensive; the second solution performs heat dissipation optimization after routing, which has high risks and resource conflicts. Therefore, in practical applications, it is necessary to weigh and select the appropriate solution according to the specific situation, or combine the advantages of both to find a more efficient optimization method. Summary of the invention

[0005] The present application provides a 3D stacked chip global wiring method, device, equipment and medium for thermal analysis optimization, aiming to solve the problems of TSV position adjustment during wiring, complex and time-consuming calculations, high resource usage, high risk and resource conflicts in the current 3D stacked chip method.

[0006] In a first aspect, an embodiment of the present application provides a 3D stacked chip global wiring method for thermal analysis optimization, which is used to wire a network of 3D stacked chips to be wired, wherein the network includes multiple bare chips; the method includes:

[0007] Acquire multiple target dies including preset network pins from multiple dies of the network to be routed, and acquire routing congestion information of each target dies;

[0008] Projecting the network pins in each target die to each of the remaining target dies to form projection pins on each target die corresponding to the network pins on the remaining target dies; the projection pins are used to realize cross-die connection of multiple network pins;

[0009] Obtaining first position information corresponding to a network pin of each target die and second pin position information corresponding to a projection pin;

[0010] forming die routing information corresponding to each target die according to routing congestion information of each target die, first pin location information, and second pin location information;

[0011] Generate cross-die connection position and thermal field distribution information corresponding to each target die according to the plurality of die wiring information;

[0012] Acquire through silicon via distribution information corresponding to each target die according to each thermal field distribution information;

[0013] The cross-die connection positions are optimized based on the TSV distribution information to complete the global routing of 3D stacked chips.

[0014] In some embodiments, die wiring information corresponding to each target die is formed based on the wiring congestion information, first pin position information and second pin position information of each target die, including: obtaining application scenario information and performance requirement information corresponding to the 3D stacked chip; generating die wiring information corresponding to each target die based on the wiring congestion information, application scenario information, performance requirement information, first pin position information and second pin position.

[0015] Exemplarily, the cross-die connection position and thermal field distribution information corresponding to each target die are generated based on multiple die wiring information, including: generating the cross-die connection position based on multiple die wiring information and multiple wiring congestion information; performing thermal analysis based on 2D structure information, die wiring information and application scenario information corresponding to each target die to obtain thermal field distribution information.

[0016] In some embodiments, the through silicon via distribution information corresponding to each target die is obtained according to each thermal field distribution information, including: obtaining the remaining resource information corresponding to the 3D stacked chip; generating the through silicon via distribution information according to the remaining resource information, the cross-die connection position and the thermal field distribution information; the through silicon via distribution information includes the through silicon via distribution positions and through silicon via distribution resources of multiple target dies.

[0017] In some embodiments, the cross-die connection positions are optimized based on the thermal field distribution information and the through silicon via distribution information, including: determining the optimization range corresponding to the target die based on the cross-die connection position corresponding to each target die and a preset range; determining the through silicon via distribution dense points based on the through silicon via distribution information corresponding to the optimization range, and updating the through silicon via distribution dense points to the cross-die connection positions corresponding to the target die.

[0018] In some embodiments, after completing the global routing of the 3D stacked chip, it also includes: updating the routing congestion information of each target die; if it is determined based on the updated routing congestion information that there is at least one target die congestion; optimizing the die routing information of the congested target die based on the routing congestion information to update the cross-die connection position.

[0019] In some embodiments, before obtaining the first position information corresponding to the network pin of each target die and the second pin position information corresponding to the projection pin, the method further includes: deleting the remaining dies except the target die from the multiple dies of the 3D stacked chip.

[0020] In a second aspect, an embodiment of the present application provides a 3D stacked chip global wiring device, which is used to wire a network of 3D stacked chips to be wired, wherein the network includes multiple bare chips; including:

[0021] An information acquisition unit, used to acquire a plurality of target dies including preset network pins from a plurality of dies of a network to be routed, and acquire routing congestion information of each target dies;

[0022] A pin projection unit is used to project the network pins in each target die to each of the remaining target dies, so as to form projection pins on each target die corresponding to the network pins on the remaining target dies; the projection pins are used to realize cross-die connection of multiple network pins;

[0023] A position acquisition unit, used to acquire first position information corresponding to a network pin of each target die and second pin position information corresponding to a projection pin;

[0024] A wiring generation unit, configured to form die wiring information corresponding to each target die according to the wiring congestion information, the first pin position information, and the second pin position information of each target die;

[0025] A thermal field distribution unit, used for generating cross-die connection positions and thermal field distribution information corresponding to each target die according to the wiring information of the plurality of dies;

[0026] A distribution acquisition unit, used for acquiring through silicon via distribution information corresponding to each target die according to each thermal field distribution information;

[0027] The routing completion unit is used to optimize the cross-die connection positions according to the through-silicon via distribution information and complete the global routing of the 3D stacked chip.

[0028] In a third aspect, the present application further provides a computer device, including:

[0029] Memory and processor;

[0030] The memory is used to store computer programs;

[0031] The processor is used to execute the computer program and implement the steps of the 3D stacked chip global wiring method for thermal analysis optimization as described in the first aspect above when executing the computer program.

[0032] In a fourth aspect, the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the processor implements the steps of the 3D stacked chip global wiring method for thermal analysis optimization as described in the first aspect above.

[0033] The present application discloses a 3D stacked chip global wiring method, device, computer equipment and storage medium for thermal analysis optimization. It is used to wire a network of 3D stacked chips to be wired, and the network includes multiple bare chips. The method mainly targets the global wiring problem of 3D stacked chips, pays special attention to thermal analysis optimization, and aims to solve the problems of complex TSV (Through Silicon Via) position adjustment, time-consuming calculation, high resource occupation and resource conflicts in the prior art.

[0034] The method obtains the target die and its corresponding routing congestion information: among the multiple dies to be routed, multiple target dies containing network pins are identified and obtained. The routing congestion information of each target die is obtained, which helps to understand the usage of the routing resources of the die. The network pins in each target die are projected onto each other target die so as to form at least one projection pin on the target die. This step is to establish potential cross-die connection points between different dies. The first position information of the network pins and the second position information of the projection pins of each target die are obtained. These position information are important basis for subsequent routing and optimization. According to the congestion information of each target die, the first position information of the network pins and the second position information of the projection pins, the die routing information corresponding to each target die is generated. This step comprehensively considers the physical layout and routing resources of the die. According to the routing information of multiple dies, the cross-die connection position and thermal field distribution information corresponding to each target die are generated. The thermal field distribution information is crucial for subsequent optimization. According to the thermal field distribution information of each target die, the corresponding through-silicon via distribution information is obtained. Through silicon vias are the key to electrical connections between different dies in 3D stacked chips. Based on the through silicon via distribution information, the cross-die connection position is optimized, and finally the global wiring of the 3D stacked chip is completed, ensuring the optimization of the thermal and electrical performance of the wiring.

[0035] In summary, this method provides a systematic and efficient global routing solution for 3D stacked chips through a series of steps, from obtaining die information to final routing optimization. The core of this method is to solve the problems of complex calculations, high resource usage, and poor thermal performance in traditional methods through reasonable pin projection, congestion information utilization, and thermal field distribution optimization, providing important support for the design and implementation of 3D stacked chips. At the same time, based on the idea of ​​divide and conquer, it reduces the demand for resources during routing, reduces the complexity of operations such as search / matching, and performs global collaborative optimization for heat in the global routing stage.

[0036] It should be noted that the provided method also has the following beneficial effects:

[0037] 1. Reduce computational complexity and resource usage: By using the projection of network pins and congestion information, the complexity of TSV position adjustment during routing is reduced, thereby reducing computational complexity and resource usage.

[0038] 2. Improve wiring efficiency and reliability: Comprehensive consideration of wiring congestion information and pin location information makes the wiring process more efficient, reduces the risk of resource conflicts, and improves wiring reliability.

[0039] 3. Optimize thermal performance: By generating and utilizing thermal field distribution information and optimizing through-silicon via distribution, the thermal performance of 3D stacked chips is effectively improved, reducing performance degradation and damage that may be caused by overheating.

[0040] 4. Enhanced design flexibility and scalability: This method provides a more flexible routing solution that can adapt to 3D stacked chips of different design requirements and complexity, enhancing the flexibility and scalability of the design.

[0041] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 It is a schematic flow chart of the steps of a 3D stacked chip global wiring method for thermal analysis optimization provided by an embodiment of the present application;

[0044] Figure 2 It is a schematic diagram of the principle of pin projection provided by an embodiment of the present application;

[0045] Figure 3 It is a schematic diagram of the principle of bare chip wiring provided by an embodiment of the present application;

[0046] Figure 4 This is a schematic diagram of the principle of a cross-die connection provided by an embodiment of the present application;

[0047] Figure 5 is a thermal field distribution diagram of a single die provided by an embodiment of the present application;

[0048] Figure 6 It is a schematic diagram of the principle of optimizing the cross-die connection position provided by an embodiment of the present application;

[0049] Figure 7 It is a structural schematic diagram of a 3D stacked chip global wiring device provided by an embodiment of the present application;

[0050] Figure 8 It is a schematic block diagram of the structure of a computer device provided in one embodiment of the present application.

[0051] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0054] It should be understood that, in order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not necessarily limit the difference.

[0055] It should be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0056] It should also be understood that the term “and / or” used in the specification and appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0057] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0058] 3D stacked chips are often used in large chips. When wiring, it is necessary to search and match available resources, which consumes a lot of computing resources and storage resources. The existing 3D-IC wiring method uses a 3D Steiner Minimal Tree. The wiring layers, via layers, and through-silicon via layers from different dies are stacked up and down in order according to their corresponding positions as the overall available wiring resources. It is a three-dimensional spatial structure. The 3D Steiner Tree algorithm searches for wiring paths, connects the pins of physical components in dies at different positions in the spatial structure, and completes the wiring task.

[0059] The position of TSV has a huge impact on heat distribution. There are two existing wiring methods: the first is to perform thermal distribution modeling and simulation based on the layout of the device and the placement of TSV during the search for the wiring path, and optimize the heat dissipation efficiency by adjusting the TSV position. TSV position adjustment is a continuous process, and its termination condition is that it exceeds the given execution time or fails to obtain better thermal performance. The second method is to optimize heat dissipation based on the results of thermal distribution modeling and simulation after the wiring is completed, calculate the wiring resource congestion, and tear up the completed wiring network and re-route it when a resource conflict occurs. TSV has good heat dissipation performance, and the wires connected to it can help distribute heat conduction. Inserting specific TSVs and corresponding connections in the wiring can improve the thermal effect.

[0060] The first solution mentioned above adjusts the TSV position during routing, which is computationally complex, time-consuming, and resource-intensive; the second solution performs heat dissipation optimization after routing, which has high risks and resource conflicts. Therefore, in practical applications, it is necessary to weigh and select the appropriate solution according to the specific situation, or combine the advantages of both to find a more efficient optimization method.

[0061] To solve the above problems, please refer to Figure 1 , Figure 1 This is a schematic flow chart of a 3D stacked chip global wiring method for thermal analysis optimization provided by an embodiment of the present application. The method is used to wire a network of 3D stacked chips to be wired, wherein the network includes multiple bare chips. The 3D stacked chip global wiring method for thermal analysis optimization can be implemented by a computer device, which can be deployed on a single server or a server cluster. It can also be deployed on a handheld terminal, a laptop computer, a wearable device, or a robot, etc.

[0062] It should be noted that this application provides a wiring method for 3D stacked chip design, and this application focuses on optimization in thermal analysis. 3D stacked chips, also known as 3D integrated circuits (3D-ICs), are multiple chips (bare die) stacked in the vertical direction to improve chip performance, reduce signal delays, increase integration, and reduce overall size. However, this design also brings a series of challenges, such as heat dissipation problems, because the distance between chips becomes smaller, resulting in concentrated heat, which may affect the performance and life of the chip.

[0063] This application designs a global wiring method for 3D stacked chips optimized for thermal analysis, and adopts a technology that specifically considers heat distribution and heat dissipation efficiency when designing the wiring of 3D stacked chips. Global wiring refers to considering how to arrange signal lines, power lines, and ground lines at the chip level to ensure electrical performance while effectively managing heat energy.

[0064] At the same time, the method is used to route the network of the 3D stacked chip to be routed, that is, the routing method is applicable to those 3D stacked chips that have not yet completed the routing design. The network refers to the communication path collection between the various functional modules inside the chip connected by wires.

[0065] Correspondingly, each individual chip in a 3D stacked chip is called a die, which are stacked together through vertical connections (usually called TSV, i.e. through silicon via technology) or other connection methods (such as micro bumps) to form a multi-level network structure. Different dies may carry different functional modules, such as processors, memories, etc., and effective electrical connections are required between them to achieve functional interaction.

[0066] This application aims to ensure uniform heat distribution inside the chip through wiring design to avoid local overheating. At the same time, optimization is made in wiring material selection and wiring layout to reduce the heat accumulation generated during signal transmission and improve heat dissipation efficiency. It also makes full use of the characteristics of the 3D stacked structure, reasonably arranges the position of heat-sensitive components in the vertical direction, avoids heat accumulation, and uses vertical space for heat dissipation. The wiring method provided plays an important role in improving the overall performance, reliability and life of 3D stacked chips, especially in high-power, high-performance application scenarios.

[0067] Please refer to Figure 1 Specifically, Figure 1 As shown, the provided 3D stacked chip global wiring method for thermal analysis optimization includes steps S101 to S107. The details are as follows:

[0068] Step S101 . Acquire multiple target dies including preset network pins from multiple dies of a network to be routed, and acquire routing congestion information of each target dies.

[0069] Specifically, first, multiple target dies containing network pins are identified and selected. Network pins are key points that need to be connected in 3D stacked chips. As shown in Figure 2, there is network A in the 3D stacked chip, and there are two pins S and T in die 1 and die 2 in network A. By obtaining the wiring congestion information of each target die, the information describes the wiring resource occupancy of different areas on the die. By obtaining the wiring congestion information, the wiring can be planned more reasonably in the subsequent steps to avoid resource conflicts and high congestion areas.

[0070] At the same time, it should be noted that the number of target dies can be as follows Figure 2 Two are shown, and there may be more, which is not limited in the embodiments of the present application.

[0071] Step S102: Project the network pins in each target die to each of the remaining target dies to form projected pins on each target die corresponding to the network pins on the remaining target dies; the projected pins are used to realize cross-die connection of multiple network pins.

[0072] Specifically, the network pins in each target die are projected onto other target dies to form projected pins on other dies. This projection helps to establish potential connection points between different dies. Figure 1 As shown, the S pin in die 2 is projected in parallel to position S1 of die 1, and the T pin in die 2 is projected in parallel to T1 of die 2. By having S1 and T pins in die 1 and S and T1 pins in die 2, the cross-die pin projection between the target dies is completed. Through the cross-die pin projection, the connection between different dies can be planned in advance, providing a reference for subsequent wiring.

[0073] Step S103: Obtain first position information corresponding to the network pin of each target die and second pin position information corresponding to the projection pin.

[0074] Specifically, the first position information of the network pins and the second position information of the projection pins of each target die are obtained. These position information are crucial for subsequent wiring planning. Figure 2 The location of the network pin T of die 1 is (x1, y1), and the location of the projected pin S1 is (x1', y1'). The location of the network pin S of die 2 is (x2, y2), and the location of the projected pin T1 is (x2', y2'). Accurate location information helps optimize the routing path and reduce unnecessary detours and resource waste.

[0075] Step S104 . Form die routing information corresponding to each target die according to the routing congestion information, the first pin location information and the second pin location information of each target die.

[0076] Specifically, the die routing information is generated based on the congestion information, the first pin location information, and the second pin location information of each target die. This process comprehensively considers the resource occupancy on the die and the specific location of the pins. Figure 3 Based on the congestion information and pin location information of die 1, the routing information, i.e., the path from S1 to T, is generated, including the optimal connection path and resource allocation scheme. Similarly, the path from S to T1 of routing information 2 of die B is generated. The generated routing information provides detailed guidance for subsequent global routing, ensuring the rationality and efficiency of routing.

[0077] Step S105 : Generate cross-die connection positions and thermal field distribution information corresponding to each target die according to the plurality of die wiring information.

[0078] Specifically, based on the wiring information of multiple dies, the cross-die connection position and thermal field distribution information of each target die are generated. The thermal field distribution information describes the thermal distribution of the die under different connection schemes. Figure 4 As shown in Figure 2, through analysis, it is found that the connection position between die 1 and 2 is (x12, y12). At the same time, the thermal field distribution diagram corresponding to a single target die is as follows: Figure 5 Similarly, the connection position and thermal field distribution information between the other two adjacent dies are generated. The determination of the die connection position of all target dies is completed ( Figure 3 Only two are shown, and the actual number of dies may be more depending on the target number, and the method is the same as for two). By generating cross-die connection location and thermal field distribution information, it helps to identify potential thermal problems, thereby optimizing wiring to improve chip stability and life.

[0079] Step S106 . Obtain TSV distribution information corresponding to each target die according to each thermal field distribution information.

[0080] Specifically, according to each thermal field distribution information, the through silicon via (TSV) distribution information corresponding to each target die is obtained. TSV is a key structure for vertical connection in 3D stacked chips, and its distribution directly affects the performance of the chip. For example, according to the thermal field distribution information, two TSV positions (tx1, ty1) and (tx2, ty2) are determined on die 1, and a TSV position (tx3, ty3) is determined on die 2. The selection of these TSV positions takes into account the heat distribution to ensure that the high-heat area has sufficient heat dissipation capacity. At the same time, it can also include the number information of TSV settings at the position to ensure that TSV is placed at the key position while avoiding the overall design cost of 3D stacked chips being too high due to the high cost of TSV. By optimizing the TSV distribution, the thermal management of the chip can be effectively improved, the risk of overheating can be reduced, and the overall performance and reliability can be improved.

[0081] Step S107: Optimize the cross-die connection positions according to the through-silicon via distribution information to complete the global wiring of the 3D stacked chip.

[0082] Specifically, the cross-die connection locations are optimized based on the TSV distribution information. The optimization goal is to ensure the shortest connection path and the least resource usage, while taking into account the uniformity of heat distribution. By adjusting the connection location and path, resource conflicts and high congestion areas can be reduced. Figure 6 As shown in FIG. 1 , the cross-die connection point under the congestion and wire length model is P1. After obtaining P1, an area with denser TSV distribution is found in P1, and it will be selected as a new cross-die connection point, such as Figure 6 Similarly, adjust the connection paths between other dies to ensure a more uniform overall heat distribution.

[0083] The optimized connection positions and paths not only reduce the wiring complexity, but also improve the thermal efficiency of the chip and reduce the risk of high-heat areas. Finally, the global wiring of the 3D stacked chip is completed to ensure that the chip operates with high performance and reliability.

[0084] Through the above steps, the method effectively solves the problems of TSV position adjustment, complex calculation, high resource occupation and thermal management encountered in the wiring process of 3D stacked chips. Specifically: Step S101 provides basic data for subsequent wiring by obtaining the target die and its congestion information. Steps S102 and S103 provide possible paths for cross-die connections by projecting network pins and obtaining position information. Step S104 comprehensively considers congestion information and pin position information to generate detailed die wiring information. Step S105 generates cross-die connection positions and thermal field distribution information, providing a basis for thermal management. Step S106 optimizes the distribution of TSVs based on the thermal field distribution information and improves the heat dissipation capacity. Step S107 optimizes the cross-die connection position to finally complete the global wiring of the 3D stacked chip, ensuring the high performance and reliability of the chip. The provided method not only improves the efficiency and accuracy of wiring, but also significantly improves the thermal management of the chip, providing important technical support for the design and manufacture of 3D stacked chips.

[0085] In some embodiments, die wiring information corresponding to each target die is formed based on the wiring congestion information, first pin position information and second pin position information of each target die, including: obtaining application scenario information and performance requirement information corresponding to the 3D stacked chip; generating die wiring information corresponding to each target die based on the wiring congestion information, application scenario information, performance requirement information, first pin position information and second pin position.

[0086] The above embodiment further refines the content in step S104, emphasizing that when generating die routing information for each target die, not only the congestion information, first pin location information, and second pin location information of the die itself should be considered, but also the application scenario information and performance requirement information of the 3D stacked chip should be combined. The introduction of these additional information helps to generate a more reasonable and efficient routing solution.

[0087] The application scenario information is used to describe the specific application fields in which the 3D stacked chips will be used, such as high-performance computing (HPC), artificial intelligence (AI), consumer electronics, automotive electronics, etc. Different application scenarios have different requirements for chip performance, power consumption, heat dissipation, etc.

[0088] Performance requirement information includes specific performance indicators that the chip needs to achieve, such as processing power (TOPS), power consumption limit (Watt), bandwidth (GB / s), latency requirements (ns), etc. These requirements directly affect the routing priority and resource allocation.

[0089] In the above embodiment, when generating the routing information of each target die, the following information needs to be comprehensively considered: Routing congestion information: describes the resource occupancy of different areas on the die to help avoid high congestion areas. First pin location information: specific location information of the network pin, used to determine the local connection path. Second pin location information: specific location information of the projection pin, used to determine the connection path across the die. Application scenario information: helps determine the routing priority and resource allocation. For example, in high-performance computing scenarios, the shortest path and the highest bandwidth may be prioritized. Performance requirement information: adjust the routing plan according to specific performance requirements (such as power consumption, latency, etc.) to ensure that the overall performance indicators of the chip are met.

[0090] Based on the above comprehensive information, the wiring information of each target die is generated. This process may involve complex algorithms and optimization techniques, such as heuristic algorithms, genetic algorithms, simulated annealing algorithms, etc., to find the best wiring solution.

[0091] The generated wiring information includes: Connection path: The specific wiring path, considering factors such as the shortest path, minimum delay, and minimum power consumption. Resource allocation: Determine which areas of resources should be used first and which areas should be avoided to reduce congestion. Thermal management: Combined with application scenarios and performance requirements, optimize wiring to improve heat distribution and reduce overheating risks.

[0092] For example, suppose there is a 3D stacked chip for artificial intelligence (AI) applications, specifically an image recognition system for self-driving cars. The performance requirements of the chip include high processing power (e.g., 100 TOPS), low latency (e.g., 10ns), and high bandwidth (e.g., 500 GB / s).

[0093] Application scenario information: Image recognition system for self-driving cars, which requires high processing power, low latency, and high bandwidth. Performance requirements: 100 TOPS processing power, 10 ns latency, and 500 GB / s bandwidth.

[0094] The congestion information of the target die shows that a certain area is very congested, so when generating routing information, try to avoid using this area. The first pin location information and the second pin location information show that some key connection paths need to pass through low-latency and high-bandwidth paths, so these paths are given priority. The application scenario information and performance requirement information show that high processing power, low latency, and high bandwidth need to be optimized, so when generating routing information, these factors are given priority and the connection solution with the shortest path, lowest latency, and highest bandwidth is selected.

[0095] Based on the above comprehensive information, the wiring information of the target bare chip is generated, including the specific connection path, resource allocation and thermal management solution, to ensure that the high performance requirements of the image recognition system of the autonomous driving vehicle are met.

[0096] By introducing application scenario information and performance requirement information, we can more reasonably allocate wiring resources, avoid high congestion areas, optimize resource usage, and improve wiring efficiency. At the same time, we generate specific wiring solutions for different application scenarios and performance requirements to ensure that the chip can meet the requirements of high performance, low latency, and high bandwidth in actual applications.

[0097] Exemplarily, the cross-die connection position and thermal field distribution information corresponding to each target die are generated based on multiple die wiring information, including: generating the cross-die connection position based on multiple die wiring information and multiple wiring congestion information; performing thermal analysis based on 2D structure information, die wiring information and application scenario information corresponding to each target die to obtain thermal field distribution information.

[0098] This example further refines the specific process of generating cross-die connection locations and thermal field distribution information in the embodiment. The example provides more detailed steps to explain how to generate cross-die connection locations and thermal field distribution information based on the routing information, congestion information, and application scenario information of multiple dies. Multiple die routing information: includes the routing scheme for each die, such as connection paths, resource allocation, etc. Multiple routing congestion information: describes the resource occupancy of different areas on each die to help avoid high congestion areas.

[0099] This example determines the best cross-die connection location based on the routing information and congestion information of multiple dies. This process needs to consider the following factors: Shortest path: Try to select the shortest cross-die connection path to reduce latency and power consumption. Resource allocation: Avoid high congestion areas and optimize resource usage. Performance requirements: Based on the application scenario and performance requirement information, give priority to paths that meet performance requirements. By generating cross-die connection location information, the specific connection points and paths between different dies are described. 2D structure information is the 2D structure information of each target die, which describes the physical layout of different components and wiring on the die. Application scenario information: Describes the specific application areas and performance requirements that the chip will be used for.

[0100] Based on the 2D structure information, die wiring information and application scenario information, thermal analysis is performed to obtain thermal field distribution information. This process may involve the following steps: Thermal model establishment: Establish a physical model of the die, including components, wiring and TSV (Through Silicon Via), etc. Thermal simulation: Use thermal simulation tools to simulate the thermal distribution of the chip under different workloads. Thermal optimization: According to the application scenario and performance requirements, optimize the wiring scheme, improve the thermal distribution, and reduce the risk of overheating. Finally, the thermal field distribution information of each target die is obtained to describe the temperature distribution on the die under different workloads.

[0101] In some embodiments, the through silicon via distribution information corresponding to each target die is obtained according to each thermal field distribution information, including: obtaining the remaining resource information corresponding to the 3D stacked chip; generating the through silicon via distribution information according to the remaining resource information, the cross-die connection position and the thermal field distribution information; the through silicon via distribution information includes the through silicon via distribution positions and through silicon via distribution resources of multiple target dies.

[0102] This embodiment further refines the specific process of obtaining through silicon via (TSV) distribution information in step S106, and emphasizes that when generating through silicon via distribution information, not only thermal field distribution information should be considered, but also the remaining resource information of the 3D stacked chip and the cross-die connection position should be combined.

[0103] By obtaining the remaining resource information of the 3D stacked chip. The remaining resource information is used to describe the unused resources in the 3D stacked chip, including available through silicon via resources, wiring resources, and physical space on different dies. The remaining resource information helps determine in which areas new TSVs can be added and how to optimally utilize the physical space and resources of the chip. Obtain the remaining resource information of each die in the current 3D stacked chip through chip design tools or simulation tools. These tools can provide detailed resource occupancy diagrams showing which areas have been used and which areas are still available. Generate through silicon via distribution information based on the remaining resource information, cross-die connection locations, and thermal field distribution information.

[0104] The cross-die connection location is used to describe the connection points and paths between different dies. This information helps determine where TSVs need to be set to achieve cross-die connections. The thermal field distribution information is used to describe the temperature distribution of the chip under working conditions, helping to determine in which areas to set TSVs to effectively improve thermal management. According to the remaining resource information, avoid setting TSVs in areas with tight resources or high congestion; according to the cross-die connection location, ensure that the setting of TSVs can achieve the optimal connection path; according to the thermal field distribution information, preferentially set TSVs in high-temperature areas to improve heat dissipation. Through algorithm optimization (such as heuristic algorithms, genetic algorithms, etc.), find the optimal distribution location and resource allocation of TSVs to ensure that TSVs can not only achieve efficient cross-die connections, but also improve the overall thermal distribution of the chip. The through-silicon via distribution information includes the TSV distribution location and TSV distribution resources on multiple target dies. Specifically: The TSV distribution location describes the specific physical location of each TSV. The TSV distribution resources describe the resources occupied by each TSV, including physical space, electrical performance, thermal performance, etc.

[0105] In some embodiments, the cross-die connection positions are optimized based on the thermal field distribution information and the through silicon via distribution information, including: determining the optimization range corresponding to the target die based on the cross-die connection position corresponding to each target die and a preset range; determining the through silicon via distribution dense points based on the through silicon via distribution information corresponding to the optimization range, and updating the through silicon via distribution dense points to the cross-die connection positions corresponding to the target die.

[0106] Based on thermal field distribution information and through silicon via distribution information. Through this method, the system can more reasonably adjust the position of cross-die connections to optimize the overall performance and thermal management of the chip. The cross-die connection position is used to describe the existing connection points and paths between different dies. The preset range is a predefined range value used to determine the adjustable area around the existing cross-die connection position. The range can be set according to the physical size, application scenario and performance requirements of the chip. For each target die, an optimization range is determined based on its existing cross-die connection position and the preset range. This optimization range defines the area where the connection position can be adjusted. The through silicon via distribution information includes TSV distribution positions and TSV distribution resources on multiple target dies. As described above, the area where the connection position can be adjusted is defined.

[0107] Within the determined optimization range, analyze the TSV distribution information and find the TSV distribution density points. These points are where TSV distribution is more concentrated, which usually means that these areas have better connection resources or thermal management capabilities. Compare and evaluate the TSV distribution density points found with the existing cross-die connection locations, and select an optimal density point as the new cross-die connection location.

[0108] For example, due to the shortage of wiring resources, the existing solution of using TSVs and wires connected to them for thermal performance is difficult to implement and has high costs (TSVs are expensive resources). In the global wiring solution merging stage, this application selects cross-die connection points based on thermal performance optimization, thereby achieving a balance between line length and thermal performance. Figure 6 As shown in the figure, the cross-die connection point under the congestion and wire length model is P1. After obtaining P1, we search in a given adjacent area of ​​P1. If an area with a denser distribution of TSVs is found, it will be selected as the new cross-die connection point. In the figure below, this point is P2.

[0109] It should be noted that in some embodiments, it is assumed that there is a 3D stacked chip, including three target dies A, B and C, for high-performance computing (HPC) applications, and the specific scenario is large-scale parallel computing in data centers. The performance requirements of the chip include high processing power (e.g., 200 TOPS), low latency (e.g., 5 ns), and high bandwidth (e.g., 1 TB / s). The existing connection position between die A and die B is (x12, y12). The preset range is 50 microns. The circular area with a radius of 50 microns centered at (x12, y12) is determined as the optimization range. The through silicon via distribution information shows that there are three dense points within the optimization range: (tx1, ty1), (tx2, ty2) and (tx3, ty3). Analyze these three dense points and evaluate their resource utilization and thermal management capabilities. Select the optimal dense point (tx2, ty2) as the new connection position. Update the connection position between die A and die B from (x12, y12) to (tx2, ty2).

[0110] In some embodiments, after completing the global routing of the 3D stacked chip, it also includes: updating the routing congestion information of each target die; if it is determined based on the updated routing congestion information that there is at least one target die congestion; optimizing the die routing information of the congested target die based on the routing congestion information to update the cross-die connection position.

[0111] After completing the global routing of the 3D stacked chip, the routing congestion information of the chip is updated, and the routing information of the congested target die is optimized according to the updated congestion situation. This embodiment focuses on congestion management and updating of cross-die connection locations to ensure that the performance and resource utilization of the chip are optimized.

[0112] After completing the global routing of the 3D stacked chip, the routing scheme for each die has been preliminarily determined. At this point, it is necessary to re-evaluate the resource usage of each die. According to the results of global routing, the routing congestion information of each target die is updated. The congestion information describes the resource occupancy of different areas on the die, including routing resources, through silicon via resources, and physical space. The updated congestion information can help identify which areas have tight resource usage (i.e., high congestion areas) and which areas have more abundant resources. According to the updated routing congestion information, it is determined whether there is at least one target die in a high congestion state. The judgment can be made by setting a congestion threshold. For example, if the resource usage of a certain area exceeds 80%, the area is considered to be in a high congestion state. If there is a congested target die, the next step is to be optimized; if there is no congested target die, the optimization process ends.

[0113] By reallocating resources based on congestion information, try to avoid routing or setting TSV in high congestion areas. This can be achieved by adjusting the routing path, moving connection points, etc. Optimize cross-die connection positions: Update cross-die connection positions based on the new routing scheme to ensure a better connection path and avoid high congestion areas, thereby improving the overall performance and resource utilization of the chip. When optimizing routing information, thermal field distribution information also needs to be considered to ensure that the optimized routing scheme does not cause overheating problems. The final updated die routing information and cross-die connection positions ensure that the chip has better resource utilization and thermal management capabilities in high-performance application scenarios.

[0114] In some embodiments, before obtaining the first position information corresponding to the network pin of each target die and the second pin position information corresponding to the projection pin, the method further includes: deleting the remaining dies except the target die from the multiple dies of the 3D stacked chip.

[0115] The above embodiment describes a preprocessing step before obtaining the network pin location information and the projected pin location information of each target die. This step involves deleting the remaining dies except the target die from the multiple dies of the 3D stacked chip, so as to more accurately obtain the pin location information of the target die.

[0116] In a 3D stacked chip, multiple dies are stacked together through through silicon vias (TSVs) and other connection methods. In order to perform detailed routing and pin location analysis on a specific die (i.e., the target die), it is first necessary to delete other dies from the current analysis environment to prevent them from interfering with the pin location calculation and projection of the target die. Before obtaining the network pin location information and projected pin location information of the target die, all other dies except the target die in the 3D stacked chip are first identified and deleted. The deletion operation can be performed in a virtual manner in the chip design tool or simulation tool, that is, during the analysis and calculation process, the existence of other dies is temporarily ignored. The deletion operation only affects the current analysis and calculation process and will not affect the actual physical chip. By deleting the remaining dies, the interference of other dies on the pin location calculation of the target die can be avoided, thereby improving the calculation accuracy. Deleting the remaining dies can simplify the analysis and calculation process, allowing the system to focus more on the pin location information of the target die and improve efficiency. At the same time, more accurate pin location information helps in subsequent routing optimization and cross-die connection location optimization, thereby improving the overall performance and resource utilization of the chip.

[0117] See also Figure 7 As shown, Figure 7 : is a schematic diagram of the structure of the 3D stacked chip global wiring device 200 provided in an embodiment of the present application. The 3D stacked chip global wiring device 200 is used to wire a network of 3D stacked chips to be wired, wherein the network includes multiple bare chips. The 3D stacked chip global wiring device 200 is used to execute the steps of the 3D stacked chip global wiring method for thermal analysis optimization shown in the above embodiments. The 3D stacked chip global wiring device 200 can be a single server or a server cluster, or the 3D stacked chip global wiring device 200 can be a terminal, which can be a handheld terminal, a laptop computer, a wearable device or a robot, etc.

[0118] like Figure 7 As shown, the 3D stacked chip global wiring device 200 includes:

[0119] The information acquisition unit 201 is used to acquire multiple target dies including preset network pins from multiple dies of the network to be routed, and acquire routing congestion information of each target die;

[0120] The pin projection unit 202 is used to project the network pins in each target die to each of the remaining target dies, so as to form projection pins on each target die corresponding to the network pins on the remaining target dies; the projection pins are used to realize cross-die connection of multiple network pins;

[0121] A position acquisition unit 203, configured to acquire first position information corresponding to a network pin of each target die and second pin position information corresponding to a projection pin;

[0122] A wiring generation unit 204, configured to generate die wiring information corresponding to each target die according to the wiring congestion information, the first pin position information, and the second pin position information of each target die;

[0123] A thermal field distribution unit 205 is used to generate cross-die connection positions and thermal field distribution information corresponding to each target die according to the wiring information of the plurality of dies;

[0124] A distribution acquisition unit 206, configured to acquire through silicon via distribution information corresponding to each target die according to each thermal field distribution information;

[0125] The wiring completion unit 207 is used to optimize the cross-die connection positions according to the through silicon via distribution information to complete the global wiring of the 3D stacked chip.

[0126] It should be noted that technical personnel in the relevant field can clearly understand that, for the convenience and simplicity of description, the specific working processes of the 3D stacked chip global wiring device and each module described above can refer to the corresponding processes in the embodiments of the 3D stacked chip global wiring method optimized for thermal analysis described in the above embodiments, and will not be repeated here.

[0127] The above-mentioned 3D stacked chip global wiring method for thermal analysis optimization can be implemented in the form of a computer program. The computer program can be used in Figure 7 Run on the device shown.

[0128] See also Figure 8 , Figure 8 1 is a schematic block diagram of the structure of a computer device provided in an embodiment of the present application. The computer device includes a processor, a memory and a network interface connected via a device bus, wherein the memory may include a storage medium and an internal memory.

[0129] The storage medium can store an operating device and a computer program. The computer program includes program instructions, and when the program instructions are executed, the processor can execute any 3D stacked chip global wiring method optimized for thermal analysis.

[0130] The processor is used to provide computing and control capabilities and support the operation of the entire computer equipment.

[0131] The internal memory provides an environment for the operation of a computer program in a non-volatile storage medium. When the computer program is executed by a processor, the processor can execute any 3D stacked chip global wiring method optimized for thermal analysis.

[0132] The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 8The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the terminal to which the scheme of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0133] It should be understood that the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0134] In one embodiment, the processor is used to run a computer program stored in the memory to implement the following steps:

[0135] Acquire multiple target dies including preset network pins from multiple dies of the network to be routed, and acquire routing congestion information of each target dies;

[0136] Projecting the network pins in each target die to each of the remaining target dies to form projection pins on each target die corresponding to the network pins on the remaining target dies; the projection pins are used to realize cross-die connection of multiple network pins;

[0137] Obtaining first position information corresponding to a network pin of each target die and second pin position information corresponding to a projection pin;

[0138] forming die routing information corresponding to each target die according to routing congestion information of each target die, first pin location information, and second pin location information;

[0139] Generate cross-die connection position and thermal field distribution information corresponding to each target die according to the plurality of die wiring information;

[0140] Acquire through silicon via distribution information corresponding to each target die according to each thermal field distribution information;

[0141] The cross-die connection positions are optimized based on the TSV distribution information to complete the global routing of 3D stacked chips.

[0142] In some embodiments, die wiring information corresponding to each target die is formed based on the wiring congestion information, first pin position information and second pin position information of each target die, including: obtaining application scenario information and performance requirement information corresponding to the 3D stacked chip; generating die wiring information corresponding to each target die based on the wiring congestion information, application scenario information, performance requirement information, first pin position information and second pin position.

[0143] Exemplarily, the cross-die connection position and thermal field distribution information corresponding to each target die are generated based on multiple die wiring information, including: generating the cross-die connection position based on multiple die wiring information and multiple wiring congestion information; performing thermal analysis based on 2D structure information, die wiring information and application scenario information corresponding to each target die to obtain thermal field distribution information.

[0144] In some embodiments, the through silicon via distribution information corresponding to each target die is obtained according to each thermal field distribution information, including: obtaining the remaining resource information corresponding to the 3D stacked chip; generating the through silicon via distribution information according to the remaining resource information, the cross-die connection position and the thermal field distribution information; the through silicon via distribution information includes the through silicon via distribution positions and through silicon via distribution resources of multiple target dies.

[0145] In some embodiments, the cross-die connection positions are optimized based on the thermal field distribution information and the through silicon via distribution information, including: determining the optimization range corresponding to the target die based on the cross-die connection position corresponding to each target die and a preset range; determining the through silicon via distribution dense points based on the through silicon via distribution information corresponding to the optimization range, and updating the through silicon via distribution dense points to the cross-die connection positions corresponding to the target die.

[0146] In some embodiments, after completing the global routing of the 3D stacked chip, it also includes: updating the routing congestion information of each target die; if it is determined based on the updated routing congestion information that there is at least one target die congestion; optimizing the die routing information of the congested target die based on the routing congestion information to update the cross-die connection position.

[0147] In some embodiments, before obtaining the first position information corresponding to the network pin of each target die and the second pin position information corresponding to the projection pin, the method further includes: deleting the remaining dies except the target die from the multiple dies of the 3D stacked chip.

[0148] A computer-readable storage medium is also provided in an embodiment of the present application, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and the processor executes the program instructions to implement the steps of the 3D stacked chip global wiring method for thermal analysis optimization provided in the above embodiments of the present application.

[0149] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (SmartMedia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc., equipped on the computer device.

[0150] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A 3D stacked chip global wiring method for thermal analysis optimization, characterized in that: The method is used for routing a network of 3D stacked chips to be routed, wherein the network includes a plurality of bare chips; the method comprises: Acquire multiple target dies including preset network pins from multiple dies of the network to be routed, and acquire routing congestion information of each of the target dies; Projecting the network pins in each of the target dies to each of the remaining target dies, so as to form projection pins on each of the target dies corresponding to the network pins on the remaining target dies; the projection pins are used to realize cross-die connection of a plurality of the network pins; Acquire first position information corresponding to the network pin of each target die and second pin position information corresponding to the projection pin; The die wiring information corresponding to each of the target die is formed according to the wiring congestion information, the first pin position information and the second pin position information of each of the target die, including: obtaining application scenario information and performance requirement information corresponding to the 3D stacked chip; generating the die wiring information corresponding to each of the target die according to the wiring congestion information, the application scenario information, the performance requirement information, the first pin position information and the second pin position; Generating the cross-die connection position and thermal field distribution information corresponding to each target die according to the plurality of die wiring information, including: generating the cross-die connection position according to the plurality of die wiring information and the plurality of wiring congestion information; performing heat analysis according to the 2D structure information, the die wiring information and the application scenario information corresponding to each target die, and acquiring the thermal field distribution information; the 2D structure information is used to describe the physical layout of different components and wiring on the die; the die wiring information includes the wiring scheme of each die, including at least the connection path and resource allocation; the wiring congestion information is used to describe the resource occupancy of different areas on each die; Acquire the through silicon via distribution information corresponding to each of the target bare chips according to each of the thermal field distribution information; The cross-die connection position is optimized according to the through silicon via distribution information to complete the global wiring of the 3D stacked chip.

2. The method according to claim 1, characterized in that: Acquiring through silicon via distribution information corresponding to each target die according to each thermal field distribution information, including: Obtaining remaining resource information corresponding to the 3D stacked chip; The TSV distribution information is generated according to the remaining resource information, the cross-die connection positions and the thermal field distribution information; the TSV distribution information includes TSV distribution positions and TSV distribution resources in a plurality of the target dies.

3. The method according to claim 1, characterized in that The optimizing the cross-die connection position according to the thermal field distribution information and the through silicon via distribution information includes: Determine the optimization range corresponding to the target die according to the cross-die connection position corresponding to each target die and the preset range; Determine a TSV distribution intensive point according to TSV distribution information corresponding to the optimization range, and update the TSV distribution intensive point to a cross-die connection position corresponding to the target die.

4. The method according to claim 1, characterized in that After completing the global wiring of the 3D stacked chip, the method further includes: updating routing congestion information of each of the target dies; If it is determined according to the updated routing congestion information that at least the target die is congested; The die routing information of the congested target die is optimized according to the routing congestion information to update the cross-die connection position.

5. The method according to claim 1, characterized in that Before acquiring the first position information corresponding to the network pin of each target die and the second pin position information corresponding to the projection pin, the method further includes: Among the plurality of dies of the 3D stacked chip, the remaining dies except the target die are deleted.

6. A 3D stacked chip global wiring device, characterized in that: The device is used for routing a network of 3D stacked chips to be routed, wherein the network includes a plurality of bare chips; the device comprises: An information acquisition unit, used to acquire a plurality of target dies including preset network pins from a plurality of dies of a network to be routed, and acquire routing congestion information of each of the target dies; A pin projection unit, used for projecting the network pins in each of the target dies to each of the remaining target dies, so as to form projection pins on each of the target dies corresponding to the network pins on the remaining target dies; the projection pins are used for realizing cross-die connection of a plurality of the network pins; A position acquisition unit, used to acquire first position information corresponding to the network pin of each target die and second pin position information corresponding to the projection pin; A wiring generation unit, configured to form die wiring information corresponding to each of the target die according to wiring congestion information, first pin position information, and second pin position information of each of the target die, including: acquiring application scenario information and performance requirement information corresponding to the 3D stacked chip; generating die wiring information corresponding to each of the target die according to the wiring congestion information, application scenario information, performance requirement information, first pin position information, and second pin position; A thermal field distribution unit is used to generate a cross-die connection position and thermal field distribution information corresponding to each target die according to the plurality of die wiring information, including: generating the cross-die connection position according to the plurality of die wiring information and the plurality of wiring congestion information; performing a thermal analysis according to the 2D structure information, the die wiring information and the application scenario information corresponding to each target die, and acquiring the thermal field distribution information; the 2D structure information is used to describe the physical layout of different components and wiring on the die; the die wiring information includes the wiring scheme of each die, including at least the connection path and resource allocation; the wiring congestion information is used to describe the resource occupancy of different areas on each die; A distribution acquisition unit, configured to acquire through silicon via distribution information corresponding to each of the target dies according to each of the thermal field distribution information; A wiring completion unit is used to optimize the cross-die connection position according to the through silicon via distribution information to complete the global wiring of the 3D stacked chip.

7. A computer device, characterized in that: The computer device includes a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and implement the method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, enables the processor to implement the method according to any one of claims 1 to 5.

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